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2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6 
 kernel/arch/arm64/include/uapi/asm/kvm.h
....@@ -35,6 +35,7 @@
3535 #include <linux/psci.h>
3636 #include <linux/types.h>
3737 #include <asm/ptrace.h>
38
+#include <asm/sve_context.h>
3839 
3940 #define __KVM_HAVE_GUEST_DEBUG
4041 #define __KVM_HAVE_IRQ_LINE
....@@ -102,6 +103,9 @@
102103 #define KVM_ARM_VCPU_EL1_32BIT		1 /* CPU running a 32bit VM */
103104 #define KVM_ARM_VCPU_PSCI_0_2		2 /* CPU uses PSCI v0.2 */
104105 #define KVM_ARM_VCPU_PMU_V3		3 /* Support guest PMUv3 */
106
+#define KVM_ARM_VCPU_SVE		4 /* enable SVE for this CPU */
107
+#define KVM_ARM_VCPU_PTRAUTH_ADDRESS	5 /* VCPU uses address authentication */
108
+#define KVM_ARM_VCPU_PTRAUTH_GENERIC	6 /* VCPU uses generic authentication */
105109 
106110 struct kvm_vcpu_init {
107111 	__u32 target;
....@@ -152,7 +156,19 @@
152156 	__u64 device_irq_level;
153157 };
154158 
155
-struct kvm_arch_memory_slot {
159
+/*
160
+ * PMU filter structure. Describe a range of events with a particular
161
+ * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
162
+ */
163
+struct kvm_pmu_event_filter {
164
+	__u16	base_event;
165
+	__u16	nevents;
166
+
167
+#define KVM_PMU_EVENT_ALLOW	0
168
+#define KVM_PMU_EVENT_DENY	1
169
+
170
+	__u8	action;
171
+	__u8	pad[3];
156172 };
157173 
158174 /* for KVM_GET/SET_VCPU_EVENTS */
....@@ -160,8 +176,9 @@
160176 	struct {
161177 		__u8 serror_pending;
162178 		__u8 serror_has_esr;
179
+		__u8 ext_dabt_pending;
163180 		/* Align it to 8 bytes */
164
-		__u8 pad[6];
181
+		__u8 pad[5];
165182 		__u64 serror_esr;
166183 	} exception;
167184 	__u32 reserved[12];
....@@ -215,16 +232,94 @@
215232 #define KVM_REG_ARM_PTIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 2, 2)
216233 #define KVM_REG_ARM_PTIMER_CNT		ARM64_SYS_REG(3, 3, 14, 0, 1)
217234 
218
-/* EL0 Virtual Timer Registers */
235
+/*
236
+ * EL0 Virtual Timer Registers
237
+ *
238
+ * WARNING:
239
+ *      KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
240
+ *      with the appropriate register encodings.  Their values have been
241
+ *      accidentally swapped.  As this is set API, the definitions here
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+ *      must be used, rather than ones derived from the encodings.
243
+ */
219244 #define KVM_REG_ARM_TIMER_CTL		ARM64_SYS_REG(3, 3, 14, 3, 1)
220
-#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)
221245 #define KVM_REG_ARM_TIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 0, 2)
246
+#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)
222247 
223248 /* KVM-as-firmware specific pseudo-registers */
224249 #define KVM_REG_ARM_FW			(0x0014 << KVM_REG_ARM_COPROC_SHIFT)
225250 #define KVM_REG_ARM_FW_REG(r)		(KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
226251 					 KVM_REG_ARM_FW | ((r) & 0xffff))
227252 #define KVM_REG_ARM_PSCI_VERSION	KVM_REG_ARM_FW_REG(0)
253
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1	KVM_REG_ARM_FW_REG(1)
254
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL		0
255
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL		1
256
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED	2
257
+
258
+/*
259
+ * Only two states can be presented by the host kernel:
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+ * - NOT_REQUIRED: the guest doesn't need to do anything
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+ * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
262
+ *
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+ * All the other values are deprecated. The host still accepts all
264
+ * values (they are ABI), but will narrow them to the above two.
265
+ */
266
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2	KVM_REG_ARM_FW_REG(2)
267
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL		0
268
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN		1
269
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL		2
270
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED	3
271
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED     	(1U << 4)
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+
273
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3	KVM_REG_ARM_FW_REG(3)
274
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL		0
275
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL		1
276
+#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED	2
277
+
278
+/* SVE registers */
279
+#define KVM_REG_ARM64_SVE		(0x15 << KVM_REG_ARM_COPROC_SHIFT)
280
+
281
+/* Z- and P-regs occupy blocks at the following offsets within this range: */
282
+#define KVM_REG_ARM64_SVE_ZREG_BASE	0
283
+#define KVM_REG_ARM64_SVE_PREG_BASE	0x400
284
+#define KVM_REG_ARM64_SVE_FFR_BASE	0x600
285
+
286
+#define KVM_ARM64_SVE_NUM_ZREGS		__SVE_NUM_ZREGS
287
+#define KVM_ARM64_SVE_NUM_PREGS		__SVE_NUM_PREGS
288
+
289
+#define KVM_ARM64_SVE_MAX_SLICES	32
290
+
291
+#define KVM_REG_ARM64_SVE_ZREG(n, i)					\
292
+	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
293
+	 KVM_REG_SIZE_U2048 |						\
294
+	 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) |			\
295
+	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
296
+
297
+#define KVM_REG_ARM64_SVE_PREG(n, i)					\
298
+	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
299
+	 KVM_REG_SIZE_U256 |						\
300
+	 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) |			\
301
+	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
302
+
303
+#define KVM_REG_ARM64_SVE_FFR(i)					\
304
+	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
305
+	 KVM_REG_SIZE_U256 |						\
306
+	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
307
+
308
+/*
309
+ * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
310
+ * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
311
+ * invariant layout which differs from the layout used for the FPSIMD
312
+ * V-registers on big-endian systems: see sigcontext.h for more explanation.
313
+ */
314
+
315
+#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
316
+#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
317
+
318
+/* Vector lengths pseudo-register: */
319
+#define KVM_REG_ARM64_SVE_VLS		(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
320
+					 KVM_REG_SIZE_U512 | 0xffff)
321
+#define KVM_ARM64_SVE_VLS_WORDS	\
322
+	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
228323 
229324 /* Device Control API: ARM VGIC */
230325 #define KVM_DEV_ARM_VGIC_GRP_ADDR	0
....@@ -260,13 +355,18 @@
260355 #define KVM_ARM_VCPU_PMU_V3_CTRL	0
261356 #define   KVM_ARM_VCPU_PMU_V3_IRQ	0
262357 #define   KVM_ARM_VCPU_PMU_V3_INIT	1
358
+#define   KVM_ARM_VCPU_PMU_V3_FILTER	2
263359 #define KVM_ARM_VCPU_TIMER_CTRL		1
264360 #define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0
265361 #define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1
362
+#define KVM_ARM_VCPU_PVTIME_CTRL	2
363
+#define   KVM_ARM_VCPU_PVTIME_IPA	0
266364 
267365 /* KVM_IRQ_LINE irq field index values */
366
+#define KVM_ARM_IRQ_VCPU2_SHIFT		28
367
+#define KVM_ARM_IRQ_VCPU2_MASK		0xf
268368 #define KVM_ARM_IRQ_TYPE_SHIFT		24
269
-#define KVM_ARM_IRQ_TYPE_MASK		0xff
369
+#define KVM_ARM_IRQ_TYPE_MASK		0xf
270370 #define KVM_ARM_IRQ_VCPU_SHIFT		16
271371 #define KVM_ARM_IRQ_VCPU_MASK		0xff
272372 #define KVM_ARM_IRQ_NUM_SHIFT		0