~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,7 +1,6 @@
	1	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1	2	/*
2		- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3		- *
4		- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	3	+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
5	4	*/
6	5
7	6	#include <dt-bindings/clock/px30-cru.h>
..	..	@@ -27,6 +26,10 @@
27	26
28	27	aliases {
29	28	ethernet0 = &gmac;
	29	+ gpio0 = &gpio0;
	30	+ gpio1 = &gpio1;
	31	+ gpio2 = &gpio2;
	32	+ gpio3 = &gpio3;
30	33	i2c0 = &i2c0;
31	34	i2c1 = &i2c1;
32	35	i2c2 = &i2c2;
..	..	@@ -42,6 +45,7 @@
42	45	serial5 = &uart5;
43	46	spi0 = &spi0;
44	47	spi1 = &spi1;
	48	+ spi2 = &sfc;
45	49	};
46	50
47	51	cpus {
..	..	@@ -50,39 +54,50 @@
50	54
51	55	cpu0: cpu@0 {
52	56	device_type = "cpu";
53		- compatible = "arm,cortex-a35", "arm,armv8";
	57	+ compatible = "arm,cortex-a35";
54	58	reg = <0x0 0x0>;
55	59	enable-method = "psci";
56	60	clocks = <&cru ARMCLK>;
57	61	#cooling-cells = <2>;
	62	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
58	63	dynamic-power-coefficient = <90>;
59	64	operating-points-v2 = <&cpu0_opp_table>;
60		- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61	65	};
62	66
63	67	cpu1: cpu@1 {
64	68	device_type = "cpu";
65		- compatible = "arm,cortex-a35", "arm,armv8";
	69	+ compatible = "arm,cortex-a35";
66	70	reg = <0x0 0x1>;
67	71	enable-method = "psci";
68		- operating-points-v2 = <&cpu0_opp_table>;
	72	+ clocks = <&cru ARMCLK>;
	73	+ #cooling-cells = <2>;
69	74	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	75	+ dynamic-power-coefficient = <90>;
	76	+ operating-points-v2 = <&cpu0_opp_table>;
70	77	};
	78	+
71	79	cpu2: cpu@2 {
72	80	device_type = "cpu";
73		- compatible = "arm,cortex-a35", "arm,armv8";
	81	+ compatible = "arm,cortex-a35";
74	82	reg = <0x0 0x2>;
75	83	enable-method = "psci";
76		- operating-points-v2 = <&cpu0_opp_table>;
	84	+ clocks = <&cru ARMCLK>;
	85	+ #cooling-cells = <2>;
77	86	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	87	+ dynamic-power-coefficient = <90>;
	88	+ operating-points-v2 = <&cpu0_opp_table>;
78	89	};
	90	+
79	91	cpu3: cpu@3 {
80	92	device_type = "cpu";
81		- compatible = "arm,cortex-a35", "arm,armv8";
	93	+ compatible = "arm,cortex-a35";
82	94	reg = <0x0 0x3>;
83	95	enable-method = "psci";
84		- operating-points-v2 = <&cpu0_opp_table>;
	96	+ clocks = <&cru ARMCLK>;
	97	+ #cooling-cells = <2>;
85	98	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	99	+ dynamic-power-coefficient = <90>;
	100	+ operating-points-v2 = <&cpu0_opp_table>;
86	101	};
87	102
88	103	idle-states {
..	..	@@ -335,12 +350,34 @@
335	350	};
336	351
337	352	arm-pmu {
338		- compatible = "arm,cortex-a53-pmu";
	353	+ compatible = "arm,cortex-a35-pmu";
339	354	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
340	355	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
341	356	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
342	357	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
343	358	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	359	+ };
	360	+
	361	+ bus_soc: bus-soc {
	362	+ compatible = "rockchip,px30-bus";
	363	+ rockchip,busfreq-policy = "autocs";
	364	+ soc-bus0 {
	365	+ bus-id = <0>;
	366	+ timer-us = <20>;
	367	+ enable-msk = <0x40f7>;
	368	+ };
	369	+ soc-bus1 {
	370	+ bus-id = <1>;
	371	+ timer-us = <200>;
	372	+ enable-msk = <0x40bf>;
	373	+ status = "disabled";
	374	+ };
	375	+ soc-bus2 {
	376	+ bus-id = <2>;
	377	+ timer-us = <200>;
	378	+ enable-msk = <0x4007>;
	379	+ status = "disabled";
	380	+ };
344	381	};
345	382
346	383	bus_apll: bus-apll {
..	..	@@ -368,7 +405,7 @@
368	405
369	406	cpuinfo {
370	407	compatible = "rockchip,cpuinfo";
371		- nvmem-cells = <&otp_id>;
	408	+ nvmem-cells = <&cpu_id>;
372	409	nvmem-cell-names = "id";
373	410	};
374	411
..	..	@@ -445,6 +482,55 @@
445	482	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
446	483	};
447	484
	485	+ thermal_zones: thermal-zones {
	486	+ soc_thermal: soc-thermal {
	487	+ polling-delay-passive = <20>;
	488	+ polling-delay = <1000>;
	489	+ sustainable-power = <750>;
	490	+ thermal-sensors = <&tsadc 0>;
	491	+
	492	+ trips {
	493	+ threshold: trip-point-0 {
	494	+ temperature = <70000>;
	495	+ hysteresis = <2000>;
	496	+ type = "passive";
	497	+ };
	498	+
	499	+ target: trip-point-1 {
	500	+ temperature = <85000>;
	501	+ hysteresis = <2000>;
	502	+ type = "passive";
	503	+ };
	504	+
	505	+ soc_crit: soc-crit {
	506	+ temperature = <115000>;
	507	+ hysteresis = <2000>;
	508	+ type = "critical";
	509	+ };
	510	+ };
	511	+
	512	+ cooling-maps {
	513	+ map0 {
	514	+ trip = <&target>;
	515	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	516	+ contribution = <4096>;
	517	+ };
	518	+
	519	+ map1 {
	520	+ trip = <&target>;
	521	+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	522	+ contribution = <4096>;
	523	+ };
	524	+ };
	525	+ };
	526	+
	527	+ gpu_thermal: gpu-thermal {
	528	+ polling-delay-passive = <100>; /* milliseconds */
	529	+ polling-delay = <1000>; /* milliseconds */
	530	+ thermal-sensors = <&tsadc 1>;
	531	+ };
	532	+ };
	533	+
448	534	xin24m: xin24m {
449	535	compatible = "fixed-clock";
450	536	#clock-cells = <0>;
..	..	@@ -475,20 +561,20 @@
475	561	#size-cells = <0>;
476	562
477	563	/* These power domains are grouped by VD_LOGIC */
478		- pd_usb@PX30_PD_USB {
	564	+ power-domain@PX30_PD_USB {
479	565	reg = <PX30_PD_USB>;
480	566	clocks = <&cru HCLK_HOST>,
481	567	<&cru HCLK_OTG>,
482	568	<&cru SCLK_OTG_ADP>;
483	569	pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
484	570	};
485		- pd_sdcard@PX30_PD_SDCARD {
	571	+ power-domain@PX30_PD_SDCARD {
486	572	reg = <PX30_PD_SDCARD>;
487	573	clocks = <&cru HCLK_SDMMC>,
488	574	<&cru SCLK_SDMMC>;
489	575	pm_qos = <&qos_sdmmc>;
490	576	};
491		- pd_gmac@PX30_PD_GMAC {
	577	+ power-domain@PX30_PD_GMAC {
492	578	reg = <PX30_PD_GMAC>;
493	579	clocks = <&cru ACLK_GMAC>,
494	580	<&cru PCLK_GMAC>,
..	..	@@ -496,7 +582,7 @@
496	582	<&cru SCLK_GMAC_RX_TX>;
497	583	pm_qos = <&qos_gmac>;
498	584	};
499		- pd_mmc_nand@PX30_PD_MMC_NAND {
	585	+ power-domain@PX30_PD_MMC_NAND {
500	586	reg = <PX30_PD_MMC_NAND>;
501	587	clocks = <&cru HCLK_NANDC>,
502	588	<&cru HCLK_EMMC>,
..	..	@@ -509,14 +595,14 @@
509	595	pm_qos = <&qos_emmc>, <&qos_nand>,
510	596	<&qos_sdio>, <&qos_sfc>;
511	597	};
512		- pd_vpu@PX30_PD_VPU {
	598	+ power-domain@PX30_PD_VPU {
513	599	reg = <PX30_PD_VPU>;
514	600	clocks = <&cru ACLK_VPU>,
515	601	<&cru HCLK_VPU>,
516	602	<&cru SCLK_CORE_VPU>;
517	603	pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
518	604	};
519		- pd_vo@PX30_PD_VO {
	605	+ power-domain@PX30_PD_VO {
520	606	reg = <PX30_PD_VO>;
521	607	clocks = <&cru ACLK_RGA>,
522	608	<&cru ACLK_VOPB>,
..	..	@@ -532,7 +618,7 @@
532	618	pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
533	619	<&qos_vop_m0>, <&qos_vop_m1>;
534	620	};
535		- pd_vi@PX30_PD_VI {
	621	+ power-domain@PX30_PD_VI {
536	622	reg = <PX30_PD_VI>;
537	623	clocks = <&cru ACLK_CIF>,
538	624	<&cru ACLK_ISP>,
..	..	@@ -543,7 +629,7 @@
543	629	<&qos_isp_wr>, <&qos_isp_m1>,
544	630	<&qos_vip>;
545	631	};
546		- pd_gpu@PX30_PD_GPU {
	632	+ power-domain@PX30_PD_GPU {
547	633	reg = <PX30_PD_GPU>;
548	634	clocks = <&cru SCLK_GPU>;
549	635	pm_qos = <&qos_gpu>;
..	..	@@ -566,12 +652,10 @@
566	652	compatible = "syscon-reboot-mode";
567	653	offset = <0x200>;
568	654	mode-bootloader = <BOOT_BL_DOWNLOAD>;
569		- mode-charge = <BOOT_CHARGING>;
570	655	mode-fastboot = <BOOT_FASTBOOT>;
571	656	mode-loader = <BOOT_BL_DOWNLOAD>;
572	657	mode-normal = <BOOT_NORMAL>;
573	658	mode-recovery = <BOOT_RECOVERY>;
574		- mode-ums = <BOOT_UMS>;
575	659	};
576	660
577	661	pmu_pvtm: pmu-pvtm {
..	..	@@ -594,9 +678,11 @@
594	678	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
595	679	clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
596	680	clock-names = "baudclk", "apb_pclk";
	681	+ dmas = <&dmac 0>, <&dmac 1>;
	682	+ /You can add it to enable dma/
	683	+ /dma-names = "tx", "rx";/
597	684	reg-shift = <2>;
598	685	reg-io-width = <4>;
599		- dmas = <&dmac 0>, <&dmac 1>;
600	686	pinctrl-names = "default";
601	687	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
602	688	status = "disabled";
..	..	@@ -638,13 +724,10 @@
638	724	clock-names = "i2s_clk", "i2s_hclk";
639	725	dmas = <&dmac 18>, <&dmac 19>;
640	726	dma-names = "tx", "rx";
641		- resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>;
642		- reset-names = "reset-m", "reset-h";
643	727	pinctrl-names = "default";
644		- pinctrl-0 = <&i2s1_2ch_sclk
645		- &i2s1_2ch_lrck
646		- &i2s1_2ch_sdi
647		- &i2s1_2ch_sdo>;
	728	+ pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
	729	+ &i2s1_2ch_sdi &i2s1_2ch_sdo>;
	730	+ #sound-dai-cells = <0>;
648	731	status = "disabled";
649	732	};
650	733
..	..	@@ -656,32 +739,10 @@
656	739	clock-names = "i2s_clk", "i2s_hclk";
657	740	dmas = <&dmac 20>, <&dmac 21>;
658	741	dma-names = "tx", "rx";
659		- resets = <&cru SRST_I2S2>, <&cru SRST_I2S2_H>;
660		- reset-names = "reset-m", "reset-h";
661	742	pinctrl-names = "default";
662		- pinctrl-0 = <&i2s2_2ch_sclk
663		- &i2s2_2ch_lrck
664		- &i2s2_2ch_sdi
665		- &i2s2_2ch_sdo>;
666		- status = "disabled";
667		- };
668		-
669		- pdm: pdm@ff0a0000 {
670		- compatible = "rockchip,px30-pdm";
671		- reg = <0x0 0xff0a0000 0x0 0x1000>;
672		- clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
673		- clock-names = "pdm_clk", "pdm_hclk";
674		- dmas = <&dmac 24>;
675		- dma-names = "rx";
676		- resets = <&cru SRST_PDM>;
677		- reset-names = "pdm-m";
678		- pinctrl-names = "default";
679		- pinctrl-0 = <&pdm_clk0m0
680		- &pdm_clk1
681		- &pdm_sdi0m0
682		- &pdm_sdi1
683		- &pdm_sdi2
684		- &pdm_sdi3>;
	743	+ pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
	744	+ &i2s2_2ch_sdi &i2s2_2ch_sdo>;
	745	+ #sound-dai-cells = <0>;
685	746	status = "disabled";
686	747	};
687	748
..	..	@@ -690,7 +751,7 @@
690	751	reg = <0x0 0xff0b0000 0x0 0x400>, <0x0 0xff0b0480 0x0 0x3B80>;
691	752	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
692	753	clocks = <&cru ACLK_CRYPTO >, <&cru HCLK_CRYPTO >,
693		- <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>;
	754	+ <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>;
694	755	clock-names = "aclk", "hclk", "sclk", "apb_pclk";
695	756	resets = <&cru SRST_CRYPTO>;
696	757	reset-names = "crypto-rst";
..	..	@@ -701,13 +762,13 @@
701	762	compatible = "rockchip,cryptov2-rng";
702	763	reg = <0x0 0xff0b0400 0x0 0x80>;
703	764	clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
704		- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
	765	+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
705	766	clock-names = "clk_crypto", "clk_crypto_apk",
706		- "aclk_crypto", "hclk_crypto";
	767	+ "aclk_crypto", "hclk_crypto";
707	768	assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
708		- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
	769	+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
709	770	assigned-clock-rates = <150000000>, <150000000>,
710		- <200000000>, <200000000>;
	771	+ <200000000>, <200000000>;
711	772	resets = <&cru SRST_CRYPTO>;
712	773	reset-names = "reset";
713	774	status = "disabled";
..	..	@@ -752,12 +813,12 @@
752	813	#address-cells = <1>;
753	814	#size-cells = <0>;
754	815
755		- lvds_in_vopb: endpoint@0 {
	816	+ lvds_vopb_in: endpoint@0 {
756	817	reg = <0>;
757	818	remote-endpoint = <&vopb_out_lvds>;
758	819	};
759	820
760		- lvds_in_vopl: endpoint@1 {
	821	+ lvds_vopl_in: endpoint@1 {
761	822	reg = <1>;
762	823	remote-endpoint = <&vopl_out_lvds>;
763	824	};
..	..	@@ -821,9 +882,11 @@
821	882	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
822	883	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
823	884	clock-names = "baudclk", "apb_pclk";
	885	+ dmas = <&dmac 2>, <&dmac 3>;
	886	+ /You can add it to enable dma/
	887	+ /dma-names = "tx", "rx";/
824	888	reg-shift = <2>;
825	889	reg-io-width = <4>;
826		- dmas = <&dmac 2>, <&dmac 3>;
827	890	pinctrl-names = "default";
828	891	pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
829	892	status = "disabled";
..	..	@@ -835,9 +898,11 @@
835	898	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
836	899	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
837	900	clock-names = "baudclk", "apb_pclk";
	901	+ dmas = <&dmac 4>, <&dmac 5>;
	902	+ /You can add it to enable dma/
	903	+ /dma-names = "tx", "rx";/
838	904	reg-shift = <2>;
839	905	reg-io-width = <4>;
840		- dmas = <&dmac 4>, <&dmac 5>;
841	906	pinctrl-names = "default";
842	907	pinctrl-0 = <&uart2m0_xfer>;
843	908	status = "disabled";
..	..	@@ -849,9 +914,11 @@
849	914	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
850	915	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
851	916	clock-names = "baudclk", "apb_pclk";
	917	+ dmas = <&dmac 6>, <&dmac 7>;
	918	+ /You can add it to enable dma/
	919	+ /dma-names = "tx", "rx";/
852	920	reg-shift = <2>;
853	921	reg-io-width = <4>;
854		- dmas = <&dmac 6>, <&dmac 7>;
855	922	pinctrl-names = "default";
856	923	pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
857	924	status = "disabled";
..	..	@@ -863,9 +930,11 @@
863	930	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
864	931	clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
865	932	clock-names = "baudclk", "apb_pclk";
	933	+ dmas = <&dmac 8>, <&dmac 9>;
	934	+ /You can add it to enable dma/
	935	+ /dma-names = "tx", "rx";/
866	936	reg-shift = <2>;
867	937	reg-io-width = <4>;
868		- dmas = <&dmac 8>, <&dmac 9>;
869	938	pinctrl-names = "default";
870	939	pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
871	940	status = "disabled";
..	..	@@ -877,16 +946,18 @@
877	946	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
878	947	clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
879	948	clock-names = "baudclk", "apb_pclk";
	949	+ dmas = <&dmac 10>, <&dmac 11>;
	950	+ /You can add it to enable dma/
	951	+ /dma-names = "tx", "rx";/
880	952	reg-shift = <2>;
881	953	reg-io-width = <4>;
882		- dmas = <&dmac 10>, <&dmac 11>;
883	954	pinctrl-names = "default";
884	955	pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
885	956	status = "disabled";
886	957	};
887	958
888	959	i2c0: i2c@ff180000 {
889		- compatible = "rockchip,rk3399-i2c";
	960	+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
890	961	reg = <0x0 0xff180000 0x0 0x1000>;
891	962	clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
892	963	clock-names = "i2c", "pclk";
..	..	@@ -899,7 +970,7 @@
899	970	};
900	971
901	972	i2c1: i2c@ff190000 {
902		- compatible = "rockchip,rk3399-i2c";
	973	+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
903	974	reg = <0x0 0xff190000 0x0 0x1000>;
904	975	clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
905	976	clock-names = "i2c", "pclk";
..	..	@@ -912,7 +983,7 @@
912	983	};
913	984
914	985	i2c2: i2c@ff1a0000 {
915		- compatible = "rockchip,rk3399-i2c";
	986	+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
916	987	reg = <0x0 0xff1a0000 0x0 0x1000>;
917	988	clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
918	989	clock-names = "i2c", "pclk";
..	..	@@ -925,7 +996,7 @@
925	996	};
926	997
927	998	i2c3: i2c@ff1b0000 {
928		- compatible = "rockchip,rk3399-i2c";
	999	+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
929	1000	reg = <0x0 0xff1b0000 0x0 0x1000>;
930	1001	clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
931	1002	clock-names = "i2c", "pclk";
..	..	@@ -941,15 +1012,14 @@
941	1012	compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
942	1013	reg = <0x0 0xff1d0000 0x0 0x1000>;
943	1014	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
944		- #address-cells = <1>;
945		- #size-cells = <0>;
946	1015	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
947	1016	clock-names = "spiclk", "apb_pclk";
948	1017	dmas = <&dmac 12>, <&dmac 13>;
949	1018	dma-names = "tx", "rx";
950		- pinctrl-names = "default", "high_speed";
	1019	+ pinctrl-names = "default";
951	1020	pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
952		- pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>;
	1021	+ #address-cells = <1>;
	1022	+ #size-cells = <0>;
953	1023	status = "disabled";
954	1024	};
955	1025
..	..	@@ -957,15 +1027,14 @@
957	1027	compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
958	1028	reg = <0x0 0xff1d8000 0x0 0x1000>;
959	1029	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
960		- #address-cells = <1>;
961		- #size-cells = <0>;
962	1030	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
963	1031	clock-names = "spiclk", "apb_pclk";
964	1032	dmas = <&dmac 14>, <&dmac 15>;
965	1033	dma-names = "tx", "rx";
966		- pinctrl-names = "default", "high_speed";
	1034	+ pinctrl-names = "default";
967	1035	pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
968		- pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>;
	1036	+ #address-cells = <1>;
	1037	+ #size-cells = <0>;
969	1038	status = "disabled";
970	1039	};
971	1040
..	..	@@ -974,108 +1043,116 @@
974	1043	reg = <0x0 0xff1e0000 0x0 0x100>;
975	1044	clocks = <&cru PCLK_WDT_NS>;
976	1045	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
977		- resets = <&cru SRST_WDT_NS_P>;
978		- reset-names = "reset";
979	1046	status = "disabled";
980	1047	};
981	1048
982	1049	pwm0: pwm@ff200000 {
983	1050	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
984	1051	reg = <0x0 0xff200000 0x0 0x10>;
985		- #pwm-cells = <3>;
986		- pinctrl-names = "active";
987		- pinctrl-0 = <&pwm0_pin>;
	1052	+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
988	1053	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
989	1054	clock-names = "pwm", "pclk";
	1055	+ pinctrl-names = "active";
	1056	+ pinctrl-0 = <&pwm0_pin>;
	1057	+ #pwm-cells = <3>;
990	1058	status = "disabled";
991	1059	};
992	1060
993	1061	pwm1: pwm@ff200010 {
994	1062	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
995	1063	reg = <0x0 0xff200010 0x0 0x10>;
996		- #pwm-cells = <3>;
997		- pinctrl-names = "active";
998		- pinctrl-0 = <&pwm1_pin>;
	1064	+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
999	1065	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
1000	1066	clock-names = "pwm", "pclk";
	1067	+ pinctrl-names = "active";
	1068	+ pinctrl-0 = <&pwm1_pin>;
	1069	+ #pwm-cells = <3>;
1001	1070	status = "disabled";
1002	1071	};
1003	1072
1004	1073	pwm2: pwm@ff200020 {
1005	1074	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1006	1075	reg = <0x0 0xff200020 0x0 0x10>;
1007		- #pwm-cells = <3>;
1008		- pinctrl-names = "active";
1009		- pinctrl-0 = <&pwm2_pin>;
	1076	+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1010	1077	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
1011	1078	clock-names = "pwm", "pclk";
	1079	+ pinctrl-names = "active";
	1080	+ pinctrl-0 = <&pwm2_pin>;
	1081	+ #pwm-cells = <3>;
1012	1082	status = "disabled";
1013	1083	};
1014	1084
1015	1085	pwm3: pwm@ff200030 {
1016	1086	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1017	1087	reg = <0x0 0xff200030 0x0 0x10>;
1018		- #pwm-cells = <3>;
1019		- pinctrl-names = "active";
1020		- pinctrl-0 = <&pwm3_pin>;
	1088	+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
	1089	+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1021	1090	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
1022	1091	clock-names = "pwm", "pclk";
	1092	+ pinctrl-names = "active";
	1093	+ pinctrl-0 = <&pwm3_pin>;
	1094	+ #pwm-cells = <3>;
1023	1095	status = "disabled";
1024	1096	};
1025	1097
1026	1098	pwm4: pwm@ff208000 {
1027	1099	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1028	1100	reg = <0x0 0xff208000 0x0 0x10>;
1029		- #pwm-cells = <3>;
1030		- pinctrl-names = "active";
1031		- pinctrl-0 = <&pwm4_pin>;
	1101	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1032	1102	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1033	1103	clock-names = "pwm", "pclk";
	1104	+ pinctrl-names = "active";
	1105	+ pinctrl-0 = <&pwm4_pin>;
	1106	+ #pwm-cells = <3>;
1034	1107	status = "disabled";
1035	1108	};
1036	1109
1037	1110	pwm5: pwm@ff208010 {
1038	1111	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1039	1112	reg = <0x0 0xff208010 0x0 0x10>;
1040		- #pwm-cells = <3>;
1041		- pinctrl-names = "active";
1042		- pinctrl-0 = <&pwm5_pin>;
	1113	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1043	1114	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1044	1115	clock-names = "pwm", "pclk";
	1116	+ pinctrl-names = "active";
	1117	+ pinctrl-0 = <&pwm5_pin>;
	1118	+ #pwm-cells = <3>;
1045	1119	status = "disabled";
1046	1120	};
1047	1121
1048	1122	pwm6: pwm@ff208020 {
1049	1123	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1050	1124	reg = <0x0 0xff208020 0x0 0x10>;
1051		- #pwm-cells = <3>;
1052		- pinctrl-names = "active";
1053		- pinctrl-0 = <&pwm6_pin>;
	1125	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1054	1126	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1055	1127	clock-names = "pwm", "pclk";
	1128	+ pinctrl-names = "active";
	1129	+ pinctrl-0 = <&pwm6_pin>;
	1130	+ #pwm-cells = <3>;
1056	1131	status = "disabled";
1057	1132	};
1058	1133
1059	1134	pwm7: pwm@ff208030 {
1060	1135	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1061	1136	reg = <0x0 0xff208030 0x0 0x10>;
1062		- #pwm-cells = <3>;
1063		- pinctrl-names = "active";
1064		- pinctrl-0 = <&pwm7_pin>;
	1137	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
	1138	+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1065	1139	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1066	1140	clock-names = "pwm", "pclk";
	1141	+ pinctrl-names = "active";
	1142	+ pinctrl-0 = <&pwm7_pin>;
	1143	+ #pwm-cells = <3>;
1067	1144	status = "disabled";
1068	1145	};
1069	1146
1070		- rktimer: rktimer@ff210000 {
1071		- compatible = "rockchip,rk3288-timer";
	1147	+ rktimer: timer@ff210000 {
	1148	+ compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
1072	1149	reg = <0x0 0xff210000 0x0 0x1000>;
1073	1150	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1074	1151	clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
1075	1152	clock-names = "pclk", "timer";
1076	1153	};
1077	1154
1078		- amba {
	1155	+ amba: bus {
1079	1156	compatible = "simple-bus";
1080	1157	#address-cells = <2>;
1081	1158	#size-cells = <2>;
..	..	@@ -1086,59 +1163,10 @@
1086	1163	reg = <0x0 0xff240000 0x0 0x4000>;
1087	1164	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
1088	1165	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	1166	+ arm,pl330-periph-burst;
1089	1167	clocks = <&cru ACLK_DMAC>;
1090	1168	clock-names = "apb_pclk";
1091	1169	#dma-cells = <1>;
1092		- arm,pl330-periph-burst;
1093		- };
1094		- };
1095		-
1096		- thermal_zones: thermal-zones {
1097		-
1098		- soc_thermal: soc-thermal {
1099		- polling-delay-passive = <20>;
1100		- polling-delay = <1000>;
1101		- sustainable-power = <750>;
1102		-
1103		- thermal-sensors = <&tsadc 0>;
1104		-
1105		- trips {
1106		- threshold: trip-point-0 {
1107		- temperature = <70000>;
1108		- hysteresis = <2000>;
1109		- type = "passive";
1110		- };
1111		- target: trip-point-1 {
1112		- temperature = <85000>;
1113		- hysteresis = <2000>;
1114		- type = "passive";
1115		- };
1116		- soc_crit: soc-crit {
1117		- temperature = <115000>;
1118		- hysteresis = <2000>;
1119		- type = "critical";
1120		- };
1121		- };
1122		-
1123		- cooling-maps {
1124		- map0 {
1125		- trip = <&target>;
1126		- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1127		- contribution = <4096>;
1128		- };
1129		- map1 {
1130		- trip = <&target>;
1131		- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1132		- contribution = <4096>;
1133		- };
1134		- };
1135		- };
1136		-
1137		- gpu_thermal: gpu-thermal {
1138		- polling-delay-passive = <100>; /* milliseconds */
1139		- polling-delay = <1000>; /* milliseconds */
1140		-
1141		- thermal-sensors = <&tsadc 1>;
1142	1170	};
1143	1171	};
1144	1172
..	..	@@ -1146,15 +1174,19 @@
1146	1174	compatible = "rockchip,px30-tsadc";
1147	1175	reg = <0x0 0xff280000 0x0 0x100>;
1148	1176	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1149		- rockchip,grf = <&grf>;
1150		- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
1151		- clock-names = "tsadc", "apb_pclk";
1152	1177	assigned-clocks = <&cru SCLK_TSADC>;
1153	1178	assigned-clock-rates = <50000>;
	1179	+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	1180	+ clock-names = "tsadc", "apb_pclk";
1154	1181	resets = <&cru SRST_TSADC>;
1155	1182	reset-names = "tsadc-apb";
1156		- #thermal-sensor-cells = <1>;
	1183	+ rockchip,grf = <&grf>;
1157	1184	rockchip,hw-tshut-temp = <120000>;
	1185	+ pinctrl-names = "init", "default", "sleep";
	1186	+ pinctrl-0 = <&tsadc_otp_pin>;
	1187	+ pinctrl-1 = <&tsadc_otp_out>;
	1188	+ pinctrl-2 = <&tsadc_otp_pin>;
	1189	+ #thermal-sensor-cells = <1>;
1158	1190	status = "disabled";
1159	1191	};
1160	1192
..	..	@@ -1170,19 +1202,19 @@
1170	1202	status = "disabled";
1171	1203	};
1172	1204
1173		- otp: otp@ff290000 {
	1205	+ otp: nvmem@ff290000 {
1174	1206	compatible = "rockchip,px30-otp";
1175	1207	reg = <0x0 0xff290000 0x0 0x4000>;
1176		- #address-cells = <1>;
1177		- #size-cells = <1>;
1178	1208	clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
1179	1209	<&cru PCLK_OTP_PHY>;
1180	1210	clock-names = "otp", "apb_pclk", "phy";
1181	1211	resets = <&cru SRST_OTP_PHY>;
1182		- reset-names = "otp_phy";
	1212	+ reset-names = "phy";
	1213	+ #address-cells = <1>;
	1214	+ #size-cells = <1>;
1183	1215
1184	1216	/* Data cells */
1185		- otp_id: id@7 {
	1217	+ cpu_id: id@7 {
1186	1218	reg = <0x07 0x10>;
1187	1219	};
1188	1220	cpu_leakage: cpu-leakage@17 {
..	..	@@ -1198,27 +1230,14 @@
1198	1230	compatible = "rockchip,px30-cru";
1199	1231	reg = <0x0 0xff2b0000 0x0 0x1000>;
1200	1232	rockchip,grf = <&grf>;
1201		- rockchip,boost = <&cpu_boost>;
1202	1233	#clock-cells = <1>;
1203	1234	#reset-cells = <1>;
	1235	+
	1236	+ assigned-clocks = <&cru PLL_NPLL>;
	1237	+ assigned-clock-rates = <1188000000>;
1204	1238	};
1205	1239
1206		- cpu_boost: cpu-boost@ff2b8000 {
1207		- compatible = "syscon";
1208		- reg = <0x0 0xff2b8000 0x0 0x1000>;
1209		- rockchip,boost-low-con0 = <0x1032>;
1210		- rockchip,boost-low-con1 = <0x1441>;
1211		- rockchip,boost-high-con0 = <0x1036>;
1212		- rockchip,boost-high-con1 = <0x1441>;
1213		- rockchip,boost-backup-pll = <1>;
1214		- rockchip,boost-backup-pll-usage = <0>;
1215		- rockchip,boost-switch-threshold = <0x249f00>;
1216		- rockchip,boost-statis-threshold = <0x100>;
1217		- rockchip,boost-statis-enable = <0>;
1218		- rockchip,boost-enable = <0>;
1219		- };
1220		-
1221		- pmucru: pmu-clock-controller@ff2bc000 {
	1240	+ pmucru: clock-controller@ff2bc000 {
1222	1241	compatible = "rockchip,px30-pmucru";
1223	1242	reg = <0x0 0xff2bc000 0x0 0x1000>;
1224	1243	rockchip,grf = <&grf>;
..	..	@@ -1247,9 +1266,8 @@
1247	1266	#size-cells = <1>;
1248	1267
1249	1268	u2phy: usb2-phy@100 {
1250		- compatible = "rockchip,px30-usb2phy",
1251		- "rockchip,rk3328-usb2phy";
1252		- reg = <0x100 0x10>;
	1269	+ compatible = "rockchip,px30-usb2phy";
	1270	+ reg = <0x100 0x20>;
1253	1271	clocks = <&pmucru SCLK_USBPHY_REF>;
1254	1272	clock-names = "phyclk";
1255	1273	#clock-cells = <0>;
..	..	@@ -1277,18 +1295,18 @@
1277	1295	};
1278	1296	};
1279	1297
1280		- video_phy: video-phy@ff2e0000 {
1281		- compatible = "rockchip,px30-video-phy";
	1298	+ video_phy: dsi_dphy: phy@ff2e0000 {
	1299	+ compatible = "rockchip,px30-dsi-dphy", "rockchip,px30-video-phy";
1282	1300	reg = <0x0 0xff2e0000 0x0 0x10000>,
1283	1301	<0x0 0xff450000 0x0 0x10000>;
	1302	+ reg-names = "phy", "host";
1284	1303	clocks = <&pmucru SCLK_MIPIDSIPHY_REF>,
1285	1304	<&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>;
1286		- clock-names = "ref", "pclk_phy", "pclk_host";
1287		- #clock-cells = <0>;
	1305	+ clock-names = "ref", "pclk", "pclk_host";
1288	1306	resets = <&cru SRST_MIPIDSIPHY_P>;
1289		- reset-names = "rst";
1290		- power-domains = <&power PX30_PD_VO>;
	1307	+ reset-names = "apb";
1291	1308	#phy-cells = <0>;
	1309	+ power-domains = <&power PX30_PD_VO>;
1292	1310	status = "disabled";
1293	1311	};
1294	1312
..	..	@@ -1309,14 +1327,13 @@
1309	1327	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1310	1328	clocks = <&cru HCLK_OTG>;
1311	1329	clock-names = "otg";
1312		- power-domains = <&power PX30_PD_USB>;
1313	1330	dr_mode = "otg";
1314	1331	g-np-tx-fifo-size = <16>;
1315	1332	g-rx-fifo-size = <280>;
1316	1333	g-tx-fifo-size = <256 128 128 64 32 16>;
1317		- g-use-dma;
1318	1334	phys = <&u2phy_otg>;
1319	1335	phy-names = "usb2-phy";
	1336	+ power-domains = <&power PX30_PD_USB>;
1320	1337	status = "disabled";
1321	1338	};
1322	1339
..	..	@@ -1326,9 +1343,9 @@
1326	1343	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1327	1344	clocks = <&cru HCLK_HOST>, <&u2phy>;
1328	1345	clock-names = "usbhost", "utmi";
1329		- power-domains = <&power PX30_PD_USB>;
1330	1346	phys = <&u2phy_host>;
1331	1347	phy-names = "usb";
	1348	+ power-domains = <&power PX30_PD_USB>;
1332	1349	status = "disabled";
1333	1350	};
1334	1351
..	..	@@ -1338,16 +1355,15 @@
1338	1355	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1339	1356	clocks = <&cru HCLK_HOST>, <&u2phy>;
1340	1357	clock-names = "usbhost", "utmi";
1341		- power-domains = <&power PX30_PD_USB>;
1342	1358	phys = <&u2phy_host>;
1343	1359	phy-names = "usb";
	1360	+ power-domains = <&power PX30_PD_USB>;
1344	1361	status = "disabled";
1345	1362	};
1346	1363
1347	1364	gmac: ethernet@ff360000 {
1348	1365	compatible = "rockchip,px30-gmac";
1349	1366	reg = <0x0 0xff360000 0x0 0x10000>;
1350		- rockchip,grf = <&grf>;
1351	1367	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1352	1368	interrupt-names = "macirq";
1353	1369	clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
..	..	@@ -1358,61 +1374,72 @@
1358	1374	"mac_clk_tx", "clk_mac_ref",
1359	1375	"clk_mac_refout", "aclk_mac",
1360	1376	"pclk_mac", "clk_mac_speed";
	1377	+ rockchip,grf = <&grf>;
1361	1378	phy-mode = "rmii";
1362	1379	pinctrl-names = "default";
1363	1380	pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
	1381	+ power-domains = <&power PX30_PD_GMAC>;
1364	1382	resets = <&cru SRST_GMAC_A>;
1365	1383	reset-names = "stmmaceth";
1366		- power-domains = <&power PX30_PD_GMAC>;
1367	1384	status = "disabled";
1368	1385	};
1369	1386
1370	1387	sdmmc: dwmmc@ff370000 {
1371	1388	compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1372	1389	reg = <0x0 0xff370000 0x0 0x4000>;
1373		- max-frequency = <150000000>;
	1390	+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1374	1391	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
1375	1392	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1376		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1377		- assigned-clocks = <&cru SCLK_SDMMC>;
1378		- assigned-clock-parents = <&cru SCLK_SDMMC_DIV50>;
1379		- power-domains = <&power PX30_PD_SDCARD>;
	1393	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	1394	+ bus-width = <4>;
1380	1395	fifo-depth = <0x100>;
1381		- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	1396	+ max-frequency = <150000000>;
1382	1397	pinctrl-names = "default";
1383	1398	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
	1399	+ power-domains = <&power PX30_PD_SDCARD>;
1384	1400	status = "disabled";
1385	1401	};
1386	1402
1387	1403	sdio: dwmmc@ff380000 {
1388	1404	compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1389	1405	reg = <0x0 0xff380000 0x0 0x4000>;
1390		- max-frequency = <150000000>;
	1406	+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1391	1407	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1392	1408	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1393		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1394		- assigned-clocks = <&cru SCLK_SDIO>;
1395		- assigned-clock-parents = <&cru SCLK_SDIO_DIV50>;
1396		- power-domains = <&power PX30_PD_MMC_NAND>;
	1409	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	1410	+ bus-width = <4>;
1397	1411	fifo-depth = <0x100>;
1398		- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	1412	+ max-frequency = <150000000>;
1399	1413	pinctrl-names = "default";
1400	1414	pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
	1415	+ power-domains = <&power PX30_PD_MMC_NAND>;
1401	1416	status = "disabled";
1402	1417	};
1403	1418
1404	1419	emmc: dwmmc@ff390000 {
1405	1420	compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1406	1421	reg = <0x0 0xff390000 0x0 0x4000>;
1407		- max-frequency = <150000000>;
	1422	+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1408	1423	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1409	1424	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1410		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1411		- assigned-clocks = <&cru SCLK_EMMC>;
1412		- assigned-clock-parents = <&cru SCLK_EMMC_DIV50>;
1413		- power-domains = <&power PX30_PD_MMC_NAND>;
	1425	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	1426	+ bus-width = <8>;
1414	1427	fifo-depth = <0x100>;
1415		- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	1428	+ max-frequency = <150000000>;
	1429	+ pinctrl-names = "default";
	1430	+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	1431	+ power-domains = <&power PX30_PD_MMC_NAND>;
	1432	+ status = "disabled";
	1433	+ };
	1434	+
	1435	+ sfc: spi@ff3a0000 {
	1436	+ compatible = "rockchip,sfc";
	1437	+ reg = <0x0 0xff3a0000 0x0 0x4000>;
	1438	+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	1439	+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
	1440	+ clock-names = "clk_sfc", "hclk_sfc";
	1441	+ assigned-clocks = <&cru SCLK_SFC>;
	1442	+ assigned-clock-rates = <100000000>;
1416	1443	status = "disabled";
1417	1444	};
1418	1445
..	..	@@ -1430,23 +1457,18 @@
1430	1457	};
1431	1458
1432	1459	gpu: gpu@ff400000 {
1433		- compatible = "arm,mali-bifrost";
	1460	+ compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1434	1461	reg = <0x0 0xff400000 0x0 0x4000>;
1435		-
1436	1462	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1437	1463	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1438	1464	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1439	1465	interrupt-names = "GPU", "MMU", "JOB";
1440		-
	1466	+ clocks = <&cru SCLK_GPU>;
	1467	+ #cooling-cells = <2>;
	1468	+ power-domains = <&power PX30_PD_GPU>;
	1469	+ operating-points-v2 = <&gpu_opp_table>;
1441	1470	upthreshold = <40>;
1442	1471	downdifferential = <10>;
1443		-
1444		- clocks = <&cru SCLK_GPU>;
1445		- clock-names = "clk_mali";
1446		- power-domains = <&power PX30_PD_GPU>;
1447		- #cooling-cells = <2>;
1448		- operating-points-v2 = <&gpu_opp_table>;
1449		-
1450	1472	status = "disabled";
1451	1473	power_model {
1452	1474	compatible = "arm,mali-simple-power-model";
..	..	@@ -1455,7 +1477,6 @@
1455	1477	ts = <32000 4700 (-80) 2>;
1456	1478	thermal-zone = "gpu-thermal";
1457	1479	};
1458		-
1459	1480	};
1460	1481
1461	1482	gpu_opp_table: gpu-opp-table {
..	..	@@ -1586,6 +1607,7 @@
1586	1607	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1587	1608	clock-names = "aclk", "iface";
1588	1609	power-domains = <&power PX30_PD_VPU>;
	1610	+ rockchip,shootdown-entire;
1589	1611	#iommu-cells = <0>;
1590	1612	status = "disabled";
1591	1613	};
..	..	@@ -1615,10 +1637,11 @@
1615	1637	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>;
1616	1638	clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
1617	1639	resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>,
1618		- <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>,
1619		- <&cru SRST_VPU_CORE>;
	1640	+ <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>,
	1641	+ <&cru SRST_VPU_CORE>;
1620	1642	reset-names = "shared_video_a", "shared_video_h",
1621		- "niu_a", "niu_h", "video_core";
	1643	+ "niu_a", "niu_h",
	1644	+ "video_core";
1622	1645	iommus = <&hevc_mmu>;
1623	1646	rockchip,srv = <&mpp_srv>;
1624	1647	rockchip,taskqueue-node = <0>;
..	..	@@ -1635,6 +1658,7 @@
1635	1658	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1636	1659	clock-names = "aclk", "iface";
1637	1660	power-domains = <&power PX30_PD_VPU>;
	1661	+ rockchip,shootdown-entire;
1638	1662	#iommu-cells = <0>;
1639	1663	status = "disabled";
1640	1664	};
..	..	@@ -1643,13 +1667,13 @@
1643	1667	compatible = "rockchip,px30-mipi-dsi";
1644	1668	reg = <0x0 0xff450000 0x0 0x10000>;
1645	1669	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1646		- clocks = <&cru PCLK_MIPI_DSI>, <&video_phy>;
1647		- clock-names = "pclk", "hs_clk";
	1670	+ clocks = <&cru PCLK_MIPI_DSI>;
	1671	+ clock-names = "pclk";
	1672	+ phys = <&video_phy>;
	1673	+ phy-names = "dphy";
	1674	+ power-domains = <&power PX30_PD_VO>;
1648	1675	resets = <&cru SRST_MIPIDSI_HOST_P>;
1649	1676	reset-names = "apb";
1650		- phys = <&video_phy>;
1651		- phy-names = "mipi_dphy";
1652		- power-domains = <&power PX30_PD_VO>;
1653	1677	rockchip,grf = <&grf>;
1654	1678	#address-cells = <1>;
1655	1679	#size-cells = <0>;
..	..	@@ -1679,29 +1703,31 @@
1679	1703
1680	1704	vopb: vop@ff460000 {
1681	1705	compatible = "rockchip,px30-vop-big";
1682		- reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>;
	1706	+ reg = <0x0 0xff460000 0x0 0x260>, <0x0 0xff460a00 0x0 0x400>;
1683	1707	rockchip,grf = <&grf>;
1684	1708	reg-names = "regs", "gamma_lut";
1685	1709	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1686	1710	clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1687	1711	<&cru HCLK_VOPB>;
1688	1712	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1689		- power-domains = <&power PX30_PD_VO>;
	1713	+ resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
	1714	+ reset-names = "axi", "ahb", "dclk";
1690	1715	iommus = <&vopb_mmu>;
	1716	+ power-domains = <&power PX30_PD_VO>;
1691	1717	status = "disabled";
1692	1718
1693	1719	vopb_out: port {
1694	1720	#address-cells = <1>;
1695	1721	#size-cells = <0>;
1696	1722
1697		- vopb_out_lvds: endpoint@0 {
	1723	+ vopb_out_dsi: endpoint@0 {
1698	1724	reg = <0>;
1699		- remote-endpoint = <&lvds_in_vopb>;
	1725	+ remote-endpoint = <&dsi_in_vopb>;
1700	1726	};
1701	1727
1702		- vopb_out_dsi: endpoint@1 {
	1728	+ vopb_out_lvds: endpoint@1 {
1703	1729	reg = <1>;
1704		- remote-endpoint = <&dsi_in_vopb>;
	1730	+ remote-endpoint = <&lvds_vopb_in>;
1705	1731	};
1706	1732
1707	1733	vopb_out_rgb: endpoint@2 {
..	..	@@ -1733,22 +1759,24 @@
1733	1759	clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1734	1760	<&cru HCLK_VOPL>;
1735	1761	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1736		- power-domains = <&power PX30_PD_VO>;
	1762	+ resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
	1763	+ reset-names = "axi", "ahb", "dclk";
1737	1764	iommus = <&vopl_mmu>;
	1765	+ power-domains = <&power PX30_PD_VO>;
1738	1766	status = "disabled";
1739	1767
1740	1768	vopl_out: port {
1741	1769	#address-cells = <1>;
1742	1770	#size-cells = <0>;
1743	1771
1744		- vopl_out_lvds: endpoint@0 {
	1772	+ vopl_out_dsi: endpoint@0 {
1745	1773	reg = <0>;
1746		- remote-endpoint = <&lvds_in_vopl>;
	1774	+ remote-endpoint = <&dsi_in_vopl>;
1747	1775	};
1748	1776
1749		- vopl_out_dsi: endpoint@1 {
	1777	+ vopl_out_lvds: endpoint@1 {
1750	1778	reg = <1>;
1751		- remote-endpoint = <&dsi_in_vopl>;
	1779	+ remote-endpoint = <&lvds_vopl_in>;
1752	1780	};
1753	1781
1754	1782	vopl_out_rgb: endpoint@2 {
..	..	@@ -1828,9 +1856,9 @@
1828	1856	reg = <0x0 0xff4a0000 0x0 0x8000>;
1829	1857	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1830	1858	clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>,
1831		- <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>;
	1859	+ <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>;
1832	1860	clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe",
1833		- "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx";
	1861	+ "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx";
1834	1862	resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>;
1835	1863	reset-names = "rst_isp", "rst_mipicsiphy";
1836	1864	power-domains = <&power PX30_PD_VI>;
..	..	@@ -1856,9 +1884,9 @@
1856	1884	<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1857	1885	interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
1858	1886	clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1859		- <&cru SCLK_ISP>, <&cru PCLK_ISP>;
	1887	+ <&cru SCLK_ISP>, <&cru PCLK_ISP>;
1860	1888	clock-names = "aclk_isp", "hclk_isp",
1861		- "clk_isp", "pclk_isp";
	1889	+ "clk_isp", "pclk_isp";
1862	1890	devfreq = <&dmc>;
1863	1891	power-domains = <&power PX30_PD_VI>;
1864	1892	iommus = <&isp_mmu>;
..	..	@@ -1999,11 +2027,11 @@
1999	2027	downdifferential = <20>;
2000	2028	system-status-freq = <
2001	2029	/system status freq(KHz)/
2002		- SYS_STATUS_NORMAL 528000
	2030	+ SYS_STATUS_NORMAL 666000
2003	2031	SYS_STATUS_REBOOT 450000
2004	2032	SYS_STATUS_SUSPEND 194000
2005	2033	SYS_STATUS_VIDEO_1080P 450000
2006		- SYS_STATUS_BOOST 528000
	2034	+ SYS_STATUS_BOOST 666000
2007	2035	SYS_STATUS_ISP 666000
2008	2036	SYS_STATUS_PERFORMANCE 1056000
2009	2037	>;
..	..	@@ -2073,14 +2101,6 @@
2073	2101	opp-microvolt-L2 = <950000>;
2074	2102	opp-microvolt-L3 = <950000>;
2075	2103	};
2076		- opp-528000000 {
2077		- opp-hz = /bits/ 64 <528000000>;
2078		- opp-microvolt = <975000>;
2079		- opp-microvolt-L0 = <975000>;
2080		- opp-microvolt-L1 = <975000>;
2081		- opp-microvolt-L2 = <950000>;
2082		- opp-microvolt-L3 = <950000>;
2083		- };
2084	2104	opp-666000000 {
2085	2105	opp-hz = /bits/ 64 <666000000>;
2086	2106	opp-microvolt = <1050000>;
..	..	@@ -2110,11 +2130,6 @@
2110	2130	opp-328000000 {
2111	2131	opp-hz = /bits/ 64 <328000000>;
2112	2132	opp-microvolt = <950000>;
2113		- };
2114		- opp-528000000 {
2115		- opp-hz = /bits/ 64 <528000000>;
2116		- opp-microvolt = <950000>;
2117		- status = "disabled";
2118	2133	};
2119	2134	opp-666000000 {
2120	2135	opp-hz = /bits/ 64 <666000000>;
..	..	@@ -2318,7 +2333,7 @@
2318	2333	};
2319	2334
2320	2335	tsadc {
2321		- tsadc_otp_gpio: tsadc-otp-gpio {
	2336	+ tsadc_otp_gpio: tsadc_otp_pin: tsadc-otp-pin {
2322	2337	rockchip,pins =
2323	2338	<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2324	2339	};
..	..	@@ -2344,11 +2359,6 @@
2344	2359	uart0_rts: uart0-rts {
2345	2360	rockchip,pins =
2346	2361	<0 RK_PB5 1 &pcfg_pull_none>;
2347		- };
2348		-
2349		- uart0_rts_gpio: uart0-rts-gpio {
2350		- rockchip,pins =
2351		- <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
2352	2362	};
2353	2363	};
2354	2364
..	..	@@ -2407,11 +2417,6 @@
2407	2417	rockchip,pins =
2408	2418	<0 RK_PC3 2 &pcfg_pull_none>;
2409	2419	};
2410		-
2411		- uart3m0_rts_gpio: uart3m0-rts-gpio {
2412		- rockchip,pins =
2413		- <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
2414		- };
2415	2420	};
2416	2421
2417	2422	uart3-m1 {
..	..	@@ -2430,15 +2435,9 @@
2430	2435	rockchip,pins =
2431	2436	<1 RK_PB5 2 &pcfg_pull_none>;
2432	2437	};
2433		-
2434		- uart3m1_rts_gpio: uart3m1-rts-gpio {
2435		- rockchip,pins =
2436		- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
2437		- };
2438	2438	};
2439	2439
2440	2440	uart4 {
2441		-
2442	2441	uart4_xfer: uart4-xfer {
2443	2442	rockchip,pins =
2444	2443	<1 RK_PD4 2 &pcfg_pull_up>,
..	..	@@ -2448,7 +2447,6 @@
2448	2447	uart4_cts: uart4-cts {
2449	2448	rockchip,pins =
2450	2449	<1 RK_PD6 2 &pcfg_pull_none>;
2451		-
2452	2450	};
2453	2451
2454	2452	uart4_rts: uart4-rts {
..	..	@@ -2458,7 +2456,6 @@
2458	2456	};
2459	2457
2460	2458	uart5 {
2461		-
2462	2459	uart5_xfer: uart5-xfer {
2463	2460	rockchip,pins =
2464	2461	<3 RK_PA2 4 &pcfg_pull_up>,
..	..	@@ -2468,7 +2465,6 @@
2468	2465	uart5_cts: uart5-cts {
2469	2466	rockchip,pins =
2470	2467	<3 RK_PA3 4 &pcfg_pull_none>;
2471		-
2472	2468	};
2473	2469
2474	2470	uart5_rts: uart5-rts {
..	..	@@ -2641,27 +2637,27 @@
2641	2637	i2s0 {
2642	2638	i2s0_8ch_mclk: i2s0-8ch-mclk {
2643	2639	rockchip,pins =
2644		- <3 RK_PC1 2 &pcfg_pull_none>;
	2640	+ <3 RK_PC1 2 &pcfg_pull_none_smt>;
2645	2641	};
2646	2642
2647	2643	i2s0_8ch_sclktx: i2s0-8ch-sclktx {
2648	2644	rockchip,pins =
2649		- <3 RK_PC3 2 &pcfg_pull_none>;
	2645	+ <3 RK_PC3 2 &pcfg_pull_none_smt>;
2650	2646	};
2651	2647
2652	2648	i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
2653	2649	rockchip,pins =
2654		- <3 RK_PB4 2 &pcfg_pull_none>;
	2650	+ <3 RK_PB4 2 &pcfg_pull_none_smt>;
2655	2651	};
2656	2652
2657	2653	i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
2658	2654	rockchip,pins =
2659		- <3 RK_PC2 2 &pcfg_pull_none>;
	2655	+ <3 RK_PC2 2 &pcfg_pull_none_smt>;
2660	2656	};
2661	2657
2662	2658	i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
2663	2659	rockchip,pins =
2664		- <3 RK_PB5 2 &pcfg_pull_none>;
	2660	+ <3 RK_PB5 2 &pcfg_pull_none_smt>;
2665	2661	};
2666	2662
2667	2663	i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
..	..	@@ -2708,17 +2704,17 @@
2708	2704	i2s1 {
2709	2705	i2s1_2ch_mclk: i2s1-2ch-mclk {
2710	2706	rockchip,pins =
2711		- <2 RK_PC3 1 &pcfg_pull_none>;
	2707	+ <2 RK_PC3 1 &pcfg_pull_none_smt>;
2712	2708	};
2713	2709
2714	2710	i2s1_2ch_sclk: i2s1-2ch-sclk {
2715	2711	rockchip,pins =
2716		- <2 RK_PC2 1 &pcfg_pull_none>;
	2712	+ <2 RK_PC2 1 &pcfg_pull_none_smt>;
2717	2713	};
2718	2714
2719	2715	i2s1_2ch_lrck: i2s1-2ch-lrck {
2720	2716	rockchip,pins =
2721		- <2 RK_PC1 1 &pcfg_pull_none>;
	2717	+ <2 RK_PC1 1 &pcfg_pull_none_smt>;
2722	2718	};
2723	2719
2724	2720	i2s1_2ch_sdi: i2s1-2ch-sdi {
..	..	@@ -2735,17 +2731,17 @@
2735	2731	i2s2 {
2736	2732	i2s2_2ch_mclk: i2s2-2ch-mclk {
2737	2733	rockchip,pins =
2738		- <3 RK_PA1 2 &pcfg_pull_none>;
	2734	+ <3 RK_PA1 2 &pcfg_pull_none_smt>;
2739	2735	};
2740	2736
2741	2737	i2s2_2ch_sclk: i2s2-2ch-sclk {
2742	2738	rockchip,pins =
2743		- <3 RK_PA2 2 &pcfg_pull_none>;
	2739	+ <3 RK_PA2 2 &pcfg_pull_none_smt>;
2744	2740	};
2745	2741
2746	2742	i2s2_2ch_lrck: i2s2-2ch-lrck {
2747	2743	rockchip,pins =
2748		- <3 RK_PA3 2 &pcfg_pull_none>;
	2744	+ <3 RK_PA3 2 &pcfg_pull_none_smt>;
2749	2745	};
2750	2746
2751	2747	i2s2_2ch_sdi: i2s2-2ch-sdi {
..	..	@@ -2787,16 +2783,6 @@
2787	2783	<1 RK_PD4 1 &pcfg_pull_up_8ma>,
2788	2784	<1 RK_PD5 1 &pcfg_pull_up_8ma>;
2789	2785	};
2790		-
2791		- sdmmc_gpio: sdmmc-gpio {
2792		- rockchip,pins =
2793		- <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2794		- <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2795		- <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2796		- <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2797		- <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2798		- <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
2799		- };
2800	2786	};
2801	2787
2802	2788	sdio {
..	..	@@ -2817,16 +2803,6 @@
2817	2803	<1 RK_PD0 1 &pcfg_pull_up>,
2818	2804	<1 RK_PD1 1 &pcfg_pull_up>;
2819	2805	};
2820		-
2821		- sdio_gpio: sdio-gpio {
2822		- rockchip,pins =
2823		- <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
2824		- <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
2825		- <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
2826		- <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
2827		- <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>,
2828		- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
2829		- };
2830	2806	};
2831	2807
2832	2808	emmc {
..	..	@@ -2838,11 +2814,6 @@
2838	2814	emmc_cmd: emmc-cmd {
2839	2815	rockchip,pins =
2840	2816	<1 RK_PB2 2 &pcfg_pull_up_8ma>;
2841		- };
2842		-
2843		- emmc_pwren: emmc-pwren {
2844		- rockchip,pins =
2845		- <1 RK_PB0 2 &pcfg_pull_none>;
2846	2817	};
2847	2818
2848	2819	emmc_rstnout: emmc-rstnout {
..	..	@@ -3055,24 +3026,15 @@
3055	3026	gmac {
3056	3027	rmii_pins: rmii-pins {
3057	3028	rockchip,pins =
3058		- /* mac_txen */
3059		- <2 RK_PA0 2 &pcfg_pull_none_12ma>,
3060		- /* mac_txd1 */
3061		- <2 RK_PA1 2 &pcfg_pull_none_12ma>,
3062		- /* mac_txd0 */
3063		- <2 RK_PA2 2 &pcfg_pull_none_12ma>,
3064		- /* mac_rxd0 */
3065		- <2 RK_PA3 2 &pcfg_pull_none>,
3066		- /* mac_rxd1 */
3067		- <2 RK_PA4 2 &pcfg_pull_none>,
3068		- /* mac_rxer */
3069		- <2 RK_PA5 2 &pcfg_pull_none>,
3070		- /* mac_rxdv */
3071		- <2 RK_PA6 2 &pcfg_pull_none>,
3072		- /* mac_mdio */
3073		- <2 RK_PA7 2 &pcfg_pull_none>,
3074		- /* mac_mdc */
3075		- <2 RK_PB1 2 &pcfg_pull_none>;
	3029	+ <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
	3030	+ <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
	3031	+ <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
	3032	+ <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
	3033	+ <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
	3034	+ <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
	3035	+ <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
	3036	+ <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
	3037	+ <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
3076	3038	};
3077	3039
3078	3040	mac_refclk_12ma: mac-refclk-12ma {
..	..	@@ -3088,75 +3050,78 @@
3088	3050
3089	3051	cif-m0 {
3090	3052	cif_clkout_m0: cif-clkout-m0 {
3091		- rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none_12ma>;/* cif_clkout */
	3053	+ rockchip,pins =
	3054	+ <2 RK_PB3 1 &pcfg_pull_none_12ma>;/* cif_clkout */
3092	3055	};
3093	3056
3094	3057	dvp_d2d9_m0: dvp-d2d9-m0 {
3095	3058	rockchip,pins =
3096		- <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */
3097		- <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */
3098		- <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */
3099		- <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */
3100		- <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */
3101		- <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */
3102		- <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */
3103		- <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */
3104		- <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */
3105		- <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */
3106		- <2 RK_PB2 1 &pcfg_pull_none>,/* cif_clkin */
3107		- <2 RK_PB3 1 &pcfg_pull_none>;/* cif_clkout */
	3059	+ <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
	3060	+ <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
	3061	+ <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
	3062	+ <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
	3063	+ <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
	3064	+ <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
	3065	+ <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
	3066	+ <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
	3067	+ <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
	3068	+ <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
	3069	+ <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
	3070	+ <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
3108	3071	};
3109	3072
3110	3073	dvp_d0d1_m0: dvp-d0d1-m0 {
3111	3074	rockchip,pins =
3112		- <2 RK_PB4 1 &pcfg_pull_none>,/* cif_data0 */
3113		- <2 RK_PB6 1 &pcfg_pull_none>;/* cif_data1 */
	3075	+ <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
	3076	+ <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
3114	3077	};
3115	3078
3116	3079	dvp_d10d11_m0:d10-d11-m0 {
3117	3080	rockchip,pins =
3118		- <2 RK_PB7 1 &pcfg_pull_none>,/* cif_data10 */
3119		- <2 RK_PC0 1 &pcfg_pull_none>;/* cif_data11 */
	3081	+ <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
	3082	+ <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
3120	3083	};
3121	3084	};
3122	3085
3123	3086	cif-m1 {
3124	3087	cif_clkout_m1: cif-clkout-m1 {
3125		- rockchip,pins = <3 RK_PD0 3 &pcfg_pull_none>;/* cif_clkout */
	3088	+ rockchip,pins =
	3089	+ <3 RK_PD0 3 &pcfg_pull_none>;
3126	3090	};
3127	3091
3128	3092	dvp_d2d9_m1: dvp-d2d9-m1 {
3129	3093	rockchip,pins =
3130		- <3 RK_PA3 3 &pcfg_pull_none>,/* cif_data2 */
3131		- <3 RK_PA5 3 &pcfg_pull_none>,/* cif_data3 */
3132		- <3 RK_PA7 3 &pcfg_pull_none>,/* cif_data4 */
3133		- <3 RK_PB0 3 &pcfg_pull_none>,/* cif_data5 */
3134		- <3 RK_PB1 3 &pcfg_pull_none>,/* cif_data6 */
3135		- <3 RK_PB4 3 &pcfg_pull_none>,/* cif_data7 */
3136		- <3 RK_PB6 3 &pcfg_pull_none>,/* cif_data8 */
3137		- <3 RK_PB7 3 &pcfg_pull_none>,/* cif_data9 */
3138		- <3 RK_PD1 3 &pcfg_pull_none>,/* cif_sync */
3139		- <3 RK_PD2 3 &pcfg_pull_none>,/* cif_href */
3140		- <3 RK_PD3 3 &pcfg_pull_none>,/* cif_clkin */
3141		- <3 RK_PD0 3 &pcfg_pull_none>;/* cif_clkout */
	3094	+ <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
	3095	+ <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
	3096	+ <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
	3097	+ <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
	3098	+ <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
	3099	+ <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
	3100	+ <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
	3101	+ <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
	3102	+ <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
	3103	+ <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
	3104	+ <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
	3105	+ <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
3142	3106	};
3143	3107
3144	3108	dvp_d0d1_m1: dvp-d0d1-m1 {
3145	3109	rockchip,pins =
3146		- <3 RK_PA1 3 &pcfg_pull_none>,/* cif_data0 */
3147		- <3 RK_PA2 3 &pcfg_pull_none>;/* cif_data1 */
	3110	+ <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
	3111	+ <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
3148	3112	};
3149	3113
3150	3114	dvp_d10d11_m1:d10-d11-m1 {
3151	3115	rockchip,pins =
3152		- <3 RK_PC6 3 &pcfg_pull_none>,/* cif_data10 */
3153		- <3 RK_PC7 3 &pcfg_pull_none>;/* cif_data11 */
	3116	+ <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
	3117	+ <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
3154	3118	};
3155	3119	};
3156	3120
3157	3121	isp {
3158	3122	isp_prelight: isp-prelight {
3159		- rockchip,pins = <3 RK_PD1 4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */
	3123	+ rockchip,pins =
	3124	+ <3 RK_PD1 4 &pcfg_pull_none>;
3160	3125	};
3161	3126	};
3162	3127	};