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2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6 
 kernel/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
....@@ -2,7 +2,7 @@
22 /*
33  * Device Tree Source for the Draak board
44  *
5
- * Copyright (C) 2016 Renesas Electronics Corp.
5
+ * Copyright (C) 2016-2018 Renesas Electronics Corp.
66  * Copyright (C) 2017 Glider bvba
77  */
88 
....@@ -19,9 +19,109 @@
1919 		ethernet0 = &avb;
2020 	};
2121 
22
+	backlight: backlight {
23
+		compatible = "pwm-backlight";
24
+		pwms = <&pwm1 0 50000>;
25
+
26
+		brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
27
+		default-brightness-level = <10>;
28
+
29
+		power-supply = <&reg_12p0v>;
30
+		enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
31
+	};
32
+
2233 	chosen {
23
-		bootargs = "ignore_loglevel";
34
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
2435 		stdout-path = "serial0:115200n8";
36
+	};
37
+
38
+	composite-in {
39
+		compatible = "composite-video-connector";
40
+
41
+		port {
42
+			composite_con_in: endpoint {
43
+				remote-endpoint = <&adv7180_in>;
44
+			};
45
+		};
46
+	};
47
+
48
+	hdmi-in {
49
+		compatible = "hdmi-connector";
50
+		type = "a";
51
+
52
+		port {
53
+			hdmi_con_in: endpoint {
54
+				remote-endpoint = <&adv7612_in>;
55
+			};
56
+		};
57
+	};
58
+
59
+	hdmi-out {
60
+		compatible = "hdmi-connector";
61
+		type = "a";
62
+
63
+		port {
64
+			hdmi_con_out: endpoint {
65
+				remote-endpoint = <&adv7511_out>;
66
+			};
67
+		};
68
+	};
69
+
70
+	lvds-decoder {
71
+		compatible = "thine,thc63lvd1024";
72
+		vcc-supply = <&reg_3p3v>;
73
+
74
+		ports {
75
+			#address-cells = <1>;
76
+			#size-cells = <0>;
77
+
78
+			port@0 {
79
+				reg = <0>;
80
+				thc63lvd1024_in: endpoint {
81
+					remote-endpoint = <&lvds0_out>;
82
+				};
83
+			};
84
+
85
+			port@2 {
86
+				reg = <2>;
87
+				thc63lvd1024_out: endpoint {
88
+					remote-endpoint = <&adv7511_in>;
89
+				};
90
+			};
91
+		};
92
+	};
93
+
94
+	memory@48000000 {
95
+		device_type = "memory";
96
+		/* first 128MB is reserved for secure area. */
97
+		reg = <0x0 0x48000000 0x0 0x18000000>;
98
+	};
99
+
100
+	reg_1p8v: regulator-1p8v {
101
+		compatible = "regulator-fixed";
102
+		regulator-name = "fixed-1.8V";
103
+		regulator-min-microvolt = <1800000>;
104
+		regulator-max-microvolt = <1800000>;
105
+		regulator-boot-on;
106
+		regulator-always-on;
107
+	};
108
+
109
+	reg_3p3v: regulator-3p3v {
110
+		compatible = "regulator-fixed";
111
+		regulator-name = "fixed-3.3V";
112
+		regulator-min-microvolt = <3300000>;
113
+		regulator-max-microvolt = <3300000>;
114
+		regulator-boot-on;
115
+		regulator-always-on;
116
+	};
117
+
118
+	reg_12p0v: regulator-12p0v {
119
+		compatible = "regulator-fixed";
120
+		regulator-name = "D12.0V";
121
+		regulator-min-microvolt = <12000000>;
122
+		regulator-max-microvolt = <12000000>;
123
+		regulator-boot-on;
124
+		regulator-always-on;
25125 	};
26126 
27127 	vga {
....@@ -56,51 +156,6 @@
56156 		};
57157 	};
58158 
59
-	composite-in {
60
-		compatible = "composite-video-connector";
61
-
62
-		port {
63
-			composite_con_in: endpoint {
64
-				remote-endpoint = <&adv7180_in>;
65
-			};
66
-		};
67
-	};
68
-
69
-	hdmi-in {
70
-		compatible = "hdmi-connector";
71
-		type = "a";
72
-
73
-		port {
74
-			hdmi_con_in: endpoint {
75
-				remote-endpoint = <&adv7612_in>;
76
-			};
77
-		};
78
-	};
79
-
80
-	memory@48000000 {
81
-		device_type = "memory";
82
-		/* first 128MB is reserved for secure area. */
83
-		reg = <0x0 0x48000000 0x0 0x18000000>;
84
-	};
85
-
86
-	reg_1p8v: regulator0 {
87
-		compatible = "regulator-fixed";
88
-		regulator-name = "fixed-1.8V";
89
-		regulator-min-microvolt = <1800000>;
90
-		regulator-max-microvolt = <1800000>;
91
-		regulator-boot-on;
92
-		regulator-always-on;
93
-	};
94
-
95
-	reg_3p3v: regulator1 {
96
-		compatible = "regulator-fixed";
97
-		regulator-name = "fixed-3.3V";
98
-		regulator-min-microvolt = <3300000>;
99
-		regulator-max-microvolt = <3300000>;
100
-		regulator-boot-on;
101
-		regulator-always-on;
102
-	};
103
-
104159 	x12_clk: x12 {
105160 		compatible = "fixed-clock";
106161 		#clock-cells = <0>;
....@@ -108,16 +163,244 @@
108163 	};
109164 };
110165 
166
+&avb {
167
+	pinctrl-0 = <&avb0_pins>;
168
+	pinctrl-names = "default";
169
+	renesas,no-ether-link;
170
+	phy-handle = <&phy0>;
171
+	status = "okay";
172
+
173
+	phy0: ethernet-phy@0 {
174
+		rxc-skew-ps = <1500>;
175
+		reg = <0>;
176
+		interrupt-parent = <&gpio5>;
177
+		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
178
+		/*
179
+		 * TX clock internal delay mode is required for reliable
180
+		 * 1Gbps communication using the KSZ9031RNX phy present on
181
+		 * the Draak board, however, TX clock internal delay mode
182
+		 * isn't supported on r8a77995.  Thus, limit speed to
183
+		 * 100Mbps for reliable communication.
184
+		 */
185
+		max-speed = <100>;
186
+	};
187
+};
188
+
189
+&can0 {
190
+	pinctrl-0 = <&can0_pins>;
191
+	pinctrl-names = "default";
192
+	status = "okay";
193
+};
194
+
195
+&can1 {
196
+	pinctrl-0 = <&can1_pins>;
197
+	pinctrl-names = "default";
198
+	status = "okay";
199
+};
200
+
201
+&du {
202
+	pinctrl-0 = <&du_pins>;
203
+	pinctrl-names = "default";
204
+	status = "okay";
205
+
206
+	clocks = <&cpg CPG_MOD 724>,
207
+		 <&cpg CPG_MOD 723>,
208
+		 <&x12_clk>;
209
+	clock-names = "du.0", "du.1", "dclkin.0";
210
+
211
+	ports {
212
+		port@0 {
213
+			endpoint {
214
+				remote-endpoint = <&adv7123_in>;
215
+			};
216
+		};
217
+	};
218
+};
219
+
220
+&ehci0 {
221
+	dr_mode = "host";
222
+	status = "okay";
223
+};
224
+
111225 &extal_clk {
112226 	clock-frequency = <48000000>;
113227 };
114228 
229
+&hsusb {
230
+	dr_mode = "host";
231
+	status = "okay";
232
+};
233
+
234
+&i2c0 {
235
+	pinctrl-0 = <&i2c0_pins>;
236
+	pinctrl-names = "default";
237
+	status = "okay";
238
+
239
+	composite-in@20 {
240
+		compatible = "adi,adv7180cp";
241
+		reg = <0x20>;
242
+
243
+		ports {
244
+			#address-cells = <1>;
245
+			#size-cells = <0>;
246
+
247
+			port@0 {
248
+				reg = <0>;
249
+				adv7180_in: endpoint {
250
+					remote-endpoint = <&composite_con_in>;
251
+				};
252
+			};
253
+
254
+			port@3 {
255
+				reg = <3>;
256
+
257
+				/*
258
+				 * The VIN4 video input path is shared between
259
+				 * CVBS and HDMI inputs through SW[49-53]
260
+				 * switches.
261
+				 *
262
+				 * CVBS is the default selection, link it to
263
+				 * VIN4 here.
264
+				 */
265
+				adv7180_out: endpoint {
266
+					remote-endpoint = <&vin4_in>;
267
+				};
268
+			};
269
+		};
270
+
271
+	};
272
+
273
+	hdmi-encoder@39 {
274
+		compatible = "adi,adv7511w";
275
+		reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
276
+		reg-names = "main", "edid", "cec", "packet";
277
+		interrupt-parent = <&gpio1>;
278
+		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
279
+
280
+		adi,input-depth = <8>;
281
+		adi,input-colorspace = "rgb";
282
+		adi,input-clock = "1x";
283
+
284
+		ports {
285
+			#address-cells = <1>;
286
+			#size-cells = <0>;
287
+
288
+			port@0 {
289
+				reg = <0>;
290
+				adv7511_in: endpoint {
291
+					remote-endpoint = <&thc63lvd1024_out>;
292
+				};
293
+			};
294
+
295
+			port@1 {
296
+				reg = <1>;
297
+				adv7511_out: endpoint {
298
+					remote-endpoint = <&hdmi_con_out>;
299
+				};
300
+			};
301
+		};
302
+	};
303
+
304
+	hdmi-decoder@4c {
305
+		compatible = "adi,adv7612";
306
+		reg = <0x4c>;
307
+		default-input = <0>;
308
+
309
+		ports {
310
+			#address-cells = <1>;
311
+			#size-cells = <0>;
312
+
313
+			port@0 {
314
+				reg = <0>;
315
+
316
+				adv7612_in: endpoint {
317
+					remote-endpoint = <&hdmi_con_in>;
318
+				};
319
+			};
320
+
321
+			port@2 {
322
+				reg = <2>;
323
+
324
+				/*
325
+				 * The VIN4 video input path is shared between
326
+				 * CVBS and HDMI inputs through SW[49-53]
327
+				 * switches.
328
+				 *
329
+				 * CVBS is the default selection, leave HDMI
330
+				 * not connected here.
331
+				 */
332
+				adv7612_out: endpoint {
333
+					pclk-sample = <0>;
334
+					hsync-active = <0>;
335
+					vsync-active = <0>;
336
+				};
337
+			};
338
+		};
339
+	};
340
+
341
+	eeprom@50 {
342
+		compatible = "rohm,br24t01", "atmel,24c01";
343
+		reg = <0x50>;
344
+		pagesize = <8>;
345
+	};
346
+};
347
+
348
+&i2c1 {
349
+	pinctrl-0 = <&i2c1_pins>;
350
+	pinctrl-names = "default";
351
+	status = "okay";
352
+};
353
+
354
+&lvds0 {
355
+	status = "okay";
356
+
357
+	clocks = <&cpg CPG_MOD 727>,
358
+		 <&x12_clk>,
359
+		 <&extal_clk>;
360
+	clock-names = "fck", "dclkin.0", "extal";
361
+
362
+	ports {
363
+		port@1 {
364
+			lvds0_out: endpoint {
365
+				remote-endpoint = <&thc63lvd1024_in>;
366
+			};
367
+		};
368
+	};
369
+};
370
+
371
+&lvds1 {
372
+	/*
373
+	 * Even though the LVDS1 output is not connected, the encoder must be
374
+	 * enabled to supply a pixel clock to the DU for the DPAD output when
375
+	 * LVDS0 is in use.
376
+	 */
377
+	status = "okay";
378
+
379
+	clocks = <&cpg CPG_MOD 727>,
380
+		 <&x12_clk>,
381
+		 <&extal_clk>;
382
+	clock-names = "fck", "dclkin.0", "extal";
383
+};
384
+
385
+&ohci0 {
386
+	dr_mode = "host";
387
+	status = "okay";
388
+};
389
+
115390 &pfc {
116391 	avb0_pins: avb {
117
-		mux {
118
-			groups = "avb0_link", "avb0_mdio", "avb0_mii";
119
-			function = "avb0";
120
-		};
392
+		groups = "avb0_link", "avb0_mdio", "avb0_mii";
393
+		function = "avb0";
394
+	};
395
+
396
+	can0_pins: can0 {
397
+		groups = "can0_data_a";
398
+		function = "can0";
399
+	};
400
+
401
+	can1_pins: can1 {
402
+		groups = "can1_data_a";
403
+		function = "can1";
121404 	};
122405 
123406 	du_pins: du {
....@@ -173,136 +456,23 @@
173456 	};
174457 };
175458 
176
-&i2c0 {
177
-	pinctrl-0 = <&i2c0_pins>;
459
+&pwm0 {
460
+	pinctrl-0 = <&pwm0_pins>;
178461 	pinctrl-names = "default";
462
+
179463 	status = "okay";
180
-
181
-	eeprom@50 {
182
-		compatible = "rohm,br24t01", "atmel,24c01";
183
-		reg = <0x50>;
184
-		pagesize = <8>;
185
-	};
186
-
187
-	composite-in@20 {
188
-		compatible = "adi,adv7180cp";
189
-		reg = <0x20>;
190
-
191
-		ports {
192
-			#address-cells = <1>;
193
-			#size-cells = <0>;
194
-
195
-			port@0 {
196
-				reg = <0>;
197
-				adv7180_in: endpoint {
198
-					remote-endpoint = <&composite_con_in>;
199
-				};
200
-			};
201
-
202
-			port@3 {
203
-				reg = <3>;
204
-
205
-				/*
206
-				 * The VIN4 video input path is shared between
207
-				 * CVBS and HDMI inputs through SW[49-53]
208
-				 * switches.
209
-				 *
210
-				 * CVBS is the default selection, link it to
211
-				 * VIN4 here.
212
-				 */
213
-				adv7180_out: endpoint {
214
-					remote-endpoint = <&vin4_in>;
215
-				};
216
-			};
217
-		};
218
-
219
-	};
220
-
221
-	hdmi-decoder@4c {
222
-		compatible = "adi,adv7612";
223
-		reg = <0x4c>;
224
-		default-input = <0>;
225
-
226
-		ports {
227
-			#address-cells = <1>;
228
-			#size-cells = <0>;
229
-
230
-			port@0 {
231
-				reg = <0>;
232
-
233
-				adv7612_in: endpoint {
234
-					remote-endpoint = <&hdmi_con_in>;
235
-				};
236
-			};
237
-
238
-			port@2 {
239
-				reg = <2>;
240
-
241
-				/*
242
-				 * The VIN4 video input path is shared between
243
-				 * CVBS and HDMI inputs through SW[49-53]
244
-				 * switches.
245
-				 *
246
-				 * CVBS is the default selection, leave HDMI
247
-				 * not connected here.
248
-				 */
249
-				adv7612_out: endpoint {
250
-					pclk-sample = <0>;
251
-					hsync-active = <0>;
252
-					vsync-active = <0>;
253
-				};
254
-			};
255
-		};
256
-	};
257464 };
258465 
259
-&i2c1 {
260
-	pinctrl-0 = <&i2c1_pins>;
466
+&pwm1 {
467
+	pinctrl-0 = <&pwm1_pins>;
261468 	pinctrl-names = "default";
469
+
262470 	status = "okay";
263471 };
264472 
265
-&du {
266
-	pinctrl-0 = <&du_pins>;
267
-	pinctrl-names = "default";
473
+&rwdt {
474
+	timeout-sec = <60>;
268475 	status = "okay";
269
-
270
-	clocks = <&cpg CPG_MOD 724>,
271
-		 <&cpg CPG_MOD 723>,
272
-		 <&x12_clk>;
273
-	clock-names = "du.0", "du.1", "dclkin.0";
274
-
275
-	ports {
276
-		port@0 {
277
-			endpoint {
278
-				remote-endpoint = <&adv7123_in>;
279
-			};
280
-		};
281
-	};
282
-};
283
-
284
-&ehci0 {
285
-	status = "okay";
286
-};
287
-
288
-&ohci0 {
289
-	status = "okay";
290
-};
291
-
292
-&avb {
293
-	pinctrl-0 = <&avb0_pins>;
294
-	pinctrl-names = "default";
295
-	renesas,no-ether-link;
296
-	phy-handle = <&phy0>;
297
-	phy-mode = "rgmii-txid";
298
-	status = "okay";
299
-
300
-	phy0: ethernet-phy@0 {
301
-		rxc-skew-ps = <1500>;
302
-		reg = <0>;
303
-		interrupt-parent = <&gpio5>;
304
-		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
305
-	};
306476 };
307477 
308478 &scif2 {
....@@ -330,25 +500,7 @@
330500 	pinctrl-0 = <&usb0_pins>;
331501 	pinctrl-names = "default";
332502 
333
-	status = "okay";
334
-};
335
-
336
-&pwm0 {
337
-	pinctrl-0 = <&pwm0_pins>;
338
-	pinctrl-names = "default";
339
-
340
-	status = "okay";
341
-};
342
-
343
-&pwm1 {
344
-	pinctrl-0 = <&pwm1_pins>;
345
-	pinctrl-names = "default";
346
-
347
-	status = "okay";
348
-};
349
-
350
-&rwdt {
351
-	timeout-sec = <60>;
503
+	renesas,no-otg-pins;
352504 	status = "okay";
353505 };
354506 
....@@ -359,12 +511,7 @@
359511 	status = "okay";
360512 
361513 	ports {
362
-		#address-cells = <1>;
363
-		#size-cells = <0>;
364
-
365
-		port@0 {
366
-			reg = <0>;
367
-
514
+		port {
368515 			vin4_in: endpoint {
369516 				remote-endpoint = <&adv7180_out>;
370517 			};