forked from ~ljy/RK356X_SDK_RELEASE
kernel/arch/arm/mm/cache-v7.S
.. .. @@ -1,12 +1,9 @@ 1 1 2 /* 2 3 * linux/arch/arm/mm/cache-v7.S 3 4 * 4 5 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 6 * Copyright (C) 2005 ARM Ltd. 6 7 8 9 10 7 * 11 8 * This is the "shell" of the ARMv7 processor support. 12 9 */ .. .. @@ -19,6 +16,14 @@ 19 16 20 17 #include "proc-macros.S" 21 18 19 20 21 22 23 24 25 26 22 27 /* 23 28 * The secondary kernel init calls v7_flush_dcache_all before it enables 24 29 * the L1; however, the L1 comes out of reset in an undefined state, so .. .. @@ -130,13 +135,13 @@ 130 135 and r1, r1, #7 @ mask of the bits for current cache only 131 136 cmp r1, #2 @ see what cache we have at this level 132 137 blt skip @ skip if no cache, or just i-cache 133 138 134 139 save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic 135 140 #endif 136 141 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 137 142 isb @ isb to sych the new cssr&csidr 138 143 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 139 144 140 145 restore_irqs_notrace r9 141 146 #endif 142 147 and r2, r1, #7 @ extract the length of the cache lines .. .. @@ -163,6 +168,9 @@ 163 168 skip: 164 169 add r10, r10, #2 @ increment cache number 165 170 cmp r3, r10 171 172 173 166 174 bgt flush_levels 167 175 finished: 168 176 mov r10, #0 @ switch back to cache level 0 .. .. @@ -284,7 +292,12 @@ 284 292 cmp r12, r1 285 293 blo 1b 286 294 dsb ishst 295 296 297 298 287 299 icache_line_size r2, r3 300 288 301 sub r3, r2, #1 289 302 bic r12, r0, r3 290 303 2:
