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2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6 
 kernel/arch/arm/mach-tegra/reset-handler.S
....@@ -1,17 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3
- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
154  */
165 
176 #include <linux/init.h>
....@@ -20,6 +9,7 @@
209 #include <soc/tegra/flowctrl.h>
2110 #include <soc/tegra/fuse.h>
2211 
12
+#include <asm/assembler.h>
2313 #include <asm/asm-offsets.h>
2414 #include <asm/cache.h>
2515 
....@@ -28,8 +18,6 @@
2818 #include "sleep.h"
2919 
3020 #define PMC_SCRATCH41	0x140
31
-
32
-#define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
3321 
3422 #ifdef CONFIG_PM_SLEEP
3523 /*
....@@ -78,6 +66,7 @@
7866 	orr	r1, r1, #1
7967 	str	r1, [r0]
8068 #endif
69
+	bl	tegra_resume_trusted_foundations
8170 
8271 #ifdef CONFIG_CACHE_L2X0
8372 	/* L2 cache resume & re-enable */
....@@ -90,6 +79,35 @@
9079 
9180 	b	cpu_resume
9281 ENDPROC(tegra_resume)
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+
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+/*
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+ *	tegra_resume_trusted_foundations
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+ *
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+ *	  Trusted Foundations firmware initialization.
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+ *
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+ *	Doesn't return if firmware presents.
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+ *	Corrupted registers: r1, r2
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+ */
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+ENTRY(tegra_resume_trusted_foundations)
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+	/* Check whether Trusted Foundations firmware presents. */
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+	mov32	r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
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+	ldr	r1, =__tegra_cpu_reset_handler_data_offset + \
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+							RESET_DATA(TF_PRESENT)
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+	ldr	r1, [r2, r1]
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+	cmp	r1, #0
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+	reteq	lr
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+
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+ .arch_extension sec
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+	/*
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+	 * First call after suspend wakes firmware. No arguments required
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+	 * for some firmware versions. Downstream kernel of ASUS TF300T uses
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+	 * r0=3 for the wake-up notification.
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+	 */
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+	mov	r0, #3
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+	smc	#0
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+
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+	b	cpu_resume
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+ENDPROC(tegra_resume_trusted_foundations)
93111 #endif
94112 
95113 	.align L1_CACHE_SHIFT
....@@ -115,12 +133,19 @@
115133  *       must be position-independent.
116134  */
117135 
136
+	.arm
118137 	.align L1_CACHE_SHIFT
119138 ENTRY(__tegra_cpu_reset_handler)
120139 
121140 	cpsid	aif, 0x13			@ SVC mode, interrupts disabled
122141 
123142 	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
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+
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+	adr	r12, __tegra_cpu_reset_handler_data
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+	ldr	r5, [r12, #RESET_DATA(TF_PRESENT)]
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+	cmp	r5, #0
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+	bne	after_errata
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+
124149 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
125150 t20_check:
126151 	cmp	r6, #TEGRA20
....@@ -155,25 +180,12 @@
155180 	and	r10, r10, #0x3			@ R10 = CPU number
156181 	mov	r11, #1
157182 	mov	r11, r11, lsl r10  		@ R11 = CPU mask
158
-	adr	r12, __tegra_cpu_reset_handler_data
159183 
160184 #ifdef CONFIG_SMP
161185 	/* Does the OS know about this CPU? */
162186 	ldr	r7, [r12, #RESET_DATA(MASK_PRESENT)]
163187 	tst	r7, r11 			@ if !present
164188 	bleq	__die				@ CPU not present (to OS)
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-#endif
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-
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-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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-	/* Are we on Tegra20? */
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-	cmp	r6, #TEGRA20
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-	bne	1f
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-	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
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-	mov32	r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
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-	mov	r0, #CPU_NOT_RESETTABLE
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-	cmp	r10, #0
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-	strneb	r0, [r5, #__tegra20_cpu1_resettable_status_offset]
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-1:
177189 #endif
178190 
179191 	/* Waking up from LP1? */
....@@ -277,14 +289,13 @@
277289 	.align L1_CACHE_SHIFT
278290 	.type	__tegra_cpu_reset_handler_data, %object
279291 	.globl	__tegra_cpu_reset_handler_data
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-__tegra_cpu_reset_handler_data:
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-	.rept	TEGRA_RESET_DATA_SIZE
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-	.long	0
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-	.endr
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-	.globl	__tegra20_cpu1_resettable_status_offset
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-	.equ	__tegra20_cpu1_resettable_status_offset, \
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+	.globl	__tegra_cpu_reset_handler_data_offset
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+	.equ	__tegra_cpu_reset_handler_data_offset, \
286294 					. - __tegra_cpu_reset_handler_start
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-	.byte	0
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+__tegra_cpu_reset_handler_data:
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+	.rept   TEGRA_RESET_DATA_SIZE
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+	.long   0
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+	.endr
288299 	.align L1_CACHE_SHIFT
289300 
290301 ENTRY(__tegra_cpu_reset_handler_end)