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2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6

 kernel/arch/arm/mach-exynos/mcpm-exynos.c
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@@ -26,6 +26,7 @@
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 #define EXYNOS5420_USE_L2_COMMON_UP_STATE	BIT(30)
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 static void __iomem *ns_sram_base_addr __ro_after_init;
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+static bool secure_firmware __ro_after_init;
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 /*
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  * The common v7_exit_coherency_flush API could not be used because of the
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@@ -58,15 +59,16 @@
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 static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
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 {
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 	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
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+	bool state;
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 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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 	if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
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 		cluster >= EXYNOS5420_NR_CLUSTERS)
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 		return -EINVAL;
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-	if (!exynos_cpu_power_state(cpunr)) {
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-		exynos_cpu_power_up(cpunr);
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-
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+	state = exynos_cpu_power_state(cpunr);
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+	exynos_cpu_power_up(cpunr);
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+	if (!state && secure_firmware) {
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 		/*
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 		 * This assumes the cluster number of the big cores(Cortex A15)
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 		 * is 0 and the Little cores(Cortex A7) is 1.
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@@ -75,14 +77,25 @@
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 		 */
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 		if (cluster &&
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 		    cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
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+			unsigned int timeout = 16;
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+
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 			/*
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 			 * Before we reset the Little cores, we should wait
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 			 * the SPARE2 register is set to 1 because the init
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 			 * codes of the iROM will set the register after
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 			 * initialization.
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 			 */
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-			while (!pmu_raw_readl(S5P_PMU_SPARE2))
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+			while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
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+				timeout--;
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 				udelay(10);
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+			}
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+
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+			if (timeout == 0) {
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+				pr_err("cpu %u cluster %u powerup failed\n",
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+				       cpu, cluster);
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+				exynos_cpu_power_down(cpunr);
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+				return -ETIMEDOUT;
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+			}
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 			pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
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 					EXYNOS_SWRESET);
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@@ -247,6 +260,8 @@
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 		return -ENOMEM;
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 	}
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+	secure_firmware = exynos_secure_firmware_available();
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+
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 	/*
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 	 * To increase the stability of KFC reset we need to program
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 	 * the PMU SPARE3 register