forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6 
 kernel/arch/arm/boot/dts/sun8i-a23-a33.dtsi
....@@ -42,8 +42,6 @@
4242  *     OTHER DEALINGS IN THE SOFTWARE.
4343  */
4444 
45
-#include "skeleton.dtsi"
46
-
4745 #include <dt-bindings/interrupt-controller/arm-gic.h>
4846 
4947 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
....@@ -51,13 +49,15 @@
5149 
5250 / {
5351 	interrupt-parent = <&gic>;
52
+	#address-cells = <1>;
53
+	#size-cells = <1>;
5454 
5555 	chosen {
5656 		#address-cells = <1>;
5757 		#size-cells = <1>;
5858 		ranges;
5959 
60
-		simplefb_lcd: framebuffer@0 {
60
+		simplefb_lcd: framebuffer-lcd0 {
6161 			compatible = "allwinner,simple-framebuffer",
6262 				     "simple-framebuffer";
6363 			allwinner,pipeline = "de_be0-lcd0";
....@@ -66,6 +66,12 @@
6666 				 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
6767 			status = "disabled";
6868 		};
69
+	};
70
+
71
+	de: display-engine {
72
+		/* compatible gets set in SoC specific dtsi file */
73
+		allwinner,pipelines = <&fe0>;
74
+		status = "disabled";
6975 	};
7076 
7177 	timer {
....@@ -118,7 +124,7 @@
118124 		};
119125 	};
120126 
121
-	soc@1c00000 {
127
+	soc {
122128 		compatible = "simple-bus";
123129 		#address-cells = <1>;
124130 		#size-cells = <1>;
....@@ -155,19 +161,58 @@
155161 			#dma-cells = <1>;
156162 		};
157163 
158
-		nfc: nand@1c03000 {
159
-			compatible = "allwinner,sun4i-a10-nand";
164
+		nfc: nand-controller@1c03000 {
165
+			compatible = "allwinner,sun8i-a23-nand-controller";
160166 			reg = <0x01c03000 0x1000>;
161167 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
162168 			clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
163169 			clock-names = "ahb", "mod";
164170 			resets = <&ccu RST_BUS_NAND>;
165171 			reset-names = "ahb";
172
+			dmas = <&dma 5>;
173
+			dma-names = "rxtx";
166174 			pinctrl-names = "default";
167
-			pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
175
+			pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
168176 			status = "disabled";
169177 			#address-cells = <1>;
170178 			#size-cells = <0>;
179
+		};
180
+
181
+		tcon0: lcd-controller@1c0c000 {
182
+			/* compatible gets set in SoC specific dtsi file */
183
+			reg = <0x01c0c000 0x1000>;
184
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
185
+			dmas = <&dma 12>;
186
+			clocks = <&ccu CLK_BUS_LCD>,
187
+				 <&ccu CLK_LCD_CH0>,
188
+				 <&ccu 13>;
189
+			clock-names = "ahb",
190
+				      "tcon-ch0",
191
+				      "lvds-alt";
192
+			clock-output-names = "tcon-pixel-clock";
193
+			#clock-cells = <0>;
194
+			resets = <&ccu RST_BUS_LCD>,
195
+				 <&ccu RST_BUS_LVDS>;
196
+			reset-names = "lcd",
197
+				      "lvds";
198
+			status = "disabled";
199
+
200
+			ports {
201
+				#address-cells = <1>;
202
+				#size-cells = <0>;
203
+
204
+				tcon0_in: port@0 {
205
+					reg = <0>;
206
+
207
+					tcon0_in_drc0: endpoint {
208
+						remote-endpoint = <&drc0_out_tcon0>;
209
+					};
210
+				};
211
+
212
+				tcon0_out: port@1 {
213
+					reg = <1>;
214
+				};
215
+			};
171216 		};
172217 
173218 		mmc0: mmc@1c0f000 {
....@@ -184,6 +229,8 @@
184229 			resets = <&ccu RST_BUS_MMC0>;
185230 			reset-names = "ahb";
186231 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
232
+			pinctrl-names = "default";
233
+			pinctrl-0 = <&mmc0_pins>;
187234 			status = "disabled";
188235 			#address-cells = <1>;
189236 			#size-cells = <0>;
....@@ -237,6 +284,7 @@
237284 			phys = <&usbphy 0>;
238285 			phy-names = "usb";
239286 			extcon = <&usbphy 0>;
287
+			dr_mode = "otg";
240288 			status = "disabled";
241289 		};
242290 
....@@ -298,22 +346,30 @@
298346 			#interrupt-cells = <3>;
299347 			#gpio-cells = <3>;
300348 
301
-			uart0_pins_a: uart0@0 {
302
-				pins = "PF2", "PF4";
303
-				function = "uart0";
349
+			i2c0_pins: i2c0-pins {
350
+				pins = "PH2", "PH3";
351
+				function = "i2c0";
304352 			};
305353 
306
-			uart1_pins_a: uart1@0 {
307
-				pins = "PG6", "PG7";
308
-				function = "uart1";
354
+			i2c1_pins: i2c1-pins {
355
+				pins = "PH4", "PH5";
356
+				function = "i2c1";
309357 			};
310358 
311
-			uart1_pins_cts_rts_a: uart1-cts-rts@0 {
312
-				pins = "PG8", "PG9";
313
-				function = "uart1";
359
+			i2c2_pins: i2c2-pins {
360
+				pins = "PE12", "PE13";
361
+				function = "i2c2";
314362 			};
315363 
316
-			mmc0_pins_a: mmc0@0 {
364
+			lcd_rgb666_pins: lcd-rgb666-pins {
365
+				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
366
+				       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
367
+				       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
368
+				       "PD24", "PD25", "PD26", "PD27";
369
+				function = "lcd0";
370
+			};
371
+
372
+			mmc0_pins: mmc0-pins {
317373 				pins = "PF0", "PF1", "PF2",
318374 				       "PF3", "PF4", "PF5";
319375 				function = "mmc0";
....@@ -321,7 +377,7 @@
321377 				bias-pull-up;
322378 			};
323379 
324
-			mmc1_pins_a: mmc1@0 {
380
+			mmc1_pg_pins: mmc1-pg-pins {
325381 				pins = "PG0", "PG1", "PG2",
326382 				       "PG3", "PG4", "PG5";
327383 				function = "mmc1";
....@@ -329,7 +385,7 @@
329385 				bias-pull-up;
330386 			};
331387 
332
-			mmc2_8bit_pins: mmc2_8bit {
388
+			mmc2_8bit_pins: mmc2-8bit-pins {
333389 				pins = "PC5", "PC6", "PC8",
334390 				       "PC9", "PC10", "PC11",
335391 				       "PC12", "PC13", "PC14",
....@@ -346,61 +402,53 @@
346402 				function = "nand0";
347403 			};
348404 
349
-			nand_pins_cs0: nand-pins-cs0 {
405
+			nand_cs0_pin: nand-cs0-pin {
350406 				pins = "PC4";
351407 				function = "nand0";
352408 				bias-pull-up;
353409 			};
354410 
355
-			nand_pins_cs1: nand-pins-cs1 {
411
+			nand_cs1_pin: nand-cs1-pin {
356412 				pins = "PC3";
357413 				function = "nand0";
358414 				bias-pull-up;
359415 			};
360416 
361
-			nand_pins_rb0: nand-pins-rb0 {
417
+			nand_rb0_pin: nand-rb0-pin {
362418 				pins = "PC6";
363419 				function = "nand0";
364420 				bias-pull-up;
365421 			};
366422 
367
-			nand_pins_rb1: nand-pins-rb1 {
423
+			nand_rb1_pin: nand-rb1-pin {
368424 				pins = "PC7";
369425 				function = "nand0";
370426 				bias-pull-up;
371427 			};
372428 
373
-			pwm0_pins: pwm0 {
429
+			pwm0_pin: pwm0-pin {
374430 				pins = "PH0";
375431 				function = "pwm0";
376432 			};
377433 
378
-			i2c0_pins_a: i2c0@0 {
379
-				pins = "PH2", "PH3";
380
-				function = "i2c0";
434
+			uart0_pf_pins: uart0-pf-pins {
435
+				pins = "PF2", "PF4";
436
+				function = "uart0";
381437 			};
382438 
383
-			i2c1_pins_a: i2c1@0 {
384
-				pins = "PH4", "PH5";
385
-				function = "i2c1";
439
+			uart1_pg_pins: uart1-pg-pins {
440
+				pins = "PG6", "PG7";
441
+				function = "uart1";
386442 			};
387443 
388
-			i2c2_pins_a: i2c2@0 {
389
-				pins = "PE12", "PE13";
390
-				function = "i2c2";
391
-			};
392
-
393
-			lcd_rgb666_pins: lcd-rgb666@0 {
394
-				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
395
-				       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
396
-				       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
397
-				       "PD24", "PD25", "PD26", "PD27";
398
-				function = "lcd0";
444
+			uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
445
+				pins = "PG8", "PG9";
446
+				function = "uart1";
399447 			};
400448 		};
401449 
402450 		timer@1c20c00 {
403
-			compatible = "allwinner,sun4i-a10-timer";
451
+			compatible = "allwinner,sun8i-a23-timer";
404452 			reg = <0x01c20c00 0xa0>;
405453 			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
406454 				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
....@@ -411,6 +459,7 @@
411459 			compatible = "allwinner,sun6i-a31-wdt";
412460 			reg = <0x01c20ca0 0x20>;
413461 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
462
+			clocks = <&osc24M>;
414463 		};
415464 
416465 		pwm: pwm@1c21400 {
....@@ -499,6 +548,8 @@
499548 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
500549 			clocks = <&ccu CLK_BUS_I2C0>;
501550 			resets = <&ccu RST_BUS_I2C0>;
551
+			pinctrl-names = "default";
552
+			pinctrl-0 = <&i2c0_pins>;
502553 			status = "disabled";
503554 			#address-cells = <1>;
504555 			#size-cells = <0>;
....@@ -510,6 +561,8 @@
510561 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
511562 			clocks = <&ccu CLK_BUS_I2C1>;
512563 			resets = <&ccu RST_BUS_I2C1>;
564
+			pinctrl-names = "default";
565
+			pinctrl-0 = <&i2c1_pins>;
513566 			status = "disabled";
514567 			#address-cells = <1>;
515568 			#size-cells = <0>;
....@@ -521,6 +574,8 @@
521574 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
522575 			clocks = <&ccu CLK_BUS_I2C2>;
523576 			resets = <&ccu RST_BUS_I2C2>;
577
+			pinctrl-names = "default";
578
+			pinctrl-0 = <&i2c2_pins>;
524579 			status = "disabled";
525580 			#address-cells = <1>;
526581 			#size-cells = <0>;
....@@ -554,7 +609,7 @@
554609 		};
555610 
556611 		gic: interrupt-controller@1c81000 {
557
-			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
612
+			compatible = "arm,gic-400";
558613 			reg = <0x01c81000 0x1000>,
559614 			      <0x01c82000 0x2000>,
560615 			      <0x01c84000 0x2000>,
....@@ -564,12 +619,99 @@
564619 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
565620 		};
566621 
622
+		fe0: display-frontend@1e00000 {
623
+			/* compatible gets set in SoC specific dtsi file */
624
+			reg = <0x01e00000 0x20000>;
625
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
626
+			clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
627
+				 <&ccu CLK_DRAM_DE_FE>;
628
+			clock-names = "ahb", "mod",
629
+				      "ram";
630
+			resets = <&ccu RST_BUS_DE_FE>;
631
+
632
+			ports {
633
+				#address-cells = <1>;
634
+				#size-cells = <0>;
635
+
636
+				fe0_out: port@1 {
637
+					reg = <1>;
638
+
639
+					fe0_out_be0: endpoint {
640
+						remote-endpoint = <&be0_in_fe0>;
641
+					};
642
+				};
643
+			};
644
+		};
645
+
646
+		be0: display-backend@1e60000 {
647
+			/* compatible gets set in SoC specific dtsi file */
648
+			reg = <0x01e60000 0x10000>;
649
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
650
+			clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
651
+				 <&ccu CLK_DRAM_DE_BE>;
652
+			clock-names = "ahb", "mod",
653
+				      "ram";
654
+			resets = <&ccu RST_BUS_DE_BE>;
655
+
656
+			ports {
657
+				#address-cells = <1>;
658
+				#size-cells = <0>;
659
+
660
+				be0_in: port@0 {
661
+					reg = <0>;
662
+
663
+					be0_in_fe0: endpoint {
664
+						remote-endpoint = <&fe0_out_be0>;
665
+					};
666
+				};
667
+
668
+				be0_out: port@1 {
669
+					reg = <1>;
670
+
671
+					be0_out_drc0: endpoint {
672
+						remote-endpoint = <&drc0_in_be0>;
673
+					};
674
+				};
675
+			};
676
+		};
677
+
678
+		drc0: drc@1e70000 {
679
+			/* compatible gets set in SoC specific dtsi file */
680
+			reg = <0x01e70000 0x10000>;
681
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
682
+			clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
683
+				 <&ccu CLK_DRAM_DRC>;
684
+			clock-names = "ahb", "mod", "ram";
685
+			resets = <&ccu RST_BUS_DRC>;
686
+
687
+			ports {
688
+				#address-cells = <1>;
689
+				#size-cells = <0>;
690
+
691
+				drc0_in: port@0 {
692
+					reg = <0>;
693
+
694
+					drc0_in_be0: endpoint {
695
+						remote-endpoint = <&be0_out_drc0>;
696
+					};
697
+				};
698
+
699
+				drc0_out: port@1 {
700
+					reg = <1>;
701
+
702
+					drc0_out_tcon0: endpoint {
703
+						remote-endpoint = <&tcon0_in_drc0>;
704
+					};
705
+				};
706
+			};
707
+		};
708
+
567709 		rtc: rtc@1f00000 {
568
-			compatible = "allwinner,sun6i-a31-rtc";
569
-			reg = <0x01f00000 0x54>;
710
+			compatible = "allwinner,sun8i-a23-rtc";
711
+			reg = <0x01f00000 0x400>;
570712 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
571713 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
572
-			clock-output-names = "osc32k";
714
+			clock-output-names = "osc32k", "osc32k-out";
573715 			clocks = <&ext_osc32k>;
574716 			#clock-cells = <1>;
575717 		};
....@@ -646,6 +788,20 @@
646788 			status = "disabled";
647789 		};
648790 
791
+		r_i2c: i2c@1f02400 {
792
+			compatible = "allwinner,sun8i-a23-i2c",
793
+				     "allwinner,sun6i-a31-i2c";
794
+			reg = <0x01f02400 0x400>;
795
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
796
+			pinctrl-names = "default";
797
+			pinctrl-0 = <&r_i2c_pins>;
798
+			clocks = <&apb0_gates 6>;
799
+			resets = <&apb0_rst 6>;
800
+			status = "disabled";
801
+			#address-cells = <1>;
802
+			#size-cells = <0>;
803
+		};
804
+
649805 		r_pio: pinctrl@1f02c00 {
650806 			compatible = "allwinner,sun8i-a23-r-pinctrl";
651807 			reg = <0x01f02c00 0x400>;
....@@ -656,18 +812,22 @@
656812 			gpio-controller;
657813 			interrupt-controller;
658814 			#interrupt-cells = <3>;
659
-			#address-cells = <1>;
660
-			#size-cells = <0>;
661815 			#gpio-cells = <3>;
662816 
663
-			r_rsb_pins: r_rsb {
817
+			r_i2c_pins: r-i2c-pins {
818
+				pins = "PL0", "PL1";
819
+				function = "s_i2c";
820
+				bias-pull-up;
821
+			};
822
+
823
+			r_rsb_pins: r-rsb-pins {
664824 				pins = "PL0", "PL1";
665825 				function = "s_rsb";
666826 				drive-strength = <20>;
667827 				bias-pull-up;
668828 			};
669829 
670
-			r_uart_pins_a: r_uart@0 {
830
+			r_uart_pins_a: r-uart-pins {
671831 				pins = "PL2", "PL3";
672832 				function = "s_uart";
673833 			};