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hc
2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6 
 kernel/arch/arm/boot/dts/qcom-msm8974.dtsi
....@@ -1,14 +1,17 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /dts-v1/;
33 
4
+#include <dt-bindings/interconnect/qcom,msm8974.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
56 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7
+#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
68 #include <dt-bindings/clock/qcom,rpmcc.h>
79 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
810 #include <dt-bindings/gpio/gpio.h>
9
-#include "skeleton.dtsi"
1011 
1112 / {
13
+	#address-cells = <1>;
14
+	#size-cells = <1>;
1215 	model = "Qualcomm MSM8974";
1316 	compatible = "qcom,msm8974";
1417 	interrupt-parent = <&intc>;
....@@ -18,17 +21,17 @@
1821 		#size-cells = <1>;
1922 		ranges;
2023 
21
-		mpss@8000000 {
24
+		mpss_region: mpss@8000000 {
2225 			reg = <0x08000000 0x5100000>;
2326 			no-map;
2427 		};
2528 
26
-		mba@d100000 {
29
+		mba_region: mba@d100000 {
2730 			reg = <0x0d100000 0x100000>;
2831 			no-map;
2932 		};
3033 
31
-		reserved@d200000 {
34
+		wcnss_region: wcnss@d200000 {
3235 			reg = <0x0d200000 0xa00000>;
3336 			no-map;
3437 		};
....@@ -59,15 +62,18 @@
5962 		};
6063 
6164 		rmtfs@fd80000 {
65
+			compatible = "qcom,rmtfs-mem";
6266 			reg = <0x0fd80000 0x180000>;
6367 			no-map;
68
+
69
+			qcom,client-id = <1>;
6470 		};
6571 	};
6672 
6773 	cpus {
6874 		#address-cells = <1>;
6975 		#size-cells = <0>;
70
-		interrupts = <1 9 0xf04>;
76
+		interrupts = <GIC_PPI 9 0xf04>;
7177 
7278 		CPU0: cpu@0 {
7379 			compatible = "qcom,krait";
....@@ -128,6 +134,11 @@
128134 				min-residency-us = <2000>;
129135 			};
130136 		};
137
+	};
138
+
139
+	memory {
140
+		device_type = "memory";
141
+		reg = <0x0 0x0>;
131142 	};
132143 
133144 	thermal-zones {
....@@ -210,11 +221,101 @@
210221 				};
211222 			};
212223 		};
224
+
225
+		q6-dsp-thermal {
226
+			polling-delay-passive = <250>;
227
+			polling-delay = <1000>;
228
+
229
+			thermal-sensors = <&tsens 1>;
230
+
231
+			trips {
232
+				q6_dsp_alert0: trip-point0 {
233
+					temperature = <90000>;
234
+					hysteresis = <2000>;
235
+					type = "hot";
236
+				};
237
+			};
238
+		};
239
+
240
+		modemtx-thermal {
241
+			polling-delay-passive = <250>;
242
+			polling-delay = <1000>;
243
+
244
+			thermal-sensors = <&tsens 2>;
245
+
246
+			trips {
247
+				modemtx_alert0: trip-point0 {
248
+					temperature = <90000>;
249
+					hysteresis = <2000>;
250
+					type = "hot";
251
+				};
252
+			};
253
+		};
254
+
255
+		video-thermal {
256
+			polling-delay-passive = <250>;
257
+			polling-delay = <1000>;
258
+
259
+			thermal-sensors = <&tsens 3>;
260
+
261
+			trips {
262
+				video_alert0: trip-point0 {
263
+					temperature = <95000>;
264
+					hysteresis = <2000>;
265
+					type = "hot";
266
+				};
267
+			};
268
+		};
269
+
270
+		wlan-thermal {
271
+			polling-delay-passive = <250>;
272
+			polling-delay = <1000>;
273
+
274
+			thermal-sensors = <&tsens 4>;
275
+
276
+			trips {
277
+				wlan_alert0: trip-point0 {
278
+					temperature = <105000>;
279
+					hysteresis = <2000>;
280
+					type = "hot";
281
+				};
282
+			};
283
+		};
284
+
285
+		gpu-thermal-top {
286
+			polling-delay-passive = <250>;
287
+			polling-delay = <1000>;
288
+
289
+			thermal-sensors = <&tsens 9>;
290
+
291
+			trips {
292
+				gpu1_alert0: trip-point0 {
293
+					temperature = <90000>;
294
+					hysteresis = <2000>;
295
+					type = "hot";
296
+				};
297
+			};
298
+		};
299
+
300
+		gpu-thermal-bottom {
301
+			polling-delay-passive = <250>;
302
+			polling-delay = <1000>;
303
+
304
+			thermal-sensors = <&tsens 10>;
305
+
306
+			trips {
307
+				gpu2_alert0: trip-point0 {
308
+					temperature = <90000>;
309
+					hysteresis = <2000>;
310
+					type = "hot";
311
+				};
312
+			};
313
+		};
213314 	};
214315 
215316 	cpu-pmu {
216317 		compatible = "qcom,krait-pmu";
217
-		interrupts = <1 7 0xf04>;
318
+		interrupts = <GIC_PPI 7 0xf04>;
218319 	};
219320 
220321 	clocks {
....@@ -233,17 +334,17 @@
233334 
234335 	timer {
235336 		compatible = "arm,armv7-timer";
236
-		interrupts = <1 2 0xf08>,
237
-			     <1 3 0xf08>,
238
-			     <1 4 0xf08>,
239
-			     <1 1 0xf08>;
337
+		interrupts = <GIC_PPI 2 0xf08>,
338
+			     <GIC_PPI 3 0xf08>,
339
+			     <GIC_PPI 4 0xf08>,
340
+			     <GIC_PPI 1 0xf08>;
240341 		clock-frequency = <19200000>;
241342 	};
242343 
243344 	adsp-pil {
244345 		compatible = "qcom,msm8974-adsp-pil";
245346 
246
-		interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
347
+		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
247348 				      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
248349 				      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
249350 				      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
....@@ -259,6 +360,15 @@
259360 
260361 		qcom,smem-states = <&adsp_smp2p_out 0>;
261362 		qcom,smem-state-names = "stop";
363
+
364
+		smd-edge {
365
+			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
366
+
367
+			qcom,ipc = <&apcs 8 8>;
368
+			qcom,smd-edge = <1>;
369
+
370
+			label = "lpass";
371
+		};
262372 	};
263373 
264374 	smem {
....@@ -275,7 +385,7 @@
275385 		qcom,smem = <443>, <429>;
276386 
277387 		interrupt-parent = <&intc>;
278
-		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
388
+		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
279389 
280390 		qcom,ipc = <&apcs 8 10>;
281391 
....@@ -300,7 +410,7 @@
300410 		qcom,smem = <435>, <428>;
301411 
302412 		interrupt-parent = <&intc>;
303
-		interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
413
+		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
304414 
305415 		qcom,ipc = <&apcs 8 14>;
306416 
....@@ -325,7 +435,7 @@
325435 		qcom,smem = <451>, <431>;
326436 
327437 		interrupt-parent = <&intc>;
328
-		interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
438
+		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
329439 
330440 		qcom,ipc = <&apcs 8 18>;
331441 
....@@ -364,7 +474,7 @@
364474 
365475 		modem_smsm: modem@1 {
366476 			reg = <1>;
367
-			interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
477
+			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
368478 
369479 			interrupt-controller;
370480 			#interrupt-cells = <2>;
....@@ -372,7 +482,7 @@
372482 
373483 		adsp_smsm: adsp@2 {
374484 			reg = <2>;
375
-			interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
485
+			interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
376486 
377487 			interrupt-controller;
378488 			#interrupt-cells = <2>;
....@@ -380,7 +490,7 @@
380490 
381491 		wcnss_smsm: wcnss@7 {
382492 			reg = <7>;
383
-			interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
493
+			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
384494 
385495 			interrupt-controller;
386496 			#interrupt-cells = <2>;
....@@ -427,11 +537,15 @@
427537 			};
428538 		};
429539 
430
-		tsens: thermal-sensor@fc4a8000 {
540
+		tsens: thermal-sensor@fc4a9000 {
431541 			compatible = "qcom,msm8974-tsens";
432
-			reg = <0xfc4a8000 0x2000>;
542
+			reg = <0xfc4a9000 0x1000>, /* TM */
543
+			      <0xfc4a8000 0x1000>; /* SROT */
433544 			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
434545 			nvmem-cell-names = "calib", "calib_backup";
546
+			#qcom,sensors = <11>;
547
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
548
+			interrupt-names = "uplow";
435549 			#thermal-sensor-cells = <1>;
436550 		};
437551 
....@@ -445,50 +559,50 @@
445559 
446560 			frame@f9021000 {
447561 				frame-number = <0>;
448
-				interrupts = <0 8 0x4>,
449
-					     <0 7 0x4>;
562
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
563
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
450564 				reg = <0xf9021000 0x1000>,
451565 				      <0xf9022000 0x1000>;
452566 			};
453567 
454568 			frame@f9023000 {
455569 				frame-number = <1>;
456
-				interrupts = <0 9 0x4>;
570
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
457571 				reg = <0xf9023000 0x1000>;
458572 				status = "disabled";
459573 			};
460574 
461575 			frame@f9024000 {
462576 				frame-number = <2>;
463
-				interrupts = <0 10 0x4>;
577
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
464578 				reg = <0xf9024000 0x1000>;
465579 				status = "disabled";
466580 			};
467581 
468582 			frame@f9025000 {
469583 				frame-number = <3>;
470
-				interrupts = <0 11 0x4>;
584
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
471585 				reg = <0xf9025000 0x1000>;
472586 				status = "disabled";
473587 			};
474588 
475589 			frame@f9026000 {
476590 				frame-number = <4>;
477
-				interrupts = <0 12 0x4>;
591
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
478592 				reg = <0xf9026000 0x1000>;
479593 				status = "disabled";
480594 			};
481595 
482596 			frame@f9027000 {
483597 				frame-number = <5>;
484
-				interrupts = <0 13 0x4>;
598
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
485599 				reg = <0xf9027000 0x1000>;
486600 				status = "disabled";
487601 			};
488602 
489603 			frame@f9028000 {
490604 				frame-number = <6>;
491
-				interrupts = <0 14 0x4>;
605
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
492606 				reg = <0xf9028000 0x1000>;
493607 				status = "disabled";
494608 			};
....@@ -586,7 +700,7 @@
586700 		blsp1_uart1: serial@f991d000 {
587701 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
588702 			reg = <0xf991d000 0x1000>;
589
-			interrupts = <0 107 0x0>;
703
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
590704 			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
591705 			clock-names = "core", "iface";
592706 			status = "disabled";
....@@ -595,17 +709,27 @@
595709 		blsp1_uart2: serial@f991e000 {
596710 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
597711 			reg = <0xf991e000 0x1000>;
598
-			interrupts = <0 108 0x0>;
712
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
599713 			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
600714 			clock-names = "core", "iface";
601715 			status = "disabled";
602716 		};
603717 
718
+		blsp2_uart10: serial@f9960000 {
719
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
720
+			reg = <0xf9960000 0x1000>;
721
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
722
+			clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
723
+			clock-names = "core", "iface";
724
+			status = "disabled";
725
+		};
726
+
604727 		sdhci@f9824900 {
605
-			compatible = "qcom,sdhci-msm-v4";
728
+			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
606729 			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
607730 			reg-names = "hc_mem", "core_mem";
608
-			interrupts = <0 123 0>, <0 138 0>;
731
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
732
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
609733 			interrupt-names = "hc_irq", "pwr_irq";
610734 			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
611735 				 <&gcc GCC_SDCC1_AHB_CLK>,
....@@ -615,11 +739,11 @@
615739 		};
616740 
617741 		sdhci@f9864900 {
618
-			compatible = "qcom,sdhci-msm-v4";
742
+			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
619743 			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
620744 			reg-names = "hc_mem", "core_mem";
621
-			interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
622
-				     <GIC_SPI 224 IRQ_TYPE_NONE>;
745
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
746
+				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
623747 			interrupt-names = "hc_irq", "pwr_irq";
624748 			clocks = <&gcc GCC_SDCC3_APPS_CLK>,
625749 				 <&gcc GCC_SDCC3_AHB_CLK>,
....@@ -629,10 +753,11 @@
629753 		};
630754 
631755 		sdhci@f98a4900 {
632
-			compatible = "qcom,sdhci-msm-v4";
756
+			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
633757 			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
634758 			reg-names = "hc_mem", "core_mem";
635
-			interrupts = <0 125 0>, <0 221 0>;
759
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
760
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
636761 			interrupt-names = "hc_irq", "pwr_irq";
637762 			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
638763 				 <&gcc GCC_SDCC2_AHB_CLK>,
....@@ -692,22 +817,169 @@
692817 			clock-names = "core";
693818 		};
694819 
820
+		remoteproc@fc880000 {
821
+			compatible = "qcom,msm8974-mss-pil";
822
+			reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
823
+			reg-names = "qdsp6", "rmb";
824
+
825
+			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
826
+					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
827
+					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
828
+					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
829
+					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
830
+			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
831
+
832
+			clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
833
+				 <&gcc GCC_MSS_CFG_AHB_CLK>,
834
+				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
835
+				 <&xo_board>;
836
+			clock-names = "iface", "bus", "mem", "xo";
837
+
838
+			resets = <&gcc GCC_MSS_RESTART>;
839
+			reset-names = "mss_restart";
840
+
841
+			cx-supply = <&pm8841_s2>;
842
+			mss-supply = <&pm8841_s3>;
843
+			mx-supply = <&pm8841_s1>;
844
+			pll-supply = <&pm8941_l12>;
845
+
846
+			qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
847
+
848
+			qcom,smem-states = <&modem_smp2p_out 0>;
849
+			qcom,smem-state-names = "stop";
850
+
851
+			mba {
852
+				memory-region = <&mba_region>;
853
+			};
854
+
855
+			mpss {
856
+				memory-region = <&mpss_region>;
857
+			};
858
+
859
+			smd-edge {
860
+				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
861
+
862
+				qcom,ipc = <&apcs 8 12>;
863
+				qcom,smd-edge = <0>;
864
+
865
+				label = "modem";
866
+			};
867
+		};
868
+
869
+		pronto: remoteproc@fb21b000 {
870
+			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
871
+			reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
872
+			reg-names = "ccu", "dxe", "pmu";
873
+
874
+			memory-region = <&wcnss_region>;
875
+
876
+			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
877
+					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
878
+					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
879
+					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
880
+					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
881
+			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
882
+
883
+			vddpx-supply = <&pm8941_s3>;
884
+
885
+			qcom,smem-states = <&wcnss_smp2p_out 0>;
886
+			qcom,smem-state-names = "stop";
887
+
888
+			status = "disabled";
889
+
890
+			iris {
891
+				compatible = "qcom,wcn3680";
892
+
893
+				clocks = <&rpmcc RPM_SMD_CXO_A2>;
894
+				clock-names = "xo";
895
+
896
+				vddxo-supply = <&pm8941_l6>;
897
+				vddrfa-supply = <&pm8941_l11>;
898
+				vddpa-supply = <&pm8941_l19>;
899
+				vdddig-supply = <&pm8941_s3>;
900
+			};
901
+
902
+			smd-edge {
903
+				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
904
+
905
+				qcom,ipc = <&apcs 8 17>;
906
+				qcom,smd-edge = <6>;
907
+
908
+				wcnss {
909
+					compatible = "qcom,wcnss";
910
+					qcom,smd-channels = "WCNSS_CTRL";
911
+					status = "disabled";
912
+
913
+					qcom,mmio = <&pronto>;
914
+
915
+					bt {
916
+						compatible = "qcom,wcnss-bt";
917
+					};
918
+
919
+					wifi {
920
+						compatible = "qcom,wcnss-wlan";
921
+
922
+						interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
923
+							     <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
924
+						interrupt-names = "tx", "rx";
925
+
926
+						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
927
+						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
928
+					};
929
+				};
930
+			};
931
+		};
932
+
695933 		msmgpio: pinctrl@fd510000 {
696934 			compatible = "qcom,msm8974-pinctrl";
697935 			reg = <0xfd510000 0x4000>;
698936 			gpio-controller;
937
+			gpio-ranges = <&msmgpio 0 0 146>;
699938 			#gpio-cells = <2>;
700939 			interrupt-controller;
701940 			#interrupt-cells = <2>;
702
-			interrupts = <0 208 0>;
941
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
942
+		};
943
+
944
+		i2c@f9923000 {
945
+			status = "disabled";
946
+			compatible = "qcom,i2c-qup-v2.1.1";
947
+			reg = <0xf9923000 0x1000>;
948
+			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
949
+			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
950
+			clock-names = "core", "iface";
951
+			#address-cells = <1>;
952
+			#size-cells = <0>;
703953 		};
704954 
705955 		i2c@f9924000 {
706956 			status = "disabled";
707957 			compatible = "qcom,i2c-qup-v2.1.1";
708958 			reg = <0xf9924000 0x1000>;
709
-			interrupts = <0 96 IRQ_TYPE_NONE>;
959
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
710960 			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
961
+			clock-names = "core", "iface";
962
+			#address-cells = <1>;
963
+			#size-cells = <0>;
964
+		};
965
+
966
+		blsp_i2c3: i2c@f9925000 {
967
+			status = "disabled";
968
+			compatible = "qcom,i2c-qup-v2.1.1";
969
+			reg = <0xf9925000 0x1000>;
970
+			interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
971
+			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
972
+			clock-names = "core", "iface";
973
+			#address-cells = <1>;
974
+			#size-cells = <0>;
975
+		};
976
+
977
+		blsp_i2c6: i2c@f9928000 {
978
+			status = "disabled";
979
+			compatible = "qcom,i2c-qup-v2.1.1";
980
+			reg = <0xf9928000 0x1000>;
981
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
982
+			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
711983 			clock-names = "core", "iface";
712984 			#address-cells = <1>;
713985 			#size-cells = <0>;
....@@ -717,7 +989,7 @@
717989 			status = "disabled";
718990 			compatible = "qcom,i2c-qup-v2.1.1";
719991 			reg = <0xf9964000 0x1000>;
720
-			interrupts = <0 102 IRQ_TYPE_NONE>;
992
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
721993 			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
722994 			clock-names = "core", "iface";
723995 			#address-cells = <1>;
....@@ -728,13 +1000,24 @@
7281000 			status = "disabled";
7291001 			compatible = "qcom,i2c-qup-v2.1.1";
7301002 			reg = <0xf9967000 0x1000>;
731
-			interrupts = <0 105 IRQ_TYPE_NONE>;
1003
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
7321004 			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
7331005 			clock-names = "core", "iface";
7341006 			#address-cells = <1>;
7351007 			#size-cells = <0>;
7361008 			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
7371009 			dma-names = "tx", "rx";
1010
+		};
1011
+
1012
+		blsp_i2c12: i2c@f9968000 {
1013
+			status = "disabled";
1014
+			compatible = "qcom,i2c-qup-v2.1.1";
1015
+			reg = <0xf9968000 0x1000>;
1016
+			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1017
+			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1018
+			clock-names = "core", "iface";
1019
+			#address-cells = <1>;
1020
+			#size-cells = <0>;
7381021 		};
7391022 
7401023 		spmi_bus: spmi@fc4cf000 {
....@@ -744,7 +1027,7 @@
7441027 			      <0xfc4cb000 0x1000>,
7451028 			      <0xfc4ca000 0x1000>;
7461029 			interrupt-names = "periph_irq";
747
-			interrupts = <0 190 0>;
1030
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
7481031 			qcom,ee = <0>;
7491032 			qcom,channel = <0>;
7501033 			#address-cells = <2>;
....@@ -770,10 +1053,11 @@
7701053 			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
7711054 			clock-names = "apb_pclk", "atclk";
7721055 
773
-			port {
774
-				etr_in: endpoint {
775
-					slave-mode;
776
-					remote-endpoint = <&replicator_out0>;
1056
+			in-ports {
1057
+				port {
1058
+					etr_in: endpoint {
1059
+						remote-endpoint = <&replicator_out0>;
1060
+					};
7771061 				};
7781062 			};
7791063 		};
....@@ -785,10 +1069,11 @@
7851069 			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
7861070 			clock-names = "apb_pclk", "atclk";
7871071 
788
-			port {
789
-				tpiu_in: endpoint {
790
-					 slave-mode;
791
-					 remote-endpoint = <&replicator_out1>;
1072
+			in-ports {
1073
+				port {
1074
+					tpiu_in: endpoint {
1075
+						remote-endpoint = <&replicator_out1>;
1076
+					};
7921077 				 };
7931078 			};
7941079 		};
....@@ -800,7 +1085,7 @@
8001085 			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
8011086 			clock-names = "apb_pclk", "atclk";
8021087 
803
-			ports {
1088
+			out-ports {
8041089 				#address-cells = <1>;
8051090 				#size-cells = <0>;
8061091 
....@@ -816,10 +1101,11 @@
8161101 						remote-endpoint = <&tpiu_in>;
8171102 					};
8181103 				};
819
-				port@2 {
820
-					reg = <0>;
1104
+			};
1105
+
1106
+			in-ports {
1107
+				port {
8211108 					replicator_in: endpoint {
822
-						slave-mode;
8231109 						remote-endpoint = <&etf_out>;
8241110 					};
8251111 				};
....@@ -833,20 +1119,17 @@
8331119 			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
8341120 			clock-names = "apb_pclk", "atclk";
8351121 
836
-			ports {
837
-				#address-cells = <1>;
838
-				#size-cells = <0>;
839
-
840
-				port@0 {
841
-					reg = <0>;
1122
+			out-ports {
1123
+				port {
8421124 					etf_out: endpoint {
8431125 						remote-endpoint = <&replicator_in>;
8441126 					};
8451127 				};
846
-				port@1 {
847
-					reg = <0>;
1128
+			};
1129
+
1130
+			in-ports {
1131
+				port {
8481132 					etf_in: endpoint {
849
-						slave-mode;
8501133 						remote-endpoint = <&merger_out>;
8511134 					};
8521135 				};
....@@ -854,13 +1137,13 @@
8541137 		};
8551138 
8561139 		funnel@fc31b000 {
857
-			compatible = "arm,coresight-funnel", "arm,primecell";
1140
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
8581141 			reg = <0xfc31b000 0x1000>;
8591142 
8601143 			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
8611144 			clock-names = "apb_pclk", "atclk";
8621145 
863
-			ports {
1146
+			in-ports {
8641147 				#address-cells = <1>;
8651148 				#size-cells = <0>;
8661149 
....@@ -873,12 +1156,13 @@
8731156 				port@1 {
8741157 					reg = <1>;
8751158 					merger_in1: endpoint {
876
-						slave-mode;
8771159 						remote-endpoint = <&funnel1_out>;
8781160 					};
8791161 				};
880
-				port@8 {
881
-					reg = <0>;
1162
+			};
1163
+
1164
+			out-ports {
1165
+				port {
8821166 					merger_out: endpoint {
8831167 						remote-endpoint = <&etf_in>;
8841168 					};
....@@ -887,13 +1171,13 @@
8871171 		};
8881172 
8891173 		funnel@fc31a000 {
890
-			compatible = "arm,coresight-funnel", "arm,primecell";
1174
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
8911175 			reg = <0xfc31a000 0x1000>;
8921176 
8931177 			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
8941178 			clock-names = "apb_pclk", "atclk";
8951179 
896
-			ports {
1180
+			in-ports {
8971181 				#address-cells = <1>;
8981182 				#size-cells = <0>;
8991183 
....@@ -910,12 +1194,13 @@
9101194 				port@5 {
9111195 					reg = <5>;
9121196 					funnel1_in5: endpoint {
913
-						slave-mode;
9141197 						remote-endpoint = <&kpss_out>;
9151198 					};
9161199 				};
917
-				port@8 {
918
-					reg = <0>;
1200
+			};
1201
+
1202
+			out-ports {
1203
+				port {
9191204 					funnel1_out: endpoint {
9201205 						remote-endpoint = <&merger_in1>;
9211206 					};
....@@ -924,46 +1209,44 @@
9241209 		};
9251210 
9261211 		funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
927
-			compatible = "arm,coresight-funnel", "arm,primecell";
1212
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
9281213 			reg = <0xfc345000 0x1000>;
9291214 
9301215 			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
9311216 			clock-names = "apb_pclk", "atclk";
9321217 
933
-			ports {
1218
+			in-ports {
9341219 				#address-cells = <1>;
9351220 				#size-cells = <0>;
9361221 
9371222 				port@0 {
9381223 					reg = <0>;
9391224 					kpss_in0: endpoint {
940
-						slave-mode;
9411225 						remote-endpoint = <&etm0_out>;
9421226 					};
9431227 				};
9441228 				port@1 {
9451229 					reg = <1>;
9461230 					kpss_in1: endpoint {
947
-						slave-mode;
9481231 						remote-endpoint = <&etm1_out>;
9491232 					};
9501233 				};
9511234 				port@2 {
9521235 					reg = <2>;
9531236 					kpss_in2: endpoint {
954
-						slave-mode;
9551237 						remote-endpoint = <&etm2_out>;
9561238 					};
9571239 				};
9581240 				port@3 {
9591241 					reg = <3>;
9601242 					kpss_in3: endpoint {
961
-						slave-mode;
9621243 						remote-endpoint = <&etm3_out>;
9631244 					};
9641245 				};
965
-				port@8 {
966
-					reg = <0>;
1246
+			};
1247
+
1248
+			out-ports {
1249
+				port {
9671250 					kpss_out: endpoint {
9681251 						remote-endpoint = <&funnel1_in5>;
9691252 					};
....@@ -980,9 +1263,11 @@
9801263 
9811264 			cpu = <&CPU0>;
9821265 
983
-			port {
984
-				etm0_out: endpoint {
985
-					remote-endpoint = <&kpss_in0>;
1266
+			out-ports {
1267
+				port {
1268
+					etm0_out: endpoint {
1269
+						remote-endpoint = <&kpss_in0>;
1270
+					};
9861271 				};
9871272 			};
9881273 		};
....@@ -996,9 +1281,11 @@
9961281 
9971282 			cpu = <&CPU1>;
9981283 
999
-			port {
1000
-				etm1_out: endpoint {
1001
-					remote-endpoint = <&kpss_in1>;
1284
+			out-ports {
1285
+				port {
1286
+					etm1_out: endpoint {
1287
+						remote-endpoint = <&kpss_in1>;
1288
+					};
10021289 				};
10031290 			};
10041291 		};
....@@ -1012,9 +1299,11 @@
10121299 
10131300 			cpu = <&CPU2>;
10141301 
1015
-			port {
1016
-				etm2_out: endpoint {
1017
-					remote-endpoint = <&kpss_in2>;
1302
+			out-ports {
1303
+				port {
1304
+					etm2_out: endpoint {
1305
+						remote-endpoint = <&kpss_in2>;
1306
+					};
10181307 				};
10191308 			};
10201309 		};
....@@ -1028,10 +1317,230 @@
10281317 
10291318 			cpu = <&CPU3>;
10301319 
1031
-			port {
1032
-				etm3_out: endpoint {
1033
-					remote-endpoint = <&kpss_in3>;
1320
+			out-ports {
1321
+				port {
1322
+					etm3_out: endpoint {
1323
+						remote-endpoint = <&kpss_in3>;
1324
+					};
10341325 				};
1326
+			};
1327
+		};
1328
+
1329
+		ocmem@fdd00000 {
1330
+			compatible = "qcom,msm8974-ocmem";
1331
+			reg = <0xfdd00000 0x2000>,
1332
+			      <0xfec00000 0x180000>;
1333
+			reg-names = "ctrl",
1334
+			            "mem";
1335
+			clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1336
+			         <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1337
+			clock-names = "core",
1338
+			              "iface";
1339
+
1340
+			#address-cells = <1>;
1341
+			#size-cells = <1>;
1342
+
1343
+			gmu_sram: gmu-sram@0 {
1344
+				reg = <0x0 0x100000>;
1345
+			};
1346
+		};
1347
+
1348
+		bimc: interconnect@fc380000 {
1349
+			reg = <0xfc380000 0x6a000>;
1350
+			compatible = "qcom,msm8974-bimc";
1351
+			#interconnect-cells = <1>;
1352
+			clock-names = "bus", "bus_a";
1353
+			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1354
+			         <&rpmcc RPM_SMD_BIMC_A_CLK>;
1355
+		};
1356
+
1357
+		snoc: interconnect@fc460000 {
1358
+			reg = <0xfc460000 0x4000>;
1359
+			compatible = "qcom,msm8974-snoc";
1360
+			#interconnect-cells = <1>;
1361
+			clock-names = "bus", "bus_a";
1362
+			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1363
+			         <&rpmcc RPM_SMD_SNOC_A_CLK>;
1364
+		};
1365
+
1366
+		pnoc: interconnect@fc468000 {
1367
+			reg = <0xfc468000 0x4000>;
1368
+			compatible = "qcom,msm8974-pnoc";
1369
+			#interconnect-cells = <1>;
1370
+			clock-names = "bus", "bus_a";
1371
+			clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1372
+			         <&rpmcc RPM_SMD_PNOC_A_CLK>;
1373
+		};
1374
+
1375
+		ocmemnoc: interconnect@fc470000 {
1376
+			reg = <0xfc470000 0x4000>;
1377
+			compatible = "qcom,msm8974-ocmemnoc";
1378
+			#interconnect-cells = <1>;
1379
+			clock-names = "bus", "bus_a";
1380
+			clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1381
+			         <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1382
+		};
1383
+
1384
+		mmssnoc: interconnect@fc478000 {
1385
+			reg = <0xfc478000 0x4000>;
1386
+			compatible = "qcom,msm8974-mmssnoc";
1387
+			#interconnect-cells = <1>;
1388
+			clock-names = "bus", "bus_a";
1389
+			clocks = <&mmcc MMSS_S0_AXI_CLK>,
1390
+			         <&mmcc MMSS_S0_AXI_CLK>;
1391
+		};
1392
+
1393
+		cnoc: interconnect@fc480000 {
1394
+			reg = <0xfc480000 0x4000>;
1395
+			compatible = "qcom,msm8974-cnoc";
1396
+			#interconnect-cells = <1>;
1397
+			clock-names = "bus", "bus_a";
1398
+			clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1399
+			         <&rpmcc RPM_SMD_CNOC_A_CLK>;
1400
+		};
1401
+
1402
+		mdss: mdss@fd900000 {
1403
+			status = "disabled";
1404
+
1405
+			compatible = "qcom,mdss";
1406
+			reg = <0xfd900000 0x100>,
1407
+			      <0xfd924000 0x1000>;
1408
+			reg-names = "mdss_phys",
1409
+			            "vbif_phys";
1410
+
1411
+			power-domains = <&mmcc MDSS_GDSC>;
1412
+
1413
+			clocks = <&mmcc MDSS_AHB_CLK>,
1414
+			         <&mmcc MDSS_AXI_CLK>,
1415
+			         <&mmcc MDSS_VSYNC_CLK>;
1416
+			clock-names = "iface",
1417
+			              "bus",
1418
+			              "vsync";
1419
+
1420
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1421
+
1422
+			interrupt-controller;
1423
+			#interrupt-cells = <1>;
1424
+
1425
+			#address-cells = <1>;
1426
+			#size-cells = <1>;
1427
+			ranges;
1428
+
1429
+			mdp: mdp@fd900000 {
1430
+				status = "disabled";
1431
+
1432
+				compatible = "qcom,mdp5";
1433
+				reg = <0xfd900100 0x22000>;
1434
+				reg-names = "mdp_phys";
1435
+
1436
+				interrupt-parent = <&mdss>;
1437
+				interrupts = <0 0>;
1438
+
1439
+				clocks = <&mmcc MDSS_AHB_CLK>,
1440
+					 <&mmcc MDSS_AXI_CLK>,
1441
+					 <&mmcc MDSS_MDP_CLK>,
1442
+					 <&mmcc MDSS_VSYNC_CLK>;
1443
+				clock-names = "iface",
1444
+				              "bus",
1445
+				              "core",
1446
+				              "vsync";
1447
+
1448
+				interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1449
+				interconnect-names = "mdp0-mem";
1450
+
1451
+				ports {
1452
+					#address-cells = <1>;
1453
+					#size-cells = <0>;
1454
+
1455
+					port@0 {
1456
+						reg = <0>;
1457
+						mdp5_intf1_out: endpoint {
1458
+							remote-endpoint = <&dsi0_in>;
1459
+						};
1460
+					};
1461
+				};
1462
+			};
1463
+
1464
+			dsi0: dsi@fd922800 {
1465
+				status = "disabled";
1466
+
1467
+				compatible = "qcom,mdss-dsi-ctrl";
1468
+				reg = <0xfd922800 0x1f8>;
1469
+				reg-names = "dsi_ctrl";
1470
+
1471
+				interrupt-parent = <&mdss>;
1472
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1473
+
1474
+				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1475
+				                  <&mmcc PCLK0_CLK_SRC>;
1476
+				assigned-clock-parents = <&dsi_phy0 0>,
1477
+				                         <&dsi_phy0 1>;
1478
+
1479
+				clocks = <&mmcc MDSS_MDP_CLK>,
1480
+				         <&mmcc MDSS_AHB_CLK>,
1481
+				         <&mmcc MDSS_AXI_CLK>,
1482
+				         <&mmcc MDSS_BYTE0_CLK>,
1483
+				         <&mmcc MDSS_PCLK0_CLK>,
1484
+				         <&mmcc MDSS_ESC0_CLK>,
1485
+				         <&mmcc MMSS_MISC_AHB_CLK>;
1486
+				clock-names = "mdp_core",
1487
+				              "iface",
1488
+				              "bus",
1489
+				              "byte",
1490
+				              "pixel",
1491
+				              "core",
1492
+				              "core_mmss";
1493
+
1494
+				phys = <&dsi_phy0>;
1495
+				phy-names = "dsi-phy";
1496
+
1497
+				ports {
1498
+					#address-cells = <1>;
1499
+					#size-cells = <0>;
1500
+
1501
+					port@0 {
1502
+						reg = <0>;
1503
+						dsi0_in: endpoint {
1504
+							remote-endpoint = <&mdp5_intf1_out>;
1505
+						};
1506
+					};
1507
+
1508
+					port@1 {
1509
+						reg = <1>;
1510
+						dsi0_out: endpoint {
1511
+						};
1512
+					};
1513
+				};
1514
+			};
1515
+
1516
+			dsi_phy0: dsi-phy@fd922a00 {
1517
+				status = "disabled";
1518
+
1519
+				compatible = "qcom,dsi-phy-28nm-hpm";
1520
+				reg = <0xfd922a00 0xd4>,
1521
+				      <0xfd922b00 0x280>,
1522
+				      <0xfd922d80 0x30>;
1523
+				reg-names = "dsi_pll",
1524
+				            "dsi_phy",
1525
+				            "dsi_phy_regulator";
1526
+
1527
+				#clock-cells = <1>;
1528
+				#phy-cells = <0>;
1529
+				qcom,dsi-phy-index = <0>;
1530
+
1531
+				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1532
+				clock-names = "iface", "ref";
1533
+			};
1534
+		};
1535
+
1536
+		imem@fe805000 {
1537
+			status = "disabled";
1538
+			compatible = "syscon", "simple-mfd";
1539
+			reg = <0xfe805000 0x1000>;
1540
+
1541
+			reboot-mode {
1542
+				compatible = "syscon-reboot-mode";
1543
+				offset = <0x65c>;
10351544 			};
10361545 		};
10371546 	};
....@@ -1039,22 +1548,8 @@
10391548 	smd {
10401549 		compatible = "qcom,smd";
10411550 
1042
-		adsp {
1043
-			interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
1044
-
1045
-			qcom,ipc = <&apcs 8 8>;
1046
-			qcom,smd-edge = <1>;
1047
-		};
1048
-
1049
-		modem {
1050
-			interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1051
-
1052
-			qcom,ipc = <&apcs 8 12>;
1053
-			qcom,smd-edge = <0>;
1054
-		};
1055
-
10561551 		rpm {
1057
-			interrupts = <0 168 1>;
1552
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
10581553 			qcom,ipc = <&apcs 8 0>;
10591554 			qcom,smd-edge = <15>;
10601555