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2024-05-10 10ebd8556b7990499c896a550e3d416b444211e6

 kernel/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
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@@ -23,11 +23,23 @@
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 - compatible:
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     Must be one of :
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-    "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs
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-    "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
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+    "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs
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+    "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI
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 						   BRCMSTB  SoCs
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-    "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"     : MSPI+BSPI on Cygnus, NSP
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-    "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"     : NS2 SoCs
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+    "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
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+    			     			  			    BRCMSTB  SoCs
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+    "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
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+    			     			  			    BRCMSTB  SoCs
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+    "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
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+    			     			  			    BRCMSTB  SoCs
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+    "brcm,spi-bcm7445-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
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+                                                                            BRCMSTB  SoCs
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+    "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
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+    			     			  			    BRCMSTB  SoCs
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+    "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
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+    			     			  			    BRCMSTB  SoCs
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+    "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"     : MSPI+BSPI on Cygnus, NSP
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+    "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"     : NS2 SoCs
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 - reg:
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     Define the bases and ranges of the associated I/O address spaces.
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@@ -76,7 +88,7 @@
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     spi@f03e3400 {
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 		#address-cells = <0x1>;
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 		#size-cells = <0x0>;
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-		compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi";
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+		compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
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 		reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
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 		reg-names = "cs_reg", "mspi", "bspi";
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 		interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
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@@ -139,7 +151,7 @@
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 		#address-cells = <1>;
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 		#size-cells = <0>;
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 		clocks = <&upg_fixed>;
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-		compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi";
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+		compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
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 		reg = <0xf0416000 0x180>;
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 		reg-names = "mspi";
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 		interrupts = <0x14>;
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@@ -150,7 +162,7 @@
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 iProc SoC Example:
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     qspi: spi@18027200 {
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-	compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
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+	compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
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 	reg = <0x18027200 0x184>,
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 	      <0x18027000 0x124>,
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 	      <0x1811c408 0x004>,
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@@ -181,7 +193,7 @@
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  NS2 SoC Example:
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 	       qspi: spi@66470200 {
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-		       compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
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+		       compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
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 		       reg = <0x66470200 0x184>,
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 			     <0x66470000 0x124>,
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 			     <0x67017408 0x004>,