add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/tools/perf/Documentation/perf-c2c.txt
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 The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
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 you to track down the cacheline contentions.
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-The tool is based on x86's load latency and precise store facility events
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-provided by Intel CPUs. These events provide:
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+On x86, the tool is based on load latency and precise store facility events
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+provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
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+with thresholding feature.
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+
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+These events provide:
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   - memory address of the access
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   - type of the access (load and store details)
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   - latency (in cycles) of the load access
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@@ -37,7 +40,7 @@
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 --------------
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 -e::
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 --event=::
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-	Select the PMU event. Use 'perf mem record -e list'
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+	Select the PMU event. Use 'perf c2c record -e list'
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 	to list available events.
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 -v::
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@@ -46,7 +49,7 @@
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 -l::
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 --ldlat::
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-	Configure mem-loads latency.
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+	Configure mem-loads latency. (x86 only)
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 -k::
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 --all-kernel::
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@@ -108,6 +111,17 @@
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 --display::
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 	Switch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default.
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+--stitch-lbr::
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+	Show callgraph with stitched LBRs, which may have more complete
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+	callgraph. The perf.data file must have been obtained using
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+	perf c2c record --call-graph lbr.
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+	Disabled by default. In common cases with call stack overflows,
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+	it can recreate better call stacks than the default lbr call stack
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+	output. But this approach is not full proof. There can be cases
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+	where it creates incorrect call stacks from incorrect matches.
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+	The known limitations include exception handing such as
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+	setjmp/longjmp will have calls/returns not match.
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+
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 C2C RECORD
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 ----------
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 The perf c2c record command setup options related to HITM cacheline analysis
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   -W,-d,--phys-data,--sample-cpu
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 Unless specified otherwise with '-e' option, following events are monitored by
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-default:
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+default on x86:
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   cpu/mem-loads,ldlat=30/P
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   cpu/mem-stores/P
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+
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+and following on PowerPC:
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+
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+  cpu/mem-loads/
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+  cpu/mem-stores/
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 User can pass any 'perf record' option behind '--' mark, like (to enable
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 callchains and system wide monitoring):
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   Cacheline
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   - cacheline address (hex number)
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-  Total records
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-  - sum of all cachelines accesses
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-
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   Rmt/Lcl Hitm
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   - cacheline percentage of all Remote/Local HITM accesses
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-  LLC Load Hitm - Total, Lcl, Rmt
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+  LLC Load Hitm - Total, LclHitm, RmtHitm
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   - count of Total/Local/Remote load HITMs
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-  Store Reference - Total, L1Hit, L1Miss
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-    Total - all store accesses
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-    L1Hit - store accesses that hit L1
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-    L1Hit - store accesses that missed L1
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+  Total records
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+  - sum of all cachelines accesses
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-  Load Dram
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-  - count of local and remote DRAM accesses
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-  LLC Ld Miss
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-  - count of all accesses that missed LLC
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-
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-  Total Loads
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+  Total loads
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   - sum of all load accesses
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+
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+  Total stores
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+  - sum of all store accesses
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+
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+  Store Reference - L1Hit, L1Miss
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+    L1Hit - store accesses that hit L1
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+    L1Miss - store accesses that missed L1
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   Core Load Hit - FB, L1, L2
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   - count of load hits in FB (Fill Buffer), L1 and L2 cache
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-  LLC Load Hit - Llc, Rmt
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-  - count of LLC and Remote load hits
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+  LLC Load Hit - LlcHit, LclHitm
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+  - count of LLC load accesses, includes LLC hits and LLC HITMs
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+
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+  RMT Load Hit - RmtHit, RmtHitm
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+  - count of remote load accesses, includes remote hits and remote HITMs
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+
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+  Load Dram - Lcl, Rmt
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+  - count of local and remote DRAM accesses
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 For each offset in the 2) list we display following data:
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