add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/tools/arch/x86/include/asm/cpufeatures.h
..
..
@@ -13,8 +13,8 @@
13
13
 /*
14
14
  * Defines x86 CPU feature bits
15
15
  */
16
-#define NCAPINTS			19	   /* N 32-bit words worth of info */
17
-#define NBUGINTS			1	   /* N 32-bit bug flags */
16
+#define NCAPINTS			20	   /* N 32-bit words worth of info */
17
+#define NBUGINTS			2	   /* N 32-bit bug flags */
18
18
 
19
19
 /*
20
20
  * Note: If the comment begins with a quoted string, that string is used
..
..
@@ -96,7 +96,7 @@
96
96
 #define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */
97
97
 #define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */
98
98
 #define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */
99
-#define X86_FEATURE_MFENCE_RDTSC	( 3*32+17) /* "" MFENCE synchronizes RDTSC */
99
+/* FREE!                                ( 3*32+17) */
100
100
 #define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */
101
101
 #define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */
102
102
 #define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
..
..
@@ -108,6 +108,7 @@
108
108
 #define X86_FEATURE_EXTD_APICID		( 3*32+26) /* Extended APICID (8 bits) */
109
109
 #define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */
110
110
 #define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
111
+/* free					( 3*32+29) */
111
112
 #define X86_FEATURE_NONSTOP_TSC_S3	( 3*32+30) /* TSC doesn't stop in S3 state */
112
113
 #define X86_FEATURE_TSC_KNOWN_FREQ	( 3*32+31) /* TSC has known frequency */
113
114
 
..
..
@@ -200,17 +201,17 @@
200
201
 #define X86_FEATURE_INVPCID_SINGLE	( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
201
202
 #define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */
202
203
 #define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */
203
-#define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */
204
+/* FREE!                                ( 7*32+10) */
204
205
 #define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */
205
-#define X86_FEATURE_RETPOLINE		( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
206
-#define X86_FEATURE_RETPOLINE_AMD	( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
206
+#define X86_FEATURE_KERNEL_IBRS		( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
207
+#define X86_FEATURE_RSB_VMEXIT		( 7*32+13) /* "" Fill RSB on VM-Exit */
207
208
 #define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */
208
209
 #define X86_FEATURE_CDP_L2		( 7*32+15) /* Code and Data Prioritization L2 */
209
210
 #define X86_FEATURE_MSR_SPEC_CTRL	( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
210
211
 #define X86_FEATURE_SSBD		( 7*32+17) /* Speculative Store Bypass Disable */
211
212
 #define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */
212
213
 #define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* "" Fill RSB on context switches */
213
-#define X86_FEATURE_SEV			( 7*32+20) /* AMD Secure Encrypted Virtualization */
214
+/* FREE!                                ( 7*32+20) */
214
215
 #define X86_FEATURE_USE_IBPB		( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
215
216
 #define X86_FEATURE_USE_IBRS_FW		( 7*32+22) /* "" Use IBRS during runtime firmware calls */
216
217
 #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* "" Disable Speculative Store Bypass. */
..
..
@@ -218,9 +219,10 @@
218
219
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
219
220
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
220
221
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
221
-#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
222
+#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
222
223
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
223
224
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
225
+#define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
224
226
 
225
227
 /* Virtualization flags: Linux defined, word 8 */
226
228
 #define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */
..
..
@@ -232,6 +234,8 @@
232
234
 #define X86_FEATURE_VMMCALL		( 8*32+15) /* Prefer VMMCALL to VMCALL */
233
235
 #define X86_FEATURE_XENPV		( 8*32+16) /* "" Xen paravirtual guest */
234
236
 #define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */
237
+#define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
238
+#define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
235
239
 
236
240
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
237
241
 #define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
..
..
@@ -239,12 +243,14 @@
239
243
 #define X86_FEATURE_BMI1		( 9*32+ 3) /* 1st group bit manipulation extensions */
240
244
 #define X86_FEATURE_HLE			( 9*32+ 4) /* Hardware Lock Elision */
241
245
 #define X86_FEATURE_AVX2		( 9*32+ 5) /* AVX2 instructions */
246
+#define X86_FEATURE_FDP_EXCPTN_ONLY	( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */
242
247
 #define X86_FEATURE_SMEP		( 9*32+ 7) /* Supervisor Mode Execution Protection */
243
248
 #define X86_FEATURE_BMI2		( 9*32+ 8) /* 2nd group bit manipulation extensions */
244
249
 #define X86_FEATURE_ERMS		( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */
245
250
 #define X86_FEATURE_INVPCID		( 9*32+10) /* Invalidate Processor Context ID */
246
251
 #define X86_FEATURE_RTM			( 9*32+11) /* Restricted Transactional Memory */
247
252
 #define X86_FEATURE_CQM			( 9*32+12) /* Cache QoS Monitoring */
253
+#define X86_FEATURE_ZERO_FCS_FDS	( 9*32+13) /* "" Zero out FPU CS and FPU DS */
248
254
 #define X86_FEATURE_MPX			( 9*32+14) /* Memory Protection Extension */
249
255
 #define X86_FEATURE_RDT_A		( 9*32+15) /* Resource Director Technology Allocation */
250
256
 #define X86_FEATURE_AVX512F		( 9*32+16) /* AVX-512 Foundation */
..
..
@@ -269,24 +275,47 @@
269
275
 #define X86_FEATURE_XGETBV1		(10*32+ 2) /* XGETBV with ECX = 1 instruction */
270
276
 #define X86_FEATURE_XSAVES		(10*32+ 3) /* XSAVES/XRSTORS instructions */
271
277
 
272
-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */
273
-#define X86_FEATURE_CQM_LLC		(11*32+ 1) /* LLC QoS if 1 */
278
+/*
279
+ * Extended auxiliary flags: Linux defined - for features scattered in various
280
+ * CPUID levels like 0xf, etc.
281
+ *
282
+ * Reuse free bits when adding new feature flags!
283
+ */
284
+#define X86_FEATURE_CQM_LLC		(11*32+ 0) /* LLC QoS if 1 */
285
+#define X86_FEATURE_CQM_OCCUP_LLC	(11*32+ 1) /* LLC occupancy monitoring */
286
+#define X86_FEATURE_CQM_MBM_TOTAL	(11*32+ 2) /* LLC Total MBM monitoring */
287
+#define X86_FEATURE_CQM_MBM_LOCAL	(11*32+ 3) /* LLC Local MBM monitoring */
288
+#define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
289
+#define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
290
+#define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split lock */
291
+#define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
292
+#define X86_FEATURE_ENTRY_IBPB		(11*32+10) /* "" Issue an IBPB on kernel entry */
293
+#define X86_FEATURE_RRSBA_CTRL		(11*32+11) /* "" RET prediction control */
294
+#define X86_FEATURE_RETPOLINE		(11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
295
+#define X86_FEATURE_RETPOLINE_LFENCE	(11*32+13) /* "" Use LFENCE for Spectre variant 2 */
296
+#define X86_FEATURE_RETHUNK		(11*32+14) /* "" Use REturn THUNK */
297
+#define X86_FEATURE_UNRET		(11*32+15) /* "" AMD BTB untrain return */
298
+#define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM-Exit when EIBRS is enabled */
274
299
 
275
-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */
276
-#define X86_FEATURE_CQM_OCCUP_LLC	(12*32+ 0) /* LLC occupancy monitoring */
277
-#define X86_FEATURE_CQM_MBM_TOTAL	(12*32+ 1) /* LLC Total MBM monitoring */
278
-#define X86_FEATURE_CQM_MBM_LOCAL	(12*32+ 2) /* LLC Local MBM monitoring */
300
+/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
301
+#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
302
+#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
279
303
 
280
304
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
281
305
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
282
306
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
283
307
 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
308
+#define X86_FEATURE_RDPRU		(13*32+ 4) /* Read processor register at user level */
309
+#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */
284
310
 #define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */
285
311
 #define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */
286
312
 #define X86_FEATURE_AMD_STIBP		(13*32+15) /* "" Single Thread Indirect Branch Predictors */
313
+#define X86_FEATURE_AMD_STIBP_ALWAYS_ON	(13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
314
+#define X86_FEATURE_AMD_PPIN		(13*32+23) /* Protected Processor Inventory Number */
287
315
 #define X86_FEATURE_AMD_SSBD		(13*32+24) /* "" Speculative Store Bypass Disable */
288
316
 #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */
289
317
 #define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
318
+#define X86_FEATURE_BTC_NO		(13*32+29) /* "" Not vulnerable to Branch Type Confusion */
290
319
 
291
320
 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
292
321
 #define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */
..
..
@@ -314,12 +343,14 @@
314
343
 #define X86_FEATURE_AVIC		(15*32+13) /* Virtual Interrupt Controller */
315
344
 #define X86_FEATURE_V_VMSAVE_VMLOAD	(15*32+15) /* Virtual VMSAVE VMLOAD */
316
345
 #define X86_FEATURE_VGIF		(15*32+16) /* Virtual GIF */
346
+#define X86_FEATURE_SVME_ADDR_CHK	(15*32+28) /* "" SVME addr check */
317
347
 
318
348
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
319
349
 #define X86_FEATURE_AVX512VBMI		(16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
320
350
 #define X86_FEATURE_UMIP		(16*32+ 2) /* User Mode Instruction Protection */
321
351
 #define X86_FEATURE_PKU			(16*32+ 3) /* Protection Keys for Userspace */
322
352
 #define X86_FEATURE_OSPKE		(16*32+ 4) /* OS Protection Keys Enable */
353
+#define X86_FEATURE_WAITPKG		(16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
323
354
 #define X86_FEATURE_AVX512_VBMI2	(16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
324
355
 #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
325
356
 #define X86_FEATURE_VAES		(16*32+ 9) /* Vector AES */
..
..
@@ -331,6 +362,9 @@
331
362
 #define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */
332
363
 #define X86_FEATURE_RDPID		(16*32+22) /* RDPID instruction */
333
364
 #define X86_FEATURE_CLDEMOTE		(16*32+25) /* CLDEMOTE instruction */
365
+#define X86_FEATURE_MOVDIRI		(16*32+27) /* MOVDIRI instruction */
366
+#define X86_FEATURE_MOVDIR64B		(16*32+28) /* MOVDIR64B instruction */
367
+#define X86_FEATURE_ENQCMD		(16*32+29) /* ENQCMD and ENQCMDS instructions */
334
368
 
335
369
 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
336
370
 #define X86_FEATURE_OVERFLOW_RECOV	(17*32+ 0) /* MCA overflow recovery support */
..
..
@@ -340,12 +374,28 @@
340
374
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
341
375
 #define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */
342
376
 #define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
377
+#define X86_FEATURE_FSRM		(18*32+ 4) /* Fast Short Rep Mov */
378
+#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
379
+#define X86_FEATURE_SRBDS_CTRL		(18*32+ 9) /* "" SRBDS mitigation MSR available */
380
+#define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
381
+#define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
382
+#define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
383
+#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */
343
384
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
385
+#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
344
386
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
345
387
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
346
388
 #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */
347
389
 #define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
390
+#define X86_FEATURE_CORE_CAPABILITIES	(18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
348
391
 #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */
392
+
393
+/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
394
+#define X86_FEATURE_SME			(19*32+ 0) /* AMD Secure Memory Encryption */
395
+#define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */
396
+#define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */
397
+#define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
398
+#define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
349
399
 
350
400
 /*
351
401
  * BUG word(s)
..
..
@@ -377,5 +427,13 @@
377
427
 #define X86_BUG_SPECTRE_V2		X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
378
428
 #define X86_BUG_SPEC_STORE_BYPASS	X86_BUG(17) /* CPU is affected by speculative store bypass attack */
379
429
 #define X86_BUG_L1TF			X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
430
+#define X86_BUG_MDS			X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
431
+#define X86_BUG_MSBDS_ONLY		X86_BUG(20) /* CPU is only affected by the  MSDBS variant of BUG_MDS */
432
+#define X86_BUG_SWAPGS			X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
433
+#define X86_BUG_TAA			X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
434
+#define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
435
+#define X86_BUG_SRBDS			X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
436
+#define X86_BUG_MMIO_STALE_DATA		X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
437
+#define X86_BUG_RETBLEED		X86_BUG(26) /* CPU is affected by RETBleed */
380
438
 
381
439
 #endif /* _ASM_X86_CPUFEATURES_H */