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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/sound/soc/qcom/lpass.h
....@@ -1,14 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
2
- * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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+ * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
124  *
135  * lpass.h - Definitions for the QTi LPASS
146  */
....@@ -20,10 +12,45 @@
2012 #include <linux/compiler.h>
2113 #include <linux/platform_device.h>
2214 #include <linux/regmap.h>
15
+#include <dt-bindings/sound/qcom,lpass.h>
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+#include "lpass-hdmi.h"
2317 
2418 #define LPASS_AHBIX_CLOCK_FREQUENCY		131072000
2519 #define LPASS_MAX_MI2S_PORTS			(8)
2620 #define LPASS_MAX_DMA_CHANNELS			(8)
21
+#define LPASS_MAX_HDMI_DMA_CHANNELS		(4)
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+
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+#define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf)    \
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+	do { \
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+		mf = devm_regmap_field_alloc(d, m, f);     \
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+		if (IS_ERR(mf))                \
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+			return -EINVAL;         \
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+	} while (0)
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+
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+struct lpaif_i2sctl {
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+	struct regmap_field *loopback;
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+	struct regmap_field *spken;
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+	struct regmap_field *spkmode;
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+	struct regmap_field *spkmono;
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+	struct regmap_field *micen;
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+	struct regmap_field *micmode;
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+	struct regmap_field *micmono;
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+	struct regmap_field *wssrc;
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+	struct regmap_field *bitwidth;
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+};
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+
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+
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+struct lpaif_dmactl {
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+	struct regmap_field *intf;
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+	struct regmap_field *bursten;
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+	struct regmap_field *wpscnt;
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+	struct regmap_field *fifowm;
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+	struct regmap_field *enable;
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+	struct regmap_field *dyncclk;
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+	struct regmap_field *burst8;
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+	struct regmap_field *burst16;
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+	struct regmap_field *dynburst;
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+};
2754 
2855 /* Both the CPU DAI and platform drivers will access this data */
2956 struct lpass_data {
....@@ -37,44 +64,174 @@
3764 	/* MI2S bit clock (derived from system clock by a divider */
3865 	struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS];
3966 
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+	/* MI2S SD lines to use for playback/capture */
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+	unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS];
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+	unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS];
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+
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+	/* The state of MI2S prepare dai_ops was called */
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+	bool mi2s_was_prepared[LPASS_MAX_MI2S_PORTS];
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+
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+	int hdmi_port_enable;
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+
4076 	/* low-power audio interface (LPAIF) registers */
4177 	void __iomem *lpaif;
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+	void __iomem *hdmiif;
4279 
4380 	/* regmap backed by the low-power audio interface (LPAIF) registers */
4481 	struct regmap *lpaif_map;
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+	struct regmap *hdmiif_map;
4583 
4684 	/* interrupts from the low-power audio interface (LPAIF) */
4785 	int lpaif_irq;
48
-
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+	int hdmiif_irq;
4987 	/* SOC specific variations in the LPASS IP integration */
5088 	struct lpass_variant *variant;
5189 
5290 	/* bit map to keep track of static channel allocations */
5391 	unsigned long dma_ch_bit_map;
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+	unsigned long hdmi_dma_ch_bit_map;
5493 
5594 	/* used it for handling interrupt per dma channel */
5695 	struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
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+	struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS];
5797 
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-	/* 8016 specific */
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-	struct clk *pcnoc_mport_clk;
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-	struct clk *pcnoc_sway_clk;
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+	/* SOC specific clock list */
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+	struct clk_bulk_data *clks;
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+	int num_clks;
61101 
102
+	/* Regmap fields of I2SCTL & DMACTL registers bitfields */
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+	struct lpaif_i2sctl *i2sctl;
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+	struct lpaif_dmactl *rd_dmactl;
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+	struct lpaif_dmactl *wr_dmactl;
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+	struct lpaif_dmactl *hdmi_rd_dmactl;
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+	/* Regmap fields of HDMI_CTRL registers*/
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+	struct regmap_field *hdmitx_legacy_en;
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+	struct regmap_field *hdmitx_parity_calc_en;
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+	struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS];
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+	struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS];
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+	struct lpass_hdmi_tx_ctl *tx_ctl;
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+	struct lpass_vbit_ctrl *vbit_ctl;
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+	struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS];
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+	struct lpass_dp_metadata_ctl *meta_ctl;
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+	struct lpass_sstream_ctl *sstream_ctl;
62117 };
63118 
64119 /* Vairant data per each SOC */
65120 struct lpass_variant {
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-	u32	i2sctrl_reg_base;
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-	u32	i2sctrl_reg_stride;
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-	u32	i2s_ports;
69121 	u32	irq_reg_base;
70122 	u32	irq_reg_stride;
71123 	u32	irq_ports;
72124 	u32	rdma_reg_base;
73125 	u32	rdma_reg_stride;
74126 	u32	rdma_channels;
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+	u32	hdmi_rdma_reg_base;
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+	u32	hdmi_rdma_reg_stride;
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+	u32	hdmi_rdma_channels;
75130 	u32	wrdma_reg_base;
76131 	u32	wrdma_reg_stride;
77132 	u32	wrdma_channels;
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+	u32	i2sctrl_reg_base;
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+	u32	i2sctrl_reg_stride;
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+	u32	i2s_ports;
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+
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+	/* I2SCTL Register fields */
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+	struct reg_field loopback;
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+	struct reg_field spken;
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+	struct reg_field spkmode;
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+	struct reg_field spkmono;
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+	struct reg_field micen;
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+	struct reg_field micmode;
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+	struct reg_field micmono;
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+	struct reg_field wssrc;
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+	struct reg_field bitwidth;
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+
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+	u32	hdmi_irq_reg_base;
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+	u32	hdmi_irq_reg_stride;
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+	u32	hdmi_irq_ports;
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+
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+	/* HDMI specific controls */
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+	u32	hdmi_tx_ctl_addr;
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+	u32	hdmi_legacy_addr;
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+	u32	hdmi_vbit_addr;
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+	u32	hdmi_ch_lsb_addr;
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+	u32	hdmi_ch_msb_addr;
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+	u32	ch_stride;
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+	u32	hdmi_parity_addr;
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+	u32	hdmi_dmactl_addr;
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+	u32	hdmi_dma_stride;
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+	u32	hdmi_DP_addr;
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+	u32	hdmi_sstream_addr;
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+
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+	/* HDMI SSTREAM CTRL fields  */
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+	struct reg_field sstream_en;
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+	struct reg_field dma_sel;
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+	struct reg_field auto_bbit_en;
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+	struct reg_field layout;
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+	struct reg_field layout_sp;
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+	struct reg_field set_sp_on_en;
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+	struct reg_field dp_audio;
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+	struct reg_field dp_staffing_en;
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+	struct reg_field dp_sp_b_hw_en;
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+
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+	/* HDMI DP METADATA CTL fields */
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+	struct reg_field mute;
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+	struct reg_field as_sdp_cc;
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+	struct reg_field as_sdp_ct;
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+	struct reg_field aif_db4;
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+	struct reg_field frequency;
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+	struct reg_field mst_index;
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+	struct reg_field dptx_index;
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+
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+	/* HDMI TX CTRL fields */
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+	struct reg_field soft_reset;
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+	struct reg_field force_reset;
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+
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+	/* HDMI TX DMA CTRL */
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+	struct reg_field use_hw_chs;
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+	struct reg_field use_hw_usr;
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+	struct reg_field hw_chs_sel;
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+	struct reg_field hw_usr_sel;
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+
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+	/* HDMI VBIT CTRL */
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+	struct reg_field replace_vbit;
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+	struct reg_field vbit_stream;
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+
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+	/* HDMI TX LEGACY */
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+	struct reg_field legacy_en;
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+
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+	/* HDMI TX PARITY */
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+	struct reg_field calc_en;
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+
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+	/* HDMI CH LSB */
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+	struct reg_field lsb_bits;
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+
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+	/* HDMI CH MSB */
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+	struct reg_field msb_bits;
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+
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+	struct reg_field hdmi_rdma_bursten;
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+	struct reg_field hdmi_rdma_wpscnt;
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+	struct reg_field hdmi_rdma_fifowm;
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+	struct reg_field hdmi_rdma_enable;
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+	struct reg_field hdmi_rdma_dyncclk;
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+	struct reg_field hdmi_rdma_burst8;
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+	struct reg_field hdmi_rdma_burst16;
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+	struct reg_field hdmi_rdma_dynburst;
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+
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+	/* RD_DMA Register fields */
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+	struct reg_field rdma_intf;
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+	struct reg_field rdma_bursten;
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+	struct reg_field rdma_wpscnt;
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+	struct reg_field rdma_fifowm;
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+	struct reg_field rdma_enable;
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+	struct reg_field rdma_dyncclk;
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+
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+	/* WR_DMA Register fields */
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+	struct reg_field wrdma_intf;
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+	struct reg_field wrdma_bursten;
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+	struct reg_field wrdma_wpscnt;
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+	struct reg_field wrdma_fifowm;
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+	struct reg_field wrdma_enable;
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+	struct reg_field wrdma_dyncclk;
78235 
79236 	/**
80237 	 * on SOCs like APQ8016 the channel control bits start
....@@ -85,14 +242,18 @@
85242 	/* SOC specific initialization like clocks */
86243 	int (*init)(struct platform_device *pdev);
87244 	int (*exit)(struct platform_device *pdev);
88
-	int (*alloc_dma_channel)(struct lpass_data *data, int direction);
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-	int (*free_dma_channel)(struct lpass_data *data, int ch);
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+	int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id);
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+	int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id);
90247 
91248 	/* SOC specific dais */
92249 	struct snd_soc_dai_driver *dai_driver;
93250 	int num_dai;
94251 	const char * const *dai_osr_clk_names;
95252 	const char * const *dai_bit_clk_names;
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+
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+	/* SOC specific clocks configuration */
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+	const char **clk_name;
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+	int num_clks;
96257 };
97258 
98259 /* register the platform driver from the CPU DAI driver */