add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/sound/hda/hdac_stream.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * HD-audio stream operations
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  */
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@@ -11,6 +12,40 @@
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 #include <sound/hdaudio.h>
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 #include <sound/hda_register.h>
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 #include "trace.h"
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+
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+/**
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+ * snd_hdac_get_stream_stripe_ctl - get stripe control value
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+ * @bus: HD-audio core bus
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+ * @substream: PCM substream
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+ */
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+int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
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+				   struct snd_pcm_substream *substream)
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+{
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+	struct snd_pcm_runtime *runtime = substream->runtime;
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+	unsigned int channels = runtime->channels,
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+		     rate = runtime->rate,
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+		     bits_per_sample = runtime->sample_bits,
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+		     max_sdo_lines, value, sdo_line;
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+
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+	/* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
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+	max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
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+
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+	/* following is from HD audio spec */
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+	for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
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+		if (rate > 48000)
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+			value = (channels * bits_per_sample *
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+					(rate / 48000)) / sdo_line;
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+		else
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+			value = (channels * bits_per_sample) / sdo_line;
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+
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+		if (value >= bus->sdo_limit)
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+			break;
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+	}
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+
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+	/* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
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+	return sdo_line >> 1;
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+}
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+EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
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 /**
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  * snd_hdac_stream_init - initialize each stream (aka device)
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@@ -48,6 +83,7 @@
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 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
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 {
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 	struct hdac_bus *bus = azx_dev->bus;
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+	int stripe_ctl;
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 	trace_snd_hdac_stream_start(bus, azx_dev);
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@@ -56,7 +92,18 @@
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 		azx_dev->start_wallclk -= azx_dev->period_wallclk;
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93
 
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 	/* enable SIE */
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-	snd_hdac_chip_updatel(bus, INTCTL, 0, 1 << azx_dev->index);
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+	snd_hdac_chip_updatel(bus, INTCTL,
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+			      1 << azx_dev->index,
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+			      1 << azx_dev->index);
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+	/* set stripe control */
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+	if (azx_dev->stripe) {
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+		if (azx_dev->substream)
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+			stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
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+		else
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+			stripe_ctl = 0;
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+		snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
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+					stripe_ctl);
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+	}
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 	/* set DMA start and interrupt mask */
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 	snd_hdac_stream_updateb(azx_dev, SD_CTL,
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 				0, SD_CTL_DMA_START | SD_INT_MASK);
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@@ -73,6 +120,8 @@
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 	snd_hdac_stream_updateb(azx_dev, SD_CTL,
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 				SD_CTL_DMA_START | SD_INT_MASK, 0);
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 	snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
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+	if (azx_dev->stripe)
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+		snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
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 	azx_dev->running = false;
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 }
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 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
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@@ -94,6 +143,33 @@
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 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
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 /**
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+ * snd_hdac_stop_streams - stop all streams
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+ * @bus: HD-audio core bus
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+ */
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+void snd_hdac_stop_streams(struct hdac_bus *bus)
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+{
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+	struct hdac_stream *stream;
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+
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+	list_for_each_entry(stream, &bus->stream_list, list)
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+		snd_hdac_stream_stop(stream);
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+}
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+EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
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+
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+/**
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+ * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
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+ * @bus: HD-audio core bus
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+ */
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+void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
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+{
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+
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+	if (bus->chip_init) {
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+		snd_hdac_stop_streams(bus);
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+		snd_hdac_bus_stop_chip(bus);
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+	}
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+}
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+EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
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+
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+/**
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  * snd_hdac_stream_reset - reset a stream
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  * @azx_dev: HD-audio core stream to reset
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  */
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@@ -101,8 +177,11 @@
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 {
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 	unsigned char val;
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 	int timeout;
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+	int dma_run_state;
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 	snd_hdac_stream_clear(azx_dev);
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+
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+	dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
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 	snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
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 	udelay(3);
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@@ -113,6 +192,10 @@
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 		if (val)
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 			break;
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 	} while (--timeout);
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+
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+	if (azx_dev->bus->dma_stop_delay && dma_run_state)
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+		udelay(azx_dev->bus->dma_stop_delay);
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+
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 	val &= ~SD_CTL_STREAM_RESET;
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 	snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
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 	udelay(3);
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@@ -183,11 +266,7 @@
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 	/* set the interrupt enable bits in the descriptor control register */
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 	snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
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-	if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
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-		azx_dev->fifo_size =
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-			snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
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-	else
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-		azx_dev->fifo_size = 0;
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+	azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
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 	/* when LPIB delay correction gives a small negative value,
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 	 * we ignore it; currently set the threshold statically to
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@@ -244,6 +323,7 @@
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 	int key = (substream->pcm->device << 16) | (substream->number << 2) |
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 		(substream->stream + 1);
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+	spin_lock_irq(&bus->reg_lock);
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 	list_for_each_entry(azx_dev, &bus->stream_list, list) {
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 		if (azx_dev->direction != substream->stream)
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 			continue;
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@@ -257,13 +337,12 @@
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 			res = azx_dev;
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 	}
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 	if (res) {
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-		spin_lock_irq(&bus->reg_lock);
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 		res->opened = 1;
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 		res->running = 0;
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 		res->assigned_key = key;
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 		res->substream = substream;
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-		spin_unlock_irq(&bus->reg_lock);
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 	}
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+	spin_unlock_irq(&bus->reg_lock);
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 	return res;
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 }
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 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
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@@ -545,7 +624,9 @@
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 /**
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  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
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  * @azx_dev: HD-audio core stream (master stream)
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+ * @set: true = set, false = clear
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  * @streams: bit flags of streams to sync
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+ * @reg: the stream sync register address
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  */
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 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
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 				  unsigned int streams, unsigned int reg)
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@@ -584,20 +665,27 @@
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 		nwait = 0;
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 		i = 0;
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 		list_for_each_entry(s, &bus->stream_list, list) {
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-			if (streams & (1 << i)) {
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-				if (start) {
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-					/* check FIFO gets ready */
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-					if (!(snd_hdac_stream_readb(s, SD_STS) &
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-					      SD_STS_FIFO_READY))
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-						nwait++;
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-				} else {
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-					/* check RUN bit is cleared */
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-					if (snd_hdac_stream_readb(s, SD_CTL) &
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-					    SD_CTL_DMA_START)
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-						nwait++;
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+			if (!(streams & (1 << i++)))
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+				continue;
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+
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+			if (start) {
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+				/* check FIFO gets ready */
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+				if (!(snd_hdac_stream_readb(s, SD_STS) &
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+				      SD_STS_FIFO_READY))
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+					nwait++;
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+			} else {
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+				/* check RUN bit is cleared */
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+				if (snd_hdac_stream_readb(s, SD_CTL) &
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+				    SD_CTL_DMA_START) {
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+					nwait++;
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+					/*
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+					 * Perform stream reset if DMA RUN
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+					 * bit not cleared within given timeout
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+					 */
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+					if (timeout == 1)
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+						snd_hdac_stream_reset(s);
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 				}
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 			}
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-			i++;
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 		}
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 		if (!nwait)
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 			break;
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@@ -634,8 +722,8 @@
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 	azx_dev->locked = true;
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 	spin_unlock_irq(&bus->reg_lock);
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724
 
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-	err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG,
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-					   byte_size, bufp);
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+	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
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+				  byte_size, bufp);
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 	if (err < 0)
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 		goto err_alloc;
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@@ -661,7 +749,7 @@
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 	return azx_dev->stream_tag;
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  error:
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-	bus->io_ops->dma_free_pages(bus, bufp);
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+	snd_dma_free_pages(bufp);
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  err_alloc:
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 	spin_lock_irq(&bus->reg_lock);
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 	azx_dev->locked = false;
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@@ -708,7 +796,7 @@
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 	azx_dev->period_bytes = 0;
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 	azx_dev->format_val = 0;
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-	bus->io_ops->dma_free_pages(bus, dmab);
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+	snd_dma_free_pages(dmab);
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 	dmab->area = NULL;
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 	spin_lock_irq(&bus->reg_lock);