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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/include/linux/mfd/rohm-bd718x7.h
....@@ -1,112 +1,122 @@
11 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 /* Copyright (C) 2018 ROHM Semiconductors */
33 
4
-#ifndef __LINUX_MFD_BD71837_H__
5
-#define __LINUX_MFD_BD71837_H__
4
+#ifndef __LINUX_MFD_BD718XX_H__
5
+#define __LINUX_MFD_BD718XX_H__
66 
7
+#include <linux/mfd/rohm-generic.h>
78 #include <linux/regmap.h>
89 
910 enum {
10
-	BD71837_BUCK1	=	0,
11
-	BD71837_BUCK2,
12
-	BD71837_BUCK3,
13
-	BD71837_BUCK4,
14
-	BD71837_BUCK5,
15
-	BD71837_BUCK6,
16
-	BD71837_BUCK7,
17
-	BD71837_BUCK8,
18
-	BD71837_LDO1,
19
-	BD71837_LDO2,
20
-	BD71837_LDO3,
21
-	BD71837_LDO4,
22
-	BD71837_LDO5,
23
-	BD71837_LDO6,
24
-	BD71837_LDO7,
25
-	BD71837_REGULATOR_CNT,
11
+	BD718XX_BUCK1 = 0,
12
+	BD718XX_BUCK2,
13
+	BD718XX_BUCK3,
14
+	BD718XX_BUCK4,
15
+	BD718XX_BUCK5,
16
+	BD718XX_BUCK6,
17
+	BD718XX_BUCK7,
18
+	BD718XX_BUCK8,
19
+	BD718XX_LDO1,
20
+	BD718XX_LDO2,
21
+	BD718XX_LDO3,
22
+	BD718XX_LDO4,
23
+	BD718XX_LDO5,
24
+	BD718XX_LDO6,
25
+	BD718XX_LDO7,
26
+	BD718XX_REGULATOR_AMOUNT,
2627 };
2728 
28
-#define BD71837_BUCK1_VOLTAGE_NUM	0x40
29
-#define BD71837_BUCK2_VOLTAGE_NUM	0x40
30
-#define BD71837_BUCK3_VOLTAGE_NUM	0x40
31
-#define BD71837_BUCK4_VOLTAGE_NUM	0x40
29
+/* Common voltage configurations */
30
+#define BD718XX_DVS_BUCK_VOLTAGE_NUM		0x3D
31
+#define BD718XX_4TH_NODVS_BUCK_VOLTAGE_NUM	0x3D
3232 
33
-#define BD71837_BUCK5_VOLTAGE_NUM	0x08
33
+#define BD718XX_LDO1_VOLTAGE_NUM	0x08
34
+#define BD718XX_LDO2_VOLTAGE_NUM	0x02
35
+#define BD718XX_LDO3_VOLTAGE_NUM	0x10
36
+#define BD718XX_LDO4_VOLTAGE_NUM	0x0A
37
+#define BD718XX_LDO6_VOLTAGE_NUM	0x0A
38
+
39
+/* BD71837 specific voltage configurations */
40
+#define BD71837_BUCK5_VOLTAGE_NUM	0x10
3441 #define BD71837_BUCK6_VOLTAGE_NUM	0x04
3542 #define BD71837_BUCK7_VOLTAGE_NUM	0x08
36
-#define BD71837_BUCK8_VOLTAGE_NUM	0x40
37
-
38
-#define BD71837_LDO1_VOLTAGE_NUM	0x04
39
-#define BD71837_LDO2_VOLTAGE_NUM	0x02
40
-#define BD71837_LDO3_VOLTAGE_NUM	0x10
41
-#define BD71837_LDO4_VOLTAGE_NUM	0x10
4243 #define BD71837_LDO5_VOLTAGE_NUM	0x10
43
-#define BD71837_LDO6_VOLTAGE_NUM	0x10
4444 #define BD71837_LDO7_VOLTAGE_NUM	0x10
4545 
46
+/* BD71847 specific voltage configurations */
47
+#define BD71847_BUCK3_VOLTAGE_NUM	0x18
48
+#define BD71847_BUCK4_VOLTAGE_NUM	0x08
49
+#define BD71847_LDO5_VOLTAGE_NUM	0x20
50
+
51
+/* Registers specific to BD71837 */
4652 enum {
47
-	BD71837_REG_REV                = 0x00,
48
-	BD71837_REG_SWRESET            = 0x01,
49
-	BD71837_REG_I2C_DEV            = 0x02,
50
-	BD71837_REG_PWRCTRL0           = 0x03,
51
-	BD71837_REG_PWRCTRL1           = 0x04,
52
-	BD71837_REG_BUCK1_CTRL         = 0x05,
53
-	BD71837_REG_BUCK2_CTRL         = 0x06,
54
-	BD71837_REG_BUCK3_CTRL         = 0x07,
55
-	BD71837_REG_BUCK4_CTRL         = 0x08,
56
-	BD71837_REG_BUCK5_CTRL         = 0x09,
57
-	BD71837_REG_BUCK6_CTRL         = 0x0A,
58
-	BD71837_REG_BUCK7_CTRL         = 0x0B,
59
-	BD71837_REG_BUCK8_CTRL         = 0x0C,
60
-	BD71837_REG_BUCK1_VOLT_RUN     = 0x0D,
61
-	BD71837_REG_BUCK1_VOLT_IDLE    = 0x0E,
62
-	BD71837_REG_BUCK1_VOLT_SUSP    = 0x0F,
63
-	BD71837_REG_BUCK2_VOLT_RUN     = 0x10,
64
-	BD71837_REG_BUCK2_VOLT_IDLE    = 0x11,
65
-	BD71837_REG_BUCK3_VOLT_RUN     = 0x12,
66
-	BD71837_REG_BUCK4_VOLT_RUN     = 0x13,
67
-	BD71837_REG_BUCK5_VOLT         = 0x14,
68
-	BD71837_REG_BUCK6_VOLT         = 0x15,
69
-	BD71837_REG_BUCK7_VOLT         = 0x16,
70
-	BD71837_REG_BUCK8_VOLT         = 0x17,
71
-	BD71837_REG_LDO1_VOLT          = 0x18,
72
-	BD71837_REG_LDO2_VOLT          = 0x19,
73
-	BD71837_REG_LDO3_VOLT          = 0x1A,
74
-	BD71837_REG_LDO4_VOLT          = 0x1B,
75
-	BD71837_REG_LDO5_VOLT          = 0x1C,
76
-	BD71837_REG_LDO6_VOLT          = 0x1D,
77
-	BD71837_REG_LDO7_VOLT          = 0x1E,
78
-	BD71837_REG_TRANS_COND0        = 0x1F,
79
-	BD71837_REG_TRANS_COND1        = 0x20,
80
-	BD71837_REG_VRFAULTEN          = 0x21,
81
-	BD718XX_REG_MVRFLTMASK0        = 0x22,
82
-	BD718XX_REG_MVRFLTMASK1        = 0x23,
83
-	BD718XX_REG_MVRFLTMASK2        = 0x24,
84
-	BD71837_REG_RCVCFG             = 0x25,
85
-	BD71837_REG_RCVNUM             = 0x26,
86
-	BD71837_REG_PWRONCONFIG0       = 0x27,
87
-	BD71837_REG_PWRONCONFIG1       = 0x28,
88
-	BD71837_REG_RESETSRC           = 0x29,
89
-	BD71837_REG_MIRQ               = 0x2A,
90
-	BD71837_REG_IRQ                = 0x2B,
91
-	BD71837_REG_IN_MON             = 0x2C,
92
-	BD71837_REG_POW_STATE          = 0x2D,
93
-	BD71837_REG_OUT32K             = 0x2E,
94
-	BD71837_REG_REGLOCK            = 0x2F,
95
-	BD71837_REG_OTPVER             = 0xFF,
96
-	BD71837_MAX_REGISTER           = 0x100,
53
+	BD71837_REG_BUCK3_CTRL =	0x07,
54
+	BD71837_REG_BUCK4_CTRL =	0x08,
55
+	BD71837_REG_BUCK3_VOLT_RUN =	0x12,
56
+	BD71837_REG_BUCK4_VOLT_RUN =	0x13,
57
+	BD71837_REG_LDO7_VOLT =		0x1E,
58
+};
59
+
60
+/* Registers common for BD71837 and BD71847 */
61
+enum {
62
+	BD718XX_REG_REV =			0x00,
63
+	BD718XX_REG_SWRESET =			0x01,
64
+	BD718XX_REG_I2C_DEV =			0x02,
65
+	BD718XX_REG_PWRCTRL0 =			0x03,
66
+	BD718XX_REG_PWRCTRL1 =			0x04,
67
+	BD718XX_REG_BUCK1_CTRL =		0x05,
68
+	BD718XX_REG_BUCK2_CTRL =		0x06,
69
+	BD718XX_REG_1ST_NODVS_BUCK_CTRL =	0x09,
70
+	BD718XX_REG_2ND_NODVS_BUCK_CTRL =	0x0A,
71
+	BD718XX_REG_3RD_NODVS_BUCK_CTRL =	0x0B,
72
+	BD718XX_REG_4TH_NODVS_BUCK_CTRL =	0x0C,
73
+	BD718XX_REG_BUCK1_VOLT_RUN =		0x0D,
74
+	BD718XX_REG_BUCK1_VOLT_IDLE =		0x0E,
75
+	BD718XX_REG_BUCK1_VOLT_SUSP =		0x0F,
76
+	BD718XX_REG_BUCK2_VOLT_RUN =		0x10,
77
+	BD718XX_REG_BUCK2_VOLT_IDLE =		0x11,
78
+	BD718XX_REG_1ST_NODVS_BUCK_VOLT =	0x14,
79
+	BD718XX_REG_2ND_NODVS_BUCK_VOLT =	0x15,
80
+	BD718XX_REG_3RD_NODVS_BUCK_VOLT =	0x16,
81
+	BD718XX_REG_4TH_NODVS_BUCK_VOLT =	0x17,
82
+	BD718XX_REG_LDO1_VOLT =			0x18,
83
+	BD718XX_REG_LDO2_VOLT =			0x19,
84
+	BD718XX_REG_LDO3_VOLT =			0x1A,
85
+	BD718XX_REG_LDO4_VOLT =			0x1B,
86
+	BD718XX_REG_LDO5_VOLT =			0x1C,
87
+	BD718XX_REG_LDO6_VOLT =			0x1D,
88
+	BD718XX_REG_TRANS_COND0 =		0x1F,
89
+	BD718XX_REG_TRANS_COND1 =		0x20,
90
+	BD718XX_REG_VRFAULTEN =			0x21,
91
+	BD718XX_REG_MVRFLTMASK0 =		0x22,
92
+	BD718XX_REG_MVRFLTMASK1 =		0x23,
93
+	BD718XX_REG_MVRFLTMASK2 =		0x24,
94
+	BD718XX_REG_RCVCFG =			0x25,
95
+	BD718XX_REG_RCVNUM =			0x26,
96
+	BD718XX_REG_PWRONCONFIG0 =		0x27,
97
+	BD718XX_REG_PWRONCONFIG1 =		0x28,
98
+	BD718XX_REG_RESETSRC =			0x29,
99
+	BD718XX_REG_MIRQ =			0x2A,
100
+	BD718XX_REG_IRQ =			0x2B,
101
+	BD718XX_REG_IN_MON =			0x2C,
102
+	BD718XX_REG_POW_STATE =			0x2D,
103
+	BD718XX_REG_OUT32K =			0x2E,
104
+	BD718XX_REG_REGLOCK =			0x2F,
105
+	BD718XX_REG_OTPVER =			0xFF,
106
+	BD718XX_MAX_REGISTER =			0x100,
97107 };
98108 
99109 #define REGLOCK_PWRSEQ	0x1
100110 #define REGLOCK_VREG	0x10
101111 
102112 /* Generic BUCK control masks */
103
-#define BD71837_BUCK_SEL	0x02
104
-#define BD71837_BUCK_EN		0x01
105
-#define BD71837_BUCK_RUN_ON	0x04
113
+#define BD718XX_BUCK_SEL	0x02
114
+#define BD718XX_BUCK_EN		0x01
115
+#define BD718XX_BUCK_RUN_ON	0x04
106116 
107117 /* Generic LDO masks */
108
-#define BD71837_LDO_SEL		0x80
109
-#define BD71837_LDO_EN		0x40
118
+#define BD718XX_LDO_SEL		0x80
119
+#define BD718XX_LDO_EN		0x40
110120 
111121 /* BD71837 BUCK ramp rate CTRL reg bits */
112122 #define BUCK_RAMPRATE_MASK	0xC0
....@@ -115,49 +125,35 @@
115125 #define BUCK_RAMPRATE_2P50MV	0x2
116126 #define BUCK_RAMPRATE_1P25MV	0x3
117127 
118
-/* BD71837_REG_BUCK1_VOLT_RUN bits */
119
-#define BUCK1_RUN_MASK		0x3F
120
-#define BUCK1_RUN_DEFAULT	0x14
128
+#define DVS_BUCK_RUN_MASK	0x3F
129
+#define DVS_BUCK_SUSP_MASK	0x3F
130
+#define DVS_BUCK_IDLE_MASK	0x3F
121131 
122
-/* BD71837_REG_BUCK1_VOLT_SUSP bits */
123
-#define BUCK1_SUSP_MASK		0x3F
124
-#define BUCK1_SUSP_DEFAULT	0x14
132
+#define BD718XX_1ST_NODVS_BUCK_MASK	0x07
133
+#define BD718XX_3RD_NODVS_BUCK_MASK	0x07
134
+#define BD718XX_4TH_NODVS_BUCK_MASK	0x3F
125135 
126
-/* BD71837_REG_BUCK1_VOLT_IDLE bits */
127
-#define BUCK1_IDLE_MASK		0x3F
128
-#define BUCK1_IDLE_DEFAULT	0x14
136
+#define BD71847_BUCK3_MASK		0x07
137
+#define BD71847_BUCK3_RANGE_MASK	0xC0
138
+#define BD71847_BUCK4_MASK		0x03
139
+#define BD71847_BUCK4_RANGE_MASK	0x40
129140 
130
-/* BD71837_REG_BUCK2_VOLT_RUN bits */
131
-#define BUCK2_RUN_MASK		0x3F
132
-#define BUCK2_RUN_DEFAULT	0x1E
141
+#define BD71837_BUCK5_MASK		0x07
142
+#define BD71837_BUCK5_RANGE_MASK	0x80
143
+#define BD71837_BUCK6_MASK		0x03
133144 
134
-/* BD71837_REG_BUCK2_VOLT_IDLE bits */
135
-#define BUCK2_IDLE_MASK		0x3F
136
-#define BUCK2_IDLE_DEFAULT	0x14
145
+#define BD718XX_LDO1_MASK		0x03
146
+#define BD718XX_LDO1_RANGE_MASK		0x20
147
+#define BD718XX_LDO2_MASK		0x20
148
+#define BD718XX_LDO3_MASK		0x0F
149
+#define BD718XX_LDO4_MASK		0x0F
150
+#define BD718XX_LDO6_MASK		0x0F
137151 
138
-/* BD71837_REG_BUCK3_VOLT_RUN bits */
139
-#define BUCK3_RUN_MASK		0x3F
140
-#define BUCK3_RUN_DEFAULT	0x1E
152
+#define BD71837_LDO5_MASK		0x0F
153
+#define BD71847_LDO5_MASK		0x0F
154
+#define BD71847_LDO5_RANGE_MASK		0x20
141155 
142
-/* BD71837_REG_BUCK4_VOLT_RUN bits */
143
-#define BUCK4_RUN_MASK		0x3F
144
-#define BUCK4_RUN_DEFAULT	0x1E
145
-
146
-/* BD71837_REG_BUCK5_VOLT bits */
147
-#define BUCK5_MASK		0x07
148
-#define BUCK5_DEFAULT		0x02
149
-
150
-/* BD71837_REG_BUCK6_VOLT bits */
151
-#define BUCK6_MASK		0x03
152
-#define BUCK6_DEFAULT		0x03
153
-
154
-/* BD71837_REG_BUCK7_VOLT bits */
155
-#define BUCK7_MASK		0x07
156
-#define BUCK7_DEFAULT		0x03
157
-
158
-/* BD71837_REG_BUCK8_VOLT bits */
159
-#define BUCK8_MASK		0x3F
160
-#define BUCK8_DEFAULT		0x1E
156
+#define BD71837_LDO7_MASK		0x0F
161157 
162158 /* BD718XX Voltage monitoring masks */
163159 #define BD718XX_BUCK1_VRMON80           0x1
....@@ -186,7 +182,7 @@
186182 #define BD71837_BUCK4_VRMON130          0x80
187183 #define BD71837_LDO7_VRMON80            0x40
188184 
189
-/* BD71837_REG_IRQ bits */
185
+/* BD718XX_REG_IRQ bits */
190186 #define IRQ_SWRST		0x40
191187 #define IRQ_PWRON_S		0x20
192188 #define IRQ_PWRON_L		0x10
....@@ -195,52 +191,25 @@
195191 #define IRQ_ON_REQ		0x02
196192 #define IRQ_STBY_REQ		0x01
197193 
198
-/* BD71837_REG_OUT32K bits */
199
-#define BD71837_OUT32K_EN	0x01
200
-
201
-/* BD71837 gated clock rate */
202
-#define BD71837_CLK_RATE 32768
203
-
204
-/* ROHM BD71837 irqs */
194
+/* ROHM BD718XX irqs */
205195 enum {
206
-	BD71837_INT_STBY_REQ,
207
-	BD71837_INT_ON_REQ,
208
-	BD71837_INT_WDOG,
209
-	BD71837_INT_PWRBTN,
210
-	BD71837_INT_PWRBTN_L,
211
-	BD71837_INT_PWRBTN_S,
212
-	BD71837_INT_SWRST
196
+	BD718XX_INT_STBY_REQ,
197
+	BD718XX_INT_ON_REQ,
198
+	BD718XX_INT_WDOG,
199
+	BD718XX_INT_PWRBTN,
200
+	BD718XX_INT_PWRBTN_L,
201
+	BD718XX_INT_PWRBTN_S,
202
+	BD718XX_INT_SWRST
213203 };
214204 
215
-/* ROHM BD71837 interrupt masks */
216
-#define BD71837_INT_SWRST_MASK		0x40
217
-#define BD71837_INT_PWRBTN_S_MASK	0x20
218
-#define BD71837_INT_PWRBTN_L_MASK	0x10
219
-#define BD71837_INT_PWRBTN_MASK		0x8
220
-#define BD71837_INT_WDOG_MASK		0x4
221
-#define BD71837_INT_ON_REQ_MASK		0x2
222
-#define BD71837_INT_STBY_REQ_MASK	0x1
223
-
224
-/* BD71837_REG_LDO1_VOLT bits */
225
-#define LDO1_MASK		0x03
226
-
227
-/* BD71837_REG_LDO1_VOLT bits */
228
-#define LDO2_MASK		0x20
229
-
230
-/* BD71837_REG_LDO3_VOLT bits */
231
-#define LDO3_MASK		0x0F
232
-
233
-/* BD71837_REG_LDO4_VOLT bits */
234
-#define LDO4_MASK		0x0F
235
-
236
-/* BD71837_REG_LDO5_VOLT bits */
237
-#define LDO5_MASK		0x0F
238
-
239
-/* BD71837_REG_LDO6_VOLT bits */
240
-#define LDO6_MASK		0x0F
241
-
242
-/* BD71837_REG_LDO7_VOLT bits */
243
-#define LDO7_MASK		0x0F
205
+/* ROHM BD718XX interrupt masks */
206
+#define BD718XX_INT_SWRST_MASK		0x40
207
+#define BD718XX_INT_PWRBTN_S_MASK	0x20
208
+#define BD718XX_INT_PWRBTN_L_MASK	0x10
209
+#define BD718XX_INT_PWRBTN_MASK		0x8
210
+#define BD718XX_INT_WDOG_MASK		0x4
211
+#define BD718XX_INT_ON_REQ_MASK		0x2
212
+#define BD718XX_INT_STBY_REQ_MASK	0x1
244213 
245214 /* Register write induced reset settings */
246215 
....@@ -250,13 +219,13 @@
250219  * write 1 to it we will trigger the action. So always write 0 to it when
251220  * changning SWRESET action - no matter what we read from it.
252221  */
253
-#define BD71837_SWRESET_TYPE_MASK	7
254
-#define BD71837_SWRESET_TYPE_DISABLED	0
255
-#define BD71837_SWRESET_TYPE_COLD	4
256
-#define BD71837_SWRESET_TYPE_WARM	6
222
+#define BD718XX_SWRESET_TYPE_MASK	7
223
+#define BD718XX_SWRESET_TYPE_DISABLED	0
224
+#define BD718XX_SWRESET_TYPE_COLD	4
225
+#define BD718XX_SWRESET_TYPE_WARM	6
257226 
258
-#define BD71837_SWRESET_RESET_MASK	1
259
-#define BD71837_SWRESET_RESET		1
227
+#define BD718XX_SWRESET_RESET_MASK	1
228
+#define BD718XX_SWRESET_RESET		1
260229 
261230 /* Poweroff state transition conditions */
262231 
....@@ -341,19 +310,17 @@
341310 	BD718XX_PWRBTN_LONG_PRESS_15S
342311 };
343312 
344
-struct bd71837_pmic;
345
-struct bd71837_clk;
346
-
347
-struct bd71837 {
348
-	struct device *dev;
349
-	struct regmap *regmap;
350
-	unsigned long int id;
313
+struct bd718xx {
314
+	/*
315
+	 * Please keep this as the first member here as some
316
+	 * drivers (clk) supporting more than one chip may only know this
317
+	 * generic struct 'struct rohm_regmap_dev' and assume it is
318
+	 * the first chunk of parent device's private data.
319
+	 */
320
+	struct rohm_regmap_dev chip;
351321 
352322 	int chip_irq;
353323 	struct regmap_irq_chip_data *irq_data;
354
-
355
-	struct bd71837_pmic *pmic;
356
-	struct bd71837_clk *clk;
357324 };
358325 
359
-#endif /* __LINUX_MFD_BD71837_H__ */
326
+#endif /* __LINUX_MFD_BD718XX_H__ */