.. | .. |
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3 | 3 | * |
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4 | 4 | * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec) |
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5 | 5 | * |
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6 | | - * Copyright (C) 2000 - 2018, Intel Corp. |
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| 6 | + * Copyright (C) 2000 - 2020, Intel Corp. |
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7 | 7 | * |
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8 | 8 | *****************************************************************************/ |
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9 | 9 | |
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.. | .. |
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43 | 43 | #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ |
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44 | 44 | #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */ |
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45 | 45 | #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ |
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| 46 | +#define ACPI_SIG_NHLT "NHLT" /* Non-HDAudio Link Table */ |
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46 | 47 | |
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47 | 48 | /* |
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48 | 49 | * All tables must be byte-packed to match the ACPI specification, since |
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.. | .. |
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143 | 144 | */ |
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144 | 145 | struct acpi_iort_its_group { |
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145 | 146 | u32 its_count; |
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146 | | - u32 identifiers[1]; /* GIC ITS identifier arrary */ |
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| 147 | + u32 identifiers[1]; /* GIC ITS identifier array */ |
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147 | 148 | }; |
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148 | 149 | |
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149 | 150 | struct acpi_iort_named_component { |
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.. | .. |
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274 | 275 | /* Values for subtable Type above */ |
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275 | 276 | |
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276 | 277 | enum acpi_ivrs_type { |
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277 | | - ACPI_IVRS_TYPE_HARDWARE = 0x10, |
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| 278 | + ACPI_IVRS_TYPE_HARDWARE1 = 0x10, |
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| 279 | + ACPI_IVRS_TYPE_HARDWARE2 = 0x11, |
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278 | 280 | ACPI_IVRS_TYPE_MEMORY1 = 0x20, |
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279 | 281 | ACPI_IVRS_TYPE_MEMORY2 = 0x21, |
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280 | 282 | ACPI_IVRS_TYPE_MEMORY3 = 0x22 |
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.. | .. |
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301 | 303 | |
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302 | 304 | /* 0x10: I/O Virtualization Hardware Definition Block (IVHD) */ |
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303 | 305 | |
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304 | | -struct acpi_ivrs_hardware { |
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| 306 | +struct acpi_ivrs_hardware_10 { |
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305 | 307 | struct acpi_ivrs_header header; |
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306 | 308 | u16 capability_offset; /* Offset for IOMMU control fields */ |
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307 | 309 | u64 base_address; /* IOMMU control registers */ |
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308 | 310 | u16 pci_segment_group; |
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309 | 311 | u16 info; /* MSI number and unit ID */ |
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310 | | - u32 reserved; |
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| 312 | + u32 feature_reporting; |
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| 313 | +}; |
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| 314 | + |
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| 315 | +/* 0x11: I/O Virtualization Hardware Definition Block (IVHD) */ |
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| 316 | + |
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| 317 | +struct acpi_ivrs_hardware_11 { |
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| 318 | + struct acpi_ivrs_header header; |
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| 319 | + u16 capability_offset; /* Offset for IOMMU control fields */ |
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| 320 | + u64 base_address; /* IOMMU control registers */ |
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| 321 | + u16 pci_segment_group; |
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| 322 | + u16 info; /* MSI number and unit ID */ |
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| 323 | + u32 attributes; |
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| 324 | + u64 efr_register_image; |
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| 325 | + u64 reserved; |
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311 | 326 | }; |
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312 | 327 | |
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313 | 328 | /* Masks for Info field above */ |
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.. | .. |
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623 | 638 | u8 reserved[3]; /* reserved - must be zero */ |
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624 | 639 | }; |
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625 | 640 | |
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626 | | -/* 11: Generic Interrupt (ACPI 5.0 + ACPI 6.0 changes) */ |
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| 641 | +/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 changes) */ |
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627 | 642 | |
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628 | 643 | struct acpi_madt_generic_interrupt { |
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629 | 644 | struct acpi_subtable_header header; |
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.. | .. |
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641 | 656 | u64 gicr_base_address; |
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642 | 657 | u64 arm_mpidr; |
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643 | 658 | u8 efficiency_class; |
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644 | | - u8 reserved2[3]; |
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| 659 | + u8 reserved2[1]; |
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| 660 | + u16 spe_interrupt; /* ACPI 6.3 */ |
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645 | 661 | }; |
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646 | 662 | |
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647 | 663 | /* Masks for Flags field above */ |
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.. | .. |
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1361 | 1377 | |
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1362 | 1378 | #define ACPI_PDTT_RUNTIME_TRIGGER (1) |
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1363 | 1379 | #define ACPI_PDTT_WAIT_COMPLETION (1<<1) |
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| 1380 | +#define ACPI_PDTT_TRIGGER_ORDER (1<<2) |
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1364 | 1381 | |
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1365 | 1382 | /******************************************************************************* |
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1366 | 1383 | * |
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