.. | .. |
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9 | 9 | * Based on sunxi_wdt.c |
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10 | 10 | */ |
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11 | 11 | |
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| 12 | +#include <dt-bindings/reset-controller/mt2712-resets.h> |
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| 13 | +#include <dt-bindings/reset-controller/mt8183-resets.h> |
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| 14 | +#include <linux/delay.h> |
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12 | 15 | #include <linux/err.h> |
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13 | 16 | #include <linux/init.h> |
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14 | 17 | #include <linux/io.h> |
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.. | .. |
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16 | 19 | #include <linux/module.h> |
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17 | 20 | #include <linux/moduleparam.h> |
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18 | 21 | #include <linux/of.h> |
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| 22 | +#include <linux/of_device.h> |
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19 | 23 | #include <linux/platform_device.h> |
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| 24 | +#include <linux/reset-controller.h> |
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20 | 25 | #include <linux/types.h> |
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21 | 26 | #include <linux/watchdog.h> |
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22 | | -#include <linux/delay.h> |
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23 | 27 | |
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24 | 28 | #define WDT_MAX_TIMEOUT 31 |
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25 | 29 | #define WDT_MIN_TIMEOUT 1 |
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.. | .. |
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44 | 48 | #define WDT_SWRST 0x14 |
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45 | 49 | #define WDT_SWRST_KEY 0x1209 |
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46 | 50 | |
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| 51 | +#define WDT_SWSYSRST 0x18U |
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| 52 | +#define WDT_SWSYS_RST_KEY 0x88000000 |
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| 53 | + |
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47 | 54 | #define DRV_NAME "mtk-wdt" |
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48 | 55 | #define DRV_VERSION "1.0" |
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49 | 56 | |
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.. | .. |
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53 | 60 | struct mtk_wdt_dev { |
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54 | 61 | struct watchdog_device wdt_dev; |
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55 | 62 | void __iomem *wdt_base; |
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| 63 | + spinlock_t lock; /* protects WDT_SWSYSRST reg */ |
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| 64 | + struct reset_controller_dev rcdev; |
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56 | 65 | }; |
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| 66 | + |
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| 67 | +struct mtk_wdt_data { |
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| 68 | + int toprgu_sw_rst_num; |
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| 69 | +}; |
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| 70 | + |
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| 71 | +static const struct mtk_wdt_data mt2712_data = { |
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| 72 | + .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, |
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| 73 | +}; |
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| 74 | + |
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| 75 | +static const struct mtk_wdt_data mt8183_data = { |
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| 76 | + .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, |
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| 77 | +}; |
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| 78 | + |
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| 79 | +static int toprgu_reset_update(struct reset_controller_dev *rcdev, |
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| 80 | + unsigned long id, bool assert) |
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| 81 | +{ |
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| 82 | + unsigned int tmp; |
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| 83 | + unsigned long flags; |
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| 84 | + struct mtk_wdt_dev *data = |
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| 85 | + container_of(rcdev, struct mtk_wdt_dev, rcdev); |
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| 86 | + |
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| 87 | + spin_lock_irqsave(&data->lock, flags); |
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| 88 | + |
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| 89 | + tmp = readl(data->wdt_base + WDT_SWSYSRST); |
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| 90 | + if (assert) |
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| 91 | + tmp |= BIT(id); |
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| 92 | + else |
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| 93 | + tmp &= ~BIT(id); |
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| 94 | + tmp |= WDT_SWSYS_RST_KEY; |
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| 95 | + writel(tmp, data->wdt_base + WDT_SWSYSRST); |
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| 96 | + |
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| 97 | + spin_unlock_irqrestore(&data->lock, flags); |
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| 98 | + |
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| 99 | + return 0; |
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| 100 | +} |
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| 101 | + |
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| 102 | +static int toprgu_reset_assert(struct reset_controller_dev *rcdev, |
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| 103 | + unsigned long id) |
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| 104 | +{ |
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| 105 | + return toprgu_reset_update(rcdev, id, true); |
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| 106 | +} |
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| 107 | + |
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| 108 | +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, |
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| 109 | + unsigned long id) |
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| 110 | +{ |
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| 111 | + return toprgu_reset_update(rcdev, id, false); |
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| 112 | +} |
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| 113 | + |
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| 114 | +static int toprgu_reset(struct reset_controller_dev *rcdev, |
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| 115 | + unsigned long id) |
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| 116 | +{ |
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| 117 | + int ret; |
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| 118 | + |
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| 119 | + ret = toprgu_reset_assert(rcdev, id); |
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| 120 | + if (ret) |
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| 121 | + return ret; |
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| 122 | + |
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| 123 | + return toprgu_reset_deassert(rcdev, id); |
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| 124 | +} |
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| 125 | + |
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| 126 | +static const struct reset_control_ops toprgu_reset_ops = { |
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| 127 | + .assert = toprgu_reset_assert, |
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| 128 | + .deassert = toprgu_reset_deassert, |
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| 129 | + .reset = toprgu_reset, |
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| 130 | +}; |
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| 131 | + |
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| 132 | +static int toprgu_register_reset_controller(struct platform_device *pdev, |
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| 133 | + int rst_num) |
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| 134 | +{ |
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| 135 | + int ret; |
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| 136 | + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); |
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| 137 | + |
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| 138 | + spin_lock_init(&mtk_wdt->lock); |
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| 139 | + |
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| 140 | + mtk_wdt->rcdev.owner = THIS_MODULE; |
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| 141 | + mtk_wdt->rcdev.nr_resets = rst_num; |
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| 142 | + mtk_wdt->rcdev.ops = &toprgu_reset_ops; |
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| 143 | + mtk_wdt->rcdev.of_node = pdev->dev.of_node; |
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| 144 | + ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev); |
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| 145 | + if (ret != 0) |
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| 146 | + dev_err(&pdev->dev, |
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| 147 | + "couldn't register wdt reset controller: %d\n", ret); |
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| 148 | + return ret; |
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| 149 | +} |
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57 | 150 | |
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58 | 151 | static int mtk_wdt_restart(struct watchdog_device *wdt_dev, |
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59 | 152 | unsigned long action, void *data) |
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.. | .. |
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153 | 246 | |
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154 | 247 | static int mtk_wdt_probe(struct platform_device *pdev) |
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155 | 248 | { |
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| 249 | + struct device *dev = &pdev->dev; |
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156 | 250 | struct mtk_wdt_dev *mtk_wdt; |
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157 | | - struct resource *res; |
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| 251 | + const struct mtk_wdt_data *wdt_data; |
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158 | 252 | int err; |
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159 | 253 | |
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160 | | - mtk_wdt = devm_kzalloc(&pdev->dev, sizeof(*mtk_wdt), GFP_KERNEL); |
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| 254 | + mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); |
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161 | 255 | if (!mtk_wdt) |
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162 | 256 | return -ENOMEM; |
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163 | 257 | |
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164 | 258 | platform_set_drvdata(pdev, mtk_wdt); |
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165 | 259 | |
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166 | | - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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167 | | - mtk_wdt->wdt_base = devm_ioremap_resource(&pdev->dev, res); |
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| 260 | + mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0); |
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168 | 261 | if (IS_ERR(mtk_wdt->wdt_base)) |
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169 | 262 | return PTR_ERR(mtk_wdt->wdt_base); |
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170 | 263 | |
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.. | .. |
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173 | 266 | mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT; |
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174 | 267 | mtk_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT; |
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175 | 268 | mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT; |
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176 | | - mtk_wdt->wdt_dev.parent = &pdev->dev; |
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| 269 | + mtk_wdt->wdt_dev.parent = dev; |
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177 | 270 | |
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178 | | - watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, &pdev->dev); |
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| 271 | + watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev); |
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179 | 272 | watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout); |
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180 | 273 | watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128); |
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181 | 274 | |
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.. | .. |
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183 | 276 | |
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184 | 277 | mtk_wdt_stop(&mtk_wdt->wdt_dev); |
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185 | 278 | |
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186 | | - err = watchdog_register_device(&mtk_wdt->wdt_dev); |
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| 279 | + watchdog_stop_on_reboot(&mtk_wdt->wdt_dev); |
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| 280 | + err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev); |
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187 | 281 | if (unlikely(err)) |
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188 | 282 | return err; |
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189 | 283 | |
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190 | | - dev_info(&pdev->dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", |
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191 | | - mtk_wdt->wdt_dev.timeout, nowayout); |
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| 284 | + dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", |
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| 285 | + mtk_wdt->wdt_dev.timeout, nowayout); |
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192 | 286 | |
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193 | | - return 0; |
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194 | | -} |
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195 | | - |
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196 | | -static void mtk_wdt_shutdown(struct platform_device *pdev) |
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197 | | -{ |
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198 | | - struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); |
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199 | | - |
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200 | | - if (watchdog_active(&mtk_wdt->wdt_dev)) |
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201 | | - mtk_wdt_stop(&mtk_wdt->wdt_dev); |
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202 | | -} |
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203 | | - |
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204 | | -static int mtk_wdt_remove(struct platform_device *pdev) |
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205 | | -{ |
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206 | | - struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); |
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207 | | - |
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208 | | - watchdog_unregister_device(&mtk_wdt->wdt_dev); |
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209 | | - |
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| 287 | + wdt_data = of_device_get_match_data(dev); |
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| 288 | + if (wdt_data) { |
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| 289 | + err = toprgu_register_reset_controller(pdev, |
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| 290 | + wdt_data->toprgu_sw_rst_num); |
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| 291 | + if (err) |
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| 292 | + return err; |
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| 293 | + } |
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210 | 294 | return 0; |
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211 | 295 | } |
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212 | 296 | |
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.. | .. |
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235 | 319 | #endif |
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236 | 320 | |
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237 | 321 | static const struct of_device_id mtk_wdt_dt_ids[] = { |
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| 322 | + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, |
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238 | 323 | { .compatible = "mediatek,mt6589-wdt" }, |
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| 324 | + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, |
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239 | 325 | { /* sentinel */ } |
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240 | 326 | }; |
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241 | 327 | MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); |
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.. | .. |
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247 | 333 | |
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248 | 334 | static struct platform_driver mtk_wdt_driver = { |
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249 | 335 | .probe = mtk_wdt_probe, |
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250 | | - .remove = mtk_wdt_remove, |
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251 | | - .shutdown = mtk_wdt_shutdown, |
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252 | 336 | .driver = { |
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253 | 337 | .name = DRV_NAME, |
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254 | 338 | .pm = &mtk_wdt_pm_ops, |
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