add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/usb/host/pci-quirks.c
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@@ -16,6 +16,9 @@
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 #include <linux/export.h>
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 #include <linux/acpi.h>
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 #include <linux/dmi.h>
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+#include <linux/of.h>
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+#include <linux/iopoll.h>
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+
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 #include "pci-quirks.h"
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 #include "xhci-ext-caps.h"
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@@ -132,7 +135,7 @@
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 	struct amd_chipset_type sb_type;
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 	int isoc_reqs;
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 	int probe_count;
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-	int probe_result;
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+	bool need_pll_quirk;
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 } amd_chipset;
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 static DEFINE_SPINLOCK(amd_lock);
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@@ -201,11 +204,11 @@
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 }
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 EXPORT_SYMBOL_GPL(sb800_prefetch);
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-int usb_amd_find_chipset_info(void)
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+static void usb_amd_find_chipset_info(void)
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 {
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 	unsigned long flags;
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 	struct amd_chipset_info info;
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-	int need_pll_quirk = 0;
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+	info.need_pll_quirk = false;
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 	spin_lock_irqsave(&amd_lock, flags);
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@@ -213,7 +216,7 @@
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 	if (amd_chipset.probe_count > 0) {
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 		amd_chipset.probe_count++;
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 		spin_unlock_irqrestore(&amd_lock, flags);
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-		return amd_chipset.probe_result;
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+		return;
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 	}
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 	memset(&info, 0, sizeof(info));
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 	spin_unlock_irqrestore(&amd_lock, flags);
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@@ -224,19 +227,19 @@
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 	switch (info.sb_type.gen) {
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 	case AMD_CHIPSET_SB700:
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-		need_pll_quirk = info.sb_type.rev <= 0x3B;
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+		info.need_pll_quirk = info.sb_type.rev <= 0x3B;
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 		break;
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 	case AMD_CHIPSET_SB800:
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 	case AMD_CHIPSET_HUDSON2:
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 	case AMD_CHIPSET_BOLTON:
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-		need_pll_quirk = 1;
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+		info.need_pll_quirk = true;
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 		break;
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 	default:
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-		need_pll_quirk = 0;
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+		info.need_pll_quirk = false;
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 		break;
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 	}
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-	if (!need_pll_quirk) {
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+	if (!info.need_pll_quirk) {
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 		if (info.smbus_dev) {
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 			pci_dev_put(info.smbus_dev);
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 			info.smbus_dev = NULL;
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@@ -259,7 +262,6 @@
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 		}
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 	}
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-	need_pll_quirk = info.probe_result = 1;
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 	printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
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 commit:
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@@ -270,7 +272,6 @@
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 		/* Mark that we where here */
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 		amd_chipset.probe_count++;
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-		need_pll_quirk = amd_chipset.probe_result;
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 		spin_unlock_irqrestore(&amd_lock, flags);
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..
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@@ -283,10 +284,7 @@
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 		amd_chipset = info;
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 		spin_unlock_irqrestore(&amd_lock, flags);
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 	}
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-
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-	return need_pll_quirk;
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 }
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-EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
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 int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev)
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 {
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@@ -321,6 +319,13 @@
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 	return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800;
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 }
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 EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk);
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+
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+bool usb_amd_quirk_pll_check(void)
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+{
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+	usb_amd_find_chipset_info();
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+	return amd_chipset.need_pll_quirk;
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+}
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+EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_check);
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 /*
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  * The hardware normally enables the A-link power management feature, which
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@@ -527,7 +532,7 @@
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 	amd_chipset.nb_type = 0;
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 	memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type));
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 	amd_chipset.isoc_reqs = 0;
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-	amd_chipset.probe_result = 0;
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+	amd_chipset.need_pll_quirk = false;
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 	spin_unlock_irqrestore(&amd_lock, flags);
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@@ -726,7 +731,7 @@
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 	if (!pio_enabled(pdev))
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 		return;
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-	for (i = 0; i < PCI_ROM_RESOURCE; i++)
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+	for (i = 0; i < PCI_STD_NUM_BARS; i++)
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 		if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
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 			base = pci_resource_start(pdev, i);
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 			break;
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@@ -790,15 +795,9 @@
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 	/* disable interrupts */
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 	writel((u32) ~0, base + OHCI_INTRDISABLE);
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-	/* Reset the USB bus, if the controller isn't already in RESET */
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-	if (control & OHCI_HCFS) {
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-		/* Go into RESET, preserving RWC (and possibly IR) */
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-		writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
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-		readl(base + OHCI_CONTROL);
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-
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-		/* drive bus reset for at least 50 ms (7.1.7.5) */
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-		msleep(50);
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-	}
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+	/* Go into the USB_RESET state, preserving RWC (and possibly IR) */
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+	writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
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+	readl(base + OHCI_CONTROL);
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 	/* software reset of the controller, preserving HcFmInterval */
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 	if (!no_fminterval)
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@@ -958,7 +957,8 @@
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 			ehci_bios_handoff(pdev, op_reg_base, cap, offset);
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 			break;
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 		case 0: /* Illegal reserved cap, set cap=0 so we exit */
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-			cap = 0; /* fall through */
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+			cap = 0;
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+			fallthrough;
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 		default:
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 			dev_warn(&pdev->dev,
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 				 "EHCI: unrecognized capability %02x\n",
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@@ -1013,15 +1013,9 @@
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 {
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 	u32	result;
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-	do {
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-		result = readl(ptr);
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-		result &= mask;
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-		if (result == done)
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-			return 0;
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-		udelay(delay_usec);
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-		wait_usec -= delay_usec;
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-	} while (wait_usec > 0);
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-	return -ETIMEDOUT;
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+	return readl_poll_timeout_atomic(ptr, result,
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+					 ((result & mask) == done),
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+					 delay_usec, wait_usec);
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 }
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 /*
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@@ -1134,7 +1128,7 @@
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 }
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 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
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-/**
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+/*
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  * PCI Quirks for xHCI.
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  *
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  * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
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@@ -1154,7 +1148,7 @@
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 	if (!mmio_resource_enabled(pdev, 0))
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 		return;
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-	base = ioremap_nocache(pci_resource_start(pdev, 0), len);
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+	base = ioremap(pci_resource_start(pdev, 0), len);
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 	if (base == NULL)
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 		return;
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..
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@@ -1247,11 +1241,27 @@
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 static void quirk_usb_early_handoff(struct pci_dev *pdev)
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 {
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+	struct device_node *parent;
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+	bool is_rpi;
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+
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 	/* Skip Netlogic mips SoC's internal PCI USB controller.
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 	 * This device does not need/support EHCI/OHCI handoff
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 	 */
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 	if (pdev->vendor == 0x184e)	/* vendor Netlogic */
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 		return;
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+
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+	/*
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+	 * Bypass the Raspberry Pi 4 controller xHCI controller, things are
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+	 * taken care of by the board's co-processor.
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+	 */
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+	if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
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+		parent = of_get_parent(pdev->bus->dev.of_node);
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+		is_rpi = of_device_is_compatible(parent, "brcm,bcm2711-pcie");
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+		of_node_put(parent);
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+		if (is_rpi)
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+			return;
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+	}
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+
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 	if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
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 			pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
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 			pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&