add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/tty/hvc/Kconfig
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@@ -1,4 +1,4 @@
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-if TTY
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+# SPDX-License-Identifier: GPL-2.0
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 config HVC_DRIVER
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 	bool
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@@ -24,7 +24,6 @@
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 config HVC_OLD_HVSI
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 	bool "Old driver for pSeries serial port (/dev/hvsi*)"
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 	depends on HVC_CONSOLE
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-	default n
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 config HVC_OPAL
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 	bool "OPAL Console support"
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@@ -70,27 +69,48 @@
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 	  Xen driver for secondary virtual consoles
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 config HVC_UDBG
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-       bool "udbg based fake hypervisor console"
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-       depends on PPC
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-       select HVC_DRIVER
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-       default n
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-       help
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-         This is meant to be used during HW bring up or debugging when
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-	 no other console mechanism exist but udbg, to get you a quick
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-	 console for userspace. Do NOT enable in production kernels. 
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+	bool "udbg based fake hypervisor console"
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+	depends on PPC
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+	select HVC_DRIVER
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+	help
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+	  This is meant to be used during HW bring up or debugging when
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+	  no other console mechanism exist but udbg, to get you a quick
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+	  console for userspace. Do NOT enable in production kernels.
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 config HVC_DCC
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-       bool "ARM JTAG DCC console"
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-       depends on ARM || ARM64
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-       select HVC_DRIVER
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-       help
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-         This console uses the JTAG DCC on ARM to create a console under the HVC
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-	 driver. This console is used through a JTAG only on ARM. If you don't have
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-	 a JTAG then you probably don't want this option.
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+	bool "ARM JTAG DCC console"
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+	depends on ARM || ARM64
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+	select HVC_DRIVER
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+	select SERIAL_CORE_CONSOLE
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+	help
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+	  This console uses the JTAG DCC on ARM to create a console under the HVC
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+	  driver. This console is used through a JTAG only on ARM. If you don't have
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+	  a JTAG then you probably don't want this option.
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+
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+config HVC_DCC_SERIALIZE_SMP
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+	bool "Use DCC only on core 0"
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+	depends on SMP && HVC_DCC
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+	help
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+	  Some debuggers, such as Trace32 from Lauterbach GmbH, do not handle
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+	  reads/writes from/to DCC on more than one core. Each core has its
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+	  own DCC device registers, so when a core reads or writes from/to DCC,
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+	  it only accesses its own DCC device. Since kernel code can run on
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+	  any core, every time the kernel wants to write to the console, it
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+	  might write to a different DCC.
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+
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+	  In SMP mode, Trace32 only uses the DCC on core 0. In AMP mode, it
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+	  creates multiple windows, and each window shows the DCC output
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+	  only from that core's DCC. The result is that console output is
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+	  either lost or scattered across windows.
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+
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+	  Selecting this option will enable code that serializes all console
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+	  input and output to core 0. The DCC driver will create input and
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+	  output FIFOs that all cores will use. Reads and writes from/to DCC
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+	  are handled by a workqueue that runs only core 0.
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 config HVC_RISCV_SBI
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 	bool "RISC-V SBI console support"
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-	depends on RISCV
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+	depends on RISCV_SBI_V01
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 	select HVC_DRIVER
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 	help
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 	  This enables support for console output via RISC-V SBI calls, which
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@@ -114,5 +134,3 @@
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 	  will depend on arch specific APIs exported from hvcserver.ko
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 	  which will also be compiled when this driver is built as a
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 	  module.
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-
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-endif # TTY