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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/thunderbolt/eeprom.c
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..
@@ -1,11 +1,13 @@
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 // SPDX-License-Identifier: GPL-2.0
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 /*
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- * Thunderbolt Cactus Ridge driver - eeprom access
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+ * Thunderbolt driver - eeprom access
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  *
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  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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+ * Copyright (C) 2018, Intel Corporation
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  */
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 #include <linux/crc32.h>
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+#include <linux/delay.h>
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 #include <linux/property.h>
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 #include <linux/slab.h>
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 #include "tb.h"
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@@ -130,12 +132,51 @@
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 }
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133
 
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 /**
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+ * tb_eeprom_get_drom_offset - get drom offset within eeprom
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+ */
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+static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
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+{
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+	struct tb_cap_plug_events cap;
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+	int res;
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+
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+	if (!sw->cap_plug_events) {
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+		tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
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+		return -ENODEV;
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+	}
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+	res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
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+			     sizeof(cap) / 4);
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+	if (res)
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+		return res;
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+
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+	if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
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+		tb_sw_warn(sw, "no NVM\n");
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+		return -ENODEV;
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+	}
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+
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+	if (cap.drom_offset > 0xffff) {
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+		tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
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+				cap.drom_offset);
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+		return -ENXIO;
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+	}
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+	*offset = cap.drom_offset;
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+	return 0;
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+}
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+
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+/**
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  * tb_eeprom_read_n - read count bytes from offset into val
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  */
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 static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
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 		size_t count)
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 {
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+	u16 drom_offset;
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 	int i, res;
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+
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+	res = tb_eeprom_get_drom_offset(sw, &drom_offset);
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+	if (res)
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+		return res;
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+
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+	offset += drom_offset;
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+
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 	res = tb_eeprom_active(sw, true);
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 	if (res)
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 		return res;
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@@ -207,7 +248,7 @@
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248
 
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 struct tb_drom_entry_generic {
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 	struct tb_drom_entry_header header;
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-	u8 data[0];
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+	u8 data[];
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 } __packed;
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253
 
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 struct tb_drom_entry_port {
..
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@@ -238,36 +279,6 @@
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279
 
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 /**
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- * tb_eeprom_get_drom_offset - get drom offset within eeprom
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- */
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-static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
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-{
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-	struct tb_cap_plug_events cap;
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-	int res;
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-	if (!sw->cap_plug_events) {
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-		tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
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-		return -ENOSYS;
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-	}
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-	res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
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-			     sizeof(cap) / 4);
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-	if (res)
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-		return res;
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-
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-	if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
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-		tb_sw_warn(sw, "no NVM\n");
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-		return -ENOSYS;
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-	}
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-
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-	if (cap.drom_offset > 0xffff) {
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-		tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
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-				cap.drom_offset);
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-		return -ENXIO;
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-	}
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-	*offset = cap.drom_offset;
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-	return 0;
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-}
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-
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-/**
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  * tb_drom_read_uid_only - read uid directly from drom
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  *
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  * Does not use the cached copy in sw->drom. Used during resume to check switch
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@@ -276,17 +287,11 @@
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 int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
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 {
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 	u8 data[9];
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-	u16 drom_offset;
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 	u8 crc;
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-	int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
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-	if (res)
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-		return res;
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-
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-	if (drom_offset == 0)
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-		return -ENODEV;
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+	int res;
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 	/* read uid */
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-	res = tb_eeprom_read_n(sw, drom_offset, data, 9);
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+	res = tb_eeprom_read_n(sw, 0, data, 9);
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 	if (res)
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 		return res;
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@@ -385,8 +390,8 @@
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 		struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
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 		if (pos + 1 == drom_size || pos + entry->len > drom_size
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 				|| !entry->len) {
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-			tb_sw_warn(sw, "drom buffer overrun, aborting\n");
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-			return -EIO;
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+			tb_sw_warn(sw, "DROM buffer overrun\n");
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+			return -EILSEQ;
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 		}
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 		switch (entry->type) {
..
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@@ -413,7 +418,7 @@
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 	struct device *dev = &sw->tb->nhi->pdev->dev;
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 	int len, res;
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420
 
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-	len = device_property_read_u8_array(dev, "ThunderboltDROM", NULL, 0);
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+	len = device_property_count_u8(dev, "ThunderboltDROM");
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 	if (len < 0 || len < sizeof(struct tb_drom_header))
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 		return -EINVAL;
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@@ -483,16 +488,47 @@
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 	return ret;
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 }
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+static int usb4_copy_host_drom(struct tb_switch *sw, u16 *size)
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+{
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+	int ret;
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+
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+	ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size));
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+	if (ret)
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+		return ret;
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+
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+	/* Size includes CRC8 + UID + CRC32 */
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+	*size += 1 + 8 + 4;
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+	sw->drom = kzalloc(*size, GFP_KERNEL);
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+	if (!sw->drom)
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+		return -ENOMEM;
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+
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+	ret = usb4_switch_drom_read(sw, 0, sw->drom, *size);
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+	if (ret) {
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+		kfree(sw->drom);
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+		sw->drom = NULL;
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+	}
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+
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+	return ret;
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+}
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+
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+static int tb_drom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
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+			  size_t count)
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+{
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+	if (tb_switch_is_usb4(sw))
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+		return usb4_switch_drom_read(sw, offset, val, count);
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+	return tb_eeprom_read_n(sw, offset, val, count);
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+}
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+
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 /**
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  * tb_drom_read - copy drom to sw->drom and parse it
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  */
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 int tb_drom_read(struct tb_switch *sw)
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 {
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-	u16 drom_offset;
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 	u16 size;
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 	u32 crc;
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 	struct tb_drom_header *header;
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-	int res;
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+	int res, retries = 1;
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+
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 	if (sw->drom)
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 		return 0;
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@@ -509,38 +545,31 @@
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 			goto parse;
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 		/*
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-		 * The root switch contains only a dummy drom (header only,
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-		 * no entries). Hardcode the configuration here.
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+		 * USB4 hosts may support reading DROM through router
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+		 * operations.
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 		 */
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-		tb_drom_read_uid_only(sw, &sw->uid);
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-
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-		sw->ports[1].link_nr = 0;
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-		sw->ports[2].link_nr = 1;
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-		sw->ports[1].dual_link_port = &sw->ports[2];
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-		sw->ports[2].dual_link_port = &sw->ports[1];
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-
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-		sw->ports[3].link_nr = 0;
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-		sw->ports[4].link_nr = 1;
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-		sw->ports[3].dual_link_port = &sw->ports[4];
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-		sw->ports[4].dual_link_port = &sw->ports[3];
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-
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-		/* Port 5 is inaccessible on this gen 1 controller */
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-		if (sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE)
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-			sw->ports[5].disabled = true;
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+		if (tb_switch_is_usb4(sw)) {
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+			usb4_switch_read_uid(sw, &sw->uid);
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+			if (!usb4_copy_host_drom(sw, &size))
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+				goto parse;
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+		} else {
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+			/*
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+			 * The root switch contains only a dummy drom
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+			 * (header only, no entries). Hardcode the
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+			 * configuration here.
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+			 */
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+			tb_drom_read_uid_only(sw, &sw->uid);
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+		}
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563
 
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 		return 0;
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 	}
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566
 
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-	res = tb_eeprom_get_drom_offset(sw, &drom_offset);
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-	if (res)
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-		return res;
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-
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-	res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
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+	res = tb_drom_read_n(sw, 14, (u8 *) &size, 2);
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 	if (res)
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569
 		return res;
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 	size &= 0x3ff;
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 	size += TB_DROM_DATA_START;
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-	tb_sw_info(sw, "reading drom (length: %#x)\n", size);
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+	tb_sw_dbg(sw, "reading drom (length: %#x)\n", size);
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 	if (size < sizeof(*header)) {
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 		tb_sw_warn(sw, "drom too small, aborting\n");
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 		return -EIO;
..
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@@ -549,7 +578,7 @@
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 	sw->drom = kzalloc(size, GFP_KERNEL);
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579
 	if (!sw->drom)
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 		return -ENOMEM;
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-	res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
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+	res = tb_drom_read_n(sw, 0, sw->drom, size);
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582
 	if (res)
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583
 		goto err;
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584
 
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@@ -572,6 +601,7 @@
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 		sw->uid = header->uid;
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 	sw->vendor = header->vendor_id;
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 	sw->device = header->model_id;
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+	tb_check_quirks(sw);
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605
 
576
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 	crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
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 	if (crc != header->data_crc32) {
..
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@@ -584,7 +614,17 @@
584
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 		tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
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 			header->device_rom_revision);
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616
 
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-	return tb_drom_parse_entries(sw);
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+	res = tb_drom_parse_entries(sw);
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+	/* If the DROM parsing fails, wait a moment and retry once */
619
+	if (res == -EILSEQ && retries--) {
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+		tb_sw_warn(sw, "parsing DROM failed, retrying\n");
621
+		msleep(100);
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+		res = tb_drom_read_n(sw, 0, sw->drom, size);
623
+		if (!res)
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+			goto parse;
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+	}
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+
627
+	return res;
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628
 err:
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629
 	kfree(sw->drom);
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 	sw->drom = NULL;