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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/spi/spi-zynqmp-gqspi.c
....@@ -1,19 +1,16 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
34  * (master mode only)
45  *
56  * Copyright (C) 2009 - 2015 Xilinx, Inc.
6
- *
7
- * This program is free software; you can redistribute it and/or modify it
8
- * under the terms of the GNU General Public License version 2 as published
9
- * by the Free Software Foundation; either version 2 of the License, or
10
- * (at your option) any later version.
117  */
128 
139 #include <linux/clk.h>
1410 #include <linux/delay.h>
1511 #include <linux/dma-mapping.h>
1612 #include <linux/dmaengine.h>
13
+#include <linux/firmware/xlnx-zynqmp.h>
1714 #include <linux/interrupt.h>
1815 #include <linux/io.h>
1916 #include <linux/module.h>
....@@ -24,6 +21,7 @@
2421 #include <linux/spi/spi.h>
2522 #include <linux/spinlock.h>
2623 #include <linux/workqueue.h>
24
+#include <linux/spi/spi-mem.h>
2725 
2826 /* Generic QSPI register offsets */
2927 #define GQSPI_CONFIG_OFST		0x00000100
....@@ -156,8 +154,10 @@
156154  * @dma_addr:		DMA address after mapping the kernel buffer
157155  * @genfifoentry:	Used for storing the genfifoentry instruction.
158156  * @mode:		Defines the mode in which QSPI is operating
157
+ * @data_completion:	completion structure
159158  */
160159 struct zynqmp_qspi {
160
+	struct spi_controller *ctlr;
161161 	void __iomem *regs;
162162 	struct clk *refclk;
163163 	struct clk *pclk;
....@@ -173,12 +173,15 @@
173173 	dma_addr_t dma_addr;
174174 	u32 genfifoentry;
175175 	enum mode_type mode;
176
+	struct completion data_completion;
177
+	struct mutex op_lock;
176178 };
177179 
178180 /**
179
- * zynqmp_gqspi_read:	For GQSPI controller read operation
181
+ * zynqmp_gqspi_read - For GQSPI controller read operation
180182  * @xqspi:	Pointer to the zynqmp_qspi structure
181183  * @offset:	Offset from where to read
184
+ * Return:      Value at the offset
182185  */
183186 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
184187 {
....@@ -186,7 +189,7 @@
186189 }
187190 
188191 /**
189
- * zynqmp_gqspi_write:	For GQSPI controller write operation
192
+ * zynqmp_gqspi_write - For GQSPI controller write operation
190193  * @xqspi:	Pointer to the zynqmp_qspi structure
191194  * @offset:	Offset where to write
192195  * @val:	Value to be written
....@@ -198,10 +201,10 @@
198201 }
199202 
200203 /**
201
- * zynqmp_gqspi_selectslave:	For selection of slave device
204
+ * zynqmp_gqspi_selectslave - For selection of slave device
202205  * @instanceptr:	Pointer to the zynqmp_qspi structure
203
- * @flashcs:	For chip select
204
- * @flashbus:	To check which bus is selected- upper or lower
206
+ * @slavecs:	For chip select
207
+ * @slavebus:	To check which bus is selected- upper or lower
205208  */
206209 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
207210 				     u8 slavecs, u8 slavebus)
....@@ -245,7 +248,7 @@
245248 }
246249 
247250 /**
248
- * zynqmp_qspi_init_hw:	Initialize the hardware
251
+ * zynqmp_qspi_init_hw - Initialize the hardware
249252  * @xqspi:	Pointer to the zynqmp_qspi structure
250253  *
251254  * The default settings of the QSPI controller's configurable parameters on
....@@ -325,15 +328,15 @@
325328 				 GQSPI_SELECT_FLASH_BUS_LOWER);
326329 	/* Initialize DMA */
327330 	zynqmp_gqspi_write(xqspi,
328
-			GQSPI_QSPIDMA_DST_CTRL_OFST,
329
-			GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
331
+			   GQSPI_QSPIDMA_DST_CTRL_OFST,
332
+			   GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
330333 
331334 	/* Enable the GQSPI */
332335 	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
333336 }
334337 
335338 /**
336
- * zynqmp_qspi_copy_read_data:	Copy data to RX buffer
339
+ * zynqmp_qspi_copy_read_data - Copy data to RX buffer
337340  * @xqspi:	Pointer to the zynqmp_qspi structure
338341  * @data:	The variable where data is stored
339342  * @size:	Number of bytes to be copied from data to RX buffer
....@@ -347,41 +350,7 @@
347350 }
348351 
349352 /**
350
- * zynqmp_prepare_transfer_hardware:	Prepares hardware for transfer.
351
- * @master:	Pointer to the spi_master structure which provides
352
- *		information about the controller.
353
- *
354
- * This function enables SPI master controller.
355
- *
356
- * Return:	0 on success; error value otherwise
357
- */
358
-static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
359
-{
360
-	struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
361
-
362
-	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
363
-	return 0;
364
-}
365
-
366
-/**
367
- * zynqmp_unprepare_transfer_hardware:	Relaxes hardware after transfer
368
- * @master:	Pointer to the spi_master structure which provides
369
- *		information about the controller.
370
- *
371
- * This function disables the SPI master controller.
372
- *
373
- * Return:	Always 0
374
- */
375
-static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
376
-{
377
-	struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
378
-
379
-	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
380
-	return 0;
381
-}
382
-
383
-/**
384
- * zynqmp_qspi_chipselect:	Select or deselect the chip select line
353
+ * zynqmp_qspi_chipselect - Select or deselect the chip select line
385354  * @qspi:	Pointer to the spi_device structure
386355  * @is_high:	Select(0) or deselect (1) the chip select line
387356  */
....@@ -389,12 +358,14 @@
389358 {
390359 	struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
391360 	ulong timeout;
392
-	u32 genfifoentry = 0x0, statusreg;
361
+	u32 genfifoentry = 0, statusreg;
393362 
394363 	genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
395
-	genfifoentry |= xqspi->genfifobus;
396364 
397365 	if (!is_high) {
366
+		xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
367
+		xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
368
+		genfifoentry |= xqspi->genfifobus;
398369 		genfifoentry |= xqspi->genfifocs;
399370 		genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
400371 	} else {
....@@ -405,8 +376,8 @@
405376 
406377 	/* Manually start the generic FIFO command */
407378 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
408
-			zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
409
-			GQSPI_CFG_START_GEN_FIFO_MASK);
379
+			   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
380
+			   GQSPI_CFG_START_GEN_FIFO_MASK);
410381 
411382 	timeout = jiffies + msecs_to_jiffies(1000);
412383 
....@@ -415,10 +386,9 @@
415386 		statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
416387 
417388 		if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
418
-			(statusreg & GQSPI_ISR_TXEMPTY_MASK))
389
+		    (statusreg & GQSPI_ISR_TXEMPTY_MASK))
419390 			break;
420
-		else
421
-			cpu_relax();
391
+		cpu_relax();
422392 	} while (!time_after_eq(jiffies, timeout));
423393 
424394 	if (time_after_eq(jiffies, timeout))
....@@ -426,244 +396,13 @@
426396 }
427397 
428398 /**
429
- * zynqmp_qspi_setup_transfer:	Configure QSPI controller for specified
430
- *				transfer
431
- * @qspi:	Pointer to the spi_device structure
432
- * @transfer:	Pointer to the spi_transfer structure which provides
433
- *		information about next transfer setup parameters
434
- *
435
- * Sets the operational mode of QSPI controller for the next QSPI transfer and
436
- * sets the requested clock frequency.
437
- *
438
- * Return:	Always 0
439
- *
440
- * Note:
441
- *	If the requested frequency is not an exact match with what can be
442
- *	obtained using the pre-scalar value, the driver sets the clock
443
- *	frequency which is lower than the requested frequency (maximum lower)
444
- *	for the transfer.
445
- *
446
- *	If the requested frequency is higher or lower than that is supported
447
- *	by the QSPI controller the driver will set the highest or lowest
448
- *	frequency supported by controller.
449
- */
450
-static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
451
-				      struct spi_transfer *transfer)
452
-{
453
-	struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
454
-	ulong clk_rate;
455
-	u32 config_reg, req_hz, baud_rate_val = 0;
456
-
457
-	if (transfer)
458
-		req_hz = transfer->speed_hz;
459
-	else
460
-		req_hz = qspi->max_speed_hz;
461
-
462
-	/* Set the clock frequency */
463
-	/* If req_hz == 0, default to lowest speed */
464
-	clk_rate = clk_get_rate(xqspi->refclk);
465
-
466
-	while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
467
-	       (clk_rate /
468
-		(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
469
-		baud_rate_val++;
470
-
471
-	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
472
-
473
-	/* Set the QSPI clock phase and clock polarity */
474
-	config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
475
-
476
-	if (qspi->mode & SPI_CPHA)
477
-		config_reg |= GQSPI_CFG_CLK_PHA_MASK;
478
-	if (qspi->mode & SPI_CPOL)
479
-		config_reg |= GQSPI_CFG_CLK_POL_MASK;
480
-
481
-	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
482
-	config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
483
-	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
484
-	return 0;
485
-}
486
-
487
-/**
488
- * zynqmp_qspi_setup:	Configure the QSPI controller
489
- * @qspi:	Pointer to the spi_device structure
490
- *
491
- * Sets the operational mode of QSPI controller for the next QSPI transfer,
492
- * baud rate and divisor value to setup the requested qspi clock.
493
- *
494
- * Return:	0 on success; error value otherwise.
495
- */
496
-static int zynqmp_qspi_setup(struct spi_device *qspi)
497
-{
498
-	if (qspi->master->busy)
499
-		return -EBUSY;
500
-	return 0;
501
-}
502
-
503
-/**
504
- * zynqmp_qspi_filltxfifo:	Fills the TX FIFO as long as there is room in
505
- *				the FIFO or the bytes required to be
506
- *				transmitted.
507
- * @xqspi:	Pointer to the zynqmp_qspi structure
508
- * @size:	Number of bytes to be copied from TX buffer to TX FIFO
509
- */
510
-static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
511
-{
512
-	u32 count = 0, intermediate;
513
-
514
-	while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
515
-		memcpy(&intermediate, xqspi->txbuf, 4);
516
-		zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
517
-
518
-		if (xqspi->bytes_to_transfer >= 4) {
519
-			xqspi->txbuf += 4;
520
-			xqspi->bytes_to_transfer -= 4;
521
-		} else {
522
-			xqspi->txbuf += xqspi->bytes_to_transfer;
523
-			xqspi->bytes_to_transfer = 0;
524
-		}
525
-		count++;
526
-	}
527
-}
528
-
529
-/**
530
- * zynqmp_qspi_readrxfifo:	Fills the RX FIFO as long as there is room in
531
- *				the FIFO.
532
- * @xqspi:	Pointer to the zynqmp_qspi structure
533
- * @size:	Number of bytes to be copied from RX buffer to RX FIFO
534
- */
535
-static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
536
-{
537
-	ulong data;
538
-	int count = 0;
539
-
540
-	while ((count < size) && (xqspi->bytes_to_receive > 0)) {
541
-		if (xqspi->bytes_to_receive >= 4) {
542
-			(*(u32 *) xqspi->rxbuf) =
543
-			zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
544
-			xqspi->rxbuf += 4;
545
-			xqspi->bytes_to_receive -= 4;
546
-			count += 4;
547
-		} else {
548
-			data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
549
-			count += xqspi->bytes_to_receive;
550
-			zynqmp_qspi_copy_read_data(xqspi, data,
551
-						   xqspi->bytes_to_receive);
552
-			xqspi->bytes_to_receive = 0;
553
-		}
554
-	}
555
-}
556
-
557
-/**
558
- * zynqmp_process_dma_irq:	Handler for DMA done interrupt of QSPI
559
- *				controller
560
- * @xqspi:	zynqmp_qspi instance pointer
561
- *
562
- * This function handles DMA interrupt only.
563
- */
564
-static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
565
-{
566
-	u32 config_reg, genfifoentry;
567
-
568
-	dma_unmap_single(xqspi->dev, xqspi->dma_addr,
569
-				xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
570
-	xqspi->rxbuf += xqspi->dma_rx_bytes;
571
-	xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
572
-	xqspi->dma_rx_bytes = 0;
573
-
574
-	/* Disabling the DMA interrupts */
575
-	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
576
-					GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
577
-
578
-	if (xqspi->bytes_to_receive > 0) {
579
-		/* Switch to IO mode,for remaining bytes to receive */
580
-		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
581
-		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
582
-		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
583
-
584
-		/* Initiate the transfer of remaining bytes */
585
-		genfifoentry = xqspi->genfifoentry;
586
-		genfifoentry |= xqspi->bytes_to_receive;
587
-		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
588
-
589
-		/* Dummy generic FIFO entry */
590
-		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
591
-
592
-		/* Manual start */
593
-		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
594
-			(zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
595
-			GQSPI_CFG_START_GEN_FIFO_MASK));
596
-
597
-		/* Enable the RX interrupts for IO mode */
598
-		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
599
-				GQSPI_IER_GENFIFOEMPTY_MASK |
600
-				GQSPI_IER_RXNEMPTY_MASK |
601
-				GQSPI_IER_RXEMPTY_MASK);
602
-	}
603
-}
604
-
605
-/**
606
- * zynqmp_qspi_irq:	Interrupt service routine of the QSPI controller
607
- * @irq:	IRQ number
608
- * @dev_id:	Pointer to the xqspi structure
609
- *
610
- * This function handles TX empty only.
611
- * On TX empty interrupt this function reads the received data from RX FIFO
612
- * and fills the TX FIFO if there is any data remaining to be transferred.
613
- *
614
- * Return:	IRQ_HANDLED when interrupt is handled
615
- *		IRQ_NONE otherwise.
616
- */
617
-static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
618
-{
619
-	struct spi_master *master = dev_id;
620
-	struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
621
-	int ret = IRQ_NONE;
622
-	u32 status, mask, dma_status = 0;
623
-
624
-	status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
625
-	zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
626
-	mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
627
-
628
-	/* Read and clear DMA status */
629
-	if (xqspi->mode == GQSPI_MODE_DMA) {
630
-		dma_status =
631
-			zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
632
-		zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
633
-								dma_status);
634
-	}
635
-
636
-	if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
637
-		zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
638
-		ret = IRQ_HANDLED;
639
-	}
640
-
641
-	if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
642
-		zynqmp_process_dma_irq(xqspi);
643
-		ret = IRQ_HANDLED;
644
-	} else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
645
-			(mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
646
-		zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
647
-		ret = IRQ_HANDLED;
648
-	}
649
-
650
-	if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
651
-			&& ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
652
-		zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
653
-		spi_finalize_current_transfer(master);
654
-		ret = IRQ_HANDLED;
655
-	}
656
-	return ret;
657
-}
658
-
659
-/**
660
- * zynqmp_qspi_selectspimode:	Selects SPI mode - x1 or x2 or x4.
399
+ * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
661400  * @xqspi:	xqspi is a pointer to the GQSPI instance
662401  * @spimode:	spimode - SPI or DUAL or QUAD.
663402  * Return:	Mask to set desired SPI mode in GENFIFO entry.
664403  */
665404 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
666
-						u8 spimode)
405
+					    u8 spimode)
667406 {
668407 	u32 mask = 0;
669408 
....@@ -685,142 +424,166 @@
685424 }
686425 
687426 /**
688
- * zynq_qspi_setuprxdma:	This function sets up the RX DMA operation
689
- * @xqspi:	xqspi is a pointer to the GQSPI instance.
690
- */
691
-static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
692
-{
693
-	u32 rx_bytes, rx_rem, config_reg;
694
-	dma_addr_t addr;
695
-	u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
696
-
697
-	if ((xqspi->bytes_to_receive < 8) ||
698
-		((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
699
-		/* Setting to IO mode */
700
-		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
701
-		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
702
-		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
703
-		xqspi->mode = GQSPI_MODE_IO;
704
-		xqspi->dma_rx_bytes = 0;
705
-		return;
706
-	}
707
-
708
-	rx_rem = xqspi->bytes_to_receive % 4;
709
-	rx_bytes = (xqspi->bytes_to_receive - rx_rem);
710
-
711
-	addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
712
-						rx_bytes, DMA_FROM_DEVICE);
713
-	if (dma_mapping_error(xqspi->dev, addr))
714
-		dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
715
-
716
-	xqspi->dma_rx_bytes = rx_bytes;
717
-	xqspi->dma_addr = addr;
718
-	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
719
-				(u32)(addr & 0xffffffff));
720
-	addr = ((addr >> 16) >> 16);
721
-	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
722
-				((u32)addr) & 0xfff);
723
-
724
-	/* Enabling the DMA mode */
725
-	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
726
-	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
727
-	config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
728
-	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
729
-
730
-	/* Switch to DMA mode */
731
-	xqspi->mode = GQSPI_MODE_DMA;
732
-
733
-	/* Write the number of bytes to transfer */
734
-	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
735
-}
736
-
737
-/**
738
- * zynqmp_qspi_txrxsetup:	This function checks the TX/RX buffers in
739
- *				the transfer and sets up the GENFIFO entries,
740
- *				TX FIFO as required.
741
- * @xqspi:	xqspi is a pointer to the GQSPI instance.
742
- * @transfer:	It is a pointer to the structure containing transfer data.
743
- * @genfifoentry:	genfifoentry is pointer to the variable in which
744
- *			GENFIFO	mask is returned to calling function
745
- */
746
-static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
747
-				  struct spi_transfer *transfer,
748
-				  u32 *genfifoentry)
749
-{
750
-	u32 config_reg;
751
-
752
-	/* Transmit */
753
-	if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
754
-		/* Setup data to be TXed */
755
-		*genfifoentry &= ~GQSPI_GENFIFO_RX;
756
-		*genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
757
-		*genfifoentry |= GQSPI_GENFIFO_TX;
758
-		*genfifoentry |=
759
-			zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
760
-		xqspi->bytes_to_transfer = transfer->len;
761
-		if (xqspi->mode == GQSPI_MODE_DMA) {
762
-			config_reg = zynqmp_gqspi_read(xqspi,
763
-							GQSPI_CONFIG_OFST);
764
-			config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
765
-			zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
766
-								config_reg);
767
-			xqspi->mode = GQSPI_MODE_IO;
768
-		}
769
-		zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
770
-		/* Discard RX data */
771
-		xqspi->bytes_to_receive = 0;
772
-	} else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
773
-		/* Receive */
774
-
775
-		/* TX auto fill */
776
-		*genfifoentry &= ~GQSPI_GENFIFO_TX;
777
-		/* Setup RX */
778
-		*genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
779
-		*genfifoentry |= GQSPI_GENFIFO_RX;
780
-		*genfifoentry |=
781
-			zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
782
-		xqspi->bytes_to_transfer = 0;
783
-		xqspi->bytes_to_receive = transfer->len;
784
-		zynq_qspi_setuprxdma(xqspi);
785
-	}
786
-}
787
-
788
-/**
789
- * zynqmp_qspi_start_transfer:	Initiates the QSPI transfer
790
- * @master:	Pointer to the spi_master structure which provides
791
- *		information about the controller.
427
+ * zynqmp_qspi_config_op - Configure QSPI controller for specified
428
+ *				transfer
429
+ * @xqspi:	Pointer to the zynqmp_qspi structure
792430  * @qspi:	Pointer to the spi_device structure
793
- * @transfer:	Pointer to the spi_transfer structure which provide information
794
- *		about next transfer parameters
795431  *
796
- * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
797
- * transfer to be completed.
432
+ * Sets the operational mode of QSPI controller for the next QSPI transfer and
433
+ * sets the requested clock frequency.
798434  *
799
- * Return:	Number of bytes transferred in the last transfer
435
+ * Return:	Always 0
436
+ *
437
+ * Note:
438
+ *	If the requested frequency is not an exact match with what can be
439
+ *	obtained using the pre-scalar value, the driver sets the clock
440
+ *	frequency which is lower than the requested frequency (maximum lower)
441
+ *	for the transfer.
442
+ *
443
+ *	If the requested frequency is higher or lower than that is supported
444
+ *	by the QSPI controller the driver will set the highest or lowest
445
+ *	frequency supported by controller.
800446  */
801
-static int zynqmp_qspi_start_transfer(struct spi_master *master,
802
-				      struct spi_device *qspi,
803
-				      struct spi_transfer *transfer)
447
+static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
448
+				 struct spi_device *qspi)
804449 {
805
-	struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
806
-	u32 genfifoentry = 0x0, transfer_len;
450
+	ulong clk_rate;
451
+	u32 config_reg, baud_rate_val = 0;
807452 
808
-	xqspi->txbuf = transfer->tx_buf;
809
-	xqspi->rxbuf = transfer->rx_buf;
453
+	/* Set the clock frequency */
454
+	/* If req_hz == 0, default to lowest speed */
455
+	clk_rate = clk_get_rate(xqspi->refclk);
810456 
811
-	zynqmp_qspi_setup_transfer(qspi, transfer);
457
+	while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
458
+	       (clk_rate /
459
+		(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
460
+		baud_rate_val++;
812461 
813
-	genfifoentry |= xqspi->genfifocs;
814
-	genfifoentry |= xqspi->genfifobus;
462
+	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
815463 
816
-	zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
464
+	/* Set the QSPI clock phase and clock polarity */
465
+	config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
817466 
818
-	if (xqspi->mode == GQSPI_MODE_DMA)
819
-		transfer_len = xqspi->dma_rx_bytes;
820
-	else
821
-		transfer_len = transfer->len;
467
+	if (qspi->mode & SPI_CPHA)
468
+		config_reg |= GQSPI_CFG_CLK_PHA_MASK;
469
+	if (qspi->mode & SPI_CPOL)
470
+		config_reg |= GQSPI_CFG_CLK_POL_MASK;
822471 
472
+	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
473
+	config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
474
+	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
475
+	return 0;
476
+}
477
+
478
+/**
479
+ * zynqmp_qspi_setup_op - Configure the QSPI controller
480
+ * @qspi:	Pointer to the spi_device structure
481
+ *
482
+ * Sets the operational mode of QSPI controller for the next QSPI transfer,
483
+ * baud rate and divisor value to setup the requested qspi clock.
484
+ *
485
+ * Return:	0 on success; error value otherwise.
486
+ */
487
+static int zynqmp_qspi_setup_op(struct spi_device *qspi)
488
+{
489
+	struct spi_controller *ctlr = qspi->master;
490
+	struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
491
+
492
+	if (ctlr->busy)
493
+		return -EBUSY;
494
+
495
+	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
496
+
497
+	return 0;
498
+}
499
+
500
+/**
501
+ * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
502
+ *				the FIFO or the bytes required to be
503
+ *				transmitted.
504
+ * @xqspi:	Pointer to the zynqmp_qspi structure
505
+ * @size:	Number of bytes to be copied from TX buffer to TX FIFO
506
+ */
507
+static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
508
+{
509
+	u32 count = 0, intermediate;
510
+
511
+	while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
512
+		memcpy(&intermediate, xqspi->txbuf, 4);
513
+		zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
514
+
515
+		if (xqspi->bytes_to_transfer >= 4) {
516
+			xqspi->txbuf += 4;
517
+			xqspi->bytes_to_transfer -= 4;
518
+		} else {
519
+			xqspi->txbuf += xqspi->bytes_to_transfer;
520
+			xqspi->bytes_to_transfer = 0;
521
+		}
522
+		count++;
523
+	}
524
+}
525
+
526
+/**
527
+ * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
528
+ *				the FIFO.
529
+ * @xqspi:	Pointer to the zynqmp_qspi structure
530
+ * @size:	Number of bytes to be copied from RX buffer to RX FIFO
531
+ */
532
+static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
533
+{
534
+	ulong data;
535
+	int count = 0;
536
+
537
+	while ((count < size) && (xqspi->bytes_to_receive > 0)) {
538
+		if (xqspi->bytes_to_receive >= 4) {
539
+			(*(u32 *)xqspi->rxbuf) =
540
+			zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
541
+			xqspi->rxbuf += 4;
542
+			xqspi->bytes_to_receive -= 4;
543
+			count += 4;
544
+		} else {
545
+			data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
546
+			count += xqspi->bytes_to_receive;
547
+			zynqmp_qspi_copy_read_data(xqspi, data,
548
+						   xqspi->bytes_to_receive);
549
+			xqspi->bytes_to_receive = 0;
550
+		}
551
+	}
552
+}
553
+
554
+/**
555
+ * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
556
+ * @xqspi:	Pointer to the zynqmp_qspi structure
557
+ * @nbits:	Transfer/Receive buswidth.
558
+ * @genfifoentry:       Variable in which GENFIFO mask is saved
559
+ */
560
+static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
561
+				    u32 genfifoentry)
562
+{
563
+	u32 transfer_len = 0;
564
+
565
+	if (xqspi->txbuf) {
566
+		genfifoentry &= ~GQSPI_GENFIFO_RX;
567
+		genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
568
+		genfifoentry |= GQSPI_GENFIFO_TX;
569
+		transfer_len = xqspi->bytes_to_transfer;
570
+	} else if (xqspi->rxbuf) {
571
+		genfifoentry &= ~GQSPI_GENFIFO_TX;
572
+		genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
573
+		genfifoentry |= GQSPI_GENFIFO_RX;
574
+		if (xqspi->mode == GQSPI_MODE_DMA)
575
+			transfer_len = xqspi->dma_rx_bytes;
576
+		else
577
+			transfer_len = xqspi->bytes_to_receive;
578
+	} else {
579
+		/* Sending dummy circles here */
580
+		genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
581
+		genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
582
+		transfer_len = xqspi->bytes_to_transfer;
583
+	}
584
+	genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
823585 	xqspi->genfifoentry = genfifoentry;
586
+
824587 	if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
825588 		genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
826589 		genfifoentry |= transfer_len;
....@@ -838,7 +601,7 @@
838601 			while (tempcount != 0) {
839602 				if (tempcount & GQSPI_GENFIFO_EXP_START) {
840603 					genfifoentry &=
841
-					    ~GQSPI_GENFIFO_IMM_DATA_MASK;
604
+						~GQSPI_GENFIFO_IMM_DATA_MASK;
842605 					genfifoentry |= exponent;
843606 					zynqmp_gqspi_write(xqspi,
844607 							   GQSPI_GEN_FIFO_OFST,
....@@ -851,51 +614,223 @@
851614 		if (imm_data != 0) {
852615 			genfifoentry &= ~GQSPI_GENFIFO_EXP;
853616 			genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
854
-			genfifoentry |= (u8) (imm_data & 0xFF);
855
-			zynqmp_gqspi_write(xqspi,
856
-					   GQSPI_GEN_FIFO_OFST, genfifoentry);
617
+			genfifoentry |= (u8)(imm_data & 0xFF);
618
+			zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
619
+					   genfifoentry);
857620 		}
858621 	}
859
-
860
-	if ((xqspi->mode == GQSPI_MODE_IO) &&
861
-			(xqspi->rxbuf != NULL)) {
622
+	if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
862623 		/* Dummy generic FIFO entry */
863624 		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
864625 	}
865
-
866
-	/* Since we are using manual mode */
867
-	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
868
-			   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
869
-			   GQSPI_CFG_START_GEN_FIFO_MASK);
870
-
871
-	if (xqspi->txbuf != NULL)
872
-		/* Enable interrupts for TX */
873
-		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
874
-				   GQSPI_IER_TXEMPTY_MASK |
875
-					GQSPI_IER_GENFIFOEMPTY_MASK |
876
-					GQSPI_IER_TXNOT_FULL_MASK);
877
-
878
-	if (xqspi->rxbuf != NULL) {
879
-		/* Enable interrupts for RX */
880
-		if (xqspi->mode == GQSPI_MODE_DMA) {
881
-			/* Enable DMA interrupts */
882
-			zynqmp_gqspi_write(xqspi,
883
-					GQSPI_QSPIDMA_DST_I_EN_OFST,
884
-					GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
885
-		} else {
886
-			zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
887
-					GQSPI_IER_GENFIFOEMPTY_MASK |
888
-					GQSPI_IER_RXNEMPTY_MASK |
889
-					GQSPI_IER_RXEMPTY_MASK);
890
-		}
891
-	}
892
-
893
-	return transfer->len;
894626 }
895627 
896628 /**
897
- * zynqmp_qspi_suspend:	Suspend method for the QSPI driver
898
- * @_dev:	Address of the platform_device structure
629
+ * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
630
+ *				controller
631
+ * @xqspi:	zynqmp_qspi instance pointer
632
+ *
633
+ * This function handles DMA interrupt only.
634
+ */
635
+static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
636
+{
637
+	u32 config_reg, genfifoentry;
638
+
639
+	dma_unmap_single(xqspi->dev, xqspi->dma_addr,
640
+			 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
641
+	xqspi->rxbuf += xqspi->dma_rx_bytes;
642
+	xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
643
+	xqspi->dma_rx_bytes = 0;
644
+
645
+	/* Disabling the DMA interrupts */
646
+	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
647
+			   GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
648
+
649
+	if (xqspi->bytes_to_receive > 0) {
650
+		/* Switch to IO mode,for remaining bytes to receive */
651
+		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
652
+		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
653
+		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
654
+
655
+		/* Initiate the transfer of remaining bytes */
656
+		genfifoentry = xqspi->genfifoentry;
657
+		genfifoentry |= xqspi->bytes_to_receive;
658
+		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
659
+
660
+		/* Dummy generic FIFO entry */
661
+		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
662
+
663
+		/* Manual start */
664
+		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
665
+				   (zynqmp_gqspi_read(xqspi,
666
+						      GQSPI_CONFIG_OFST) |
667
+				   GQSPI_CFG_START_GEN_FIFO_MASK));
668
+
669
+		/* Enable the RX interrupts for IO mode */
670
+		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
671
+				   GQSPI_IER_GENFIFOEMPTY_MASK |
672
+				   GQSPI_IER_RXNEMPTY_MASK |
673
+				   GQSPI_IER_RXEMPTY_MASK);
674
+	}
675
+}
676
+
677
+/**
678
+ * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
679
+ * @irq:	IRQ number
680
+ * @dev_id:	Pointer to the xqspi structure
681
+ *
682
+ * This function handles TX empty only.
683
+ * On TX empty interrupt this function reads the received data from RX FIFO
684
+ * and fills the TX FIFO if there is any data remaining to be transferred.
685
+ *
686
+ * Return:	IRQ_HANDLED when interrupt is handled
687
+ *		IRQ_NONE otherwise.
688
+ */
689
+static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
690
+{
691
+	struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
692
+	irqreturn_t ret = IRQ_NONE;
693
+	u32 status, mask, dma_status = 0;
694
+
695
+	status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
696
+	zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
697
+	mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
698
+
699
+	/* Read and clear DMA status */
700
+	if (xqspi->mode == GQSPI_MODE_DMA) {
701
+		dma_status =
702
+			zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
703
+		zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
704
+				   dma_status);
705
+	}
706
+
707
+	if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
708
+		zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
709
+		ret = IRQ_HANDLED;
710
+	}
711
+
712
+	if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
713
+		zynqmp_process_dma_irq(xqspi);
714
+		ret = IRQ_HANDLED;
715
+	} else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
716
+			(mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
717
+		zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
718
+		ret = IRQ_HANDLED;
719
+	}
720
+
721
+	if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
722
+	    ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
723
+		zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
724
+		complete(&xqspi->data_completion);
725
+		ret = IRQ_HANDLED;
726
+	}
727
+	return ret;
728
+}
729
+
730
+/**
731
+ * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
732
+ * @xqspi:	xqspi is a pointer to the GQSPI instance.
733
+ */
734
+static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
735
+{
736
+	u32 rx_bytes, rx_rem, config_reg;
737
+	dma_addr_t addr;
738
+	u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
739
+
740
+	if (xqspi->bytes_to_receive < 8 ||
741
+	    ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
742
+		/* Setting to IO mode */
743
+		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
744
+		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
745
+		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
746
+		xqspi->mode = GQSPI_MODE_IO;
747
+		xqspi->dma_rx_bytes = 0;
748
+		return 0;
749
+	}
750
+
751
+	rx_rem = xqspi->bytes_to_receive % 4;
752
+	rx_bytes = (xqspi->bytes_to_receive - rx_rem);
753
+
754
+	addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
755
+			      rx_bytes, DMA_FROM_DEVICE);
756
+	if (dma_mapping_error(xqspi->dev, addr)) {
757
+		dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
758
+		return -ENOMEM;
759
+	}
760
+
761
+	xqspi->dma_rx_bytes = rx_bytes;
762
+	xqspi->dma_addr = addr;
763
+	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
764
+			   (u32)(addr & 0xffffffff));
765
+	addr = ((addr >> 16) >> 16);
766
+	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
767
+			   ((u32)addr) & 0xfff);
768
+
769
+	/* Enabling the DMA mode */
770
+	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
771
+	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
772
+	config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
773
+	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
774
+
775
+	/* Switch to DMA mode */
776
+	xqspi->mode = GQSPI_MODE_DMA;
777
+
778
+	/* Write the number of bytes to transfer */
779
+	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
780
+
781
+	return 0;
782
+}
783
+
784
+/**
785
+ * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
786
+ *			TX FIFO, and fills the TX FIFO with as many
787
+ *			bytes as possible.
788
+ * @xqspi:	Pointer to the GQSPI instance.
789
+ * @tx_nbits:	Transfer buswidth.
790
+ * @genfifoentry:	Variable in which GENFIFO mask is returned
791
+ *			to calling function
792
+ */
793
+static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
794
+				 u32 genfifoentry)
795
+{
796
+	u32 config_reg;
797
+
798
+	zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
799
+	zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
800
+	if (xqspi->mode == GQSPI_MODE_DMA) {
801
+		config_reg = zynqmp_gqspi_read(xqspi,
802
+					       GQSPI_CONFIG_OFST);
803
+		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
804
+		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
805
+				   config_reg);
806
+		xqspi->mode = GQSPI_MODE_IO;
807
+	}
808
+}
809
+
810
+/**
811
+ * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
812
+ *				RX DMA operation.
813
+ * @xqspi:	xqspi is a pointer to the GQSPI instance.
814
+ * @rx_nbits:	Receive buswidth.
815
+ * @genfifoentry:	genfifoentry is pointer to the variable in which
816
+ *			GENFIFO	mask is returned to calling function
817
+ */
818
+static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
819
+				u32 genfifoentry)
820
+{
821
+	int ret;
822
+
823
+	ret = zynqmp_qspi_setuprxdma(xqspi);
824
+	if (ret)
825
+		return ret;
826
+	zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
827
+
828
+	return 0;
829
+}
830
+
831
+/**
832
+ * zynqmp_qspi_suspend - Suspend method for the QSPI driver
833
+ * @dev:	Address of the platform_device structure
899834  *
900835  * This function stops the QSPI driver queue and disables the QSPI controller
901836  *
....@@ -903,17 +838,21 @@
903838  */
904839 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
905840 {
906
-	struct spi_master *master = dev_get_drvdata(dev);
841
+	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
842
+	struct spi_controller *ctlr = xqspi->ctlr;
843
+	int ret;
907844 
908
-	spi_master_suspend(master);
845
+	ret = spi_controller_suspend(ctlr);
846
+	if (ret)
847
+		return ret;
909848 
910
-	zynqmp_unprepare_transfer_hardware(master);
849
+	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
911850 
912851 	return 0;
913852 }
914853 
915854 /**
916
- * zynqmp_qspi_resume:	Resume method for the QSPI driver
855
+ * zynqmp_qspi_resume - Resume method for the QSPI driver
917856  * @dev:	Address of the platform_device structure
918857  *
919858  * The function starts the QSPI driver queue and initializes the QSPI
....@@ -923,27 +862,13 @@
923862  */
924863 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
925864 {
926
-	struct spi_master *master = dev_get_drvdata(dev);
927
-	struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
928
-	int ret = 0;
865
+	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
866
+	struct spi_controller *ctlr = xqspi->ctlr;
929867 
930
-	ret = clk_enable(xqspi->pclk);
931
-	if (ret) {
932
-		dev_err(dev, "Cannot enable APB clock.\n");
933
-		return ret;
934
-	}
868
+	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
935869 
936
-	ret = clk_enable(xqspi->refclk);
937
-	if (ret) {
938
-		dev_err(dev, "Cannot enable device clock.\n");
939
-		clk_disable(xqspi->pclk);
940
-		return ret;
941
-	}
870
+	spi_controller_resume(ctlr);
942871 
943
-	spi_master_resume(master);
944
-
945
-	clk_disable(xqspi->refclk);
946
-	clk_disable(xqspi->pclk);
947872 	return 0;
948873 }
949874 
....@@ -957,12 +882,10 @@
957882  */
958883 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
959884 {
960
-	struct platform_device *pdev = to_platform_device(dev);
961
-	struct spi_master *master = platform_get_drvdata(pdev);
962
-	struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
885
+	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
963886 
964
-	clk_disable(xqspi->refclk);
965
-	clk_disable(xqspi->pclk);
887
+	clk_disable_unprepare(xqspi->refclk);
888
+	clk_disable_unprepare(xqspi->pclk);
966889 
967890 	return 0;
968891 }
....@@ -977,25 +900,176 @@
977900  */
978901 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
979902 {
980
-	struct platform_device *pdev = to_platform_device(dev);
981
-	struct spi_master *master = platform_get_drvdata(pdev);
982
-	struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
903
+	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
983904 	int ret;
984905 
985
-	ret = clk_enable(xqspi->pclk);
906
+	ret = clk_prepare_enable(xqspi->pclk);
986907 	if (ret) {
987908 		dev_err(dev, "Cannot enable APB clock.\n");
988909 		return ret;
989910 	}
990911 
991
-	ret = clk_enable(xqspi->refclk);
912
+	ret = clk_prepare_enable(xqspi->refclk);
992913 	if (ret) {
993914 		dev_err(dev, "Cannot enable device clock.\n");
994
-		clk_disable(xqspi->pclk);
915
+		clk_disable_unprepare(xqspi->pclk);
995916 		return ret;
996917 	}
997918 
998919 	return 0;
920
+}
921
+
922
+/**
923
+ * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
924
+ * @mem: The SPI memory
925
+ * @op: The memory operation to execute
926
+ *
927
+ * Executes a memory operation.
928
+ *
929
+ * This function first selects the chip and starts the memory operation.
930
+ *
931
+ * Return: 0 in case of success, a negative error code otherwise.
932
+ */
933
+static int zynqmp_qspi_exec_op(struct spi_mem *mem,
934
+			       const struct spi_mem_op *op)
935
+{
936
+	struct zynqmp_qspi *xqspi = spi_controller_get_devdata
937
+				    (mem->spi->master);
938
+	int err = 0, i;
939
+	u32 genfifoentry = 0;
940
+	u16 opcode = op->cmd.opcode;
941
+	u64 opaddr;
942
+
943
+	dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
944
+		op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
945
+		op->dummy.buswidth, op->data.buswidth);
946
+
947
+	mutex_lock(&xqspi->op_lock);
948
+	zynqmp_qspi_config_op(xqspi, mem->spi);
949
+	zynqmp_qspi_chipselect(mem->spi, false);
950
+	genfifoentry |= xqspi->genfifocs;
951
+	genfifoentry |= xqspi->genfifobus;
952
+
953
+	if (op->cmd.opcode) {
954
+		reinit_completion(&xqspi->data_completion);
955
+		xqspi->txbuf = &opcode;
956
+		xqspi->rxbuf = NULL;
957
+		xqspi->bytes_to_transfer = op->cmd.nbytes;
958
+		xqspi->bytes_to_receive = 0;
959
+		zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
960
+		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
961
+				   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
962
+				   GQSPI_CFG_START_GEN_FIFO_MASK);
963
+		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
964
+				   GQSPI_IER_GENFIFOEMPTY_MASK |
965
+				   GQSPI_IER_TXNOT_FULL_MASK);
966
+		if (!wait_for_completion_timeout
967
+		    (&xqspi->data_completion, msecs_to_jiffies(1000))) {
968
+			err = -ETIMEDOUT;
969
+			goto return_err;
970
+		}
971
+	}
972
+
973
+	if (op->addr.nbytes) {
974
+		xqspi->txbuf = &opaddr;
975
+		for (i = 0; i < op->addr.nbytes; i++) {
976
+			*(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
977
+					(8 * (op->addr.nbytes - i - 1));
978
+		}
979
+
980
+		reinit_completion(&xqspi->data_completion);
981
+		xqspi->rxbuf = NULL;
982
+		xqspi->bytes_to_transfer = op->addr.nbytes;
983
+		xqspi->bytes_to_receive = 0;
984
+		zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
985
+		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
986
+				   zynqmp_gqspi_read(xqspi,
987
+						     GQSPI_CONFIG_OFST) |
988
+				   GQSPI_CFG_START_GEN_FIFO_MASK);
989
+		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
990
+				   GQSPI_IER_TXEMPTY_MASK |
991
+				   GQSPI_IER_GENFIFOEMPTY_MASK |
992
+				   GQSPI_IER_TXNOT_FULL_MASK);
993
+		if (!wait_for_completion_timeout
994
+		    (&xqspi->data_completion, msecs_to_jiffies(1000))) {
995
+			err = -ETIMEDOUT;
996
+			goto return_err;
997
+		}
998
+	}
999
+
1000
+	if (op->dummy.nbytes) {
1001
+		xqspi->txbuf = NULL;
1002
+		xqspi->rxbuf = NULL;
1003
+		/*
1004
+		 * xqspi->bytes_to_transfer here represents the dummy circles
1005
+		 * which need to be sent.
1006
+		 */
1007
+		xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
1008
+		xqspi->bytes_to_receive = 0;
1009
+		/*
1010
+		 * Using op->data.buswidth instead of op->dummy.buswidth here because
1011
+		 * we need to use it to configure the correct SPI mode.
1012
+		 */
1013
+		zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1014
+				     genfifoentry);
1015
+		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1016
+				   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1017
+				   GQSPI_CFG_START_GEN_FIFO_MASK);
1018
+	}
1019
+
1020
+	if (op->data.nbytes) {
1021
+		reinit_completion(&xqspi->data_completion);
1022
+		if (op->data.dir == SPI_MEM_DATA_OUT) {
1023
+			xqspi->txbuf = (u8 *)op->data.buf.out;
1024
+			xqspi->rxbuf = NULL;
1025
+			xqspi->bytes_to_transfer = op->data.nbytes;
1026
+			xqspi->bytes_to_receive = 0;
1027
+			zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1028
+					     genfifoentry);
1029
+			zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1030
+					   zynqmp_gqspi_read
1031
+					   (xqspi, GQSPI_CONFIG_OFST) |
1032
+					   GQSPI_CFG_START_GEN_FIFO_MASK);
1033
+			zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1034
+					   GQSPI_IER_TXEMPTY_MASK |
1035
+					   GQSPI_IER_GENFIFOEMPTY_MASK |
1036
+					   GQSPI_IER_TXNOT_FULL_MASK);
1037
+		} else {
1038
+			xqspi->txbuf = NULL;
1039
+			xqspi->rxbuf = (u8 *)op->data.buf.in;
1040
+			xqspi->bytes_to_receive = op->data.nbytes;
1041
+			xqspi->bytes_to_transfer = 0;
1042
+			err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,
1043
+					    genfifoentry);
1044
+			if (err)
1045
+				goto return_err;
1046
+
1047
+			zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1048
+					   zynqmp_gqspi_read
1049
+					   (xqspi, GQSPI_CONFIG_OFST) |
1050
+					   GQSPI_CFG_START_GEN_FIFO_MASK);
1051
+			if (xqspi->mode == GQSPI_MODE_DMA) {
1052
+				zynqmp_gqspi_write
1053
+					(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
1054
+					 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1055
+			} else {
1056
+				zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1057
+						   GQSPI_IER_GENFIFOEMPTY_MASK |
1058
+						   GQSPI_IER_RXNEMPTY_MASK |
1059
+						   GQSPI_IER_RXEMPTY_MASK);
1060
+			}
1061
+		}
1062
+		if (!wait_for_completion_timeout
1063
+		    (&xqspi->data_completion, msecs_to_jiffies(1000)))
1064
+			err = -ETIMEDOUT;
1065
+	}
1066
+
1067
+return_err:
1068
+
1069
+	zynqmp_qspi_chipselect(mem->spi, true);
1070
+	mutex_unlock(&xqspi->op_lock);
1071
+
1072
+	return err;
9991073 }
10001074 
10011075 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
....@@ -1004,8 +1078,12 @@
10041078 	SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
10051079 };
10061080 
1081
+static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
1082
+	.exec_op = zynqmp_qspi_exec_op,
1083
+};
1084
+
10071085 /**
1008
- * zynqmp_qspi_probe:	Probe method for the QSPI driver
1086
+ * zynqmp_qspi_probe - Probe method for the QSPI driver
10091087  * @pdev:	Pointer to the platform_device structure
10101088  *
10111089  * This function initializes the driver data structures and the hardware.
....@@ -1015,31 +1093,37 @@
10151093 static int zynqmp_qspi_probe(struct platform_device *pdev)
10161094 {
10171095 	int ret = 0;
1018
-	struct spi_master *master;
1096
+	struct spi_controller *ctlr;
10191097 	struct zynqmp_qspi *xqspi;
1020
-	struct resource *res;
10211098 	struct device *dev = &pdev->dev;
1099
+	struct device_node *np = dev->of_node;
10221100 
1023
-	master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1024
-	if (!master)
1101
+	ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1102
+	if (!ctlr)
10251103 		return -ENOMEM;
10261104 
1027
-	xqspi = spi_master_get_devdata(master);
1028
-	master->dev.of_node = pdev->dev.of_node;
1029
-	platform_set_drvdata(pdev, master);
1105
+	xqspi = spi_controller_get_devdata(ctlr);
1106
+	xqspi->dev = dev;
1107
+	xqspi->ctlr = ctlr;
1108
+	platform_set_drvdata(pdev, xqspi);
10301109 
1031
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1032
-	xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
1110
+	xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
10331111 	if (IS_ERR(xqspi->regs)) {
10341112 		ret = PTR_ERR(xqspi->regs);
10351113 		goto remove_master;
10361114 	}
10371115 
1038
-	xqspi->dev = dev;
10391116 	xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
10401117 	if (IS_ERR(xqspi->pclk)) {
10411118 		dev_err(dev, "pclk clock not found.\n");
10421119 		ret = PTR_ERR(xqspi->pclk);
1120
+		goto remove_master;
1121
+	}
1122
+
1123
+	xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1124
+	if (IS_ERR(xqspi->refclk)) {
1125
+		dev_err(dev, "ref_clk clock not found.\n");
1126
+		ret = PTR_ERR(xqspi->refclk);
10431127 		goto remove_master;
10441128 	}
10451129 
....@@ -1049,78 +1133,84 @@
10491133 		goto remove_master;
10501134 	}
10511135 
1052
-	xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1053
-	if (IS_ERR(xqspi->refclk)) {
1054
-		dev_err(dev, "ref_clk clock not found.\n");
1055
-		ret = PTR_ERR(xqspi->refclk);
1056
-		goto clk_dis_pclk;
1057
-	}
1058
-
10591136 	ret = clk_prepare_enable(xqspi->refclk);
10601137 	if (ret) {
10611138 		dev_err(dev, "Unable to enable device clock.\n");
10621139 		goto clk_dis_pclk;
10631140 	}
10641141 
1142
+	init_completion(&xqspi->data_completion);
1143
+
1144
+	mutex_init(&xqspi->op_lock);
1145
+
10651146 	pm_runtime_use_autosuspend(&pdev->dev);
10661147 	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
10671148 	pm_runtime_set_active(&pdev->dev);
10681149 	pm_runtime_enable(&pdev->dev);
1150
+
1151
+	ret = pm_runtime_get_sync(&pdev->dev);
1152
+	if (ret < 0) {
1153
+		dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);
1154
+		goto clk_dis_all;
1155
+	}
1156
+
10691157 	/* QSPI controller initializations */
10701158 	zynqmp_qspi_init_hw(xqspi);
10711159 
1072
-	pm_runtime_mark_last_busy(&pdev->dev);
1073
-	pm_runtime_put_autosuspend(&pdev->dev);
10741160 	xqspi->irq = platform_get_irq(pdev, 0);
10751161 	if (xqspi->irq <= 0) {
10761162 		ret = -ENXIO;
1077
-		dev_err(dev, "irq resource not found\n");
10781163 		goto clk_dis_all;
10791164 	}
10801165 	ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1081
-			       0, pdev->name, master);
1166
+			       0, pdev->name, xqspi);
10821167 	if (ret != 0) {
10831168 		ret = -ENXIO;
10841169 		dev_err(dev, "request_irq failed\n");
10851170 		goto clk_dis_all;
10861171 	}
10871172 
1088
-	master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1089
-
1090
-	master->setup = zynqmp_qspi_setup;
1091
-	master->set_cs = zynqmp_qspi_chipselect;
1092
-	master->transfer_one = zynqmp_qspi_start_transfer;
1093
-	master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1094
-	master->unprepare_transfer_hardware =
1095
-					zynqmp_unprepare_transfer_hardware;
1096
-	master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1097
-	master->bits_per_word_mask = SPI_BPW_MASK(8);
1098
-	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1099
-			    SPI_TX_DUAL | SPI_TX_QUAD;
1100
-
1101
-	if (master->dev.parent == NULL)
1102
-		master->dev.parent = &master->dev;
1103
-
1104
-	ret = spi_register_master(master);
1173
+	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
11051174 	if (ret)
11061175 		goto clk_dis_all;
1176
+
1177
+	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1178
+	ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1179
+	ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1180
+	ctlr->setup = zynqmp_qspi_setup_op;
1181
+	ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1182
+	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1183
+	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1184
+			    SPI_TX_DUAL | SPI_TX_QUAD;
1185
+	ctlr->dev.of_node = np;
1186
+	ctlr->auto_runtime_pm = true;
1187
+
1188
+	ret = devm_spi_register_controller(&pdev->dev, ctlr);
1189
+	if (ret) {
1190
+		dev_err(&pdev->dev, "spi_register_controller failed\n");
1191
+		goto clk_dis_all;
1192
+	}
1193
+
1194
+	pm_runtime_mark_last_busy(&pdev->dev);
1195
+	pm_runtime_put_autosuspend(&pdev->dev);
11071196 
11081197 	return 0;
11091198 
11101199 clk_dis_all:
1111
-	pm_runtime_set_suspended(&pdev->dev);
11121200 	pm_runtime_disable(&pdev->dev);
1201
+	pm_runtime_put_noidle(&pdev->dev);
1202
+	pm_runtime_set_suspended(&pdev->dev);
11131203 	clk_disable_unprepare(xqspi->refclk);
11141204 clk_dis_pclk:
11151205 	clk_disable_unprepare(xqspi->pclk);
11161206 remove_master:
1117
-	spi_master_put(master);
1207
+	spi_controller_put(ctlr);
11181208 
11191209 	return ret;
11201210 }
11211211 
11221212 /**
1123
- * zynqmp_qspi_remove:	Remove method for the QSPI driver
1213
+ * zynqmp_qspi_remove - Remove method for the QSPI driver
11241214  * @pdev:	Pointer to the platform_device structure
11251215  *
11261216  * This function is called if a device is physically removed from the system or
....@@ -1131,16 +1221,17 @@
11311221  */
11321222 static int zynqmp_qspi_remove(struct platform_device *pdev)
11331223 {
1134
-	struct spi_master *master = platform_get_drvdata(pdev);
1135
-	struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1224
+	struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
1225
+
1226
+	pm_runtime_get_sync(&pdev->dev);
11361227 
11371228 	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1229
+
1230
+	pm_runtime_disable(&pdev->dev);
1231
+	pm_runtime_put_noidle(&pdev->dev);
1232
+	pm_runtime_set_suspended(&pdev->dev);
11381233 	clk_disable_unprepare(xqspi->refclk);
11391234 	clk_disable_unprepare(xqspi->pclk);
1140
-	pm_runtime_set_suspended(&pdev->dev);
1141
-	pm_runtime_disable(&pdev->dev);
1142
-
1143
-	spi_unregister_master(master);
11441235 
11451236 	return 0;
11461237 }