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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/spi/spi-tegra20-sflash.c
....@@ -1,21 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * SPI driver for Nvidia's Tegra20 Serial Flash Controller.
34  *
45  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
56  *
67  * Author: Laxman Dewangan <ldewangan@nvidia.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify it
9
- * under the terms and conditions of the GNU General Public License,
10
- * version 2, as published by the Free Software Foundation.
11
- *
12
- * This program is distributed in the hope it will be useful, but WITHOUT
13
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15
- * more details.
16
- *
17
- * You should have received a copy of the GNU General Public License
18
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
198  */
209 
2110 #include <linux/clk.h>
....@@ -352,10 +341,11 @@
352341 			goto exit;
353342 		}
354343 		msg->actual_length += xfer->len;
355
-		if (xfer->cs_change && xfer->delay_usecs) {
344
+		if (xfer->cs_change &&
345
+		    (xfer->delay_usecs || xfer->delay.value)) {
356346 			tegra_sflash_writel(tsd, tsd->def_command_reg,
357347 					SPI_COMMAND);
358
-			udelay(xfer->delay_usecs);
348
+			spi_transfer_delay_exec(xfer);
359349 		}
360350 	}
361351 	ret = 0;
....@@ -369,9 +359,8 @@
369359 static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
370360 {
371361 	struct spi_transfer *t = tsd->curr_xfer;
372
-	unsigned long flags;
373362 
374
-	spin_lock_irqsave(&tsd->lock, flags);
363
+	spin_lock(&tsd->lock);
375364 	if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {
376365 		dev_err(tsd->dev,
377366 			"CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);
....@@ -401,7 +390,7 @@
401390 	tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);
402391 	tegra_sflash_start_cpu_based_transfer(tsd, t);
403392 exit:
404
-	spin_unlock_irqrestore(&tsd->lock, flags);
393
+	spin_unlock(&tsd->lock);
405394 	return IRQ_HANDLED;
406395 }
407396 
....@@ -430,7 +419,6 @@
430419 {
431420 	struct spi_master	*master;
432421 	struct tegra_sflash_data	*tsd;
433
-	struct resource		*r;
434422 	int ret;
435423 	const struct of_device_id *match;
436424 
....@@ -462,14 +450,17 @@
462450 				 &master->max_speed_hz))
463451 		master->max_speed_hz = 25000000; /* 25MHz */
464452 
465
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
466
-	tsd->base = devm_ioremap_resource(&pdev->dev, r);
453
+	tsd->base = devm_platform_ioremap_resource(pdev, 0);
467454 	if (IS_ERR(tsd->base)) {
468455 		ret = PTR_ERR(tsd->base);
469456 		goto exit_free_master;
470457 	}
471458 
472
-	tsd->irq = platform_get_irq(pdev, 0);
459
+	ret = platform_get_irq(pdev, 0);
460
+	if (ret < 0)
461
+		goto exit_free_master;
462
+	tsd->irq = ret;
463
+
473464 	ret = request_irq(tsd->irq, tegra_sflash_isr, 0,
474465 			dev_name(&pdev->dev), tsd);
475466 	if (ret < 0) {
....@@ -503,6 +494,7 @@
503494 	ret = pm_runtime_get_sync(&pdev->dev);
504495 	if (ret < 0) {
505496 		dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
497
+		pm_runtime_put_noidle(&pdev->dev);
506498 		goto exit_pm_disable;
507499 	}
508500