~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,131 +1,270 @@
1		-/*
2		- * STMicroelectronics STM32 SPI Controller driver (master mode only)
3		- *
4		- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5		- * Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
6		- *
7		- * License terms: GPL V2.0.
8		- *
9		- * spi_stm32 driver is free software; you can redistribute it and/or modify it
10		- * under the terms of the GNU General Public License version 2 as published by
11		- * the Free Software Foundation.
12		- *
13		- * spi_stm32 driver is distributed in the hope that it will be useful, but
14		- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15		- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
16		- * details.
17		- *
18		- * You should have received a copy of the GNU General Public License along with
19		- * spi_stm32 driver. If not, see <http://www.gnu.org/licenses/>.
20		- */
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// STMicroelectronics STM32 SPI Controller driver (master mode only)
	4	+//
	5	+// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
	6	+// Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
	7	+
21	8	#include <linux/debugfs.h>
22	9	#include <linux/clk.h>
23	10	#include <linux/delay.h>
24	11	#include <linux/dmaengine.h>
25		-#include <linux/gpio.h>
26	12	#include <linux/interrupt.h>
27	13	#include <linux/iopoll.h>
28	14	#include <linux/module.h>
29	15	#include <linux/of_platform.h>
	16	+#include <linux/pinctrl/consumer.h>
30	17	#include <linux/pm_runtime.h>
31	18	#include <linux/reset.h>
32	19	#include <linux/spi/spi.h>
33	20
34	21	#define DRIVER_NAME "spi_stm32"
35	22
36		-/* STM32 SPI registers */
37		-#define STM32_SPI_CR1 0x00
38		-#define STM32_SPI_CR2 0x04
39		-#define STM32_SPI_CFG1 0x08
40		-#define STM32_SPI_CFG2 0x0C
41		-#define STM32_SPI_IER 0x10
42		-#define STM32_SPI_SR 0x14
43		-#define STM32_SPI_IFCR 0x18
44		-#define STM32_SPI_TXDR 0x20
45		-#define STM32_SPI_RXDR 0x30
46		-#define STM32_SPI_I2SCFGR 0x50
	23	+/* STM32F4 SPI registers */
	24	+#define STM32F4_SPI_CR1 0x00
	25	+#define STM32F4_SPI_CR2 0x04
	26	+#define STM32F4_SPI_SR 0x08
	27	+#define STM32F4_SPI_DR 0x0C
	28	+#define STM32F4_SPI_I2SCFGR 0x1C
47	29
48		-/* STM32_SPI_CR1 bit fields */
49		-#define SPI_CR1_SPE BIT(0)
50		-#define SPI_CR1_MASRX BIT(8)
51		-#define SPI_CR1_CSTART BIT(9)
52		-#define SPI_CR1_CSUSP BIT(10)
53		-#define SPI_CR1_HDDIR BIT(11)
54		-#define SPI_CR1_SSI BIT(12)
	30	+/* STM32F4_SPI_CR1 bit fields */
	31	+#define STM32F4_SPI_CR1_CPHA BIT(0)
	32	+#define STM32F4_SPI_CR1_CPOL BIT(1)
	33	+#define STM32F4_SPI_CR1_MSTR BIT(2)
	34	+#define STM32F4_SPI_CR1_BR_SHIFT 3
	35	+#define STM32F4_SPI_CR1_BR GENMASK(5, 3)
	36	+#define STM32F4_SPI_CR1_SPE BIT(6)
	37	+#define STM32F4_SPI_CR1_LSBFRST BIT(7)
	38	+#define STM32F4_SPI_CR1_SSI BIT(8)
	39	+#define STM32F4_SPI_CR1_SSM BIT(9)
	40	+#define STM32F4_SPI_CR1_RXONLY BIT(10)
	41	+#define STM32F4_SPI_CR1_DFF BIT(11)
	42	+#define STM32F4_SPI_CR1_CRCNEXT BIT(12)
	43	+#define STM32F4_SPI_CR1_CRCEN BIT(13)
	44	+#define STM32F4_SPI_CR1_BIDIOE BIT(14)
	45	+#define STM32F4_SPI_CR1_BIDIMODE BIT(15)
	46	+#define STM32F4_SPI_CR1_BR_MIN 0
	47	+#define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
55	48
56		-/* STM32_SPI_CR2 bit fields */
57		-#define SPI_CR2_TSIZE_SHIFT 0
58		-#define SPI_CR2_TSIZE GENMASK(15, 0)
	49	+/* STM32F4_SPI_CR2 bit fields */
	50	+#define STM32F4_SPI_CR2_RXDMAEN BIT(0)
	51	+#define STM32F4_SPI_CR2_TXDMAEN BIT(1)
	52	+#define STM32F4_SPI_CR2_SSOE BIT(2)
	53	+#define STM32F4_SPI_CR2_FRF BIT(4)
	54	+#define STM32F4_SPI_CR2_ERRIE BIT(5)
	55	+#define STM32F4_SPI_CR2_RXNEIE BIT(6)
	56	+#define STM32F4_SPI_CR2_TXEIE BIT(7)
59	57
60		-/* STM32_SPI_CFG1 bit fields */
61		-#define SPI_CFG1_DSIZE_SHIFT 0
62		-#define SPI_CFG1_DSIZE GENMASK(4, 0)
63		-#define SPI_CFG1_FTHLV_SHIFT 5
64		-#define SPI_CFG1_FTHLV GENMASK(8, 5)
65		-#define SPI_CFG1_RXDMAEN BIT(14)
66		-#define SPI_CFG1_TXDMAEN BIT(15)
67		-#define SPI_CFG1_MBR_SHIFT 28
68		-#define SPI_CFG1_MBR GENMASK(30, 28)
69		-#define SPI_CFG1_MBR_MIN 0
70		-#define SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
	58	+/* STM32F4_SPI_SR bit fields */
	59	+#define STM32F4_SPI_SR_RXNE BIT(0)
	60	+#define STM32F4_SPI_SR_TXE BIT(1)
	61	+#define STM32F4_SPI_SR_CHSIDE BIT(2)
	62	+#define STM32F4_SPI_SR_UDR BIT(3)
	63	+#define STM32F4_SPI_SR_CRCERR BIT(4)
	64	+#define STM32F4_SPI_SR_MODF BIT(5)
	65	+#define STM32F4_SPI_SR_OVR BIT(6)
	66	+#define STM32F4_SPI_SR_BSY BIT(7)
	67	+#define STM32F4_SPI_SR_FRE BIT(8)
71	68
72		-/* STM32_SPI_CFG2 bit fields */
73		-#define SPI_CFG2_MIDI_SHIFT 4
74		-#define SPI_CFG2_MIDI GENMASK(7, 4)
75		-#define SPI_CFG2_COMM_SHIFT 17
76		-#define SPI_CFG2_COMM GENMASK(18, 17)
77		-#define SPI_CFG2_SP_SHIFT 19
78		-#define SPI_CFG2_SP GENMASK(21, 19)
79		-#define SPI_CFG2_MASTER BIT(22)
80		-#define SPI_CFG2_LSBFRST BIT(23)
81		-#define SPI_CFG2_CPHA BIT(24)
82		-#define SPI_CFG2_CPOL BIT(25)
83		-#define SPI_CFG2_SSM BIT(26)
84		-#define SPI_CFG2_AFCNTR BIT(31)
	69	+/* STM32F4_SPI_I2SCFGR bit fields */
	70	+#define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
85	71
86		-/* STM32_SPI_IER bit fields */
87		-#define SPI_IER_RXPIE BIT(0)
88		-#define SPI_IER_TXPIE BIT(1)
89		-#define SPI_IER_DXPIE BIT(2)
90		-#define SPI_IER_EOTIE BIT(3)
91		-#define SPI_IER_TXTFIE BIT(4)
92		-#define SPI_IER_OVRIE BIT(6)
93		-#define SPI_IER_MODFIE BIT(9)
94		-#define SPI_IER_ALL GENMASK(10, 0)
	72	+/* STM32F4 SPI Baud Rate min/max divisor */
	73	+#define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
	74	+#define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
95	75
96		-/* STM32_SPI_SR bit fields */
97		-#define SPI_SR_RXP BIT(0)
98		-#define SPI_SR_TXP BIT(1)
99		-#define SPI_SR_EOT BIT(3)
100		-#define SPI_SR_OVR BIT(6)
101		-#define SPI_SR_MODF BIT(9)
102		-#define SPI_SR_SUSP BIT(11)
103		-#define SPI_SR_RXPLVL_SHIFT 13
104		-#define SPI_SR_RXPLVL GENMASK(14, 13)
105		-#define SPI_SR_RXWNE BIT(15)
	76	+/* STM32H7 SPI registers */
	77	+#define STM32H7_SPI_CR1 0x00
	78	+#define STM32H7_SPI_CR2 0x04
	79	+#define STM32H7_SPI_CFG1 0x08
	80	+#define STM32H7_SPI_CFG2 0x0C
	81	+#define STM32H7_SPI_IER 0x10
	82	+#define STM32H7_SPI_SR 0x14
	83	+#define STM32H7_SPI_IFCR 0x18
	84	+#define STM32H7_SPI_TXDR 0x20
	85	+#define STM32H7_SPI_RXDR 0x30
	86	+#define STM32H7_SPI_I2SCFGR 0x50
106	87
107		-/* STM32_SPI_IFCR bit fields */
108		-#define SPI_IFCR_ALL GENMASK(11, 3)
	88	+/* STM32H7_SPI_CR1 bit fields */
	89	+#define STM32H7_SPI_CR1_SPE BIT(0)
	90	+#define STM32H7_SPI_CR1_MASRX BIT(8)
	91	+#define STM32H7_SPI_CR1_CSTART BIT(9)
	92	+#define STM32H7_SPI_CR1_CSUSP BIT(10)
	93	+#define STM32H7_SPI_CR1_HDDIR BIT(11)
	94	+#define STM32H7_SPI_CR1_SSI BIT(12)
109	95
110		-/* STM32_SPI_I2SCFGR bit fields */
111		-#define SPI_I2SCFGR_I2SMOD BIT(0)
	96	+/* STM32H7_SPI_CR2 bit fields */
	97	+#define STM32H7_SPI_CR2_TSIZE_SHIFT 0
	98	+#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
112	99
113		-/* SPI Master Baud Rate min/max divisor */
114		-#define SPI_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
115		-#define SPI_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
	100	+/* STM32H7_SPI_CFG1 bit fields */
	101	+#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
	102	+#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
	103	+#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
	104	+#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
	105	+#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
	106	+#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
	107	+#define STM32H7_SPI_CFG1_MBR_SHIFT 28
	108	+#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
	109	+#define STM32H7_SPI_CFG1_MBR_MIN 0
	110	+#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
116	111
117		-/* SPI Communication mode */
	112	+/* STM32H7_SPI_CFG2 bit fields */
	113	+#define STM32H7_SPI_CFG2_MIDI_SHIFT 4
	114	+#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
	115	+#define STM32H7_SPI_CFG2_COMM_SHIFT 17
	116	+#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
	117	+#define STM32H7_SPI_CFG2_SP_SHIFT 19
	118	+#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
	119	+#define STM32H7_SPI_CFG2_MASTER BIT(22)
	120	+#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
	121	+#define STM32H7_SPI_CFG2_CPHA BIT(24)
	122	+#define STM32H7_SPI_CFG2_CPOL BIT(25)
	123	+#define STM32H7_SPI_CFG2_SSM BIT(26)
	124	+#define STM32H7_SPI_CFG2_AFCNTR BIT(31)
	125	+
	126	+/* STM32H7_SPI_IER bit fields */
	127	+#define STM32H7_SPI_IER_RXPIE BIT(0)
	128	+#define STM32H7_SPI_IER_TXPIE BIT(1)
	129	+#define STM32H7_SPI_IER_DXPIE BIT(2)
	130	+#define STM32H7_SPI_IER_EOTIE BIT(3)
	131	+#define STM32H7_SPI_IER_TXTFIE BIT(4)
	132	+#define STM32H7_SPI_IER_OVRIE BIT(6)
	133	+#define STM32H7_SPI_IER_MODFIE BIT(9)
	134	+#define STM32H7_SPI_IER_ALL GENMASK(10, 0)
	135	+
	136	+/* STM32H7_SPI_SR bit fields */
	137	+#define STM32H7_SPI_SR_RXP BIT(0)
	138	+#define STM32H7_SPI_SR_TXP BIT(1)
	139	+#define STM32H7_SPI_SR_EOT BIT(3)
	140	+#define STM32H7_SPI_SR_OVR BIT(6)
	141	+#define STM32H7_SPI_SR_MODF BIT(9)
	142	+#define STM32H7_SPI_SR_SUSP BIT(11)
	143	+#define STM32H7_SPI_SR_RXPLVL_SHIFT 13
	144	+#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
	145	+#define STM32H7_SPI_SR_RXWNE BIT(15)
	146	+
	147	+/* STM32H7_SPI_IFCR bit fields */
	148	+#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
	149	+
	150	+/* STM32H7_SPI_I2SCFGR bit fields */
	151	+#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
	152	+
	153	+/* STM32H7 SPI Master Baud Rate min/max divisor */
	154	+#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
	155	+#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
	156	+
	157	+/* STM32H7 SPI Communication mode */
	158	+#define STM32H7_SPI_FULL_DUPLEX 0
	159	+#define STM32H7_SPI_SIMPLEX_TX 1
	160	+#define STM32H7_SPI_SIMPLEX_RX 2
	161	+#define STM32H7_SPI_HALF_DUPLEX 3
	162	+
	163	+/* SPI Communication type */
118	164	#define SPI_FULL_DUPLEX 0
119	165	#define SPI_SIMPLEX_TX 1
120	166	#define SPI_SIMPLEX_RX 2
121		-#define SPI_HALF_DUPLEX 3
	167	+#define SPI_3WIRE_TX 3
	168	+#define SPI_3WIRE_RX 4
122	169
123	170	#define SPI_1HZ_NS 1000000000
	171	+
	172	+/*
	173	+ * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
	174	+ * without fifo buffers.
	175	+ */
	176	+#define SPI_DMA_MIN_BYTES 16
	177	+
	178	+/**
	179	+ * struct stm32_spi_reg - stm32 SPI register & bitfield desc
	180	+ * @reg: register offset
	181	+ * @mask: bitfield mask
	182	+ * @shift: left shift
	183	+ */
	184	+struct stm32_spi_reg {
	185	+ int reg;
	186	+ int mask;
	187	+ int shift;
	188	+};
	189	+
	190	+/**
	191	+ * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
	192	+ * @en: enable register and SPI enable bit
	193	+ * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
	194	+ * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
	195	+ * @cpol: clock polarity register and polarity bit
	196	+ * @cpha: clock phase register and phase bit
	197	+ * @lsb_first: LSB transmitted first register and bit
	198	+ * @br: baud rate register and bitfields
	199	+ * @rx: SPI RX data register
	200	+ * @tx: SPI TX data register
	201	+ */
	202	+struct stm32_spi_regspec {
	203	+ const struct stm32_spi_reg en;
	204	+ const struct stm32_spi_reg dma_rx_en;
	205	+ const struct stm32_spi_reg dma_tx_en;
	206	+ const struct stm32_spi_reg cpol;
	207	+ const struct stm32_spi_reg cpha;
	208	+ const struct stm32_spi_reg lsb_first;
	209	+ const struct stm32_spi_reg br;
	210	+ const struct stm32_spi_reg rx;
	211	+ const struct stm32_spi_reg tx;
	212	+};
	213	+
	214	+struct stm32_spi;
	215	+
	216	+/**
	217	+ * struct stm32_spi_cfg - stm32 compatible configuration data
	218	+ * @regs: registers descriptions
	219	+ * @get_fifo_size: routine to get fifo size
	220	+ * @get_bpw_mask: routine to get bits per word mask
	221	+ * @disable: routine to disable controller
	222	+ * @config: routine to configure controller as SPI Master
	223	+ * @set_bpw: routine to configure registers to for bits per word
	224	+ * @set_mode: routine to configure registers to desired mode
	225	+ * @set_data_idleness: optional routine to configure registers to desired idle
	226	+ * time between frames (if driver has this functionality)
	227	+ * @set_number_of_data: optional routine to configure registers to desired
	228	+ * number of data (if driver has this functionality)
	229	+ * @can_dma: routine to determine if the transfer is eligible for DMA use
	230	+ * @transfer_one_dma_start: routine to start transfer a single spi_transfer
	231	+ * using DMA
	232	+ * @dma_rx_cb: routine to call after DMA RX channel operation is complete
	233	+ * @dma_tx_cb: routine to call after DMA TX channel operation is complete
	234	+ * @transfer_one_irq: routine to configure interrupts for driver
	235	+ * @irq_handler_event: Interrupt handler for SPI controller events
	236	+ * @irq_handler_thread: thread of interrupt handler for SPI controller
	237	+ * @baud_rate_div_min: minimum baud rate divisor
	238	+ * @baud_rate_div_max: maximum baud rate divisor
	239	+ * @has_fifo: boolean to know if fifo is used for driver
	240	+ * @has_startbit: boolean to know if start bit is used to start transfer
	241	+ */
	242	+struct stm32_spi_cfg {
	243	+ const struct stm32_spi_regspec *regs;
	244	+ int (get_fifo_size)(struct stm32_spi spi);
	245	+ int (get_bpw_mask)(struct stm32_spi spi);
	246	+ void (disable)(struct stm32_spi spi);
	247	+ int (config)(struct stm32_spi spi);
	248	+ void (set_bpw)(struct stm32_spi spi);
	249	+ int (set_mode)(struct stm32_spi spi, unsigned int comm_type);
	250	+ void (set_data_idleness)(struct stm32_spi spi, u32 length);
	251	+ int (set_number_of_data)(struct stm32_spi spi, u32 length);
	252	+ void (transfer_one_dma_start)(struct stm32_spi spi);
	253	+ void (dma_rx_cb)(void data);
	254	+ void (dma_tx_cb)(void data);
	255	+ int (transfer_one_irq)(struct stm32_spi spi);
	256	+ irqreturn_t (irq_handler_event)(int irq, void dev_id);
	257	+ irqreturn_t (irq_handler_thread)(int irq, void dev_id);
	258	+ unsigned int baud_rate_div_min;
	259	+ unsigned int baud_rate_div_max;
	260	+ bool has_fifo;
	261	+};
124	262
125	263	/**
126	264	* struct stm32_spi - private data of the SPI controller
127	265	* @dev: driver model representation of the controller
128	266	* @master: controller master interface
	267	+ * @cfg: compatible configuration data
129	268	* @base: virtual memory area
130	269	* @clk: hw kernel clock feeding the SPI clock generator
131	270	* @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
..	..	@@ -151,6 +290,7 @@
151	290	struct stm32_spi {
152	291	struct device *dev;
153	292	struct spi_master *master;
	293	+ const struct stm32_spi_cfg *cfg;
154	294	void __iomem *base;
155	295	struct clk *clk;
156	296	u32 clk_rate;
..	..	@@ -176,6 +316,40 @@
176	316	dma_addr_t phys_addr;
177	317	};
178	318
	319	+static const struct stm32_spi_regspec stm32f4_spi_regspec = {
	320	+ .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
	321	+
	322	+ .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
	323	+ .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
	324	+
	325	+ .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
	326	+ .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
	327	+ .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
	328	+ .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
	329	+
	330	+ .rx = { STM32F4_SPI_DR },
	331	+ .tx = { STM32F4_SPI_DR },
	332	+};
	333	+
	334	+static const struct stm32_spi_regspec stm32h7_spi_regspec = {
	335	+ /* SPI data transfer is enabled but spi_ker_ck is idle.
	336	+ * CFG1 and CFG2 registers are write protected when SPE is enabled.
	337	+ */
	338	+ .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
	339	+
	340	+ .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
	341	+ .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
	342	+
	343	+ .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
	344	+ .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
	345	+ .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
	346	+ .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
	347	+ STM32H7_SPI_CFG1_MBR_SHIFT },
	348	+
	349	+ .rx = { STM32H7_SPI_RXDR },
	350	+ .tx = { STM32H7_SPI_TXDR },
	351	+};
	352	+
179	353	static inline void stm32_spi_set_bits(struct stm32_spi *spi,
180	354	u32 offset, u32 bits)
181	355	{
..	..	@@ -191,22 +365,22 @@
191	365	}
192	366
193	367	/**
194		- * stm32_spi_get_fifo_size - Return fifo size
	368	+ * stm32h7_spi_get_fifo_size - Return fifo size
195	369	* @spi: pointer to the spi controller data structure
196	370	*/
197		-static int stm32_spi_get_fifo_size(struct stm32_spi *spi)
	371	+static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
198	372	{
199	373	unsigned long flags;
200	374	u32 count = 0;
201	375
202	376	spin_lock_irqsave(&spi->lock, flags);
203	377
204		- stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
	378	+ stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
205	379
206		- while (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)
207		- writeb_relaxed(++count, spi->base + STM32_SPI_TXDR);
	380	+ while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
	381	+ writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
208	382
209		- stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
	383	+ stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
210	384
211	385	spin_unlock_irqrestore(&spi->lock, flags);
212	386
..	..	@@ -216,10 +390,20 @@
216	390	}
217	391
218	392	/**
219		- * stm32_spi_get_bpw_mask - Return bits per word mask
	393	+ * stm32f4_spi_get_bpw_mask - Return bits per word mask
220	394	* @spi: pointer to the spi controller data structure
221	395	*/
222		-static int stm32_spi_get_bpw_mask(struct stm32_spi *spi)
	396	+static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
	397	+{
	398	+ dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
	399	+ return SPI_BPW_MASK(8) \| SPI_BPW_MASK(16);
	400	+}
	401	+
	402	+/**
	403	+ * stm32h7_spi_get_bpw_mask - Return bits per word mask
	404	+ * @spi: pointer to the spi controller data structure
	405	+ */
	406	+static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
223	407	{
224	408	unsigned long flags;
225	409	u32 cfg1, max_bpw;
..	..	@@ -230,10 +414,11 @@
230	414	* The most significant bit at DSIZE bit field is reserved when the
231	415	* maximum data size of periperal instances is limited to 16-bit
232	416	*/
233		- stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_DSIZE);
	417	+ stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
234	418
235		- cfg1 = readl_relaxed(spi->base + STM32_SPI_CFG1);
236		- max_bpw = (cfg1 & SPI_CFG1_DSIZE) >> SPI_CFG1_DSIZE_SHIFT;
	419	+ cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
	420	+ max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
	421	+ STM32H7_SPI_CFG1_DSIZE_SHIFT;
237	422	max_bpw += 1;
238	423
239	424	spin_unlock_irqrestore(&spi->lock, flags);
..	..	@@ -244,18 +429,21 @@
244	429	}
245	430
246	431	/**
247		- * stm32_spi_prepare_mbr - Determine SPI_CFG1.MBR value
	432	+ * stm32_spi_prepare_mbr - Determine baud rate divisor value
248	433	* @spi: pointer to the spi controller data structure
249	434	* @speed_hz: requested speed
	435	+ * @min_div: minimum baud rate divisor
	436	+ * @max_div: maximum baud rate divisor
250	437	*
251		- * Return SPI_CFG1.MBR value in case of success or -EINVAL
	438	+ * Return baud rate divisor value in case of success or -EINVAL
252	439	*/
253		-static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
	440	+static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
	441	+ u32 min_div, u32 max_div)
254	442	{
255	443	u32 div, mbrdiv;
256	444
257	445	/* Ensure spi->clk_rate is even */
258		- div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
	446	+ div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
259	447
260	448	/*
261	449	* SPI framework set xfer->speed_hz to master->max_speed_hz if
..	..	@@ -264,8 +452,7 @@
264	452	* no need to check it there.
265	453	* However, we need to ensure the following calculations.
266	454	*/
267		- if (div < SPI_MBR_DIV_MIN \|\|
268		- div > SPI_MBR_DIV_MAX)
	455	+ if ((div < min_div) \|\| (div > max_div))
269	456	return -EINVAL;
270	457
271	458	/* Determine the first power of 2 greater than or equal to div */
..	..	@@ -280,22 +467,29 @@
280	467	}
281	468
282	469	/**
283		- * stm32_spi_prepare_fthlv - Determine FIFO threshold level
	470	+ * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
284	471	* @spi: pointer to the spi controller data structure
	472	+ * @xfer_len: length of the message to be transferred
285	473	*/
286		-static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi)
	474	+static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
287	475	{
288		- u32 fthlv, half_fifo;
	476	+ u32 fthlv, half_fifo, packet;
289	477
290	478	/* data packet should not exceed 1/2 of fifo space */
291	479	half_fifo = (spi->fifo_size / 2);
292	480
293		- if (spi->cur_bpw <= 8)
294		- fthlv = half_fifo;
295		- else if (spi->cur_bpw <= 16)
296		- fthlv = half_fifo / 2;
	481	+ /* data_packet should not exceed transfer length */
	482	+ if (half_fifo > xfer_len)
	483	+ packet = xfer_len;
297	484	else
298		- fthlv = half_fifo / 4;
	485	+ packet = half_fifo;
	486	+
	487	+ if (spi->cur_bpw <= 8)
	488	+ fthlv = packet;
	489	+ else if (spi->cur_bpw <= 16)
	490	+ fthlv = packet / 2;
	491	+ else
	492	+ fthlv = packet / 4;
299	493
300	494	/* align packet size with data registers access */
301	495	if (spi->cur_bpw > 8)
..	..	@@ -303,36 +497,34 @@
303	497	else
304	498	fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
305	499
	500	+ if (!fthlv)
	501	+ fthlv = 1;
	502	+
306	503	return fthlv;
307	504	}
308	505
309	506	/**
310		- * stm32_spi_write_txfifo - Write bytes in Transmit Data Register
	507	+ * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
311	508	* @spi: pointer to the spi controller data structure
312	509	*
313	510	* Read from tx_buf depends on remaining bytes to avoid to read beyond
314	511	* tx_buf end.
315	512	*/
316		-static void stm32_spi_write_txfifo(struct stm32_spi *spi)
	513	+static void stm32f4_spi_write_tx(struct stm32_spi *spi)
317	514	{
318		- while ((spi->tx_len > 0) &&
319		- (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)) {
	515	+ if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
	516	+ STM32F4_SPI_SR_TXE)) {
320	517	u32 offs = spi->cur_xferlen - spi->tx_len;
321	518
322		- if (spi->tx_len >= sizeof(u32)) {
323		- const u32 tx_buf32 = (const u32 )(spi->tx_buf + offs);
324		-
325		- writel_relaxed(*tx_buf32, spi->base + STM32_SPI_TXDR);
326		- spi->tx_len -= sizeof(u32);
327		- } else if (spi->tx_len >= sizeof(u16)) {
	519	+ if (spi->cur_bpw == 16) {
328	520	const u16 tx_buf16 = (const u16 )(spi->tx_buf + offs);
329	521
330		- writew_relaxed(*tx_buf16, spi->base + STM32_SPI_TXDR);
	522	+ writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
331	523	spi->tx_len -= sizeof(u16);
332	524	} else {
333	525	const u8 tx_buf8 = (const u8 )(spi->tx_buf + offs);
334	526
335		- writeb_relaxed(*tx_buf8, spi->base + STM32_SPI_TXDR);
	527	+ writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
336	528	spi->tx_len -= sizeof(u8);
337	529	}
338	530	}
..	..	@@ -341,43 +533,110 @@
341	533	}
342	534
343	535	/**
344		- * stm32_spi_read_rxfifo - Read bytes in Receive Data Register
	536	+ * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
	537	+ * @spi: pointer to the spi controller data structure
	538	+ *
	539	+ * Read from tx_buf depends on remaining bytes to avoid to read beyond
	540	+ * tx_buf end.
	541	+ */
	542	+static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
	543	+{
	544	+ while ((spi->tx_len > 0) &&
	545	+ (readl_relaxed(spi->base + STM32H7_SPI_SR) &
	546	+ STM32H7_SPI_SR_TXP)) {
	547	+ u32 offs = spi->cur_xferlen - spi->tx_len;
	548	+
	549	+ if (spi->tx_len >= sizeof(u32)) {
	550	+ const u32 tx_buf32 = (const u32 )(spi->tx_buf + offs);
	551	+
	552	+ writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
	553	+ spi->tx_len -= sizeof(u32);
	554	+ } else if (spi->tx_len >= sizeof(u16)) {
	555	+ const u16 tx_buf16 = (const u16 )(spi->tx_buf + offs);
	556	+
	557	+ writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
	558	+ spi->tx_len -= sizeof(u16);
	559	+ } else {
	560	+ const u8 tx_buf8 = (const u8 )(spi->tx_buf + offs);
	561	+
	562	+ writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
	563	+ spi->tx_len -= sizeof(u8);
	564	+ }
	565	+ }
	566	+
	567	+ dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
	568	+}
	569	+
	570	+/**
	571	+ * stm32f4_spi_read_rx - Read bytes from Receive Data Register
345	572	* @spi: pointer to the spi controller data structure
346	573	*
347	574	* Write in rx_buf depends on remaining bytes to avoid to write beyond
348	575	* rx_buf end.
349	576	*/
350		-static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
	577	+static void stm32f4_spi_read_rx(struct stm32_spi *spi)
351	578	{
352		- u32 sr = readl_relaxed(spi->base + STM32_SPI_SR);
353		- u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
	579	+ if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
	580	+ STM32F4_SPI_SR_RXNE)) {
	581	+ u32 offs = spi->cur_xferlen - spi->rx_len;
	582	+
	583	+ if (spi->cur_bpw == 16) {
	584	+ u16 rx_buf16 = (u16 )(spi->rx_buf + offs);
	585	+
	586	+ *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
	587	+ spi->rx_len -= sizeof(u16);
	588	+ } else {
	589	+ u8 rx_buf8 = (u8 )(spi->rx_buf + offs);
	590	+
	591	+ *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
	592	+ spi->rx_len -= sizeof(u8);
	593	+ }
	594	+ }
	595	+
	596	+ dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
	597	+}
	598	+
	599	+/**
	600	+ * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
	601	+ * @spi: pointer to the spi controller data structure
	602	+ * @flush: boolean indicating that FIFO should be flushed
	603	+ *
	604	+ * Write in rx_buf depends on remaining bytes to avoid to write beyond
	605	+ * rx_buf end.
	606	+ */
	607	+static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
	608	+{
	609	+ u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
	610	+ u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
	611	+ STM32H7_SPI_SR_RXPLVL_SHIFT;
354	612
355	613	while ((spi->rx_len > 0) &&
356		- ((sr & SPI_SR_RXP) \|\|
357		- (flush && ((sr & SPI_SR_RXWNE) \|\| (rxplvl > 0))))) {
	614	+ ((sr & STM32H7_SPI_SR_RXP) \|\|
	615	+ (flush && ((sr & STM32H7_SPI_SR_RXWNE) \|\| (rxplvl > 0))))) {
358	616	u32 offs = spi->cur_xferlen - spi->rx_len;
359	617
360	618	if ((spi->rx_len >= sizeof(u32)) \|\|
361		- (flush && (sr & SPI_SR_RXWNE))) {
	619	+ (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
362	620	u32 rx_buf32 = (u32 )(spi->rx_buf + offs);
363	621
364		- *rx_buf32 = readl_relaxed(spi->base + STM32_SPI_RXDR);
	622	+ *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
365	623	spi->rx_len -= sizeof(u32);
366	624	} else if ((spi->rx_len >= sizeof(u16)) \|\|
367	625	(flush && (rxplvl >= 2 \|\| spi->cur_bpw > 8))) {
368	626	u16 rx_buf16 = (u16 )(spi->rx_buf + offs);
369	627
370		- *rx_buf16 = readw_relaxed(spi->base + STM32_SPI_RXDR);
	628	+ *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
371	629	spi->rx_len -= sizeof(u16);
372	630	} else {
373	631	u8 rx_buf8 = (u8 )(spi->rx_buf + offs);
374	632
375		- *rx_buf8 = readb_relaxed(spi->base + STM32_SPI_RXDR);
	633	+ *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
376	634	spi->rx_len -= sizeof(u8);
377	635	}
378	636
379		- sr = readl_relaxed(spi->base + STM32_SPI_SR);
380		- rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
	637	+ sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
	638	+ rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
	639	+ STM32H7_SPI_SR_RXPLVL_SHIFT;
381	640	}
382	641
383	642	dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
..	..	@@ -387,26 +646,76 @@
387	646	/**
388	647	* stm32_spi_enable - Enable SPI controller
389	648	* @spi: pointer to the spi controller data structure
390		- *
391		- * SPI data transfer is enabled but spi_ker_ck is idle.
392		- * SPI_CFG1 and SPI_CFG2 are now write protected.
393	649	*/
394	650	static void stm32_spi_enable(struct stm32_spi *spi)
395	651	{
396	652	dev_dbg(spi->dev, "enable controller\n");
397	653
398		- stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
	654	+ stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
	655	+ spi->cfg->regs->en.mask);
399	656	}
400	657
401	658	/**
402		- * stm32_spi_disable - Disable SPI controller
	659	+ * stm32f4_spi_disable - Disable SPI controller
	660	+ * @spi: pointer to the spi controller data structure
	661	+ */
	662	+static void stm32f4_spi_disable(struct stm32_spi *spi)
	663	+{
	664	+ unsigned long flags;
	665	+ u32 sr;
	666	+
	667	+ dev_dbg(spi->dev, "disable controller\n");
	668	+
	669	+ spin_lock_irqsave(&spi->lock, flags);
	670	+
	671	+ if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
	672	+ STM32F4_SPI_CR1_SPE)) {
	673	+ spin_unlock_irqrestore(&spi->lock, flags);
	674	+ return;
	675	+ }
	676	+
	677	+ /* Disable interrupts */
	678	+ stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE \|
	679	+ STM32F4_SPI_CR2_RXNEIE \|
	680	+ STM32F4_SPI_CR2_ERRIE);
	681	+
	682	+ /* Wait until BSY = 0 */
	683	+ if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
	684	+ sr, !(sr & STM32F4_SPI_SR_BSY),
	685	+ 10, 100000) < 0) {
	686	+ dev_warn(spi->dev, "disabling condition timeout\n");
	687	+ }
	688	+
	689	+ if (spi->cur_usedma && spi->dma_tx)
	690	+ dmaengine_terminate_all(spi->dma_tx);
	691	+ if (spi->cur_usedma && spi->dma_rx)
	692	+ dmaengine_terminate_all(spi->dma_rx);
	693	+
	694	+ stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
	695	+
	696	+ stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN \|
	697	+ STM32F4_SPI_CR2_RXDMAEN);
	698	+
	699	+ /* Sequence to clear OVR flag */
	700	+ readl_relaxed(spi->base + STM32F4_SPI_DR);
	701	+ readl_relaxed(spi->base + STM32F4_SPI_SR);
	702	+
	703	+ spin_unlock_irqrestore(&spi->lock, flags);
	704	+}
	705	+
	706	+/**
	707	+ * stm32h7_spi_disable - Disable SPI controller
403	708	* @spi: pointer to the spi controller data structure
404	709	*
405	710	* RX-Fifo is flushed when SPI controller is disabled. To prevent any data
406		- * loss, use stm32_spi_read_rxfifo(flush) to read the remaining bytes in
	711	+ * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
407	712	* RX-Fifo.
	713	+ * Normally, if TSIZE has been configured, we should relax the hardware at the
	714	+ * reception of the EOT interrupt. But in case of error, EOT will not be
	715	+ * raised. So the subsystem unprepare_message call allows us to properly
	716	+ * complete the transfer from an hardware point of view.
408	717	*/
409		-static void stm32_spi_disable(struct stm32_spi *spi)
	718	+static void stm32h7_spi_disable(struct stm32_spi *spi)
410	719	{
411	720	unsigned long flags;
412	721	u32 cr1, sr;
..	..	@@ -415,23 +724,23 @@
415	724
416	725	spin_lock_irqsave(&spi->lock, flags);
417	726
418		- cr1 = readl_relaxed(spi->base + STM32_SPI_CR1);
	727	+ cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
419	728
420		- if (!(cr1 & SPI_CR1_SPE)) {
	729	+ if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
421	730	spin_unlock_irqrestore(&spi->lock, flags);
422	731	return;
423	732	}
424	733
425	734	/* Wait on EOT or suspend the flow */
426		- if (readl_relaxed_poll_timeout_atomic(spi->base + STM32_SPI_SR,
427		- sr, !(sr & SPI_SR_EOT),
	735	+ if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
	736	+ sr, !(sr & STM32H7_SPI_SR_EOT),
428	737	10, 100000) < 0) {
429		- if (cr1 & SPI_CR1_CSTART) {
430		- writel_relaxed(cr1 \| SPI_CR1_CSUSP,
431		- spi->base + STM32_SPI_CR1);
	738	+ if (cr1 & STM32H7_SPI_CR1_CSTART) {
	739	+ writel_relaxed(cr1 \| STM32H7_SPI_CR1_CSUSP,
	740	+ spi->base + STM32H7_SPI_CR1);
432	741	if (readl_relaxed_poll_timeout_atomic(
433		- spi->base + STM32_SPI_SR,
434		- sr, !(sr & SPI_SR_SUSP),
	742	+ spi->base + STM32H7_SPI_SR,
	743	+ sr, !(sr & STM32H7_SPI_SR_SUSP),
435	744	10, 100000) < 0)
436	745	dev_warn(spi->dev,
437	746	"Suspend request timeout\n");
..	..	@@ -439,48 +748,162 @@
439	748	}
440	749
441	750	if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
442		- stm32_spi_read_rxfifo(spi, true);
	751	+ stm32h7_spi_read_rxfifo(spi, true);
443	752
444		- if (spi->cur_usedma && spi->tx_buf)
	753	+ if (spi->cur_usedma && spi->dma_tx)
445	754	dmaengine_terminate_all(spi->dma_tx);
446		- if (spi->cur_usedma && spi->rx_buf)
	755	+ if (spi->cur_usedma && spi->dma_rx)
447	756	dmaengine_terminate_all(spi->dma_rx);
448	757
449		- stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
	758	+ stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
450	759
451		- stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN \|
452		- SPI_CFG1_RXDMAEN);
	760	+ stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN \|
	761	+ STM32H7_SPI_CFG1_RXDMAEN);
453	762
454	763	/* Disable interrupts and clear status flags */
455		- writel_relaxed(0, spi->base + STM32_SPI_IER);
456		- writel_relaxed(SPI_IFCR_ALL, spi->base + STM32_SPI_IFCR);
	764	+ writel_relaxed(0, spi->base + STM32H7_SPI_IER);
	765	+ writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
457	766
458	767	spin_unlock_irqrestore(&spi->lock, flags);
459	768	}
460	769
461	770	/**
462	771	* stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
	772	+ * @master: controller master interface
	773	+ * @spi_dev: pointer to the spi device
	774	+ * @transfer: pointer to spi transfer
463	775	*
464		- * If the current transfer size is greater than fifo size, use DMA.
	776	+ * If driver has fifo and the current transfer size is greater than fifo size,
	777	+ * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
465	778	*/
466	779	static bool stm32_spi_can_dma(struct spi_master *master,
467	780	struct spi_device *spi_dev,
468	781	struct spi_transfer *transfer)
469	782	{
	783	+ unsigned int dma_size;
470	784	struct stm32_spi *spi = spi_master_get_devdata(master);
471	785
472		- dev_dbg(spi->dev, "%s: %s\n", __func__,
473		- (transfer->len > spi->fifo_size) ? "true" : "false");
	786	+ if (spi->cfg->has_fifo)
	787	+ dma_size = spi->fifo_size;
	788	+ else
	789	+ dma_size = SPI_DMA_MIN_BYTES;
474	790
475		- return (transfer->len > spi->fifo_size);
	791	+ dev_dbg(spi->dev, "%s: %s\n", __func__,
	792	+ (transfer->len > dma_size) ? "true" : "false");
	793	+
	794	+ return (transfer->len > dma_size);
476	795	}
477	796
478	797	/**
479		- * stm32_spi_irq - Interrupt handler for SPI controller events
	798	+ * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
480	799	* @irq: interrupt line
481	800	* @dev_id: SPI controller master interface
482	801	*/
483		-static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
	802	+static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
	803	+{
	804	+ struct spi_master *master = dev_id;
	805	+ struct stm32_spi *spi = spi_master_get_devdata(master);
	806	+ u32 sr, mask = 0;
	807	+ bool end = false;
	808	+
	809	+ spin_lock(&spi->lock);
	810	+
	811	+ sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
	812	+ /*
	813	+ * BSY flag is not handled in interrupt but it is normal behavior when
	814	+ * this flag is set.
	815	+ */
	816	+ sr &= ~STM32F4_SPI_SR_BSY;
	817	+
	818	+ if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX \|\|
	819	+ spi->cur_comm == SPI_3WIRE_TX)) {
	820	+ /* OVR flag shouldn't be handled for TX only mode */
	821	+ sr &= ~STM32F4_SPI_SR_OVR \| STM32F4_SPI_SR_RXNE;
	822	+ mask \|= STM32F4_SPI_SR_TXE;
	823	+ }
	824	+
	825	+ if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX \|\|
	826	+ spi->cur_comm == SPI_SIMPLEX_RX \|\|
	827	+ spi->cur_comm == SPI_3WIRE_RX)) {
	828	+ /* TXE flag is set and is handled when RXNE flag occurs */
	829	+ sr &= ~STM32F4_SPI_SR_TXE;
	830	+ mask \|= STM32F4_SPI_SR_RXNE \| STM32F4_SPI_SR_OVR;
	831	+ }
	832	+
	833	+ if (!(sr & mask)) {
	834	+ dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
	835	+ spin_unlock(&spi->lock);
	836	+ return IRQ_NONE;
	837	+ }
	838	+
	839	+ if (sr & STM32F4_SPI_SR_OVR) {
	840	+ dev_warn(spi->dev, "Overrun: received value discarded\n");
	841	+
	842	+ /* Sequence to clear OVR flag */
	843	+ readl_relaxed(spi->base + STM32F4_SPI_DR);
	844	+ readl_relaxed(spi->base + STM32F4_SPI_SR);
	845	+
	846	+ /*
	847	+ * If overrun is detected, it means that something went wrong,
	848	+ * so stop the current transfer. Transfer can wait for next
	849	+ * RXNE but DR is already read and end never happens.
	850	+ */
	851	+ end = true;
	852	+ goto end_irq;
	853	+ }
	854	+
	855	+ if (sr & STM32F4_SPI_SR_TXE) {
	856	+ if (spi->tx_buf)
	857	+ stm32f4_spi_write_tx(spi);
	858	+ if (spi->tx_len == 0)
	859	+ end = true;
	860	+ }
	861	+
	862	+ if (sr & STM32F4_SPI_SR_RXNE) {
	863	+ stm32f4_spi_read_rx(spi);
	864	+ if (spi->rx_len == 0)
	865	+ end = true;
	866	+ else if (spi->tx_buf)/* Load data for discontinuous mode */
	867	+ stm32f4_spi_write_tx(spi);
	868	+ }
	869	+
	870	+end_irq:
	871	+ if (end) {
	872	+ /* Immediately disable interrupts to do not generate new one */
	873	+ stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
	874	+ STM32F4_SPI_CR2_TXEIE \|
	875	+ STM32F4_SPI_CR2_RXNEIE \|
	876	+ STM32F4_SPI_CR2_ERRIE);
	877	+ spin_unlock(&spi->lock);
	878	+ return IRQ_WAKE_THREAD;
	879	+ }
	880	+
	881	+ spin_unlock(&spi->lock);
	882	+ return IRQ_HANDLED;
	883	+}
	884	+
	885	+/**
	886	+ * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
	887	+ * @irq: interrupt line
	888	+ * @dev_id: SPI controller master interface
	889	+ */
	890	+static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
	891	+{
	892	+ struct spi_master *master = dev_id;
	893	+ struct stm32_spi *spi = spi_master_get_devdata(master);
	894	+
	895	+ spi_finalize_current_transfer(master);
	896	+ stm32f4_spi_disable(spi);
	897	+
	898	+ return IRQ_HANDLED;
	899	+}
	900	+
	901	+/**
	902	+ * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
	903	+ * @irq: interrupt line
	904	+ * @dev_id: SPI controller master interface
	905	+ */
	906	+static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
484	907	{
485	908	struct spi_master *master = dev_id;
486	909	struct stm32_spi *spi = spi_master_get_devdata(master);
..	..	@@ -490,31 +913,39 @@
490	913
491	914	spin_lock_irqsave(&spi->lock, flags);
492	915
493		- sr = readl_relaxed(spi->base + STM32_SPI_SR);
494		- ier = readl_relaxed(spi->base + STM32_SPI_IER);
	916	+ sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
	917	+ ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
495	918
496	919	mask = ier;
497		- /* EOTIE is triggered on EOT, SUSP and TXC events. */
498		- mask \|= SPI_SR_SUSP;
499	920	/*
500		- * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
501		- * Full-Duplex, need to poll RXP event to know if there are remaining
502		- * data, before disabling SPI.
	921	+ * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
	922	+ * SUSP to acknowledge it later. TXC is automatically cleared
503	923	*/
504		- if (spi->rx_buf && !spi->cur_usedma)
505		- mask \|= SPI_SR_RXP;
	924	+
	925	+ mask \|= STM32H7_SPI_SR_SUSP;
	926	+ /*
	927	+ * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
	928	+ * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
	929	+ */
	930	+ if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
	931	+ mask \|= STM32H7_SPI_SR_TXP \| STM32H7_SPI_SR_RXP;
506	932
507	933	if (!(sr & mask)) {
508		- dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
509		- sr, ier);
	934	+ dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
	935	+ sr, ier);
510	936	spin_unlock_irqrestore(&spi->lock, flags);
511	937	return IRQ_NONE;
512	938	}
513	939
514		- if (sr & SPI_SR_SUSP) {
515		- dev_warn(spi->dev, "Communication suspended\n");
	940	+ if (sr & STM32H7_SPI_SR_SUSP) {
	941	+ static DEFINE_RATELIMIT_STATE(rs,
	942	+ DEFAULT_RATELIMIT_INTERVAL * 10,
	943	+ 1);
	944	+ ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
	945	+ if (__ratelimit(&rs))
	946	+ dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
516	947	if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
517		- stm32_spi_read_rxfifo(spi, false);
	948	+ stm32h7_spi_read_rxfifo(spi, false);
518	949	/*
519	950	* If communication is suspended while using DMA, it means
520	951	* that something went wrong, so stop the current transfer
..	..	@@ -523,74 +954,46 @@
523	954	end = true;
524	955	}
525	956
526		- if (sr & SPI_SR_MODF) {
	957	+ if (sr & STM32H7_SPI_SR_MODF) {
527	958	dev_warn(spi->dev, "Mode fault: transfer aborted\n");
528	959	end = true;
529	960	}
530	961
531		- if (sr & SPI_SR_OVR) {
532		- dev_warn(spi->dev, "Overrun: received value discarded\n");
533		- if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
534		- stm32_spi_read_rxfifo(spi, false);
535		- /*
536		- * If overrun is detected while using DMA, it means that
537		- * something went wrong, so stop the current transfer
538		- */
539		- if (spi->cur_usedma)
540		- end = true;
541		- }
542		-
543		- if (sr & SPI_SR_EOT) {
544		- if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
545		- stm32_spi_read_rxfifo(spi, true);
	962	+ if (sr & STM32H7_SPI_SR_OVR) {
	963	+ dev_err(spi->dev, "Overrun: RX data lost\n");
546	964	end = true;
547	965	}
548	966
549		- if (sr & SPI_SR_TXP)
550		- if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
551		- stm32_spi_write_txfifo(spi);
552		-
553		- if (sr & SPI_SR_RXP)
	967	+ if (sr & STM32H7_SPI_SR_EOT) {
554	968	if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
555		- stm32_spi_read_rxfifo(spi, false);
	969	+ stm32h7_spi_read_rxfifo(spi, true);
	970	+ end = true;
	971	+ }
556	972
557		- writel_relaxed(mask, spi->base + STM32_SPI_IFCR);
	973	+ if (sr & STM32H7_SPI_SR_TXP)
	974	+ if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
	975	+ stm32h7_spi_write_txfifo(spi);
	976	+
	977	+ if (sr & STM32H7_SPI_SR_RXP)
	978	+ if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
	979	+ stm32h7_spi_read_rxfifo(spi, false);
	980	+
	981	+ writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
558	982
559	983	spin_unlock_irqrestore(&spi->lock, flags);
560	984
561	985	if (end) {
	986	+ stm32h7_spi_disable(spi);
562	987	spi_finalize_current_transfer(master);
563		- stm32_spi_disable(spi);
564	988	}
565	989
566	990	return IRQ_HANDLED;
567	991	}
568	992
569	993	/**
570		- * stm32_spi_setup - setup device chip select
571		- */
572		-static int stm32_spi_setup(struct spi_device *spi_dev)
573		-{
574		- int ret = 0;
575		-
576		- if (!gpio_is_valid(spi_dev->cs_gpio)) {
577		- dev_err(&spi_dev->dev, "%d is not a valid gpio\n",
578		- spi_dev->cs_gpio);
579		- return -EINVAL;
580		- }
581		-
582		- dev_dbg(&spi_dev->dev, "%s: set gpio%d output %s\n", __func__,
583		- spi_dev->cs_gpio,
584		- (spi_dev->mode & SPI_CS_HIGH) ? "low" : "high");
585		-
586		- ret = gpio_direction_output(spi_dev->cs_gpio,
587		- !(spi_dev->mode & SPI_CS_HIGH));
588		-
589		- return ret;
590		-}
591		-
592		-/**
593	994	* stm32_spi_prepare_msg - set up the controller to transfer a single message
	995	+ * @master: controller master interface
	996	+ * @msg: pointer to spi message
594	997	*/
595	998	static int stm32_spi_prepare_msg(struct spi_master *master,
596	999	struct spi_message *msg)
..	..	@@ -599,7 +1002,7 @@
599	1002	struct spi_device *spi_dev = msg->spi;
600	1003	struct device_node *np = spi_dev->dev.of_node;
601	1004	unsigned long flags;
602		- u32 cfg2_clrb = 0, cfg2_setb = 0;
	1005	+ u32 clrb = 0, setb = 0;
603	1006
604	1007	/* SPI slave device may need time between data frames */
605	1008	spi->cur_midi = 0;
..	..	@@ -607,19 +1010,19 @@
607	1010	dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
608	1011
609	1012	if (spi_dev->mode & SPI_CPOL)
610		- cfg2_setb \|= SPI_CFG2_CPOL;
	1013	+ setb \|= spi->cfg->regs->cpol.mask;
611	1014	else
612		- cfg2_clrb \|= SPI_CFG2_CPOL;
	1015	+ clrb \|= spi->cfg->regs->cpol.mask;
613	1016
614	1017	if (spi_dev->mode & SPI_CPHA)
615		- cfg2_setb \|= SPI_CFG2_CPHA;
	1018	+ setb \|= spi->cfg->regs->cpha.mask;
616	1019	else
617		- cfg2_clrb \|= SPI_CFG2_CPHA;
	1020	+ clrb \|= spi->cfg->regs->cpha.mask;
618	1021
619	1022	if (spi_dev->mode & SPI_LSB_FIRST)
620		- cfg2_setb \|= SPI_CFG2_LSBFRST;
	1023	+ setb \|= spi->cfg->regs->lsb_first.mask;
621	1024	else
622		- cfg2_clrb \|= SPI_CFG2_LSBFRST;
	1025	+ clrb \|= spi->cfg->regs->lsb_first.mask;
623	1026
624	1027	dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
625	1028	spi_dev->mode & SPI_CPOL,
..	..	@@ -629,11 +1032,12 @@
629	1032
630	1033	spin_lock_irqsave(&spi->lock, flags);
631	1034
632		- if (cfg2_clrb \|\| cfg2_setb)
	1035	+ /* CPOL, CPHA and LSB FIRST bits have common register */
	1036	+ if (clrb \|\| setb)
633	1037	writel_relaxed(
634		- (readl_relaxed(spi->base + STM32_SPI_CFG2) &
635		- ~cfg2_clrb) \| cfg2_setb,
636		- spi->base + STM32_SPI_CFG2);
	1038	+ (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
	1039	+ ~clrb) \| setb,
	1040	+ spi->base + spi->cfg->regs->cpol.reg);
637	1041
638	1042	spin_unlock_irqrestore(&spi->lock, flags);
639	1043
..	..	@@ -641,12 +1045,43 @@
641	1045	}
642	1046
643	1047	/**
644		- * stm32_spi_dma_cb - dma callback
	1048	+ * stm32f4_spi_dma_tx_cb - dma callback
	1049	+ * @data: pointer to the spi controller data structure
	1050	+ *
	1051	+ * DMA callback is called when the transfer is complete for DMA TX channel.
	1052	+ */
	1053	+static void stm32f4_spi_dma_tx_cb(void *data)
	1054	+{
	1055	+ struct stm32_spi *spi = data;
	1056	+
	1057	+ if (spi->cur_comm == SPI_SIMPLEX_TX \|\| spi->cur_comm == SPI_3WIRE_TX) {
	1058	+ spi_finalize_current_transfer(spi->master);
	1059	+ stm32f4_spi_disable(spi);
	1060	+ }
	1061	+}
	1062	+
	1063	+/**
	1064	+ * stm32f4_spi_dma_rx_cb - dma callback
	1065	+ * @data: pointer to the spi controller data structure
	1066	+ *
	1067	+ * DMA callback is called when the transfer is complete for DMA RX channel.
	1068	+ */
	1069	+static void stm32f4_spi_dma_rx_cb(void *data)
	1070	+{
	1071	+ struct stm32_spi *spi = data;
	1072	+
	1073	+ spi_finalize_current_transfer(spi->master);
	1074	+ stm32f4_spi_disable(spi);
	1075	+}
	1076	+
	1077	+/**
	1078	+ * stm32h7_spi_dma_cb - dma callback
	1079	+ * @data: pointer to the spi controller data structure
645	1080	*
646	1081	* DMA callback is called when the transfer is complete or when an error
647	1082	* occurs. If the transfer is complete, EOT flag is raised.
648	1083	*/
649		-static void stm32_spi_dma_cb(void *data)
	1084	+static void stm32h7_spi_dma_cb(void *data)
650	1085	{
651	1086	struct stm32_spi *spi = data;
652	1087	unsigned long flags;
..	..	@@ -654,11 +1089,11 @@
654	1089
655	1090	spin_lock_irqsave(&spi->lock, flags);
656	1091
657		- sr = readl_relaxed(spi->base + STM32_SPI_SR);
	1092	+ sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
658	1093
659	1094	spin_unlock_irqrestore(&spi->lock, flags);
660	1095
661		- if (!(sr & SPI_SR_EOT))
	1096	+ if (!(sr & STM32H7_SPI_SR_EOT))
662	1097	dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
663	1098
664	1099	/* Now wait for EOT, or SUSP or OVR in case of error */
..	..	@@ -667,6 +1102,9 @@
667	1102	/**
668	1103	* stm32_spi_dma_config - configure dma slave channel depending on current
669	1104	* transfer bits_per_word.
	1105	+ * @spi: pointer to the spi controller data structure
	1106	+ * @dma_conf: pointer to the dma_slave_config structure
	1107	+ * @dir: direction of the dma transfer
670	1108	*/
671	1109	static void stm32_spi_dma_config(struct stm32_spi *spi,
672	1110	struct dma_slave_config *dma_conf,
..	..	@@ -682,23 +1120,27 @@
682	1120	else
683	1121	buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
684	1122
685		- /* Valid for DMA Half or Full Fifo threshold */
686		- if (spi->cur_fthlv == 2)
	1123	+ if (spi->cfg->has_fifo) {
	1124	+ /* Valid for DMA Half or Full Fifo threshold */
	1125	+ if (spi->cur_fthlv == 2)
	1126	+ maxburst = 1;
	1127	+ else
	1128	+ maxburst = spi->cur_fthlv;
	1129	+ } else {
687	1130	maxburst = 1;
688		- else
689		- maxburst = spi->cur_fthlv;
	1131	+ }
690	1132
691	1133	memset(dma_conf, 0, sizeof(struct dma_slave_config));
692	1134	dma_conf->direction = dir;
693	1135	if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
694		- dma_conf->src_addr = spi->phys_addr + STM32_SPI_RXDR;
	1136	+ dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
695	1137	dma_conf->src_addr_width = buswidth;
696	1138	dma_conf->src_maxburst = maxburst;
697	1139
698	1140	dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
699	1141	buswidth, maxburst);
700	1142	} else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
701		- dma_conf->dst_addr = spi->phys_addr + STM32_SPI_TXDR;
	1143	+ dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
702	1144	dma_conf->dst_addr_width = buswidth;
703	1145	dma_conf->dst_maxburst = maxburst;
704	1146
..	..	@@ -708,39 +1150,42 @@
708	1150	}
709	1151
710	1152	/**
711		- * stm32_spi_transfer_one_irq - transfer a single spi_transfer using
712		- * interrupts
	1153	+ * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
	1154	+ * interrupts
	1155	+ * @spi: pointer to the spi controller data structure
713	1156	*
714	1157	* It must returns 0 if the transfer is finished or 1 if the transfer is still
715	1158	* in progress.
716	1159	*/
717		-static int stm32_spi_transfer_one_irq(struct stm32_spi *spi)
	1160	+static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
718	1161	{
719	1162	unsigned long flags;
720		- u32 ier = 0;
	1163	+ u32 cr2 = 0;
721	1164
722	1165	/* Enable the interrupts relative to the current communication mode */
723		- if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
724		- ier \|= SPI_IER_DXPIE;
725		- else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
726		- ier \|= SPI_IER_TXPIE;
727		- else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
728		- ier \|= SPI_IER_RXPIE;
729		-
730		- /* Enable the interrupts relative to the end of transfer */
731		- ier \|= SPI_IER_EOTIE \| SPI_IER_TXTFIE \| SPI_IER_OVRIE \| SPI_IER_MODFIE;
	1166	+ if (spi->cur_comm == SPI_SIMPLEX_TX \|\| spi->cur_comm == SPI_3WIRE_TX) {
	1167	+ cr2 \|= STM32F4_SPI_CR2_TXEIE;
	1168	+ } else if (spi->cur_comm == SPI_FULL_DUPLEX \|\|
	1169	+ spi->cur_comm == SPI_SIMPLEX_RX \|\|
	1170	+ spi->cur_comm == SPI_3WIRE_RX) {
	1171	+ /* In transmit-only mode, the OVR flag is set in the SR register
	1172	+ * since the received data are never read. Therefore set OVR
	1173	+ * interrupt only when rx buffer is available.
	1174	+ */
	1175	+ cr2 \|= STM32F4_SPI_CR2_RXNEIE \| STM32F4_SPI_CR2_ERRIE;
	1176	+ } else {
	1177	+ return -EINVAL;
	1178	+ }
732	1179
733	1180	spin_lock_irqsave(&spi->lock, flags);
734	1181
	1182	+ stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
	1183	+
735	1184	stm32_spi_enable(spi);
736	1185
737		- /* Be sure to have data in fifo before starting data transfer */
	1186	+ /* starting data transfer when buffer is loaded */
738	1187	if (spi->tx_buf)
739		- stm32_spi_write_txfifo(spi);
740		-
741		- stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
742		-
743		- writel_relaxed(ier, spi->base + STM32_SPI_IER);
	1188	+ stm32f4_spi_write_tx(spi);
744	1189
745	1190	spin_unlock_irqrestore(&spi->lock, flags);
746	1191
..	..	@@ -748,7 +1193,90 @@
748	1193	}
749	1194
750	1195	/**
	1196	+ * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
	1197	+ * interrupts
	1198	+ * @spi: pointer to the spi controller data structure
	1199	+ *
	1200	+ * It must returns 0 if the transfer is finished or 1 if the transfer is still
	1201	+ * in progress.
	1202	+ */
	1203	+static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
	1204	+{
	1205	+ unsigned long flags;
	1206	+ u32 ier = 0;
	1207	+
	1208	+ /* Enable the interrupts relative to the current communication mode */
	1209	+ if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
	1210	+ ier \|= STM32H7_SPI_IER_DXPIE;
	1211	+ else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
	1212	+ ier \|= STM32H7_SPI_IER_TXPIE;
	1213	+ else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
	1214	+ ier \|= STM32H7_SPI_IER_RXPIE;
	1215	+
	1216	+ /* Enable the interrupts relative to the end of transfer */
	1217	+ ier \|= STM32H7_SPI_IER_EOTIE \| STM32H7_SPI_IER_TXTFIE \|
	1218	+ STM32H7_SPI_IER_OVRIE \| STM32H7_SPI_IER_MODFIE;
	1219	+
	1220	+ spin_lock_irqsave(&spi->lock, flags);
	1221	+
	1222	+ stm32_spi_enable(spi);
	1223	+
	1224	+ /* Be sure to have data in fifo before starting data transfer */
	1225	+ if (spi->tx_buf)
	1226	+ stm32h7_spi_write_txfifo(spi);
	1227	+
	1228	+ stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
	1229	+
	1230	+ writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
	1231	+
	1232	+ spin_unlock_irqrestore(&spi->lock, flags);
	1233	+
	1234	+ return 1;
	1235	+}
	1236	+
	1237	+/**
	1238	+ * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
	1239	+ * transfer using DMA
	1240	+ * @spi: pointer to the spi controller data structure
	1241	+ */
	1242	+static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
	1243	+{
	1244	+ /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
	1245	+ if (spi->cur_comm == SPI_SIMPLEX_RX \|\| spi->cur_comm == SPI_3WIRE_RX \|\|
	1246	+ spi->cur_comm == SPI_FULL_DUPLEX) {
	1247	+ /*
	1248	+ * In transmit-only mode, the OVR flag is set in the SR register
	1249	+ * since the received data are never read. Therefore set OVR
	1250	+ * interrupt only when rx buffer is available.
	1251	+ */
	1252	+ stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
	1253	+ }
	1254	+
	1255	+ stm32_spi_enable(spi);
	1256	+}
	1257	+
	1258	+/**
	1259	+ * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
	1260	+ * transfer using DMA
	1261	+ * @spi: pointer to the spi controller data structure
	1262	+ */
	1263	+static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
	1264	+{
	1265	+ /* Enable the interrupts relative to the end of transfer */
	1266	+ stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE \|
	1267	+ STM32H7_SPI_IER_TXTFIE \|
	1268	+ STM32H7_SPI_IER_OVRIE \|
	1269	+ STM32H7_SPI_IER_MODFIE);
	1270	+
	1271	+ stm32_spi_enable(spi);
	1272	+
	1273	+ stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
	1274	+}
	1275	+
	1276	+/**
751	1277	* stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
	1278	+ * @spi: pointer to the spi controller data structure
	1279	+ * @xfer: pointer to the spi_transfer structure
752	1280	*
753	1281	* It must returns 0 if the transfer is finished or 1 if the transfer is still
754	1282	* in progress.
..	..	@@ -759,17 +1287,17 @@
759	1287	struct dma_slave_config tx_dma_conf, rx_dma_conf;
760	1288	struct dma_async_tx_descriptor tx_dma_desc, rx_dma_desc;
761	1289	unsigned long flags;
762		- u32 ier = 0;
763	1290
764	1291	spin_lock_irqsave(&spi->lock, flags);
765	1292
766	1293	rx_dma_desc = NULL;
767		- if (spi->rx_buf) {
	1294	+ if (spi->rx_buf && spi->dma_rx) {
768	1295	stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
769	1296	dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
770	1297
771	1298	/* Enable Rx DMA request */
772		- stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
	1299	+ stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
	1300	+ spi->cfg->regs->dma_rx_en.mask);
773	1301
774	1302	rx_dma_desc = dmaengine_prep_slave_sg(
775	1303	spi->dma_rx, xfer->rx_sg.sgl,
..	..	@@ -779,7 +1307,7 @@
779	1307	}
780	1308
781	1309	tx_dma_desc = NULL;
782		- if (spi->tx_buf) {
	1310	+ if (spi->tx_buf && spi->dma_tx) {
783	1311	stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
784	1312	dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
785	1313
..	..	@@ -790,12 +1318,15 @@
790	1318	DMA_PREP_INTERRUPT);
791	1319	}
792	1320
793		- if ((spi->tx_buf && !tx_dma_desc) \|\|
794		- (spi->rx_buf && !rx_dma_desc))
	1321	+ if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) \|\|
	1322	+ (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
	1323	+ goto dma_desc_error;
	1324	+
	1325	+ if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc \|\| !rx_dma_desc))
795	1326	goto dma_desc_error;
796	1327
797	1328	if (rx_dma_desc) {
798		- rx_dma_desc->callback = stm32_spi_dma_cb;
	1329	+ rx_dma_desc->callback = spi->cfg->dma_rx_cb;
799	1330	rx_dma_desc->callback_param = spi;
800	1331
801	1332	if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
..	..	@@ -807,8 +1338,9 @@
807	1338	}
808	1339
809	1340	if (tx_dma_desc) {
810		- if (spi->cur_comm == SPI_SIMPLEX_TX) {
811		- tx_dma_desc->callback = stm32_spi_dma_cb;
	1341	+ if (spi->cur_comm == SPI_SIMPLEX_TX \|\|
	1342	+ spi->cur_comm == SPI_3WIRE_TX) {
	1343	+ tx_dma_desc->callback = spi->cfg->dma_tx_cb;
812	1344	tx_dma_desc->callback_param = spi;
813	1345	}
814	1346
..	..	@@ -820,130 +1352,281 @@
820	1352	dma_async_issue_pending(spi->dma_tx);
821	1353
822	1354	/* Enable Tx DMA request */
823		- stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN);
	1355	+ stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
	1356	+ spi->cfg->regs->dma_tx_en.mask);
824	1357	}
825	1358
826		- /* Enable the interrupts relative to the end of transfer */
827		- ier \|= SPI_IER_EOTIE \| SPI_IER_TXTFIE \| SPI_IER_OVRIE \| SPI_IER_MODFIE;
828		- writel_relaxed(ier, spi->base + STM32_SPI_IER);
829		-
830		- stm32_spi_enable(spi);
831		-
832		- stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
	1359	+ spi->cfg->transfer_one_dma_start(spi);
833	1360
834	1361	spin_unlock_irqrestore(&spi->lock, flags);
835	1362
836	1363	return 1;
837	1364
838	1365	dma_submit_error:
839		- if (spi->rx_buf)
	1366	+ if (spi->dma_rx)
840	1367	dmaengine_terminate_all(spi->dma_rx);
841	1368
842	1369	dma_desc_error:
843		- stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
	1370	+ stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
	1371	+ spi->cfg->regs->dma_rx_en.mask);
844	1372
845	1373	spin_unlock_irqrestore(&spi->lock, flags);
846	1374
847	1375	dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
848	1376
849		- return stm32_spi_transfer_one_irq(spi);
	1377	+ spi->cur_usedma = false;
	1378	+ return spi->cfg->transfer_one_irq(spi);
	1379	+}
	1380	+
	1381	+/**
	1382	+ * stm32f4_spi_set_bpw - Configure bits per word
	1383	+ * @spi: pointer to the spi controller data structure
	1384	+ */
	1385	+static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
	1386	+{
	1387	+ if (spi->cur_bpw == 16)
	1388	+ stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
	1389	+ else
	1390	+ stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
	1391	+}
	1392	+
	1393	+/**
	1394	+ * stm32h7_spi_set_bpw - configure bits per word
	1395	+ * @spi: pointer to the spi controller data structure
	1396	+ */
	1397	+static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
	1398	+{
	1399	+ u32 bpw, fthlv;
	1400	+ u32 cfg1_clrb = 0, cfg1_setb = 0;
	1401	+
	1402	+ bpw = spi->cur_bpw - 1;
	1403	+
	1404	+ cfg1_clrb \|= STM32H7_SPI_CFG1_DSIZE;
	1405	+ cfg1_setb \|= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
	1406	+ STM32H7_SPI_CFG1_DSIZE;
	1407	+
	1408	+ spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
	1409	+ fthlv = spi->cur_fthlv - 1;
	1410	+
	1411	+ cfg1_clrb \|= STM32H7_SPI_CFG1_FTHLV;
	1412	+ cfg1_setb \|= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
	1413	+ STM32H7_SPI_CFG1_FTHLV;
	1414	+
	1415	+ writel_relaxed(
	1416	+ (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
	1417	+ ~cfg1_clrb) \| cfg1_setb,
	1418	+ spi->base + STM32H7_SPI_CFG1);
	1419	+}
	1420	+
	1421	+/**
	1422	+ * stm32_spi_set_mbr - Configure baud rate divisor in master mode
	1423	+ * @spi: pointer to the spi controller data structure
	1424	+ * @mbrdiv: baud rate divisor value
	1425	+ */
	1426	+static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
	1427	+{
	1428	+ u32 clrb = 0, setb = 0;
	1429	+
	1430	+ clrb \|= spi->cfg->regs->br.mask;
	1431	+ setb \|= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
	1432	+ spi->cfg->regs->br.mask;
	1433	+
	1434	+ writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
	1435	+ ~clrb) \| setb,
	1436	+ spi->base + spi->cfg->regs->br.reg);
	1437	+}
	1438	+
	1439	+/**
	1440	+ * stm32_spi_communication_type - return transfer communication type
	1441	+ * @spi_dev: pointer to the spi device
	1442	+ * @transfer: pointer to spi transfer
	1443	+ */
	1444	+static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
	1445	+ struct spi_transfer *transfer)
	1446	+{
	1447	+ unsigned int type = SPI_FULL_DUPLEX;
	1448	+
	1449	+ if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
	1450	+ /*
	1451	+ * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
	1452	+ * is forbidden and unvalidated by SPI subsystem so depending
	1453	+ * on the valid buffer, we can determine the direction of the
	1454	+ * transfer.
	1455	+ */
	1456	+ if (!transfer->tx_buf)
	1457	+ type = SPI_3WIRE_RX;
	1458	+ else
	1459	+ type = SPI_3WIRE_TX;
	1460	+ } else {
	1461	+ if (!transfer->tx_buf)
	1462	+ type = SPI_SIMPLEX_RX;
	1463	+ else if (!transfer->rx_buf)
	1464	+ type = SPI_SIMPLEX_TX;
	1465	+ }
	1466	+
	1467	+ return type;
	1468	+}
	1469	+
	1470	+/**
	1471	+ * stm32f4_spi_set_mode - configure communication mode
	1472	+ * @spi: pointer to the spi controller data structure
	1473	+ * @comm_type: type of communication to configure
	1474	+ */
	1475	+static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
	1476	+{
	1477	+ if (comm_type == SPI_3WIRE_TX \|\| comm_type == SPI_SIMPLEX_TX) {
	1478	+ stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
	1479	+ STM32F4_SPI_CR1_BIDIMODE \|
	1480	+ STM32F4_SPI_CR1_BIDIOE);
	1481	+ } else if (comm_type == SPI_FULL_DUPLEX \|\|
	1482	+ comm_type == SPI_SIMPLEX_RX) {
	1483	+ stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
	1484	+ STM32F4_SPI_CR1_BIDIMODE \|
	1485	+ STM32F4_SPI_CR1_BIDIOE);
	1486	+ } else if (comm_type == SPI_3WIRE_RX) {
	1487	+ stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
	1488	+ STM32F4_SPI_CR1_BIDIMODE);
	1489	+ stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
	1490	+ STM32F4_SPI_CR1_BIDIOE);
	1491	+ } else {
	1492	+ return -EINVAL;
	1493	+ }
	1494	+
	1495	+ return 0;
	1496	+}
	1497	+
	1498	+/**
	1499	+ * stm32h7_spi_set_mode - configure communication mode
	1500	+ * @spi: pointer to the spi controller data structure
	1501	+ * @comm_type: type of communication to configure
	1502	+ */
	1503	+static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
	1504	+{
	1505	+ u32 mode;
	1506	+ u32 cfg2_clrb = 0, cfg2_setb = 0;
	1507	+
	1508	+ if (comm_type == SPI_3WIRE_RX) {
	1509	+ mode = STM32H7_SPI_HALF_DUPLEX;
	1510	+ stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
	1511	+ } else if (comm_type == SPI_3WIRE_TX) {
	1512	+ mode = STM32H7_SPI_HALF_DUPLEX;
	1513	+ stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
	1514	+ } else if (comm_type == SPI_SIMPLEX_RX) {
	1515	+ mode = STM32H7_SPI_SIMPLEX_RX;
	1516	+ } else if (comm_type == SPI_SIMPLEX_TX) {
	1517	+ mode = STM32H7_SPI_SIMPLEX_TX;
	1518	+ } else {
	1519	+ mode = STM32H7_SPI_FULL_DUPLEX;
	1520	+ }
	1521	+
	1522	+ cfg2_clrb \|= STM32H7_SPI_CFG2_COMM;
	1523	+ cfg2_setb \|= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
	1524	+ STM32H7_SPI_CFG2_COMM;
	1525	+
	1526	+ writel_relaxed(
	1527	+ (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
	1528	+ ~cfg2_clrb) \| cfg2_setb,
	1529	+ spi->base + STM32H7_SPI_CFG2);
	1530	+
	1531	+ return 0;
	1532	+}
	1533	+
	1534	+/**
	1535	+ * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
	1536	+ * consecutive data frames in master mode
	1537	+ * @spi: pointer to the spi controller data structure
	1538	+ * @len: transfer len
	1539	+ */
	1540	+static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
	1541	+{
	1542	+ u32 cfg2_clrb = 0, cfg2_setb = 0;
	1543	+
	1544	+ cfg2_clrb \|= STM32H7_SPI_CFG2_MIDI;
	1545	+ if ((len > 1) && (spi->cur_midi > 0)) {
	1546	+ u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
	1547	+ u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
	1548	+ (u32)STM32H7_SPI_CFG2_MIDI >>
	1549	+ STM32H7_SPI_CFG2_MIDI_SHIFT);
	1550	+
	1551	+ dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
	1552	+ sck_period_ns, midi, midi * sck_period_ns);
	1553	+ cfg2_setb \|= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
	1554	+ STM32H7_SPI_CFG2_MIDI;
	1555	+ }
	1556	+
	1557	+ writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
	1558	+ ~cfg2_clrb) \| cfg2_setb,
	1559	+ spi->base + STM32H7_SPI_CFG2);
	1560	+}
	1561	+
	1562	+/**
	1563	+ * stm32h7_spi_number_of_data - configure number of data at current transfer
	1564	+ * @spi: pointer to the spi controller data structure
	1565	+ * @nb_words: transfer length (in words)
	1566	+ */
	1567	+static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
	1568	+{
	1569	+ u32 cr2_clrb = 0, cr2_setb = 0;
	1570	+
	1571	+ if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
	1572	+ STM32H7_SPI_CR2_TSIZE_SHIFT)) {
	1573	+ cr2_clrb \|= STM32H7_SPI_CR2_TSIZE;
	1574	+ cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
	1575	+ writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
	1576	+ ~cr2_clrb) \| cr2_setb,
	1577	+ spi->base + STM32H7_SPI_CR2);
	1578	+ } else {
	1579	+ return -EMSGSIZE;
	1580	+ }
	1581	+
	1582	+ return 0;
850	1583	}
851	1584
852	1585	/**
853	1586	* stm32_spi_transfer_one_setup - common setup to transfer a single
854	1587	* spi_transfer either using DMA or
855	1588	* interrupts.
	1589	+ * @spi: pointer to the spi controller data structure
	1590	+ * @spi_dev: pointer to the spi device
	1591	+ * @transfer: pointer to spi transfer
856	1592	*/
857	1593	static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
858	1594	struct spi_device *spi_dev,
859	1595	struct spi_transfer *transfer)
860	1596	{
861	1597	unsigned long flags;
862		- u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0;
863		- u32 mode, nb_words;
864		- int ret = 0;
	1598	+ unsigned int comm_type;
	1599	+ int nb_words, ret = 0;
	1600	+ int mbr;
865	1601
866	1602	spin_lock_irqsave(&spi->lock, flags);
867	1603
868		- if (spi->cur_bpw != transfer->bits_per_word) {
869		- u32 bpw, fthlv;
	1604	+ spi->cur_xferlen = transfer->len;
870	1605
871		- spi->cur_bpw = transfer->bits_per_word;
872		- bpw = spi->cur_bpw - 1;
	1606	+ spi->cur_bpw = transfer->bits_per_word;
	1607	+ spi->cfg->set_bpw(spi);
873	1608
874		- cfg1_clrb \|= SPI_CFG1_DSIZE;
875		- cfg1_setb \|= (bpw << SPI_CFG1_DSIZE_SHIFT) & SPI_CFG1_DSIZE;
876		-
877		- spi->cur_fthlv = stm32_spi_prepare_fthlv(spi);
878		- fthlv = spi->cur_fthlv - 1;
879		-
880		- cfg1_clrb \|= SPI_CFG1_FTHLV;
881		- cfg1_setb \|= (fthlv << SPI_CFG1_FTHLV_SHIFT) & SPI_CFG1_FTHLV;
	1609	+ /* Update spi->cur_speed with real clock speed */
	1610	+ mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
	1611	+ spi->cfg->baud_rate_div_min,
	1612	+ spi->cfg->baud_rate_div_max);
	1613	+ if (mbr < 0) {
	1614	+ ret = mbr;
	1615	+ goto out;
882	1616	}
883	1617
884		- if (spi->cur_speed != transfer->speed_hz) {
885		- int mbr;
	1618	+ transfer->speed_hz = spi->cur_speed;
	1619	+ stm32_spi_set_mbr(spi, mbr);
886	1620
887		- /* Update spi->cur_speed with real clock speed */
888		- mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz);
889		- if (mbr < 0) {
890		- ret = mbr;
891		- goto out;
892		- }
	1621	+ comm_type = stm32_spi_communication_type(spi_dev, transfer);
	1622	+ ret = spi->cfg->set_mode(spi, comm_type);
	1623	+ if (ret < 0)
	1624	+ goto out;
893	1625
894		- transfer->speed_hz = spi->cur_speed;
	1626	+ spi->cur_comm = comm_type;
895	1627
896		- cfg1_clrb \|= SPI_CFG1_MBR;
897		- cfg1_setb \|= ((u32)mbr << SPI_CFG1_MBR_SHIFT) & SPI_CFG1_MBR;
898		- }
899		-
900		- if (cfg1_clrb \|\| cfg1_setb)
901		- writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG1) &
902		- ~cfg1_clrb) \| cfg1_setb,
903		- spi->base + STM32_SPI_CFG1);
904		-
905		- mode = SPI_FULL_DUPLEX;
906		- if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
907		- /*
908		- * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
909		- * is forbidden und unvalidated by SPI subsystem so depending
910		- * on the valid buffer, we can determine the direction of the
911		- * transfer.
912		- */
913		- mode = SPI_HALF_DUPLEX;
914		- if (!transfer->tx_buf)
915		- stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
916		- else if (!transfer->rx_buf)
917		- stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
918		- } else {
919		- if (!transfer->tx_buf)
920		- mode = SPI_SIMPLEX_RX;
921		- else if (!transfer->rx_buf)
922		- mode = SPI_SIMPLEX_TX;
923		- }
924		- if (spi->cur_comm != mode) {
925		- spi->cur_comm = mode;
926		-
927		- cfg2_clrb \|= SPI_CFG2_COMM;
928		- cfg2_setb \|= (mode << SPI_CFG2_COMM_SHIFT) & SPI_CFG2_COMM;
929		- }
930		-
931		- cfg2_clrb \|= SPI_CFG2_MIDI;
932		- if ((transfer->len > 1) && (spi->cur_midi > 0)) {
933		- u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
934		- u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
935		- (u32)SPI_CFG2_MIDI >> SPI_CFG2_MIDI_SHIFT);
936		-
937		- dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
938		- sck_period_ns, midi, midi * sck_period_ns);
939		-
940		- cfg2_setb \|= (midi << SPI_CFG2_MIDI_SHIFT) & SPI_CFG2_MIDI;
941		- }
942		-
943		- if (cfg2_clrb \|\| cfg2_setb)
944		- writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG2) &
945		- ~cfg2_clrb) \| cfg2_setb,
946		- spi->base + STM32_SPI_CFG2);
	1628	+ if (spi->cfg->set_data_idleness)
	1629	+ spi->cfg->set_data_idleness(spi, transfer->len);
947	1630
948	1631	if (spi->cur_bpw <= 8)
949	1632	nb_words = transfer->len;
..	..	@@ -951,16 +1634,12 @@
951	1634	nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
952	1635	else
953	1636	nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
954		- nb_words <<= SPI_CR2_TSIZE_SHIFT;
955	1637
956		- if (nb_words <= SPI_CR2_TSIZE) {
957		- writel_relaxed(nb_words, spi->base + STM32_SPI_CR2);
958		- } else {
959		- ret = -EMSGSIZE;
960		- goto out;
	1638	+ if (spi->cfg->set_number_of_data) {
	1639	+ ret = spi->cfg->set_number_of_data(spi, nb_words);
	1640	+ if (ret < 0)
	1641	+ goto out;
961	1642	}
962		-
963		- spi->cur_xferlen = transfer->len;
964	1643
965	1644	dev_dbg(spi->dev, "transfer communication mode set to %d\n",
966	1645	spi->cur_comm);
..	..	@@ -981,6 +1660,9 @@
981	1660
982	1661	/**
983	1662	* stm32_spi_transfer_one - transfer a single spi_transfer
	1663	+ * @master: controller master interface
	1664	+ * @spi_dev: pointer to the spi device
	1665	+ * @transfer: pointer to spi transfer
984	1666	*
985	1667	* It must return 0 if the transfer is finished or 1 if the transfer is still
986	1668	* in progress.
..	..	@@ -1002,7 +1684,7 @@
1002	1684	spi->rx_len = spi->rx_buf ? transfer->len : 0;
1003	1685
1004	1686	spi->cur_usedma = (master->can_dma &&
1005		- stm32_spi_can_dma(master, spi_dev, transfer));
	1687	+ master->can_dma(master, spi_dev, transfer));
1006	1688
1007	1689	ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1008	1690	if (ret) {
..	..	@@ -1013,47 +1695,77 @@
1013	1695	if (spi->cur_usedma)
1014	1696	return stm32_spi_transfer_one_dma(spi, transfer);
1015	1697	else
1016		- return stm32_spi_transfer_one_irq(spi);
	1698	+ return spi->cfg->transfer_one_irq(spi);
1017	1699	}
1018	1700
1019	1701	/**
1020	1702	* stm32_spi_unprepare_msg - relax the hardware
1021		- *
1022		- * Normally, if TSIZE has been configured, we should relax the hardware at the
1023		- * reception of the EOT interrupt. But in case of error, EOT will not be
1024		- * raised. So the subsystem unprepare_message call allows us to properly
1025		- * complete the transfer from an hardware point of view.
	1703	+ * @master: controller master interface
	1704	+ * @msg: pointer to the spi message
1026	1705	*/
1027	1706	static int stm32_spi_unprepare_msg(struct spi_master *master,
1028	1707	struct spi_message *msg)
1029	1708	{
1030	1709	struct stm32_spi *spi = spi_master_get_devdata(master);
1031	1710
1032		- stm32_spi_disable(spi);
	1711	+ spi->cfg->disable(spi);
1033	1712
1034	1713	return 0;
1035	1714	}
1036	1715
1037	1716	/**
1038		- * stm32_spi_config - Configure SPI controller as SPI master
	1717	+ * stm32f4_spi_config - Configure SPI controller as SPI master
	1718	+ * @spi: pointer to the spi controller data structure
1039	1719	*/
1040		-static int stm32_spi_config(struct stm32_spi *spi)
	1720	+static int stm32f4_spi_config(struct stm32_spi *spi)
1041	1721	{
1042	1722	unsigned long flags;
1043	1723
1044	1724	spin_lock_irqsave(&spi->lock, flags);
1045	1725
1046	1726	/* Ensure I2SMOD bit is kept cleared */
1047		- stm32_spi_clr_bits(spi, STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
	1727	+ stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
	1728	+ STM32F4_SPI_I2SCFGR_I2SMOD);
	1729	+
	1730	+ /*
	1731	+ * - SS input value high
	1732	+ * - transmitter half duplex direction
	1733	+ * - Set the master mode (default Motorola mode)
	1734	+ * - Consider 1 master/n slaves configuration and
	1735	+ * SS input value is determined by the SSI bit
	1736	+ */
	1737	+ stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI \|
	1738	+ STM32F4_SPI_CR1_BIDIOE \|
	1739	+ STM32F4_SPI_CR1_MSTR \|
	1740	+ STM32F4_SPI_CR1_SSM);
	1741	+
	1742	+ spin_unlock_irqrestore(&spi->lock, flags);
	1743	+
	1744	+ return 0;
	1745	+}
	1746	+
	1747	+/**
	1748	+ * stm32h7_spi_config - Configure SPI controller as SPI master
	1749	+ * @spi: pointer to the spi controller data structure
	1750	+ */
	1751	+static int stm32h7_spi_config(struct stm32_spi *spi)
	1752	+{
	1753	+ unsigned long flags;
	1754	+
	1755	+ spin_lock_irqsave(&spi->lock, flags);
	1756	+
	1757	+ /* Ensure I2SMOD bit is kept cleared */
	1758	+ stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
	1759	+ STM32H7_SPI_I2SCFGR_I2SMOD);
1048	1760
1049	1761	/*
1050	1762	* - SS input value high
1051	1763	* - transmitter half duplex direction
1052	1764	* - automatic communication suspend when RX-Fifo is full
1053	1765	*/
1054		- stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SSI \|
1055		- SPI_CR1_HDDIR \|
1056		- SPI_CR1_MASRX);
	1766	+ stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI \|
	1767	+ STM32H7_SPI_CR1_HDDIR \|
	1768	+ STM32H7_SPI_CR1_MASRX);
1057	1769
1058	1770	/*
1059	1771	* - Set the master mode (default Motorola mode)
..	..	@@ -1061,17 +1773,56 @@
1061	1773	* SS input value is determined by the SSI bit
1062	1774	* - keep control of all associated GPIOs
1063	1775	*/
1064		- stm32_spi_set_bits(spi, STM32_SPI_CFG2, SPI_CFG2_MASTER \|
1065		- SPI_CFG2_SSM \|
1066		- SPI_CFG2_AFCNTR);
	1776	+ stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER \|
	1777	+ STM32H7_SPI_CFG2_SSM \|
	1778	+ STM32H7_SPI_CFG2_AFCNTR);
1067	1779
1068	1780	spin_unlock_irqrestore(&spi->lock, flags);
1069	1781
1070	1782	return 0;
1071	1783	}
1072	1784
	1785	+static const struct stm32_spi_cfg stm32f4_spi_cfg = {
	1786	+ .regs = &stm32f4_spi_regspec,
	1787	+ .get_bpw_mask = stm32f4_spi_get_bpw_mask,
	1788	+ .disable = stm32f4_spi_disable,
	1789	+ .config = stm32f4_spi_config,
	1790	+ .set_bpw = stm32f4_spi_set_bpw,
	1791	+ .set_mode = stm32f4_spi_set_mode,
	1792	+ .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
	1793	+ .dma_tx_cb = stm32f4_spi_dma_tx_cb,
	1794	+ .dma_rx_cb = stm32f4_spi_dma_rx_cb,
	1795	+ .transfer_one_irq = stm32f4_spi_transfer_one_irq,
	1796	+ .irq_handler_event = stm32f4_spi_irq_event,
	1797	+ .irq_handler_thread = stm32f4_spi_irq_thread,
	1798	+ .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
	1799	+ .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
	1800	+ .has_fifo = false,
	1801	+};
	1802	+
	1803	+static const struct stm32_spi_cfg stm32h7_spi_cfg = {
	1804	+ .regs = &stm32h7_spi_regspec,
	1805	+ .get_fifo_size = stm32h7_spi_get_fifo_size,
	1806	+ .get_bpw_mask = stm32h7_spi_get_bpw_mask,
	1807	+ .disable = stm32h7_spi_disable,
	1808	+ .config = stm32h7_spi_config,
	1809	+ .set_bpw = stm32h7_spi_set_bpw,
	1810	+ .set_mode = stm32h7_spi_set_mode,
	1811	+ .set_data_idleness = stm32h7_spi_data_idleness,
	1812	+ .set_number_of_data = stm32h7_spi_number_of_data,
	1813	+ .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
	1814	+ .dma_rx_cb = stm32h7_spi_dma_cb,
	1815	+ .dma_tx_cb = stm32h7_spi_dma_cb,
	1816	+ .transfer_one_irq = stm32h7_spi_transfer_one_irq,
	1817	+ .irq_handler_thread = stm32h7_spi_irq_thread,
	1818	+ .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
	1819	+ .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
	1820	+ .has_fifo = true,
	1821	+};
	1822	+
1073	1823	static const struct of_device_id stm32_spi_of_match[] = {
1074		- { .compatible = "st,stm32h7-spi", },
	1824	+ { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
	1825	+ { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1075	1826	{},
1076	1827	};
1077	1828	MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
..	..	@@ -1081,9 +1832,9 @@
1081	1832	struct spi_master *master;
1082	1833	struct stm32_spi *spi;
1083	1834	struct resource *res;
1084		- int i, ret;
	1835	+ int ret;
1085	1836
1086		- master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
	1837	+ master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1087	1838	if (!master) {
1088	1839	dev_err(&pdev->dev, "spi master allocation failed\n");
1089	1840	return -ENOMEM;
..	..	@@ -1095,40 +1846,43 @@
1095	1846	spi->master = master;
1096	1847	spin_lock_init(&spi->lock);
1097	1848
	1849	+ spi->cfg = (const struct stm32_spi_cfg *)
	1850	+ of_match_device(pdev->dev.driver->of_match_table,
	1851	+ &pdev->dev)->data;
	1852	+
1098	1853	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099	1854	spi->base = devm_ioremap_resource(&pdev->dev, res);
1100		- if (IS_ERR(spi->base)) {
1101		- ret = PTR_ERR(spi->base);
1102		- goto err_master_put;
1103		- }
	1855	+ if (IS_ERR(spi->base))
	1856	+ return PTR_ERR(spi->base);
	1857	+
1104	1858	spi->phys_addr = (dma_addr_t)res->start;
1105	1859
1106	1860	spi->irq = platform_get_irq(pdev, 0);
1107		- if (spi->irq <= 0) {
1108		- dev_err(&pdev->dev, "no irq: %d\n", spi->irq);
1109		- ret = -ENOENT;
1110		- goto err_master_put;
1111		- }
1112		- ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL,
1113		- stm32_spi_irq, IRQF_ONESHOT,
1114		- pdev->name, master);
	1861	+ if (spi->irq <= 0)
	1862	+ return dev_err_probe(&pdev->dev, spi->irq,
	1863	+ "failed to get irq\n");
	1864	+
	1865	+ ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
	1866	+ spi->cfg->irq_handler_event,
	1867	+ spi->cfg->irq_handler_thread,
	1868	+ IRQF_ONESHOT, pdev->name, master);
1115	1869	if (ret) {
1116	1870	dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1117	1871	ret);
1118		- goto err_master_put;
	1872	+ return ret;
1119	1873	}
1120	1874
1121		- spi->clk = devm_clk_get(&pdev->dev, 0);
	1875	+ spi->clk = devm_clk_get(&pdev->dev, NULL);
1122	1876	if (IS_ERR(spi->clk)) {
1123	1877	ret = PTR_ERR(spi->clk);
1124	1878	dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1125		- goto err_master_put;
	1879	+ return ret;
1126	1880	}
1127	1881
1128	1882	ret = clk_prepare_enable(spi->clk);
1129	1883	if (ret) {
1130	1884	dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1131		- goto err_master_put;
	1885	+ return ret;
1132	1886	}
1133	1887	spi->clk_rate = clk_get_rate(spi->clk);
1134	1888	if (!spi->clk_rate) {
..	..	@@ -1144,9 +1898,10 @@
1144	1898	reset_control_deassert(spi->rst);
1145	1899	}
1146	1900
1147		- spi->fifo_size = stm32_spi_get_fifo_size(spi);
	1901	+ if (spi->cfg->has_fifo)
	1902	+ spi->fifo_size = spi->cfg->get_fifo_size(spi);
1148	1903
1149		- ret = stm32_spi_config(spi);
	1904	+ ret = spi->cfg->config(spi);
1150	1905	if (ret) {
1151	1906	dev_err(&pdev->dev, "controller configuration failed: %d\n",
1152	1907	ret);
..	..	@@ -1156,79 +1911,76 @@
1156	1911	master->dev.of_node = pdev->dev.of_node;
1157	1912	master->auto_runtime_pm = true;
1158	1913	master->bus_num = pdev->id;
1159		- master->mode_bits = SPI_MODE_3 \| SPI_CS_HIGH \| SPI_LSB_FIRST \|
1160		- SPI_3WIRE \| SPI_LOOP;
1161		- master->bits_per_word_mask = stm32_spi_get_bpw_mask(spi);
1162		- master->max_speed_hz = spi->clk_rate / SPI_MBR_DIV_MIN;
1163		- master->min_speed_hz = spi->clk_rate / SPI_MBR_DIV_MAX;
1164		- master->setup = stm32_spi_setup;
	1914	+ master->mode_bits = SPI_CPHA \| SPI_CPOL \| SPI_CS_HIGH \| SPI_LSB_FIRST \|
	1915	+ SPI_3WIRE;
	1916	+ master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
	1917	+ master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
	1918	+ master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
	1919	+ master->use_gpio_descriptors = true;
1165	1920	master->prepare_message = stm32_spi_prepare_msg;
1166	1921	master->transfer_one = stm32_spi_transfer_one;
1167	1922	master->unprepare_message = stm32_spi_unprepare_msg;
	1923	+ master->flags = SPI_MASTER_MUST_TX;
1168	1924
1169		- spi->dma_tx = dma_request_slave_channel(spi->dev, "tx");
1170		- if (!spi->dma_tx)
	1925	+ spi->dma_tx = dma_request_chan(spi->dev, "tx");
	1926	+ if (IS_ERR(spi->dma_tx)) {
	1927	+ ret = PTR_ERR(spi->dma_tx);
	1928	+ spi->dma_tx = NULL;
	1929	+ if (ret == -EPROBE_DEFER)
	1930	+ goto err_clk_disable;
	1931	+
1171	1932	dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1172		- else
	1933	+ } else {
1173	1934	master->dma_tx = spi->dma_tx;
	1935	+ }
1174	1936
1175		- spi->dma_rx = dma_request_slave_channel(spi->dev, "rx");
1176		- if (!spi->dma_rx)
	1937	+ spi->dma_rx = dma_request_chan(spi->dev, "rx");
	1938	+ if (IS_ERR(spi->dma_rx)) {
	1939	+ ret = PTR_ERR(spi->dma_rx);
	1940	+ spi->dma_rx = NULL;
	1941	+ if (ret == -EPROBE_DEFER)
	1942	+ goto err_dma_release;
	1943	+
1177	1944	dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1178		- else
	1945	+ } else {
1179	1946	master->dma_rx = spi->dma_rx;
	1947	+ }
1180	1948
1181	1949	if (spi->dma_tx \|\| spi->dma_rx)
1182	1950	master->can_dma = stm32_spi_can_dma;
1183	1951
1184	1952	pm_runtime_set_active(&pdev->dev);
	1953	+ pm_runtime_get_noresume(&pdev->dev);
1185	1954	pm_runtime_enable(&pdev->dev);
1186	1955
1187		- ret = devm_spi_register_master(&pdev->dev, master);
	1956	+ ret = spi_register_master(master);
1188	1957	if (ret) {
1189	1958	dev_err(&pdev->dev, "spi master registration failed: %d\n",
1190	1959	ret);
1191		- goto err_dma_release;
	1960	+ goto err_pm_disable;
1192	1961	}
1193	1962
1194		- if (!master->cs_gpios) {
	1963	+ if (!master->cs_gpiods) {
1195	1964	dev_err(&pdev->dev, "no CS gpios available\n");
1196	1965	ret = -EINVAL;
1197		- goto err_dma_release;
1198		- }
1199		-
1200		- for (i = 0; i < master->num_chipselect; i++) {
1201		- if (!gpio_is_valid(master->cs_gpios[i])) {
1202		- dev_err(&pdev->dev, "%i is not a valid gpio\n",
1203		- master->cs_gpios[i]);
1204		- ret = -EINVAL;
1205		- goto err_dma_release;
1206		- }
1207		-
1208		- ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
1209		- DRIVER_NAME);
1210		- if (ret) {
1211		- dev_err(&pdev->dev, "can't get CS gpio %i\n",
1212		- master->cs_gpios[i]);
1213		- goto err_dma_release;
1214		- }
	1966	+ goto err_pm_disable;
1215	1967	}
1216	1968
1217	1969	dev_info(&pdev->dev, "driver initialized\n");
1218	1970
1219	1971	return 0;
1220	1972
	1973	+err_pm_disable:
	1974	+ pm_runtime_disable(&pdev->dev);
	1975	+ pm_runtime_put_noidle(&pdev->dev);
	1976	+ pm_runtime_set_suspended(&pdev->dev);
1221	1977	err_dma_release:
1222	1978	if (spi->dma_tx)
1223	1979	dma_release_channel(spi->dma_tx);
1224	1980	if (spi->dma_rx)
1225	1981	dma_release_channel(spi->dma_rx);
1226		-
1227		- pm_runtime_disable(&pdev->dev);
1228	1982	err_clk_disable:
1229	1983	clk_disable_unprepare(spi->clk);
1230		-err_master_put:
1231		- spi_master_put(master);
1232	1984
1233	1985	return ret;
1234	1986	}
..	..	@@ -1238,8 +1990,14 @@
1238	1990	struct spi_master *master = platform_get_drvdata(pdev);
1239	1991	struct stm32_spi *spi = spi_master_get_devdata(master);
1240	1992
1241		- stm32_spi_disable(spi);
	1993	+ pm_runtime_get_sync(&pdev->dev);
1242	1994
	1995	+ spi_unregister_master(master);
	1996	+ spi->cfg->disable(spi);
	1997	+
	1998	+ pm_runtime_disable(&pdev->dev);
	1999	+ pm_runtime_put_noidle(&pdev->dev);
	2000	+ pm_runtime_set_suspended(&pdev->dev);
1243	2001	if (master->dma_tx)
1244	2002	dma_release_channel(master->dma_tx);
1245	2003	if (master->dma_rx)
..	..	@@ -1247,7 +2005,8 @@
1247	2005
1248	2006	clk_disable_unprepare(spi->clk);
1249	2007
1250		- pm_runtime_disable(&pdev->dev);
	2008	+
	2009	+ pinctrl_pm_select_sleep_state(&pdev->dev);
1251	2010
1252	2011	return 0;
1253	2012	}
..	..	@@ -1260,13 +2019,18 @@
1260	2019
1261	2020	clk_disable_unprepare(spi->clk);
1262	2021
1263		- return 0;
	2022	+ return pinctrl_pm_select_sleep_state(dev);
1264	2023	}
1265	2024
1266	2025	static int stm32_spi_runtime_resume(struct device *dev)
1267	2026	{
1268	2027	struct spi_master *master = dev_get_drvdata(dev);
1269	2028	struct stm32_spi *spi = spi_master_get_devdata(master);
	2029	+ int ret;
	2030	+
	2031	+ ret = pinctrl_pm_select_default_state(dev);
	2032	+ if (ret)
	2033	+ return ret;
1270	2034
1271	2035	return clk_prepare_enable(spi->clk);
1272	2036	}
..	..	@@ -1296,10 +2060,24 @@
1296	2060	return ret;
1297	2061
1298	2062	ret = spi_master_resume(master);
1299		- if (ret)
	2063	+ if (ret) {
1300	2064	clk_disable_unprepare(spi->clk);
	2065	+ return ret;
	2066	+ }
1301	2067
1302		- return ret;
	2068	+ ret = pm_runtime_get_sync(dev);
	2069	+ if (ret < 0) {
	2070	+ pm_runtime_put_noidle(dev);
	2071	+ dev_err(dev, "Unable to power device:%d\n", ret);
	2072	+ return ret;
	2073	+ }
	2074	+
	2075	+ spi->cfg->config(spi);
	2076	+
	2077	+ pm_runtime_mark_last_busy(dev);
	2078	+ pm_runtime_put_autosuspend(dev);
	2079	+
	2080	+ return 0;
1303	2081	}
1304	2082	#endif
1305	2083