.. | .. |
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77 | 77 | |
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78 | 78 | /* Bits definitions for register REG_WDG_CTRL */ |
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79 | 79 | #define BIT_WDG_RUN BIT(1) |
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| 80 | +#define BIT_WDG_NEW BIT(2) |
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80 | 81 | #define BIT_WDG_RST BIT(3) |
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81 | 82 | |
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82 | 83 | /* Registers definitions for PMIC */ |
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.. | .. |
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86 | 87 | #define BIT_WDG_EN BIT(2) |
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87 | 88 | |
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88 | 89 | /* Definition of PMIC reset status register */ |
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| 90 | +#define HWRST_STATUS_SECURITY 0x02 |
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89 | 91 | #define HWRST_STATUS_RECOVERY 0x20 |
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90 | 92 | #define HWRST_STATUS_NORMAL 0x40 |
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91 | 93 | #define HWRST_STATUS_ALARM 0x50 |
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.. | .. |
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97 | 99 | #define HWRST_STATUS_AUTODLOADER 0xa0 |
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98 | 100 | #define HWRST_STATUS_IQMODE 0xb0 |
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99 | 101 | #define HWRST_STATUS_SPRDISK 0xc0 |
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| 102 | +#define HWRST_STATUS_FACTORYTEST 0xe0 |
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| 103 | +#define HWRST_STATUS_WATCHDOG 0xf0 |
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100 | 104 | |
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101 | 105 | /* Use default timeout 50 ms that converts to watchdog values */ |
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102 | 106 | #define WDG_LOAD_VAL ((50 * 32768) / 1000) |
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.. | .. |
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162 | 166 | int read_timeout = ADI_READ_TIMEOUT; |
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163 | 167 | unsigned long flags; |
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164 | 168 | u32 val, rd_addr; |
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165 | | - int ret; |
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| 169 | + int ret = 0; |
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166 | 170 | |
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167 | | - ret = hwspin_lock_timeout_irqsave(sadi->hwlock, |
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168 | | - ADI_HWSPINLOCK_TIMEOUT, |
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169 | | - &flags); |
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170 | | - if (ret) { |
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171 | | - dev_err(sadi->dev, "get the hw lock failed\n"); |
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172 | | - return ret; |
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| 171 | + if (sadi->hwlock) { |
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| 172 | + ret = hwspin_lock_timeout_irqsave(sadi->hwlock, |
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| 173 | + ADI_HWSPINLOCK_TIMEOUT, |
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| 174 | + &flags); |
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| 175 | + if (ret) { |
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| 176 | + dev_err(sadi->dev, "get the hw lock failed\n"); |
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| 177 | + return ret; |
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| 178 | + } |
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173 | 179 | } |
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174 | 180 | |
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175 | 181 | /* |
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.. | .. |
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216 | 222 | *read_val = val & RD_VALUE_MASK; |
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217 | 223 | |
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218 | 224 | out: |
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219 | | - hwspin_unlock_irqrestore(sadi->hwlock, &flags); |
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| 225 | + if (sadi->hwlock) |
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| 226 | + hwspin_unlock_irqrestore(sadi->hwlock, &flags); |
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220 | 227 | return ret; |
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221 | 228 | } |
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222 | 229 | |
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.. | .. |
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227 | 234 | unsigned long flags; |
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228 | 235 | int ret; |
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229 | 236 | |
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230 | | - ret = hwspin_lock_timeout_irqsave(sadi->hwlock, |
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231 | | - ADI_HWSPINLOCK_TIMEOUT, |
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232 | | - &flags); |
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233 | | - if (ret) { |
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234 | | - dev_err(sadi->dev, "get the hw lock failed\n"); |
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235 | | - return ret; |
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| 237 | + if (sadi->hwlock) { |
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| 238 | + ret = hwspin_lock_timeout_irqsave(sadi->hwlock, |
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| 239 | + ADI_HWSPINLOCK_TIMEOUT, |
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| 240 | + &flags); |
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| 241 | + if (ret) { |
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| 242 | + dev_err(sadi->dev, "get the hw lock failed\n"); |
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| 243 | + return ret; |
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| 244 | + } |
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236 | 245 | } |
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237 | 246 | |
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238 | 247 | ret = sprd_adi_drain_fifo(sadi); |
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.. | .. |
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258 | 267 | } |
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259 | 268 | |
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260 | 269 | out: |
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261 | | - hwspin_unlock_irqrestore(sadi->hwlock, &flags); |
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| 270 | + if (sadi->hwlock) |
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| 271 | + hwspin_unlock_irqrestore(sadi->hwlock, &flags); |
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262 | 272 | return ret; |
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263 | 273 | } |
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264 | 274 | |
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.. | .. |
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307 | 317 | return 0; |
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308 | 318 | } |
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309 | 319 | |
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| 320 | +static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi) |
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| 321 | +{ |
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| 322 | +#if IS_ENABLED(CONFIG_SPRD_WATCHDOG) |
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| 323 | + u32 val; |
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| 324 | + |
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| 325 | + /* Set default watchdog reboot mode */ |
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| 326 | + sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val); |
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| 327 | + val |= HWRST_STATUS_WATCHDOG; |
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| 328 | + sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val); |
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| 329 | +#endif |
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| 330 | +} |
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| 331 | + |
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310 | 332 | static int sprd_adi_restart_handler(struct notifier_block *this, |
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311 | 333 | unsigned long mode, void *cmd) |
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312 | 334 | { |
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.. | .. |
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336 | 358 | reboot_mode = HWRST_STATUS_IQMODE; |
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337 | 359 | else if (!strncmp(cmd, "sprdisk", 7)) |
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338 | 360 | reboot_mode = HWRST_STATUS_SPRDISK; |
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| 361 | + else if (!strncmp(cmd, "tospanic", 8)) |
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| 362 | + reboot_mode = HWRST_STATUS_SECURITY; |
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| 363 | + else if (!strncmp(cmd, "factorytest", 11)) |
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| 364 | + reboot_mode = HWRST_STATUS_FACTORYTEST; |
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339 | 365 | else |
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340 | 366 | reboot_mode = HWRST_STATUS_NORMAL; |
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341 | 367 | |
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342 | 368 | /* Record the reboot mode */ |
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343 | 369 | sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val); |
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| 370 | + val &= ~HWRST_STATUS_WATCHDOG; |
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344 | 371 | val |= reboot_mode; |
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345 | 372 | sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val); |
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346 | 373 | |
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.. | .. |
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356 | 383 | |
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357 | 384 | /* Unlock the watchdog */ |
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358 | 385 | sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY); |
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| 386 | + |
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| 387 | + sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val); |
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| 388 | + val |= BIT_WDG_NEW; |
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| 389 | + sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val); |
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359 | 390 | |
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360 | 391 | /* Load the watchdog timeout value, 50ms is always enough. */ |
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361 | 392 | sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0); |
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.. | .. |
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382 | 413 | int i, size, chn_cnt; |
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383 | 414 | const __be32 *list; |
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384 | 415 | u32 tmp; |
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385 | | - |
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386 | | - /* Address bits select default 12 bits */ |
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387 | | - writel_relaxed(0, sadi->base + REG_ADI_CTRL0); |
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388 | 416 | |
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389 | 417 | /* Set all channels as default priority */ |
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390 | 418 | writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL); |
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.. | .. |
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462 | 490 | sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET; |
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463 | 491 | sadi->ctlr = ctlr; |
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464 | 492 | sadi->dev = &pdev->dev; |
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465 | | - ret = of_hwspin_lock_get_id_byname(np, "adi"); |
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466 | | - if (ret < 0) { |
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467 | | - dev_err(&pdev->dev, "can not get the hardware spinlock\n"); |
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468 | | - goto put_ctlr; |
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469 | | - } |
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470 | | - |
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471 | | - sadi->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret); |
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472 | | - if (!sadi->hwlock) { |
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473 | | - ret = -ENXIO; |
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474 | | - goto put_ctlr; |
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| 493 | + ret = of_hwspin_lock_get_id(np, 0); |
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| 494 | + if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) { |
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| 495 | + sadi->hwlock = |
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| 496 | + devm_hwspin_lock_request_specific(&pdev->dev, ret); |
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| 497 | + if (!sadi->hwlock) { |
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| 498 | + ret = -ENXIO; |
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| 499 | + goto put_ctlr; |
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| 500 | + } |
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| 501 | + } else { |
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| 502 | + switch (ret) { |
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| 503 | + case -ENOENT: |
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| 504 | + dev_info(&pdev->dev, "no hardware spinlock supplied\n"); |
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| 505 | + break; |
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| 506 | + default: |
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| 507 | + dev_err_probe(&pdev->dev, ret, "failed to find hwlock id\n"); |
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| 508 | + goto put_ctlr; |
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| 509 | + } |
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475 | 510 | } |
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476 | 511 | |
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477 | 512 | sprd_adi_hw_init(sadi); |
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| 513 | + sprd_adi_set_wdt_rst_mode(sadi); |
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478 | 514 | |
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479 | 515 | ctlr->dev.of_node = pdev->dev.of_node; |
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480 | 516 | ctlr->bus_num = pdev->id; |
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