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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/spi/spi-sh-msiof.c
....@@ -1,14 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
2
- * SuperH MSIOF SPI Master Interface
3
+ * SuperH MSIOF SPI Controller Interface
34  *
45  * Copyright (c) 2009 Magnus Damm
56  * Copyright (C) 2014 Renesas Electronics Corporation
67  * Copyright (C) 2014-2017 Glider bvba
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
11
- *
128  */
139 
1410 #include <linux/bitmap.h>
....@@ -18,10 +14,9 @@
1814 #include <linux/dma-mapping.h>
1915 #include <linux/dmaengine.h>
2016 #include <linux/err.h>
21
-#include <linux/gpio.h>
22
-#include <linux/gpio/consumer.h>
2317 #include <linux/interrupt.h>
2418 #include <linux/io.h>
19
+#include <linux/iopoll.h>
2520 #include <linux/kernel.h>
2621 #include <linux/module.h>
2722 #include <linux/of.h>
....@@ -36,14 +31,15 @@
3631 #include <asm/unaligned.h>
3732 
3833 struct sh_msiof_chipdata {
34
+	u32 bits_per_word_mask;
3935 	u16 tx_fifo_size;
4036 	u16 rx_fifo_size;
41
-	u16 master_flags;
37
+	u16 ctlr_flags;
4238 	u16 min_div_pow;
4339 };
4440 
4541 struct sh_msiof_spi_priv {
46
-	struct spi_master *master;
42
+	struct spi_controller *ctlr;
4743 	void __iomem *mapbase;
4844 	struct clk *clk;
4945 	struct platform_device *pdev;
....@@ -57,7 +53,6 @@
5753 	void *rx_dma_page;
5854 	dma_addr_t tx_dma_addr;
5955 	dma_addr_t rx_dma_addr;
60
-	unsigned short unused_ss;
6156 	bool native_cs_inited;
6257 	bool native_cs_high;
6358 	bool slave_aborted;
....@@ -65,138 +60,140 @@
6560 
6661 #define MAX_SS	3	/* Maximum number of native chip selects */
6762 
68
-#define TMDR1	0x00	/* Transmit Mode Register 1 */
69
-#define TMDR2	0x04	/* Transmit Mode Register 2 */
70
-#define TMDR3	0x08	/* Transmit Mode Register 3 */
71
-#define RMDR1	0x10	/* Receive Mode Register 1 */
72
-#define RMDR2	0x14	/* Receive Mode Register 2 */
73
-#define RMDR3	0x18	/* Receive Mode Register 3 */
74
-#define TSCR	0x20	/* Transmit Clock Select Register */
75
-#define RSCR	0x22	/* Receive Clock Select Register (SH, A1, APE6) */
76
-#define CTR	0x28	/* Control Register */
77
-#define FCTR	0x30	/* FIFO Control Register */
78
-#define STR	0x40	/* Status Register */
79
-#define IER	0x44	/* Interrupt Enable Register */
80
-#define TDR1	0x48	/* Transmit Control Data Register 1 (SH, A1) */
81
-#define TDR2	0x4c	/* Transmit Control Data Register 2 (SH, A1) */
82
-#define TFDR	0x50	/* Transmit FIFO Data Register */
83
-#define RDR1	0x58	/* Receive Control Data Register 1 (SH, A1) */
84
-#define RDR2	0x5c	/* Receive Control Data Register 2 (SH, A1) */
85
-#define RFDR	0x60	/* Receive FIFO Data Register */
63
+#define SITMDR1	0x00	/* Transmit Mode Register 1 */
64
+#define SITMDR2	0x04	/* Transmit Mode Register 2 */
65
+#define SITMDR3	0x08	/* Transmit Mode Register 3 */
66
+#define SIRMDR1	0x10	/* Receive Mode Register 1 */
67
+#define SIRMDR2	0x14	/* Receive Mode Register 2 */
68
+#define SIRMDR3	0x18	/* Receive Mode Register 3 */
69
+#define SITSCR	0x20	/* Transmit Clock Select Register */
70
+#define SIRSCR	0x22	/* Receive Clock Select Register (SH, A1, APE6) */
71
+#define SICTR	0x28	/* Control Register */
72
+#define SIFCTR	0x30	/* FIFO Control Register */
73
+#define SISTR	0x40	/* Status Register */
74
+#define SIIER	0x44	/* Interrupt Enable Register */
75
+#define SITDR1	0x48	/* Transmit Control Data Register 1 (SH, A1) */
76
+#define SITDR2	0x4c	/* Transmit Control Data Register 2 (SH, A1) */
77
+#define SITFDR	0x50	/* Transmit FIFO Data Register */
78
+#define SIRDR1	0x58	/* Receive Control Data Register 1 (SH, A1) */
79
+#define SIRDR2	0x5c	/* Receive Control Data Register 2 (SH, A1) */
80
+#define SIRFDR	0x60	/* Receive FIFO Data Register */
8681 
87
-/* TMDR1 and RMDR1 */
88
-#define MDR1_TRMD	 0x80000000 /* Transfer Mode (1 = Master mode) */
89
-#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
90
-#define MDR1_SYNCMD_SPI	 0x20000000 /*   Level mode/SPI */
91
-#define MDR1_SYNCMD_LR	 0x30000000 /*   L/R mode */
92
-#define MDR1_SYNCAC_SHIFT	 25 /* Sync Polarity (1 = Active-low) */
93
-#define MDR1_BITLSB_SHIFT	 24 /* MSB/LSB First (1 = LSB first) */
94
-#define MDR1_DTDL_SHIFT		 20 /* Data Pin Bit Delay for MSIOF_SYNC */
95
-#define MDR1_SYNCDL_SHIFT	 16 /* Frame Sync Signal Timing Delay */
96
-#define MDR1_FLD_MASK	 0x0000000c /* Frame Sync Signal Interval (0-3) */
97
-#define MDR1_FLD_SHIFT		  2
98
-#define MDR1_XXSTP	 0x00000001 /* Transmission/Reception Stop on FIFO */
99
-/* TMDR1 */
100
-#define TMDR1_PCON	 0x40000000 /* Transfer Signal Connection */
101
-#define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */
102
-#define TMDR1_SYNCCH_SHIFT	 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
82
+/* SITMDR1 and SIRMDR1 */
83
+#define SIMDR1_TRMD		BIT(31)		/* Transfer Mode (1 = Master mode) */
84
+#define SIMDR1_SYNCMD_MASK	GENMASK(29, 28)	/* SYNC Mode */
85
+#define SIMDR1_SYNCMD_SPI	(2 << 28)	/*   Level mode/SPI */
86
+#define SIMDR1_SYNCMD_LR	(3 << 28)	/*   L/R mode */
87
+#define SIMDR1_SYNCAC_SHIFT	25		/* Sync Polarity (1 = Active-low) */
88
+#define SIMDR1_BITLSB_SHIFT	24		/* MSB/LSB First (1 = LSB first) */
89
+#define SIMDR1_DTDL_SHIFT	20		/* Data Pin Bit Delay for MSIOF_SYNC */
90
+#define SIMDR1_SYNCDL_SHIFT	16		/* Frame Sync Signal Timing Delay */
91
+#define SIMDR1_FLD_MASK		GENMASK(3, 2)	/* Frame Sync Signal Interval (0-3) */
92
+#define SIMDR1_FLD_SHIFT	2
93
+#define SIMDR1_XXSTP		BIT(0)		/* Transmission/Reception Stop on FIFO */
94
+/* SITMDR1 */
95
+#define SITMDR1_PCON		BIT(30)		/* Transfer Signal Connection */
96
+#define SITMDR1_SYNCCH_MASK	GENMASK(27, 26)	/* Sync Signal Channel Select */
97
+#define SITMDR1_SYNCCH_SHIFT	26		/* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
10398 
104
-/* TMDR2 and RMDR2 */
105
-#define MDR2_BITLEN1(i)	(((i) - 1) << 24) /* Data Size (8-32 bits) */
106
-#define MDR2_WDLEN1(i)	(((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
107
-#define MDR2_GRPMASK1	0x00000001 /* Group Output Mask 1 (SH, A1) */
99
+/* SITMDR2 and SIRMDR2 */
100
+#define SIMDR2_BITLEN1(i)	(((i) - 1) << 24) /* Data Size (8-32 bits) */
101
+#define SIMDR2_WDLEN1(i)	(((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
102
+#define SIMDR2_GRPMASK1		BIT(0)		/* Group Output Mask 1 (SH, A1) */
108103 
109
-/* TSCR and RSCR */
110
-#define SCR_BRPS_MASK	    0x1f00 /* Prescaler Setting (1-32) */
111
-#define SCR_BRPS(i)	(((i) - 1) << 8)
112
-#define SCR_BRDV_MASK	    0x0007 /* Baud Rate Generator's Division Ratio */
113
-#define SCR_BRDV_DIV_2	    0x0000
114
-#define SCR_BRDV_DIV_4	    0x0001
115
-#define SCR_BRDV_DIV_8	    0x0002
116
-#define SCR_BRDV_DIV_16	    0x0003
117
-#define SCR_BRDV_DIV_32	    0x0004
118
-#define SCR_BRDV_DIV_1	    0x0007
104
+/* SITSCR and SIRSCR */
105
+#define SISCR_BRPS_MASK		GENMASK(12, 8)	/* Prescaler Setting (1-32) */
106
+#define SISCR_BRPS(i)		(((i) - 1) << 8)
107
+#define SISCR_BRDV_MASK		GENMASK(2, 0)	/* Baud Rate Generator's Division Ratio */
108
+#define SISCR_BRDV_DIV_2	0
109
+#define SISCR_BRDV_DIV_4	1
110
+#define SISCR_BRDV_DIV_8	2
111
+#define SISCR_BRDV_DIV_16	3
112
+#define SISCR_BRDV_DIV_32	4
113
+#define SISCR_BRDV_DIV_1	7
119114 
120
-/* CTR */
121
-#define CTR_TSCKIZ_MASK	0xc0000000 /* Transmit Clock I/O Polarity Select */
122
-#define CTR_TSCKIZ_SCK	0x80000000 /*   Disable SCK when TX disabled */
123
-#define CTR_TSCKIZ_POL_SHIFT	30 /*   Transmit Clock Polarity */
124
-#define CTR_RSCKIZ_MASK	0x30000000 /* Receive Clock Polarity Select */
125
-#define CTR_RSCKIZ_SCK	0x20000000 /*   Must match CTR_TSCKIZ_SCK */
126
-#define CTR_RSCKIZ_POL_SHIFT	28 /*   Receive Clock Polarity */
127
-#define CTR_TEDG_SHIFT		27 /* Transmit Timing (1 = falling edge) */
128
-#define CTR_REDG_SHIFT		26 /* Receive Timing (1 = falling edge) */
129
-#define CTR_TXDIZ_MASK	0x00c00000 /* Pin Output When TX is Disabled */
130
-#define CTR_TXDIZ_LOW	0x00000000 /*   0 */
131
-#define CTR_TXDIZ_HIGH	0x00400000 /*   1 */
132
-#define CTR_TXDIZ_HIZ	0x00800000 /*   High-impedance */
133
-#define CTR_TSCKE	0x00008000 /* Transmit Serial Clock Output Enable */
134
-#define CTR_TFSE	0x00004000 /* Transmit Frame Sync Signal Output Enable */
135
-#define CTR_TXE		0x00000200 /* Transmit Enable */
136
-#define CTR_RXE		0x00000100 /* Receive Enable */
115
+/* SICTR */
116
+#define SICTR_TSCKIZ_MASK	GENMASK(31, 30)	/* Transmit Clock I/O Polarity Select */
117
+#define SICTR_TSCKIZ_SCK	BIT(31)		/*   Disable SCK when TX disabled */
118
+#define SICTR_TSCKIZ_POL_SHIFT	30		/*   Transmit Clock Polarity */
119
+#define SICTR_RSCKIZ_MASK	GENMASK(29, 28) /* Receive Clock Polarity Select */
120
+#define SICTR_RSCKIZ_SCK	BIT(29)		/*   Must match CTR_TSCKIZ_SCK */
121
+#define SICTR_RSCKIZ_POL_SHIFT	28		/*   Receive Clock Polarity */
122
+#define SICTR_TEDG_SHIFT	27		/* Transmit Timing (1 = falling edge) */
123
+#define SICTR_REDG_SHIFT	26		/* Receive Timing (1 = falling edge) */
124
+#define SICTR_TXDIZ_MASK	GENMASK(23, 22)	/* Pin Output When TX is Disabled */
125
+#define SICTR_TXDIZ_LOW		(0 << 22)	/*   0 */
126
+#define SICTR_TXDIZ_HIGH	(1 << 22)	/*   1 */
127
+#define SICTR_TXDIZ_HIZ		(2 << 22)	/*   High-impedance */
128
+#define SICTR_TSCKE		BIT(15)		/* Transmit Serial Clock Output Enable */
129
+#define SICTR_TFSE		BIT(14)		/* Transmit Frame Sync Signal Output Enable */
130
+#define SICTR_TXE		BIT(9)		/* Transmit Enable */
131
+#define SICTR_RXE		BIT(8)		/* Receive Enable */
132
+#define SICTR_TXRST		BIT(1)		/* Transmit Reset */
133
+#define SICTR_RXRST		BIT(0)		/* Receive Reset */
137134 
138
-/* FCTR */
139
-#define FCTR_TFWM_MASK	0xe0000000 /* Transmit FIFO Watermark */
140
-#define FCTR_TFWM_64	0x00000000 /*  Transfer Request when 64 empty stages */
141
-#define FCTR_TFWM_32	0x20000000 /*  Transfer Request when 32 empty stages */
142
-#define FCTR_TFWM_24	0x40000000 /*  Transfer Request when 24 empty stages */
143
-#define FCTR_TFWM_16	0x60000000 /*  Transfer Request when 16 empty stages */
144
-#define FCTR_TFWM_12	0x80000000 /*  Transfer Request when 12 empty stages */
145
-#define FCTR_TFWM_8	0xa0000000 /*  Transfer Request when 8 empty stages */
146
-#define FCTR_TFWM_4	0xc0000000 /*  Transfer Request when 4 empty stages */
147
-#define FCTR_TFWM_1	0xe0000000 /*  Transfer Request when 1 empty stage */
148
-#define FCTR_TFUA_MASK	0x07f00000 /* Transmit FIFO Usable Area */
149
-#define FCTR_TFUA_SHIFT		20
150
-#define FCTR_TFUA(i)	((i) << FCTR_TFUA_SHIFT)
151
-#define FCTR_RFWM_MASK	0x0000e000 /* Receive FIFO Watermark */
152
-#define FCTR_RFWM_1	0x00000000 /*  Transfer Request when 1 valid stages */
153
-#define FCTR_RFWM_4	0x00002000 /*  Transfer Request when 4 valid stages */
154
-#define FCTR_RFWM_8	0x00004000 /*  Transfer Request when 8 valid stages */
155
-#define FCTR_RFWM_16	0x00006000 /*  Transfer Request when 16 valid stages */
156
-#define FCTR_RFWM_32	0x00008000 /*  Transfer Request when 32 valid stages */
157
-#define FCTR_RFWM_64	0x0000a000 /*  Transfer Request when 64 valid stages */
158
-#define FCTR_RFWM_128	0x0000c000 /*  Transfer Request when 128 valid stages */
159
-#define FCTR_RFWM_256	0x0000e000 /*  Transfer Request when 256 valid stages */
160
-#define FCTR_RFUA_MASK	0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
161
-#define FCTR_RFUA_SHIFT		 4
162
-#define FCTR_RFUA(i)	((i) << FCTR_RFUA_SHIFT)
135
+/* SIFCTR */
136
+#define SIFCTR_TFWM_MASK	GENMASK(31, 29)	/* Transmit FIFO Watermark */
137
+#define SIFCTR_TFWM_64		(0 << 29)	/*  Transfer Request when 64 empty stages */
138
+#define SIFCTR_TFWM_32		(1 << 29)	/*  Transfer Request when 32 empty stages */
139
+#define SIFCTR_TFWM_24		(2 << 29)	/*  Transfer Request when 24 empty stages */
140
+#define SIFCTR_TFWM_16		(3 << 29)	/*  Transfer Request when 16 empty stages */
141
+#define SIFCTR_TFWM_12		(4 << 29)	/*  Transfer Request when 12 empty stages */
142
+#define SIFCTR_TFWM_8		(5 << 29)	/*  Transfer Request when 8 empty stages */
143
+#define SIFCTR_TFWM_4		(6 << 29)	/*  Transfer Request when 4 empty stages */
144
+#define SIFCTR_TFWM_1		(7 << 29)	/*  Transfer Request when 1 empty stage */
145
+#define SIFCTR_TFUA_MASK	GENMASK(26, 20) /* Transmit FIFO Usable Area */
146
+#define SIFCTR_TFUA_SHIFT	20
147
+#define SIFCTR_TFUA(i)		((i) << SIFCTR_TFUA_SHIFT)
148
+#define SIFCTR_RFWM_MASK	GENMASK(15, 13)	/* Receive FIFO Watermark */
149
+#define SIFCTR_RFWM_1		(0 << 13)	/*  Transfer Request when 1 valid stages */
150
+#define SIFCTR_RFWM_4		(1 << 13)	/*  Transfer Request when 4 valid stages */
151
+#define SIFCTR_RFWM_8		(2 << 13)	/*  Transfer Request when 8 valid stages */
152
+#define SIFCTR_RFWM_16		(3 << 13)	/*  Transfer Request when 16 valid stages */
153
+#define SIFCTR_RFWM_32		(4 << 13)	/*  Transfer Request when 32 valid stages */
154
+#define SIFCTR_RFWM_64		(5 << 13)	/*  Transfer Request when 64 valid stages */
155
+#define SIFCTR_RFWM_128		(6 << 13)	/*  Transfer Request when 128 valid stages */
156
+#define SIFCTR_RFWM_256		(7 << 13)	/*  Transfer Request when 256 valid stages */
157
+#define SIFCTR_RFUA_MASK	GENMASK(12, 4)	/* Receive FIFO Usable Area (0x40 = full) */
158
+#define SIFCTR_RFUA_SHIFT	4
159
+#define SIFCTR_RFUA(i)		((i) << SIFCTR_RFUA_SHIFT)
163160 
164
-/* STR */
165
-#define STR_TFEMP	0x20000000 /* Transmit FIFO Empty */
166
-#define STR_TDREQ	0x10000000 /* Transmit Data Transfer Request */
167
-#define STR_TEOF	0x00800000 /* Frame Transmission End */
168
-#define STR_TFSERR	0x00200000 /* Transmit Frame Synchronization Error */
169
-#define STR_TFOVF	0x00100000 /* Transmit FIFO Overflow */
170
-#define STR_TFUDF	0x00080000 /* Transmit FIFO Underflow */
171
-#define STR_RFFUL	0x00002000 /* Receive FIFO Full */
172
-#define STR_RDREQ	0x00001000 /* Receive Data Transfer Request */
173
-#define STR_REOF	0x00000080 /* Frame Reception End */
174
-#define STR_RFSERR	0x00000020 /* Receive Frame Synchronization Error */
175
-#define STR_RFUDF	0x00000010 /* Receive FIFO Underflow */
176
-#define STR_RFOVF	0x00000008 /* Receive FIFO Overflow */
161
+/* SISTR */
162
+#define SISTR_TFEMP		BIT(29) /* Transmit FIFO Empty */
163
+#define SISTR_TDREQ		BIT(28) /* Transmit Data Transfer Request */
164
+#define SISTR_TEOF		BIT(23) /* Frame Transmission End */
165
+#define SISTR_TFSERR		BIT(21) /* Transmit Frame Synchronization Error */
166
+#define SISTR_TFOVF		BIT(20) /* Transmit FIFO Overflow */
167
+#define SISTR_TFUDF		BIT(19) /* Transmit FIFO Underflow */
168
+#define SISTR_RFFUL		BIT(13) /* Receive FIFO Full */
169
+#define SISTR_RDREQ		BIT(12) /* Receive Data Transfer Request */
170
+#define SISTR_REOF		BIT(7)  /* Frame Reception End */
171
+#define SISTR_RFSERR		BIT(5)  /* Receive Frame Synchronization Error */
172
+#define SISTR_RFUDF		BIT(4)  /* Receive FIFO Underflow */
173
+#define SISTR_RFOVF		BIT(3)  /* Receive FIFO Overflow */
177174 
178
-/* IER */
179
-#define IER_TDMAE	0x80000000 /* Transmit Data DMA Transfer Req. Enable */
180
-#define IER_TFEMPE	0x20000000 /* Transmit FIFO Empty Enable */
181
-#define IER_TDREQE	0x10000000 /* Transmit Data Transfer Request Enable */
182
-#define IER_TEOFE	0x00800000 /* Frame Transmission End Enable */
183
-#define IER_TFSERRE	0x00200000 /* Transmit Frame Sync Error Enable */
184
-#define IER_TFOVFE	0x00100000 /* Transmit FIFO Overflow Enable */
185
-#define IER_TFUDFE	0x00080000 /* Transmit FIFO Underflow Enable */
186
-#define IER_RDMAE	0x00008000 /* Receive Data DMA Transfer Req. Enable */
187
-#define IER_RFFULE	0x00002000 /* Receive FIFO Full Enable */
188
-#define IER_RDREQE	0x00001000 /* Receive Data Transfer Request Enable */
189
-#define IER_REOFE	0x00000080 /* Frame Reception End Enable */
190
-#define IER_RFSERRE	0x00000020 /* Receive Frame Sync Error Enable */
191
-#define IER_RFUDFE	0x00000010 /* Receive FIFO Underflow Enable */
192
-#define IER_RFOVFE	0x00000008 /* Receive FIFO Overflow Enable */
175
+/* SIIER */
176
+#define SIIER_TDMAE		BIT(31) /* Transmit Data DMA Transfer Req. Enable */
177
+#define SIIER_TFEMPE		BIT(29) /* Transmit FIFO Empty Enable */
178
+#define SIIER_TDREQE		BIT(28) /* Transmit Data Transfer Request Enable */
179
+#define SIIER_TEOFE		BIT(23) /* Frame Transmission End Enable */
180
+#define SIIER_TFSERRE		BIT(21) /* Transmit Frame Sync Error Enable */
181
+#define SIIER_TFOVFE		BIT(20) /* Transmit FIFO Overflow Enable */
182
+#define SIIER_TFUDFE		BIT(19) /* Transmit FIFO Underflow Enable */
183
+#define SIIER_RDMAE		BIT(15) /* Receive Data DMA Transfer Req. Enable */
184
+#define SIIER_RFFULE		BIT(13) /* Receive FIFO Full Enable */
185
+#define SIIER_RDREQE		BIT(12) /* Receive Data Transfer Request Enable */
186
+#define SIIER_REOFE		BIT(7)  /* Frame Reception End Enable */
187
+#define SIIER_RFSERRE		BIT(5)  /* Receive Frame Sync Error Enable */
188
+#define SIIER_RFUDFE		BIT(4)  /* Receive FIFO Underflow Enable */
189
+#define SIIER_RFOVFE		BIT(3)  /* Receive FIFO Overflow Enable */
193190 
194191 
195192 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
196193 {
197194 	switch (reg_offs) {
198
-	case TSCR:
199
-	case RSCR:
195
+	case SITSCR:
196
+	case SIRSCR:
200197 		return ioread16(p->mapbase + reg_offs);
201198 	default:
202199 		return ioread32(p->mapbase + reg_offs);
....@@ -207,8 +204,8 @@
207204 			   u32 value)
208205 {
209206 	switch (reg_offs) {
210
-	case TSCR:
211
-	case RSCR:
207
+	case SITSCR:
208
+	case SIRSCR:
212209 		iowrite16(value, p->mapbase + reg_offs);
213210 		break;
214211 	default:
....@@ -222,21 +219,14 @@
222219 {
223220 	u32 mask = clr | set;
224221 	u32 data;
225
-	int k;
226222 
227
-	data = sh_msiof_read(p, CTR);
223
+	data = sh_msiof_read(p, SICTR);
228224 	data &= ~clr;
229225 	data |= set;
230
-	sh_msiof_write(p, CTR, data);
226
+	sh_msiof_write(p, SICTR, data);
231227 
232
-	for (k = 100; k > 0; k--) {
233
-		if ((sh_msiof_read(p, CTR) & mask) == set)
234
-			break;
235
-
236
-		udelay(10);
237
-	}
238
-
239
-	return k > 0 ? 0 : -ETIMEDOUT;
228
+	return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
229
+					 (data & mask) == set, 1, 100);
240230 }
241231 
242232 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
....@@ -244,15 +234,28 @@
244234 	struct sh_msiof_spi_priv *p = data;
245235 
246236 	/* just disable the interrupt and wake up */
247
-	sh_msiof_write(p, IER, 0);
237
+	sh_msiof_write(p, SIIER, 0);
248238 	complete(&p->done);
249239 
250240 	return IRQ_HANDLED;
251241 }
252242 
243
+static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
244
+{
245
+	u32 mask = SICTR_TXRST | SICTR_RXRST;
246
+	u32 data;
247
+
248
+	data = sh_msiof_read(p, SICTR);
249
+	data |= mask;
250
+	sh_msiof_write(p, SICTR, data);
251
+
252
+	readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,
253
+				  100);
254
+}
255
+
253256 static const u32 sh_msiof_spi_div_array[] = {
254
-	SCR_BRDV_DIV_1, SCR_BRDV_DIV_2,	 SCR_BRDV_DIV_4,
255
-	SCR_BRDV_DIV_8,	SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
257
+	SISCR_BRDV_DIV_1, SISCR_BRDV_DIV_2, SISCR_BRDV_DIV_4,
258
+	SISCR_BRDV_DIV_8, SISCR_BRDV_DIV_16, SISCR_BRDV_DIV_32,
256259 };
257260 
258261 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
....@@ -270,7 +273,7 @@
270273 
271274 	div = DIV_ROUND_UP(parent_rate, spi_hz);
272275 	if (div <= 1024) {
273
-		/* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
276
+		/* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
274277 		if (!div_pow && div <= 32 && div > 2)
275278 			div_pow = 1;
276279 
....@@ -289,10 +292,10 @@
289292 		brps = 32;
290293 	}
291294 
292
-	scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
293
-	sh_msiof_write(p, TSCR, scr);
294
-	if (!(p->master->flags & SPI_MASTER_MUST_TX))
295
-		sh_msiof_write(p, RSCR, scr);
295
+	scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);
296
+	sh_msiof_write(p, SITSCR, scr);
297
+	if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
298
+		sh_msiof_write(p, SIRSCR, scr);
296299 }
297300 
298301 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
....@@ -331,8 +334,8 @@
331334 		return 0;
332335 	}
333336 
334
-	val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
335
-	val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
337
+	val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT;
338
+	val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT;
336339 
337340 	return val;
338341 }
....@@ -351,54 +354,54 @@
351354 	 *    1    0         11     11    0    0
352355 	 *    1    1         11     11    1    1
353356 	 */
354
-	tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
355
-	tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
356
-	tmp |= lsb_first << MDR1_BITLSB_SHIFT;
357
+	tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP;
358
+	tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
359
+	tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
357360 	tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
358
-	if (spi_controller_is_slave(p->master)) {
359
-		sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
361
+	if (spi_controller_is_slave(p->ctlr)) {
362
+		sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
360363 	} else {
361
-		sh_msiof_write(p, TMDR1,
362
-			       tmp | MDR1_TRMD | TMDR1_PCON |
363
-			       (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
364
+		sh_msiof_write(p, SITMDR1,
365
+			       tmp | SIMDR1_TRMD | SITMDR1_PCON |
366
+			       (ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT);
364367 	}
365
-	if (p->master->flags & SPI_MASTER_MUST_TX) {
368
+	if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
366369 		/* These bits are reserved if RX needs TX */
367370 		tmp &= ~0x0000ffff;
368371 	}
369
-	sh_msiof_write(p, RMDR1, tmp);
372
+	sh_msiof_write(p, SIRMDR1, tmp);
370373 
371374 	tmp = 0;
372
-	tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
373
-	tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
375
+	tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT;
376
+	tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT;
374377 
375378 	edge = cpol ^ !cpha;
376379 
377
-	tmp |= edge << CTR_TEDG_SHIFT;
378
-	tmp |= edge << CTR_REDG_SHIFT;
379
-	tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
380
-	sh_msiof_write(p, CTR, tmp);
380
+	tmp |= edge << SICTR_TEDG_SHIFT;
381
+	tmp |= edge << SICTR_REDG_SHIFT;
382
+	tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW;
383
+	sh_msiof_write(p, SICTR, tmp);
381384 }
382385 
383386 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
384387 				       const void *tx_buf, void *rx_buf,
385388 				       u32 bits, u32 words)
386389 {
387
-	u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
390
+	u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words);
388391 
389
-	if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
390
-		sh_msiof_write(p, TMDR2, dr2);
392
+	if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
393
+		sh_msiof_write(p, SITMDR2, dr2);
391394 	else
392
-		sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
395
+		sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1);
393396 
394397 	if (rx_buf)
395
-		sh_msiof_write(p, RMDR2, dr2);
398
+		sh_msiof_write(p, SIRMDR2, dr2);
396399 }
397400 
398401 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
399402 {
400
-	sh_msiof_write(p, STR,
401
-		       sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
403
+	sh_msiof_write(p, SISTR,
404
+		       sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ));
402405 }
403406 
404407 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
....@@ -408,7 +411,7 @@
408411 	int k;
409412 
410413 	for (k = 0; k < words; k++)
411
-		sh_msiof_write(p, TFDR, buf_8[k] << fs);
414
+		sh_msiof_write(p, SITFDR, buf_8[k] << fs);
412415 }
413416 
414417 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
....@@ -418,7 +421,7 @@
418421 	int k;
419422 
420423 	for (k = 0; k < words; k++)
421
-		sh_msiof_write(p, TFDR, buf_16[k] << fs);
424
+		sh_msiof_write(p, SITFDR, buf_16[k] << fs);
422425 }
423426 
424427 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
....@@ -428,7 +431,7 @@
428431 	int k;
429432 
430433 	for (k = 0; k < words; k++)
431
-		sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
434
+		sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);
432435 }
433436 
434437 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
....@@ -438,7 +441,7 @@
438441 	int k;
439442 
440443 	for (k = 0; k < words; k++)
441
-		sh_msiof_write(p, TFDR, buf_32[k] << fs);
444
+		sh_msiof_write(p, SITFDR, buf_32[k] << fs);
442445 }
443446 
444447 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
....@@ -448,7 +451,7 @@
448451 	int k;
449452 
450453 	for (k = 0; k < words; k++)
451
-		sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
454
+		sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);
452455 }
453456 
454457 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
....@@ -458,7 +461,7 @@
458461 	int k;
459462 
460463 	for (k = 0; k < words; k++)
461
-		sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
464
+		sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));
462465 }
463466 
464467 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
....@@ -468,7 +471,7 @@
468471 	int k;
469472 
470473 	for (k = 0; k < words; k++)
471
-		sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
474
+		sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));
472475 }
473476 
474477 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
....@@ -478,7 +481,7 @@
478481 	int k;
479482 
480483 	for (k = 0; k < words; k++)
481
-		buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
484
+		buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;
482485 }
483486 
484487 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
....@@ -488,7 +491,7 @@
488491 	int k;
489492 
490493 	for (k = 0; k < words; k++)
491
-		buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
494
+		buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;
492495 }
493496 
494497 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
....@@ -498,7 +501,7 @@
498501 	int k;
499502 
500503 	for (k = 0; k < words; k++)
501
-		put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
504
+		put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);
502505 }
503506 
504507 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
....@@ -508,7 +511,7 @@
508511 	int k;
509512 
510513 	for (k = 0; k < words; k++)
511
-		buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
514
+		buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;
512515 }
513516 
514517 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
....@@ -518,7 +521,7 @@
518521 	int k;
519522 
520523 	for (k = 0; k < words; k++)
521
-		put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
524
+		put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);
522525 }
523526 
524527 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
....@@ -528,7 +531,7 @@
528531 	int k;
529532 
530533 	for (k = 0; k < words; k++)
531
-		buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
534
+		buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);
532535 }
533536 
534537 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
....@@ -538,29 +541,16 @@
538541 	int k;
539542 
540543 	for (k = 0; k < words; k++)
541
-		put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
544
+		put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);
542545 }
543546 
544547 static int sh_msiof_spi_setup(struct spi_device *spi)
545548 {
546
-	struct device_node	*np = spi->master->dev.of_node;
547
-	struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
549
+	struct sh_msiof_spi_priv *p =
550
+		spi_controller_get_devdata(spi->controller);
548551 	u32 clr, set, tmp;
549552 
550
-	if (!np) {
551
-		/*
552
-		 * Use spi->controller_data for CS (same strategy as spi_gpio),
553
-		 * if any. otherwise let HW control CS
554
-		 */
555
-		spi->cs_gpio = (uintptr_t)spi->controller_data;
556
-	}
557
-
558
-	if (gpio_is_valid(spi->cs_gpio)) {
559
-		gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
560
-		return 0;
561
-	}
562
-
563
-	if (spi_controller_is_slave(p->master))
553
+	if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr))
564554 		return 0;
565555 
566556 	if (p->native_cs_inited &&
....@@ -568,33 +558,33 @@
568558 		return 0;
569559 
570560 	/* Configure native chip select mode/polarity early */
571
-	clr = MDR1_SYNCMD_MASK;
572
-	set = MDR1_SYNCMD_SPI;
561
+	clr = SIMDR1_SYNCMD_MASK;
562
+	set = SIMDR1_SYNCMD_SPI;
573563 	if (spi->mode & SPI_CS_HIGH)
574
-		clr |= BIT(MDR1_SYNCAC_SHIFT);
564
+		clr |= BIT(SIMDR1_SYNCAC_SHIFT);
575565 	else
576
-		set |= BIT(MDR1_SYNCAC_SHIFT);
566
+		set |= BIT(SIMDR1_SYNCAC_SHIFT);
577567 	pm_runtime_get_sync(&p->pdev->dev);
578
-	tmp = sh_msiof_read(p, TMDR1) & ~clr;
579
-	sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
580
-	tmp = sh_msiof_read(p, RMDR1) & ~clr;
581
-	sh_msiof_write(p, RMDR1, tmp | set);
568
+	tmp = sh_msiof_read(p, SITMDR1) & ~clr;
569
+	sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);
570
+	tmp = sh_msiof_read(p, SIRMDR1) & ~clr;
571
+	sh_msiof_write(p, SIRMDR1, tmp | set);
582572 	pm_runtime_put(&p->pdev->dev);
583573 	p->native_cs_high = spi->mode & SPI_CS_HIGH;
584574 	p->native_cs_inited = true;
585575 	return 0;
586576 }
587577 
588
-static int sh_msiof_prepare_message(struct spi_master *master,
578
+static int sh_msiof_prepare_message(struct spi_controller *ctlr,
589579 				    struct spi_message *msg)
590580 {
591
-	struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
581
+	struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
592582 	const struct spi_device *spi = msg->spi;
593583 	u32 ss, cs_high;
594584 
595585 	/* Configure pins before asserting CS */
596
-	if (gpio_is_valid(spi->cs_gpio)) {
597
-		ss = p->unused_ss;
586
+	if (spi->cs_gpiod) {
587
+		ss = ctlr->unused_native_cs;
598588 		cs_high = p->native_cs_high;
599589 	} else {
600590 		ss = spi->chip_select;
....@@ -609,45 +599,45 @@
609599 
610600 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
611601 {
612
-	bool slave = spi_controller_is_slave(p->master);
602
+	bool slave = spi_controller_is_slave(p->ctlr);
613603 	int ret = 0;
614604 
615605 	/* setup clock and rx/tx signals */
616606 	if (!slave)
617
-		ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
607
+		ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE);
618608 	if (rx_buf && !ret)
619
-		ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
609
+		ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE);
620610 	if (!ret)
621
-		ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
611
+		ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE);
622612 
623613 	/* start by setting frame bit */
624614 	if (!ret && !slave)
625
-		ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
615
+		ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE);
626616 
627617 	return ret;
628618 }
629619 
630620 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
631621 {
632
-	bool slave = spi_controller_is_slave(p->master);
622
+	bool slave = spi_controller_is_slave(p->ctlr);
633623 	int ret = 0;
634624 
635625 	/* shut down frame, rx/tx and clock signals */
636626 	if (!slave)
637
-		ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
627
+		ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0);
638628 	if (!ret)
639
-		ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
629
+		ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0);
640630 	if (rx_buf && !ret)
641
-		ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
631
+		ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0);
642632 	if (!ret && !slave)
643
-		ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
633
+		ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0);
644634 
645635 	return ret;
646636 }
647637 
648
-static int sh_msiof_slave_abort(struct spi_master *master)
638
+static int sh_msiof_slave_abort(struct spi_controller *ctlr)
649639 {
650
-	struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
640
+	struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
651641 
652642 	p->slave_aborted = true;
653643 	complete(&p->done);
....@@ -658,7 +648,7 @@
658648 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
659649 					struct completion *x)
660650 {
661
-	if (spi_controller_is_slave(p->master)) {
651
+	if (spi_controller_is_slave(p->ctlr)) {
662652 		if (wait_for_completion_interruptible(x) ||
663653 		    p->slave_aborted) {
664654 			dev_dbg(&p->pdev->dev, "interrupted\n");
....@@ -695,11 +685,11 @@
695685 	fifo_shift = 32 - bits;
696686 
697687 	/* default FIFO watermarks for PIO */
698
-	sh_msiof_write(p, FCTR, 0);
688
+	sh_msiof_write(p, SIFCTR, 0);
699689 
700690 	/* setup msiof transfer mode registers */
701691 	sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
702
-	sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
692
+	sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE);
703693 
704694 	/* write tx fifo */
705695 	if (tx_buf)
....@@ -738,7 +728,7 @@
738728 	sh_msiof_reset_str(p);
739729 	sh_msiof_spi_stop(p, rx_buf);
740730 stop_ier:
741
-	sh_msiof_write(p, IER, 0);
731
+	sh_msiof_write(p, SIIER, 0);
742732 	return ret;
743733 }
744734 
....@@ -757,8 +747,8 @@
757747 
758748 	/* First prepare and submit the DMA request(s), as this may fail */
759749 	if (rx) {
760
-		ier_bits |= IER_RDREQE | IER_RDMAE;
761
-		desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
750
+		ier_bits |= SIIER_RDREQE | SIIER_RDMAE;
751
+		desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
762752 					p->rx_dma_addr, len, DMA_DEV_TO_MEM,
763753 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
764754 		if (!desc_rx)
....@@ -772,10 +762,10 @@
772762 	}
773763 
774764 	if (tx) {
775
-		ier_bits |= IER_TDREQE | IER_TDMAE;
776
-		dma_sync_single_for_device(p->master->dma_tx->device->dev,
765
+		ier_bits |= SIIER_TDREQE | SIIER_TDMAE;
766
+		dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
777767 					   p->tx_dma_addr, len, DMA_TO_DEVICE);
778
-		desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
768
+		desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
779769 					p->tx_dma_addr, len, DMA_MEM_TO_DEV,
780770 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
781771 		if (!desc_tx) {
....@@ -793,12 +783,12 @@
793783 	}
794784 
795785 	/* 1 stage FIFO watermarks for DMA */
796
-	sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
786
+	sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1);
797787 
798788 	/* setup msiof transfer mode registers (32-bit words) */
799789 	sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
800790 
801
-	sh_msiof_write(p, IER, ier_bits);
791
+	sh_msiof_write(p, SIIER, ier_bits);
802792 
803793 	reinit_completion(&p->done);
804794 	if (tx)
....@@ -807,9 +797,9 @@
807797 
808798 	/* Now start DMA */
809799 	if (rx)
810
-		dma_async_issue_pending(p->master->dma_rx);
800
+		dma_async_issue_pending(p->ctlr->dma_rx);
811801 	if (tx)
812
-		dma_async_issue_pending(p->master->dma_tx);
802
+		dma_async_issue_pending(p->ctlr->dma_tx);
813803 
814804 	ret = sh_msiof_spi_start(p, rx);
815805 	if (ret) {
....@@ -830,10 +820,10 @@
830820 		if (ret)
831821 			goto stop_reset;
832822 
833
-		sh_msiof_write(p, IER, 0);
823
+		sh_msiof_write(p, SIIER, 0);
834824 	} else {
835825 		/* wait for tx fifo to be emptied */
836
-		sh_msiof_write(p, IER, IER_TEOFE);
826
+		sh_msiof_write(p, SIIER, SIIER_TEOFE);
837827 		ret = sh_msiof_wait_for_completion(p, &p->done);
838828 		if (ret)
839829 			goto stop_reset;
....@@ -849,9 +839,8 @@
849839 	}
850840 
851841 	if (rx)
852
-		dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
853
-					p->rx_dma_addr, len,
854
-					DMA_FROM_DEVICE);
842
+		dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
843
+					p->rx_dma_addr, len, DMA_FROM_DEVICE);
855844 
856845 	return 0;
857846 
....@@ -860,11 +849,11 @@
860849 	sh_msiof_spi_stop(p, rx);
861850 stop_dma:
862851 	if (tx)
863
-		dmaengine_terminate_all(p->master->dma_tx);
852
+		dmaengine_terminate_all(p->ctlr->dma_tx);
864853 no_dma_tx:
865854 	if (rx)
866
-		dmaengine_terminate_all(p->master->dma_rx);
867
-	sh_msiof_write(p, IER, 0);
855
+		dmaengine_terminate_all(p->ctlr->dma_rx);
856
+	sh_msiof_write(p, SIIER, 0);
868857 	return ret;
869858 }
870859 
....@@ -911,11 +900,11 @@
911900 	memcpy(dst, src, words * 4);
912901 }
913902 
914
-static int sh_msiof_transfer_one(struct spi_master *master,
903
+static int sh_msiof_transfer_one(struct spi_controller *ctlr,
915904 				 struct spi_device *spi,
916905 				 struct spi_transfer *t)
917906 {
918
-	struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
907
+	struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
919908 	void (*copy32)(u32 *, const u32 *, unsigned int);
920909 	void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
921910 	void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
....@@ -929,11 +918,14 @@
929918 	bool swab;
930919 	int ret;
931920 
921
+	/* reset registers */
922
+	sh_msiof_spi_reset_regs(p);
923
+
932924 	/* setup clocks (clock already enabled in chipselect()) */
933
-	if (!spi_controller_is_slave(p->master))
925
+	if (!spi_controller_is_slave(p->ctlr))
934926 		sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
935927 
936
-	while (master->dma_tx && len > 15) {
928
+	while (ctlr->dma_tx && len > 15) {
937929 		/*
938930 		 *  DMA supports 32-bit words only, hence pack 8-bit and 16-bit
939931 		 *  words, with byte resp. word swapping.
....@@ -941,17 +933,13 @@
941933 		unsigned int l = 0;
942934 
943935 		if (tx_buf)
944
-			l = min(len, p->tx_fifo_size * 4);
936
+			l = min(round_down(len, 4), p->tx_fifo_size * 4);
945937 		if (rx_buf)
946
-			l = min(len, p->rx_fifo_size * 4);
938
+			l = min(round_down(len, 4), p->rx_fifo_size * 4);
947939 
948940 		if (bits <= 8) {
949
-			if (l & 3)
950
-				break;
951941 			copy32 = copy_bswap32;
952942 		} else if (bits <= 16) {
953
-			if (l & 3)
954
-				break;
955943 			copy32 = copy_wswap32;
956944 		} else {
957945 			copy32 = copy_plain32;
....@@ -981,7 +969,7 @@
981969 			return 0;
982970 	}
983971 
984
-	if (bits <= 8 && len > 15 && !(len & 3)) {
972
+	if (bits <= 8 && len > 15) {
985973 		bits = 32;
986974 		swab = true;
987975 	} else {
....@@ -1042,29 +1030,42 @@
10421030 		if (rx_buf)
10431031 			rx_buf += n * bytes_per_word;
10441032 		words -= n;
1033
+
1034
+		if (words == 0 && (len % bytes_per_word)) {
1035
+			words = len % bytes_per_word;
1036
+			bits = t->bits_per_word;
1037
+			bytes_per_word = 1;
1038
+			tx_fifo = sh_msiof_spi_write_fifo_8;
1039
+			rx_fifo = sh_msiof_spi_read_fifo_8;
1040
+		}
10451041 	}
10461042 
10471043 	return 0;
10481044 }
10491045 
10501046 static const struct sh_msiof_chipdata sh_data = {
1047
+	.bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
10511048 	.tx_fifo_size = 64,
10521049 	.rx_fifo_size = 64,
1053
-	.master_flags = 0,
1050
+	.ctlr_flags = 0,
10541051 	.min_div_pow = 0,
10551052 };
10561053 
10571054 static const struct sh_msiof_chipdata rcar_gen2_data = {
1055
+	.bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1056
+			      SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
10581057 	.tx_fifo_size = 64,
10591058 	.rx_fifo_size = 64,
1060
-	.master_flags = SPI_MASTER_MUST_TX,
1059
+	.ctlr_flags = SPI_CONTROLLER_MUST_TX,
10611060 	.min_div_pow = 0,
10621061 };
10631062 
10641063 static const struct sh_msiof_chipdata rcar_gen3_data = {
1064
+	.bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1065
+			      SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
10651066 	.tx_fifo_size = 64,
10661067 	.rx_fifo_size = 64,
1067
-	.master_flags = SPI_MASTER_MUST_TX,
1068
+	.ctlr_flags = SPI_CONTROLLER_MUST_TX,
10681069 	.min_div_pow = 1,
10691070 };
10701071 
....@@ -1120,45 +1121,6 @@
11201121 }
11211122 #endif
11221123 
1123
-static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1124
-{
1125
-	struct device *dev = &p->pdev->dev;
1126
-	unsigned int used_ss_mask = 0;
1127
-	unsigned int cs_gpios = 0;
1128
-	unsigned int num_cs, i;
1129
-	int ret;
1130
-
1131
-	ret = gpiod_count(dev, "cs");
1132
-	if (ret <= 0)
1133
-		return 0;
1134
-
1135
-	num_cs = max_t(unsigned int, ret, p->master->num_chipselect);
1136
-	for (i = 0; i < num_cs; i++) {
1137
-		struct gpio_desc *gpiod;
1138
-
1139
-		gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1140
-		if (!IS_ERR(gpiod)) {
1141
-			cs_gpios++;
1142
-			continue;
1143
-		}
1144
-
1145
-		if (PTR_ERR(gpiod) != -ENOENT)
1146
-			return PTR_ERR(gpiod);
1147
-
1148
-		if (i >= MAX_SS) {
1149
-			dev_err(dev, "Invalid native chip select %d\n", i);
1150
-			return -EINVAL;
1151
-		}
1152
-		used_ss_mask |= BIT(i);
1153
-	}
1154
-	p->unused_ss = ffz(used_ss_mask);
1155
-	if (cs_gpios && p->unused_ss >= MAX_SS) {
1156
-		dev_err(dev, "No unused native chip select available\n");
1157
-		return -EINVAL;
1158
-	}
1159
-	return 0;
1160
-}
1161
-
11621124 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
11631125 	enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
11641126 {
....@@ -1202,10 +1164,10 @@
12021164 {
12031165 	struct platform_device *pdev = p->pdev;
12041166 	struct device *dev = &pdev->dev;
1205
-	const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1167
+	const struct sh_msiof_spi_info *info = p->info;
12061168 	unsigned int dma_tx_id, dma_rx_id;
12071169 	const struct resource *res;
1208
-	struct spi_master *master;
1170
+	struct spi_controller *ctlr;
12091171 	struct device *tx_dev, *rx_dev;
12101172 
12111173 	if (dev->of_node) {
....@@ -1225,17 +1187,15 @@
12251187 	if (!res)
12261188 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
12271189 
1228
-	master = p->master;
1229
-	master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1230
-						   dma_tx_id,
1231
-						   res->start + TFDR);
1232
-	if (!master->dma_tx)
1190
+	ctlr = p->ctlr;
1191
+	ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1192
+						 dma_tx_id, res->start + SITFDR);
1193
+	if (!ctlr->dma_tx)
12331194 		return -ENODEV;
12341195 
1235
-	master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1236
-						   dma_rx_id,
1237
-						   res->start + RFDR);
1238
-	if (!master->dma_rx)
1196
+	ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1197
+						 dma_rx_id, res->start + SIRFDR);
1198
+	if (!ctlr->dma_rx)
12391199 		goto free_tx_chan;
12401200 
12411201 	p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
....@@ -1246,13 +1206,13 @@
12461206 	if (!p->rx_dma_page)
12471207 		goto free_tx_page;
12481208 
1249
-	tx_dev = master->dma_tx->device->dev;
1209
+	tx_dev = ctlr->dma_tx->device->dev;
12501210 	p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
12511211 					DMA_TO_DEVICE);
12521212 	if (dma_mapping_error(tx_dev, p->tx_dma_addr))
12531213 		goto free_rx_page;
12541214 
1255
-	rx_dev = master->dma_rx->device->dev;
1215
+	rx_dev = ctlr->dma_rx->device->dev;
12561216 	p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
12571217 					DMA_FROM_DEVICE);
12581218 	if (dma_mapping_error(rx_dev, p->rx_dma_addr))
....@@ -1268,34 +1228,33 @@
12681228 free_tx_page:
12691229 	free_page((unsigned long)p->tx_dma_page);
12701230 free_rx_chan:
1271
-	dma_release_channel(master->dma_rx);
1231
+	dma_release_channel(ctlr->dma_rx);
12721232 free_tx_chan:
1273
-	dma_release_channel(master->dma_tx);
1274
-	master->dma_tx = NULL;
1233
+	dma_release_channel(ctlr->dma_tx);
1234
+	ctlr->dma_tx = NULL;
12751235 	return -ENODEV;
12761236 }
12771237 
12781238 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
12791239 {
1280
-	struct spi_master *master = p->master;
1240
+	struct spi_controller *ctlr = p->ctlr;
12811241 
1282
-	if (!master->dma_tx)
1242
+	if (!ctlr->dma_tx)
12831243 		return;
12841244 
1285
-	dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1286
-			 PAGE_SIZE, DMA_FROM_DEVICE);
1287
-	dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1288
-			 PAGE_SIZE, DMA_TO_DEVICE);
1245
+	dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
1246
+			 DMA_FROM_DEVICE);
1247
+	dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
1248
+			 DMA_TO_DEVICE);
12891249 	free_page((unsigned long)p->rx_dma_page);
12901250 	free_page((unsigned long)p->tx_dma_page);
1291
-	dma_release_channel(master->dma_rx);
1292
-	dma_release_channel(master->dma_tx);
1251
+	dma_release_channel(ctlr->dma_rx);
1252
+	dma_release_channel(ctlr->dma_tx);
12931253 }
12941254 
12951255 static int sh_msiof_spi_probe(struct platform_device *pdev)
12961256 {
1297
-	struct resource	*r;
1298
-	struct spi_master *master;
1257
+	struct spi_controller *ctlr;
12991258 	const struct sh_msiof_chipdata *chipdata;
13001259 	struct sh_msiof_spi_info *info;
13011260 	struct sh_msiof_spi_priv *p;
....@@ -1316,18 +1275,18 @@
13161275 	}
13171276 
13181277 	if (info->mode == MSIOF_SPI_SLAVE)
1319
-		master = spi_alloc_slave(&pdev->dev,
1320
-					 sizeof(struct sh_msiof_spi_priv));
1278
+		ctlr = spi_alloc_slave(&pdev->dev,
1279
+				       sizeof(struct sh_msiof_spi_priv));
13211280 	else
1322
-		master = spi_alloc_master(&pdev->dev,
1323
-					  sizeof(struct sh_msiof_spi_priv));
1324
-	if (master == NULL)
1281
+		ctlr = spi_alloc_master(&pdev->dev,
1282
+					sizeof(struct sh_msiof_spi_priv));
1283
+	if (ctlr == NULL)
13251284 		return -ENOMEM;
13261285 
1327
-	p = spi_master_get_devdata(master);
1286
+	p = spi_controller_get_devdata(ctlr);
13281287 
13291288 	platform_set_drvdata(pdev, p);
1330
-	p->master = master;
1289
+	p->ctlr = ctlr;
13311290 	p->info = info;
13321291 	p->min_div_pow = chipdata->min_div_pow;
13331292 
....@@ -1343,13 +1302,11 @@
13431302 
13441303 	i = platform_get_irq(pdev, 0);
13451304 	if (i < 0) {
1346
-		dev_err(&pdev->dev, "cannot get IRQ\n");
13471305 		ret = i;
13481306 		goto err1;
13491307 	}
13501308 
1351
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1352
-	p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1309
+	p->mapbase = devm_platform_ioremap_resource(pdev, 0);
13531310 	if (IS_ERR(p->mapbase)) {
13541311 		ret = PTR_ERR(p->mapbase);
13551312 		goto err1;
....@@ -1373,32 +1330,29 @@
13731330 	if (p->info->rx_fifo_override)
13741331 		p->rx_fifo_size = p->info->rx_fifo_override;
13751332 
1376
-	/* Setup GPIO chip selects */
1377
-	master->num_chipselect = p->info->num_chipselect;
1378
-	ret = sh_msiof_get_cs_gpios(p);
1379
-	if (ret)
1380
-		goto err1;
1381
-
1382
-	/* init master code */
1383
-	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1384
-	master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1385
-	master->flags = chipdata->master_flags;
1386
-	master->bus_num = pdev->id;
1387
-	master->dev.of_node = pdev->dev.of_node;
1388
-	master->setup = sh_msiof_spi_setup;
1389
-	master->prepare_message = sh_msiof_prepare_message;
1390
-	master->slave_abort = sh_msiof_slave_abort;
1391
-	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1392
-	master->auto_runtime_pm = true;
1393
-	master->transfer_one = sh_msiof_transfer_one;
1333
+	/* init controller code */
1334
+	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1335
+	ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1336
+	ctlr->flags = chipdata->ctlr_flags;
1337
+	ctlr->bus_num = pdev->id;
1338
+	ctlr->num_chipselect = p->info->num_chipselect;
1339
+	ctlr->dev.of_node = pdev->dev.of_node;
1340
+	ctlr->setup = sh_msiof_spi_setup;
1341
+	ctlr->prepare_message = sh_msiof_prepare_message;
1342
+	ctlr->slave_abort = sh_msiof_slave_abort;
1343
+	ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;
1344
+	ctlr->auto_runtime_pm = true;
1345
+	ctlr->transfer_one = sh_msiof_transfer_one;
1346
+	ctlr->use_gpio_descriptors = true;
1347
+	ctlr->max_native_cs = MAX_SS;
13941348 
13951349 	ret = sh_msiof_request_dma(p);
13961350 	if (ret < 0)
13971351 		dev_warn(&pdev->dev, "DMA not available, using PIO\n");
13981352 
1399
-	ret = devm_spi_register_master(&pdev->dev, master);
1353
+	ret = devm_spi_register_controller(&pdev->dev, ctlr);
14001354 	if (ret < 0) {
1401
-		dev_err(&pdev->dev, "spi_register_master error.\n");
1355
+		dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
14021356 		goto err2;
14031357 	}
14041358 
....@@ -1408,7 +1362,7 @@
14081362 	sh_msiof_release_dma(p);
14091363 	pm_runtime_disable(&pdev->dev);
14101364  err1:
1411
-	spi_master_put(master);
1365
+	spi_controller_put(ctlr);
14121366 	return ret;
14131367 }
14141368 
....@@ -1430,23 +1384,21 @@
14301384 #ifdef CONFIG_PM_SLEEP
14311385 static int sh_msiof_spi_suspend(struct device *dev)
14321386 {
1433
-	struct platform_device *pdev = to_platform_device(dev);
1434
-	struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1387
+	struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
14351388 
1436
-	return spi_master_suspend(p->master);
1389
+	return spi_controller_suspend(p->ctlr);
14371390 }
14381391 
14391392 static int sh_msiof_spi_resume(struct device *dev)
14401393 {
1441
-	struct platform_device *pdev = to_platform_device(dev);
1442
-	struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1394
+	struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
14431395 
1444
-	return spi_master_resume(p->master);
1396
+	return spi_controller_resume(p->ctlr);
14451397 }
14461398 
14471399 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
14481400 			 sh_msiof_spi_resume);
1449
-#define DEV_PM_OPS	&sh_msiof_spi_pm_ops
1401
+#define DEV_PM_OPS	(&sh_msiof_spi_pm_ops)
14501402 #else
14511403 #define DEV_PM_OPS	NULL
14521404 #endif /* CONFIG_PM_SLEEP */
....@@ -1463,7 +1415,7 @@
14631415 };
14641416 module_platform_driver(sh_msiof_spi_drv);
14651417 
1466
-MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1418
+MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
14671419 MODULE_AUTHOR("Magnus Damm");
14681420 MODULE_LICENSE("GPL v2");
14691421 MODULE_ALIAS("platform:spi_sh_msiof");