forked from ~ljy/RK356X_SDK_RELEASE

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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/spi/spi-rockchip.c
....@@ -1,22 +1,13 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
34  * Author: Addy Ke <addy.ke@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
145  */
156 
7
+#include <linux/acpi.h>
168 #include <linux/clk.h>
179 #include <linux/delay.h>
1810 #include <linux/dmaengine.h>
19
-#include <linux/gpio.h>
2011 #include <linux/interrupt.h>
2112 #include <linux/miscdevice.h>
2213 #include <linux/module.h>
....@@ -197,6 +188,7 @@
197188 
198189 	struct clk *spiclk;
199190 	struct clk *apb_pclk;
191
+	struct clk *sclk_in;
200192 
201193 	void __iomem *regs;
202194 	dma_addr_t dma_addr_rx;
....@@ -227,8 +219,10 @@
227219 
228220 	struct pinctrl_state *high_speed_state;
229221 	bool slave_aborted;
230
-	bool gpio_requested;
231222 	bool cs_inactive; /* spi slave tansmition stop when cs inactive */
223
+	bool cs_high_supported; /* native CS supports active-high polarity */
224
+	struct gpio_desc *ready; /* spi slave transmission ready */
225
+
232226 	struct spi_transfer *xfer; /* Store xfer temporarily */
233227 	phys_addr_t base_addr_phy;
234228 	struct miscdevice miscdev;
....@@ -296,12 +290,12 @@
296290 		/* Keep things powered as long as CS is asserted */
297291 		pm_runtime_get_sync(rs->dev);
298292 
299
-		if (gpio_is_valid(spi->cs_gpio))
293
+		if (spi->cs_gpiod)
300294 			ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
301295 		else
302296 			ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
303297 	} else {
304
-		if (gpio_is_valid(spi->cs_gpio))
298
+		if (spi->cs_gpiod)
305299 			ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
306300 		else
307301 			ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
....@@ -362,7 +356,7 @@
362356 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
363357 {
364358 	u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
365
-	u32 rx_left = rs->rx_left > words ? rs->rx_left - words : 0;
359
+	u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
366360 
367361 	/* the hardware doesn't allow us to change fifo threshold
368362 	 * level while spi is enabled, so instead make sure to leave
....@@ -484,8 +478,8 @@
484478 {
485479 	u32 i;
486480 
487
-	/* burst size: 1, 2, 4, 8 */
488
-	for (i = 1; i < 8; i <<= 1) {
481
+	/* burst size: 1, 2, 4, 8, 16 */
482
+	for (i = 1; i < 16; i <<= 1) {
489483 		if (data_len & i)
490484 			break;
491485 	}
....@@ -528,7 +522,7 @@
528522 			.direction = DMA_MEM_TO_DEV,
529523 			.dst_addr = rs->dma_addr_tx,
530524 			.dst_addr_width = rs->n_bytes,
531
-			.dst_maxburst = 8,
525
+			.dst_maxburst = rs->fifo_len / 4,
532526 		};
533527 
534528 		dmaengine_slave_config(ctlr->dma_tx, &txconf);
....@@ -678,7 +672,9 @@
678672 		 * ctlr->bits_per_word_mask, so this shouldn't
679673 		 * happen
680674 		 */
681
-		unreachable();
675
+		dev_err(rs->dev, "unknown bits per word: %d\n",
676
+			xfer->bits_per_word);
677
+		return -EINVAL;
682678 	}
683679 
684680 	if (xfer_mode == ROCKCHIP_SPI_DMA) {
....@@ -864,8 +860,17 @@
864860 		ret = rockchip_spi_prepare_irq(rs, ctlr, xfer);
865861 	}
866862 
863
+	if (rs->ready) {
864
+		gpiod_set_value(rs->ready, 0);
865
+		udelay(1);
866
+		gpiod_set_value(rs->ready, 1);
867
+	}
868
+
867869 	if (ret > 0)
868870 		ret = rockchip_spi_transfer_wait(ctlr, xfer);
871
+
872
+	if (rs->ready)
873
+		gpiod_set_value(rs->ready, 0);
869874 
870875 	return ret;
871876 }
....@@ -886,10 +891,13 @@
886891 
887892 static int rockchip_spi_setup(struct spi_device *spi)
888893 {
889
-
890
-	int ret = -EINVAL;
891894 	struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
892895 	u32 cr0;
896
+
897
+	if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
898
+		dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
899
+		return -EINVAL;
900
+	}
893901 
894902 	pm_runtime_get_sync(rs->dev);
895903 
....@@ -898,44 +906,14 @@
898906 	cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
899907 	if (spi->mode & SPI_CS_HIGH)
900908 		cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
909
+	if (spi_controller_is_slave(spi->controller))
910
+		cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
901911 
902912 	writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
903913 
904914 	pm_runtime_put(rs->dev);
905915 
906
-	if (spi->cs_gpio == -ENOENT)
907
-		return 0;
908
-
909
-	if (!rs->gpio_requested && gpio_is_valid(spi->cs_gpio)) {
910
-		ret = gpio_request_one(spi->cs_gpio,
911
-				       (spi->mode & SPI_CS_HIGH) ?
912
-				       GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
913
-				       dev_name(&spi->dev));
914
-		if (ret)
915
-			dev_err(&spi->dev, "can't request chipselect gpio %d\n",
916
-				spi->cs_gpio);
917
-		else
918
-			rs->gpio_requested = true;
919
-	} else {
920
-		if (gpio_is_valid(spi->cs_gpio)) {
921
-			int mode = ((spi->mode & SPI_CS_HIGH) ? 0 : 1);
922
-
923
-			ret = gpio_direction_output(spi->cs_gpio, mode);
924
-			if (ret)
925
-				dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n",
926
-					spi->cs_gpio, ret);
927
-		}
928
-	}
929
-
930
-	return ret;
931
-}
932
-
933
-static void rockchip_spi_cleanup(struct spi_device *spi)
934
-{
935
-	struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
936
-
937
-	if (rs->gpio_requested)
938
-		gpio_free(spi->cs_gpio);
916
+	return 0;
939917 }
940918 
941919 static int rockchip_spi_misc_open(struct inode *inode, struct file *filp)
....@@ -999,10 +977,11 @@
999977 	struct spi_controller *ctlr;
1000978 	struct resource *mem;
1001979 	struct device_node *np = pdev->dev.of_node;
1002
-	u32 rsd_nsecs, csm;
980
+	u32 rsd_nsecs, num_cs, csm;
1003981 	bool slave_mode;
1004982 	struct pinctrl *pinctrl = NULL;
1005983 	const struct rockchip_spi_quirks *quirks_cfg;
984
+	u32 val;
1006985 
1007986 	slave_mode = of_property_read_bool(np, "spi-slave");
1008987 
....@@ -1016,6 +995,7 @@
1016995 	if (!ctlr)
1017996 		return -ENOMEM;
1018997 
998
+	ctlr->rt = device_property_read_bool(&pdev->dev, "rockchip,rt");
1019999 	platform_set_drvdata(pdev, ctlr);
10201000 
10211001 	rs = spi_controller_get_devdata(ctlr);
....@@ -1030,17 +1010,26 @@
10301010 	}
10311011 	rs->base_addr_phy = mem->start;
10321012 
1033
-	rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1013
+	if (!has_acpi_companion(&pdev->dev))
1014
+		rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
10341015 	if (IS_ERR(rs->apb_pclk)) {
10351016 		dev_err(&pdev->dev, "Failed to get apb_pclk\n");
10361017 		ret = PTR_ERR(rs->apb_pclk);
10371018 		goto err_put_ctlr;
10381019 	}
10391020 
1040
-	rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
1021
+	if (!has_acpi_companion(&pdev->dev))
1022
+		rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
10411023 	if (IS_ERR(rs->spiclk)) {
10421024 		dev_err(&pdev->dev, "Failed to get spi_pclk\n");
10431025 		ret = PTR_ERR(rs->spiclk);
1026
+		goto err_put_ctlr;
1027
+	}
1028
+
1029
+	rs->sclk_in = devm_clk_get_optional(&pdev->dev, "sclk_in");
1030
+	if (IS_ERR(rs->sclk_in)) {
1031
+		dev_err(&pdev->dev, "Failed to get sclk_in\n");
1032
+		ret = PTR_ERR(rs->sclk_in);
10441033 		goto err_put_ctlr;
10451034 	}
10461035 
....@@ -1056,23 +1045,35 @@
10561045 		goto err_disable_apbclk;
10571046 	}
10581047 
1048
+	ret = clk_prepare_enable(rs->sclk_in);
1049
+	if (ret < 0) {
1050
+		dev_err(&pdev->dev, "Failed to enable sclk_in\n");
1051
+		goto err_disable_spiclk;
1052
+	}
1053
+
10591054 	spi_enable_chip(rs, false);
10601055 
10611056 	ret = platform_get_irq(pdev, 0);
10621057 	if (ret < 0)
1063
-		goto err_disable_spiclk;
1058
+		goto err_disable_sclk_in;
10641059 
10651060 	ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
10661061 			IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
10671062 	if (ret)
1068
-		goto err_disable_spiclk;
1063
+		goto err_disable_sclk_in;
10691064 
10701065 	rs->dev = &pdev->dev;
1071
-	rs->freq = clk_get_rate(rs->spiclk);
1072
-	rs->gpio_requested = false;
10731066 
1074
-	if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
1075
-				  &rsd_nsecs)) {
1067
+	rs->freq = clk_get_rate(rs->spiclk);
1068
+	if (!rs->freq) {
1069
+		ret = device_property_read_u32(&pdev->dev, "clock-frequency", &rs->freq);
1070
+		if (ret) {
1071
+			dev_warn(rs->dev, "Failed to get clock or clock-frequency property\n");
1072
+			goto err_disable_sclk_in;
1073
+		}
1074
+	}
1075
+
1076
+	if (!device_property_read_u32(&pdev->dev, "rx-sample-delay-ns", &rsd_nsecs)) {
10761077 		/* rx sample delay is expressed in parent clock cycles (max 3) */
10771078 		u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
10781079 				1000000000 >> 8);
....@@ -1102,33 +1103,47 @@
11021103 	if (!rs->fifo_len) {
11031104 		dev_err(&pdev->dev, "Failed to get fifo length\n");
11041105 		ret = -EINVAL;
1105
-		goto err_disable_spiclk;
1106
+		goto err_disable_sclk_in;
11061107 	}
11071108 	quirks_cfg = device_get_match_data(&pdev->dev);
11081109 	if (quirks_cfg)
11091110 		rs->max_baud_div_in_cpha = quirks_cfg->max_baud_div_in_cpha;
1111
+
1112
+	if (!device_property_read_u32(&pdev->dev, "rockchip,autosuspend-delay-ms", &val)) {
1113
+		if (val > 0) {
1114
+			pm_runtime_set_autosuspend_delay(&pdev->dev, val);
1115
+			pm_runtime_use_autosuspend(&pdev->dev);
1116
+		}
1117
+	}
11101118 
11111119 	pm_runtime_set_active(&pdev->dev);
11121120 	pm_runtime_enable(&pdev->dev);
11131121 
11141122 	ctlr->auto_runtime_pm = true;
11151123 	ctlr->bus_num = pdev->id;
1116
-	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST | SPI_CS_HIGH;
1124
+	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
11171125 	if (slave_mode) {
11181126 		ctlr->mode_bits |= SPI_NO_CS;
11191127 		ctlr->slave_abort = rockchip_spi_slave_abort;
11201128 	} else {
11211129 		ctlr->flags = SPI_MASTER_GPIO_SS;
1130
+		ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
1131
+		/*
1132
+		 * rk spi0 has two native cs, spi1..5 one cs only
1133
+		 * if num-cs is missing in the dts, default to 1
1134
+		 */
1135
+		if (device_property_read_u32(&pdev->dev, "num-cs", &num_cs))
1136
+			num_cs = 1;
1137
+		ctlr->num_chipselect = num_cs;
1138
+		ctlr->use_gpio_descriptors = true;
11221139 	}
1123
-	ctlr->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
11241140 	ctlr->dev.of_node = pdev->dev.of_node;
11251141 	ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
11261142 	ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
11271143 	ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
11281144 
1129
-	ctlr->set_cs = rockchip_spi_set_cs;
11301145 	ctlr->setup = rockchip_spi_setup;
1131
-	ctlr->cleanup = rockchip_spi_cleanup;
1146
+	ctlr->set_cs = rockchip_spi_set_cs;
11321147 	ctlr->transfer_one = rockchip_spi_transfer_one;
11331148 	ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
11341149 	ctlr->handle_err = rockchip_spi_handle_err;
....@@ -1169,8 +1184,9 @@
11691184 	}
11701185 
11711186 	switch (rs->version) {
1172
-	case ROCKCHIP_SPI_VER2_TYPE1:
11731187 	case ROCKCHIP_SPI_VER2_TYPE2:
1188
+		rs->cs_high_supported = true;
1189
+		ctlr->mode_bits |= SPI_CS_HIGH;
11741190 		if (slave_mode)
11751191 			rs->cs_inactive = true;
11761192 		else
....@@ -1178,7 +1194,11 @@
11781194 		break;
11791195 	default:
11801196 		rs->cs_inactive = false;
1197
+		break;
11811198 	}
1199
+	if (device_property_read_bool(&pdev->dev, "rockchip,cs-inactive-disable"))
1200
+		rs->cs_inactive = false;
1201
+
11821202 	pinctrl = devm_pinctrl_get(&pdev->dev);
11831203 	if (!IS_ERR(pinctrl)) {
11841204 		rs->high_speed_state = pinctrl_lookup_state(pinctrl, "high_speed");
....@@ -1186,6 +1206,13 @@
11861206 			dev_warn(&pdev->dev, "no high_speed pinctrl state\n");
11871207 			rs->high_speed_state = NULL;
11881208 		}
1209
+	}
1210
+
1211
+	rs->ready = devm_gpiod_get_optional(&pdev->dev, "ready", GPIOD_OUT_HIGH);
1212
+	if (IS_ERR(rs->ready)) {
1213
+		ret = dev_err_probe(&pdev->dev, PTR_ERR(rs->ready),
1214
+				    "invalid ready-gpios property in node\n");
1215
+		goto err_free_dma_rx;
11891216 	}
11901217 
11911218 	ret = devm_spi_register_controller(&pdev->dev, ctlr);
....@@ -1210,7 +1237,8 @@
12101237 			dev_info(&pdev->dev, "register misc device %s\n", misc_name);
12111238 	}
12121239 
1213
-	dev_info(rs->dev, "probed, poll=%d, rsd=%d\n", rs->poll, rs->rsd);
1240
+	dev_info(rs->dev, "probed, poll=%d, rsd=%d, cs-inactive=%d, ready=%d\n",
1241
+		 rs->poll, rs->rsd, rs->cs_inactive, rs->ready ? 1 : 0);
12141242 
12151243 	return 0;
12161244 
....@@ -1222,6 +1250,8 @@
12221250 		dma_release_channel(ctlr->dma_tx);
12231251 err_disable_pm_runtime:
12241252 	pm_runtime_disable(&pdev->dev);
1253
+err_disable_sclk_in:
1254
+	clk_disable_unprepare(rs->sclk_in);
12251255 err_disable_spiclk:
12261256 	clk_disable_unprepare(rs->spiclk);
12271257 err_disable_apbclk:
....@@ -1242,6 +1272,7 @@
12421272 
12431273 	pm_runtime_get_sync(&pdev->dev);
12441274 
1275
+	clk_disable_unprepare(rs->sclk_in);
12451276 	clk_disable_unprepare(rs->spiclk);
12461277 	clk_disable_unprepare(rs->apb_pclk);
12471278 
....@@ -1344,15 +1375,18 @@
13441375 		.compatible = "rockchip,px30-spi",
13451376 		.data = &rockchip_spi_quirks_cfg,
13461377 	},
1347
-	{ .compatible = "rockchip,rv1108-spi", },
1348
-	{ .compatible = "rockchip,rv1126-spi", },
13491378 	{ .compatible = "rockchip,rk3036-spi", },
13501379 	{ .compatible = "rockchip,rk3066-spi", },
13511380 	{ .compatible = "rockchip,rk3188-spi", },
13521381 	{ .compatible = "rockchip,rk3228-spi", },
13531382 	{ .compatible = "rockchip,rk3288-spi", },
1383
+	{ .compatible = "rockchip,rk3308-spi", },
1384
+	{ .compatible = "rockchip,rk3328-spi", },
13541385 	{ .compatible = "rockchip,rk3368-spi", },
13551386 	{ .compatible = "rockchip,rk3399-spi", },
1387
+	{ .compatible = "rockchip,rv1106-spi", },
1388
+	{ .compatible = "rockchip,rv1108-spi", },
1389
+	{ .compatible = "rockchip,rv1126-spi", },
13561390 	{ },
13571391 };
13581392 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);