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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/spi/spi-qup.c
..
..
@@ -1030,23 +1030,8 @@
1030
1030
 		return -ENXIO;
1031
1031
 	}
1032
1032
 
1033
-	ret = clk_prepare_enable(cclk);
1034
-	if (ret) {
1035
-		dev_err(dev, "cannot enable core clock\n");
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-		return ret;
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-	}
1038
-
1039
-	ret = clk_prepare_enable(iclk);
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-	if (ret) {
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-		clk_disable_unprepare(cclk);
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-		dev_err(dev, "cannot enable iface clock\n");
1043
-		return ret;
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-	}
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-
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 	master = spi_alloc_master(dev, sizeof(struct spi_qup));
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 	if (!master) {
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-		clk_disable_unprepare(cclk);
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-		clk_disable_unprepare(iclk);
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 		dev_err(dev, "cannot allocate master\n");
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 		return -ENOMEM;
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1037
 	}
..
..
@@ -1092,6 +1077,19 @@
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 	spin_lock_init(&controller->lock);
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 	init_completion(&controller->done);
1094
1079
 
1080
+	ret = clk_prepare_enable(cclk);
1081
+	if (ret) {
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+		dev_err(dev, "cannot enable core clock\n");
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+		goto error_dma;
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+	}
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+
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+	ret = clk_prepare_enable(iclk);
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+	if (ret) {
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+		clk_disable_unprepare(cclk);
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+		dev_err(dev, "cannot enable iface clock\n");
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+		goto error_dma;
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+	}
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+
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 	iomode = readl_relaxed(base + QUP_IO_M_MODES);
1096
1094
 
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 	size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
..
..
@@ -1121,7 +1119,7 @@
1121
1119
 	ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1122
1120
 	if (ret) {
1123
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 		dev_err(dev, "cannot set RESET state\n");
1124
-		goto error_dma;
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+		goto error_clk;
1125
1123
 	}
1126
1124
 
1127
1125
 	writel_relaxed(0, base + QUP_OPERATIONAL);
..
..
@@ -1145,7 +1143,7 @@
1145
1143
 	ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
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 			       IRQF_TRIGGER_HIGH, pdev->name, controller);
1147
1145
 	if (ret)
1148
-		goto error_dma;
1146
+		goto error_clk;
1149
1147
 
1150
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 	pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
1151
1149
 	pm_runtime_use_autosuspend(dev);
..
..
@@ -1160,11 +1158,12 @@
1160
1158
 
1161
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 disable_pm:
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 	pm_runtime_disable(&pdev->dev);
1161
+error_clk:
1162
+	clk_disable_unprepare(cclk);
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+	clk_disable_unprepare(iclk);
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 error_dma:
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 	spi_qup_release_dma(master);
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 error:
1166
-	clk_disable_unprepare(cclk);
1167
-	clk_disable_unprepare(iclk);
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 	spi_master_put(master);
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 	return ret;
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 }
..
..
@@ -1276,18 +1275,22 @@
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 	struct spi_qup *controller = spi_master_get_devdata(master);
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 	int ret;
1278
1277
 
1279
-	ret = pm_runtime_resume_and_get(&pdev->dev);
1280
-	if (ret < 0)
1281
-		return ret;
1278
+	ret = pm_runtime_get_sync(&pdev->dev);
1282
1279
 
1283
-	ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1284
-	if (ret)
1285
-		return ret;
1280
+	if (ret >= 0) {
1281
+		ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1282
+		if (ret)
1283
+			dev_warn(&pdev->dev, "failed to reset controller (%pe)\n",
1284
+				 ERR_PTR(ret));
1285
+
1286
+		clk_disable_unprepare(controller->cclk);
1287
+		clk_disable_unprepare(controller->iclk);
1288
+	} else {
1289
+		dev_warn(&pdev->dev, "failed to resume, skip hw disable (%pe)\n",
1290
+			 ERR_PTR(ret));
1291
+	}
1286
1292
 
1287
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 	spi_qup_release_dma(master);
1288
-
1289
-	clk_disable_unprepare(controller->cclk);
1290
-	clk_disable_unprepare(controller->iclk);
1291
1294
 
1292
1295
 	pm_runtime_put_noidle(&pdev->dev);
1293
1296
 	pm_runtime_disable(&pdev->dev);