~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,38 +1,32 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/*
2	3	* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3	4	* Copyright (C) 2013, Intel Corporation
4		- *
5		- * This program is free software; you can redistribute it and/or modify
6		- * it under the terms of the GNU General Public License as published by
7		- * the Free Software Foundation; either version 2 of the License, or
8		- * (at your option) any later version.
9		- *
10		- * This program is distributed in the hope that it will be useful,
11		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13		- * GNU General Public License for more details.
14	5	*/
15	6
	7	+#include <linux/acpi.h>
16	8	#include <linux/bitops.h>
17		-#include <linux/init.h>
18		-#include <linux/module.h>
	9	+#include <linux/clk.h>
	10	+#include <linux/delay.h>
19	11	#include <linux/device.h>
20		-#include <linux/ioport.h>
21		-#include <linux/errno.h>
22	12	#include <linux/err.h>
	13	+#include <linux/errno.h>
	14	+#include <linux/gpio/consumer.h>
	15	+#include <linux/gpio.h>
	16	+#include <linux/init.h>
23	17	#include <linux/interrupt.h>
	18	+#include <linux/ioport.h>
24	19	#include <linux/kernel.h>
	20	+#include <linux/module.h>
	21	+#include <linux/mod_devicetable.h>
	22	+#include <linux/of.h>
25	23	#include <linux/pci.h>
26	24	#include <linux/platform_device.h>
	25	+#include <linux/pm_runtime.h>
	26	+#include <linux/property.h>
	27	+#include <linux/slab.h>
27	28	#include <linux/spi/pxa2xx_spi.h>
28	29	#include <linux/spi/spi.h>
29		-#include <linux/delay.h>
30		-#include <linux/gpio.h>
31		-#include <linux/gpio/consumer.h>
32		-#include <linux/slab.h>
33		-#include <linux/clk.h>
34		-#include <linux/pm_runtime.h>
35		-#include <linux/acpi.h>
36	30
37	31	#include "spi-pxa2xx.h"
38	32
..	..	@@ -199,6 +193,11 @@
199	193	return drv_data->ssp_type == QUARK_X1000_SSP;
200	194	}
201	195
	196	+static bool is_mmp2_ssp(const struct driver_data *drv_data)
	197	+{
	198	+ return drv_data->ssp_type == MMP2_SSP;
	199	+}
	200	+
202	201	static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
203	202	{
204	203	switch (drv_data->ssp_type) {
..	..	@@ -335,7 +334,7 @@
335	334	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
336	335
337	336	/* Enable multiblock DMA transfers */
338		- if (drv_data->master_info->enable_dma) {
	337	+ if (drv_data->controller_info->enable_dma) {
339	338	__lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
340	339
341	340	if (config->reg_general >= 0) {
..	..	@@ -375,7 +374,7 @@
375	374	__lpss_ssp_write_priv(drv_data,
376	375	config->reg_cs_ctrl, value);
377	376	ndelay(1000000000 /
378		- (drv_data->master->max_speed_hz / 2));
	377	+ (drv_data->controller->max_speed_hz / 2));
379	378	}
380	379	}
381	380
..	..	@@ -491,6 +490,16 @@
491	490	return limit;
492	491	}
493	492
	493	+static void pxa2xx_spi_off(struct driver_data *drv_data)
	494	+{
	495	+ /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
	496	+ if (is_mmp2_ssp(drv_data))
	497	+ return;
	498	+
	499	+ pxa2xx_spi_write(drv_data, SSCR0,
	500	+ pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
	501	+}
	502	+
494	503	static int null_writer(struct driver_data *drv_data)
495	504	{
496	505	u8 n_bytes = drv_data->n_bytes;
..	..	@@ -590,7 +599,7 @@
590	599	static void reset_sccr1(struct driver_data *drv_data)
591	600	{
592	601	struct chip_data *chip =
593		- spi_get_ctldata(drv_data->master->cur_msg->spi);
	602	+ spi_get_ctldata(drv_data->controller->cur_msg->spi);
594	603	u32 sccr1_reg;
595	604
596	605	sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
..	..	@@ -617,13 +626,12 @@
617	626	if (!pxa25x_ssp_comp(drv_data))
618	627	pxa2xx_spi_write(drv_data, SSTO, 0);
619	628	pxa2xx_spi_flush(drv_data);
620		- pxa2xx_spi_write(drv_data, SSCR0,
621		- pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
	629	+ pxa2xx_spi_off(drv_data);
622	630
623	631	dev_err(&drv_data->pdev->dev, "%s\n", msg);
624	632
625		- drv_data->master->cur_msg->status = -EIO;
626		- spi_finalize_current_transfer(drv_data->master);
	633	+ drv_data->controller->cur_msg->status = -EIO;
	634	+ spi_finalize_current_transfer(drv_data->controller);
627	635	}
628	636
629	637	static void int_transfer_complete(struct driver_data *drv_data)
..	..	@@ -634,7 +642,7 @@
634	642	if (!pxa25x_ssp_comp(drv_data))
635	643	pxa2xx_spi_write(drv_data, SSTO, 0);
636	644
637		- spi_finalize_current_transfer(drv_data->master);
	645	+ spi_finalize_current_transfer(drv_data->controller);
638	646	}
639	647
640	648	static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
..	..	@@ -646,6 +654,11 @@
646	654
647	655	if (irq_status & SSSR_ROR) {
648	656	int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
	657	+ return IRQ_HANDLED;
	658	+ }
	659	+
	660	+ if (irq_status & SSSR_TUR) {
	661	+ int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
649	662	return IRQ_HANDLED;
650	663	}
651	664
..	..	@@ -689,9 +702,11 @@
689	702	bytes_left = drv_data->rx_end - drv_data->rx;
690	703	switch (drv_data->n_bytes) {
691	704	case 4:
692		- bytes_left >>= 1;
	705	+ bytes_left >>= 2;
	706	+ break;
693	707	case 2:
694	708	bytes_left >>= 1;
	709	+ break;
695	710	}
696	711
697	712	rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
..	..	@@ -709,8 +724,7 @@
709	724
710	725	static void handle_bad_msg(struct driver_data *drv_data)
711	726	{
712		- pxa2xx_spi_write(drv_data, SSCR0,
713		- pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
	727	+ pxa2xx_spi_off(drv_data);
714	728	pxa2xx_spi_write(drv_data, SSCR1,
715	729	pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
716	730	if (!pxa25x_ssp_comp(drv_data))
..	..	@@ -763,7 +777,7 @@
763	777	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
764	778	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
765	779
766		- if (!drv_data->master->cur_msg) {
	780	+ if (!drv_data->controller->cur_msg) {
767	781	handle_bad_msg(drv_data);
768	782	/* Never fail */
769	783	return IRQ_HANDLED;
..	..	@@ -895,7 +909,7 @@
895	909
896	910	static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
897	911	{
898		- unsigned long ssp_clk = drv_data->master->max_speed_hz;
	912	+ unsigned long ssp_clk = drv_data->controller->max_speed_hz;
899	913	const struct ssp_device *ssp = drv_data->ssp;
900	914
901	915	rate = min_t(int, ssp_clk, rate);
..	..	@@ -914,7 +928,7 @@
914	928	int rate)
915	929	{
916	930	struct chip_data *chip =
917		- spi_get_ctldata(drv_data->master->cur_msg->spi);
	931	+ spi_get_ctldata(drv_data->controller->cur_msg->spi);
918	932	unsigned int clk_div;
919	933
920	934	switch (drv_data->ssp_type) {
..	..	@@ -928,7 +942,7 @@
928	942	return clk_div << 8;
929	943	}
930	944
931		-static bool pxa2xx_spi_can_dma(struct spi_controller *master,
	945	+static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
932	946	struct spi_device *spi,
933	947	struct spi_transfer *xfer)
934	948	{
..	..	@@ -939,13 +953,13 @@
939	953	xfer->len >= chip->dma_burst_size;
940	954	}
941	955
942		-static int pxa2xx_spi_transfer_one(struct spi_controller *master,
	956	+static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
943	957	struct spi_device *spi,
944	958	struct spi_transfer *transfer)
945	959	{
946		- struct driver_data *drv_data = spi_controller_get_devdata(master);
947		- struct spi_message *message = master->cur_msg;
948		- struct chip_data *chip = spi_get_ctldata(message->spi);
	960	+ struct driver_data *drv_data = spi_controller_get_devdata(controller);
	961	+ struct spi_message *message = controller->cur_msg;
	962	+ struct chip_data *chip = spi_get_ctldata(spi);
949	963	u32 dma_thresh = chip->dma_threshold;
950	964	u32 dma_burst = chip->dma_burst_size;
951	965	u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
..	..	@@ -963,21 +977,21 @@
963	977	/* reject already-mapped transfers; PIO won't always work */
964	978	if (message->is_dma_mapped
965	979	\|\| transfer->rx_dma \|\| transfer->tx_dma) {
966		- dev_err(&drv_data->pdev->dev,
	980	+ dev_err(&spi->dev,
967	981	"Mapped transfer length of %u is greater than %d\n",
968	982	transfer->len, MAX_DMA_LEN);
969	983	return -EINVAL;
970	984	}
971	985
972	986	/* warn ... we force this to PIO mode */
973		- dev_warn_ratelimited(&message->spi->dev,
	987	+ dev_warn_ratelimited(&spi->dev,
974	988	"DMA disabled for transfer length %ld greater than %d\n",
975	989	(long)transfer->len, MAX_DMA_LEN);
976	990	}
977	991
978	992	/* Setup the transfer state based on the type of transfer */
979	993	if (pxa2xx_spi_flush(drv_data) == 0) {
980		- dev_err(&drv_data->pdev->dev, "Flush failed\n");
	994	+ dev_err(&spi->dev, "Flush failed\n");
981	995	return -EIO;
982	996	}
983	997	drv_data->n_bytes = chip->n_bytes;
..	..	@@ -1019,16 +1033,16 @@
1019	1033	*/
1020	1034	if (chip->enable_dma) {
1021	1035	if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1022		- message->spi,
	1036	+ spi,
1023	1037	bits, &dma_burst,
1024	1038	&dma_thresh))
1025		- dev_warn_ratelimited(&message->spi->dev,
	1039	+ dev_warn_ratelimited(&spi->dev,
1026	1040	"DMA burst size reduced to match bits_per_word\n");
1027	1041	}
1028	1042
1029		- dma_mapped = master->can_dma &&
1030		- master->can_dma(master, message->spi, transfer) &&
1031		- master->cur_msg_mapped;
	1043	+ dma_mapped = controller->can_dma &&
	1044	+ controller->can_dma(controller, spi, transfer) &&
	1045	+ controller->cur_msg_mapped;
1032	1046	if (dma_mapped) {
1033	1047
1034	1048	/* Ensure we have the correct interrupt handler */
..	..	@@ -1055,13 +1069,13 @@
1055	1069	/* NOTE: PXA25x_SSP _could_ use external clocking ... */
1056	1070	cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1057	1071	if (!pxa25x_ssp_comp(drv_data))
1058		- dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1059		- master->max_speed_hz
	1072	+ dev_dbg(&spi->dev, "%u Hz actual, %s\n",
	1073	+ controller->max_speed_hz
1060	1074	/ (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1061	1075	dma_mapped ? "DMA" : "PIO");
1062	1076	else
1063		- dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1064		- master->max_speed_hz / 2
	1077	+ dev_dbg(&spi->dev, "%u Hz actual, %s\n",
	1078	+ controller->max_speed_hz / 2
1065	1079	/ (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1066	1080	dma_mapped ? "DMA" : "PIO");
1067	1081
..	..	@@ -1085,7 +1099,8 @@
1085	1099	\|\| (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1086	1100	!= (cr1 & change_mask)) {
1087	1101	/* stop the SSP, and update the other bits */
1088		- pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
	1102	+ if (!is_mmp2_ssp(drv_data))
	1103	+ pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1089	1104	if (!pxa25x_ssp_comp(drv_data))
1090	1105	pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1091	1106	/* first set CR1 without interrupt and service enables */
..	..	@@ -1098,6 +1113,30 @@
1098	1113	pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1099	1114	}
1100	1115
	1116	+ if (is_mmp2_ssp(drv_data)) {
	1117	+ u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
	1118	+ & SSSR_TFL_MASK) >> 8;
	1119	+
	1120	+ if (tx_level) {
	1121	+ /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
	1122	+ dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
	1123	+ tx_level);
	1124	+ if (tx_level > transfer->len)
	1125	+ tx_level = transfer->len;
	1126	+ drv_data->tx += tx_level;
	1127	+ }
	1128	+ }
	1129	+
	1130	+ if (spi_controller_is_slave(controller)) {
	1131	+ while (drv_data->write(drv_data))
	1132	+ ;
	1133	+ if (drv_data->gpiod_ready) {
	1134	+ gpiod_set_value(drv_data->gpiod_ready, 1);
	1135	+ udelay(1);
	1136	+ gpiod_set_value(drv_data->gpiod_ready, 0);
	1137	+ }
	1138	+ }
	1139	+
1101	1140	/*
1102	1141	* Release the data by enabling service requests and interrupts,
1103	1142	* without changing any mode bits
..	..	@@ -1107,14 +1146,33 @@
1107	1146	return 1;
1108	1147	}
1109	1148
1110		-static void pxa2xx_spi_handle_err(struct spi_controller *master,
	1149	+static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
	1150	+{
	1151	+ struct driver_data *drv_data = spi_controller_get_devdata(controller);
	1152	+
	1153	+ /* Stop and reset SSP */
	1154	+ write_SSSR_CS(drv_data, drv_data->clear_sr);
	1155	+ reset_sccr1(drv_data);
	1156	+ if (!pxa25x_ssp_comp(drv_data))
	1157	+ pxa2xx_spi_write(drv_data, SSTO, 0);
	1158	+ pxa2xx_spi_flush(drv_data);
	1159	+ pxa2xx_spi_off(drv_data);
	1160	+
	1161	+ dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
	1162	+
	1163	+ drv_data->controller->cur_msg->status = -EINTR;
	1164	+ spi_finalize_current_transfer(drv_data->controller);
	1165	+
	1166	+ return 0;
	1167	+}
	1168	+
	1169	+static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1111	1170	struct spi_message *msg)
1112	1171	{
1113		- struct driver_data *drv_data = spi_controller_get_devdata(master);
	1172	+ struct driver_data *drv_data = spi_controller_get_devdata(controller);
1114	1173
1115	1174	/* Disable the SSP */
1116		- pxa2xx_spi_write(drv_data, SSCR0,
1117		- pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
	1175	+ pxa2xx_spi_off(drv_data);
1118	1176	/* Clear and disable interrupts and service requests */
1119	1177	write_SSSR_CS(drv_data, drv_data->clear_sr);
1120	1178	pxa2xx_spi_write(drv_data, SSCR1,
..	..	@@ -1134,13 +1192,12 @@
1134	1192	pxa2xx_spi_dma_stop(drv_data);
1135	1193	}
1136	1194
1137		-static int pxa2xx_spi_unprepare_transfer(struct spi_controller *master)
	1195	+static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1138	1196	{
1139		- struct driver_data *drv_data = spi_controller_get_devdata(master);
	1197	+ struct driver_data *drv_data = spi_controller_get_devdata(controller);
1140	1198
1141	1199	/* Disable the SSP now */
1142		- pxa2xx_spi_write(drv_data, SSCR0,
1143		- pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
	1200	+ pxa2xx_spi_off(drv_data);
1144	1201
1145	1202	return 0;
1146	1203	}
..	..	@@ -1197,6 +1254,8 @@
1197	1254	chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1198	1255
1199	1256	err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
	1257	+ if (err)
	1258	+ gpiod_put(chip->gpiod_cs);
1200	1259	}
1201	1260
1202	1261	return err;
..	..	@@ -1210,6 +1269,7 @@
1210	1269	struct driver_data *drv_data =
1211	1270	spi_controller_get_devdata(spi->controller);
1212	1271	uint tx_thres, tx_hi_thres, rx_thres;
	1272	+ int err;
1213	1273
1214	1274	switch (drv_data->ssp_type) {
1215	1275	case QUARK_X1000_SSP:
..	..	@@ -1234,9 +1294,14 @@
1234	1294	rx_thres = config->rx_threshold;
1235	1295	break;
1236	1296	default:
1237		- tx_thres = TX_THRESH_DFLT;
1238	1297	tx_hi_thres = 0;
1239		- rx_thres = RX_THRESH_DFLT;
	1298	+ if (spi_controller_is_slave(drv_data->controller)) {
	1299	+ tx_thres = 1;
	1300	+ rx_thres = 2;
	1301	+ } else {
	1302	+ tx_thres = TX_THRESH_DFLT;
	1303	+ rx_thres = RX_THRESH_DFLT;
	1304	+ }
1240	1305	break;
1241	1306	}
1242	1307
..	..	@@ -1257,7 +1322,7 @@
1257	1322
1258	1323	chip->frm = spi->chip_select;
1259	1324	}
1260		- chip->enable_dma = drv_data->master_info->enable_dma;
	1325	+ chip->enable_dma = drv_data->controller_info->enable_dma;
1261	1326	chip->timeout = TIMOUT_DFLT;
1262	1327	}
1263	1328
..	..	@@ -1280,6 +1345,12 @@
1280	1345	if (chip_info->enable_loopback)
1281	1346	chip->cr1 = SSCR1_LBM;
1282	1347	}
	1348	+ if (spi_controller_is_slave(drv_data->controller)) {
	1349	+ chip->cr1 \|= SSCR1_SCFR;
	1350	+ chip->cr1 \|= SSCR1_SCLKDIR;
	1351	+ chip->cr1 \|= SSCR1_SFRMDIR;
	1352	+ chip->cr1 \|= SSCR1_SPH;
	1353	+ }
1283	1354
1284	1355	chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1285	1356	chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
..	..	@@ -1297,6 +1368,9 @@
1297	1368	dev_warn(&spi->dev,
1298	1369	"in setup: DMA burst size reduced to match bits_per_word\n");
1299	1370	}
	1371	+ dev_dbg(&spi->dev,
	1372	+ "in setup: DMA burst size set to %u\n",
	1373	+ chip->dma_burst_size);
1300	1374	}
1301	1375
1302	1376	switch (drv_data->ssp_type) {
..	..	@@ -1342,7 +1416,11 @@
1342	1416	if (drv_data->ssp_type == CE4100_SSP)
1343	1417	return 0;
1344	1418
1345		- return setup_cs(spi, chip, chip_info);
	1419	+ err = setup_cs(spi, chip, chip_info);
	1420	+ if (err)
	1421	+ kfree(chip);
	1422	+
	1423	+ return err;
1346	1424	}
1347	1425
1348	1426	static void cleanup(struct spi_device *spi)
..	..	@@ -1361,9 +1439,7 @@
1361	1439	kfree(chip);
1362	1440	}
1363	1441
1364		-#ifdef CONFIG_PCI
1365	1442	#ifdef CONFIG_ACPI
1366		-
1367	1443	static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1368	1444	{ "INT33C0", LPSS_LPT_SSP },
1369	1445	{ "INT33C1", LPSS_LPT_SSP },
..	..	@@ -1374,22 +1450,6 @@
1374	1450	{ },
1375	1451	};
1376	1452	MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1377		-
1378		-static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1379		-{
1380		- unsigned int devid;
1381		- int port_id = -1;
1382		-
1383		- if (adev && adev->pnp.unique_id &&
1384		- !kstrtouint(adev->pnp.unique_id, 0, &devid))
1385		- port_id = devid;
1386		- return port_id;
1387		-}
1388		-#else /* !CONFIG_ACPI */
1389		-static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1390		-{
1391		- return -1;
1392		-}
1393	1453	#endif
1394	1454
1395	1455	/*
..	..	@@ -1407,6 +1467,9 @@
1407	1467	/* KBL-H */
1408	1468	{ PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1409	1469	{ PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
	1470	+ /* CML-V */
	1471	+ { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
	1472	+ { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
1410	1473	/* BXT A-Step */
1411	1474	{ PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1412	1475	{ PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
..	..	@@ -1423,6 +1486,19 @@
1423	1486	{ PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1424	1487	{ PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1425	1488	{ PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
	1489	+ /* EHL */
	1490	+ { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
	1491	+ { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
	1492	+ { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
	1493	+ /* JSL */
	1494	+ { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
	1495	+ { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
	1496	+ { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
	1497	+ /* TGL-H */
	1498	+ { PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP },
	1499	+ { PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
	1500	+ { PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
	1501	+ { PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
1426	1502	/* APL */
1427	1503	{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1428	1504	{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
..	..	@@ -1435,94 +1511,133 @@
1435	1511	{ PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1436	1512	{ PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1437	1513	{ PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
	1514	+ /* CML-LP */
	1515	+ { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
	1516	+ { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
	1517	+ { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
	1518	+ /* CML-H */
	1519	+ { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
	1520	+ { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
	1521	+ { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
	1522	+ /* TGL-LP */
	1523	+ { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
	1524	+ { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
	1525	+ { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
	1526	+ { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
	1527	+ { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
	1528	+ { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
	1529	+ { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1438	1530	{ },
1439	1531	};
	1532	+
	1533	+static const struct of_device_id pxa2xx_spi_of_match[] = {
	1534	+ { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
	1535	+ {},
	1536	+};
	1537	+MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
	1538	+
	1539	+#ifdef CONFIG_ACPI
	1540	+
	1541	+static int pxa2xx_spi_get_port_id(struct device *dev)
	1542	+{
	1543	+ struct acpi_device *adev;
	1544	+ unsigned int devid;
	1545	+ int port_id = -1;
	1546	+
	1547	+ adev = ACPI_COMPANION(dev);
	1548	+ if (adev && adev->pnp.unique_id &&
	1549	+ !kstrtouint(adev->pnp.unique_id, 0, &devid))
	1550	+ port_id = devid;
	1551	+ return port_id;
	1552	+}
	1553	+
	1554	+#else /* !CONFIG_ACPI */
	1555	+
	1556	+static int pxa2xx_spi_get_port_id(struct device *dev)
	1557	+{
	1558	+ return -1;
	1559	+}
	1560	+
	1561	+#endif /* CONFIG_ACPI */
	1562	+
	1563	+
	1564	+#ifdef CONFIG_PCI
1440	1565
1441	1566	static bool pxa2xx_spi_idma_filter(struct dma_chan chan, void param)
1442	1567	{
1443	1568	return param == chan->device->dev;
1444	1569	}
1445	1570
1446		-static struct pxa2xx_spi_master *
	1571	+#endif /* CONFIG_PCI */
	1572	+
	1573	+static struct pxa2xx_spi_controller *
1447	1574	pxa2xx_spi_init_pdata(struct platform_device *pdev)
1448	1575	{
1449		- struct pxa2xx_spi_master *pdata;
1450		- struct acpi_device *adev;
	1576	+ struct pxa2xx_spi_controller *pdata;
1451	1577	struct ssp_device *ssp;
1452	1578	struct resource *res;
1453		- const struct acpi_device_id *adev_id = NULL;
	1579	+ struct device *parent = pdev->dev.parent;
	1580	+ struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
1454	1581	const struct pci_device_id *pcidev_id = NULL;
1455		- int type;
	1582	+ enum pxa_ssp_type type;
	1583	+ const void *match;
1456	1584
1457		- adev = ACPI_COMPANION(&pdev->dev);
	1585	+ if (pcidev)
	1586	+ pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
1458	1587
1459		- if (dev_is_pci(pdev->dev.parent))
1460		- pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1461		- to_pci_dev(pdev->dev.parent));
1462		- else if (adev)
1463		- adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1464		- &pdev->dev);
1465		- else
1466		- return NULL;
1467		-
1468		- if (adev_id)
1469		- type = (int)adev_id->driver_data;
	1588	+ match = device_get_match_data(&pdev->dev);
	1589	+ if (match)
	1590	+ type = (enum pxa_ssp_type)match;
1470	1591	else if (pcidev_id)
1471		- type = (int)pcidev_id->driver_data;
	1592	+ type = (enum pxa_ssp_type)pcidev_id->driver_data;
1472	1593	else
1473		- return NULL;
	1594	+ return ERR_PTR(-EINVAL);
1474	1595
1475	1596	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1476	1597	if (!pdata)
1477		- return NULL;
1478		-
1479		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1480		- if (!res)
1481		- return NULL;
	1598	+ return ERR_PTR(-ENOMEM);
1482	1599
1483	1600	ssp = &pdata->ssp;
1484	1601
1485		- ssp->phys_base = res->start;
	1602	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1486	1603	ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1487	1604	if (IS_ERR(ssp->mmio_base))
1488		- return NULL;
	1605	+ return ERR_CAST(ssp->mmio_base);
1489	1606
	1607	+ ssp->phys_base = res->start;
	1608	+
	1609	+#ifdef CONFIG_PCI
1490	1610	if (pcidev_id) {
1491		- pdata->tx_param = pdev->dev.parent;
1492		- pdata->rx_param = pdev->dev.parent;
	1611	+ pdata->tx_param = parent;
	1612	+ pdata->rx_param = parent;
1493	1613	pdata->dma_filter = pxa2xx_spi_idma_filter;
1494	1614	}
	1615	+#endif
1495	1616
1496	1617	ssp->clk = devm_clk_get(&pdev->dev, NULL);
1497	1618	if (IS_ERR(ssp->clk))
1498		- return NULL;
	1619	+ return ERR_CAST(ssp->clk);
1499	1620
1500	1621	ssp->irq = platform_get_irq(pdev, 0);
1501	1622	if (ssp->irq < 0)
1502		- return NULL;
	1623	+ return ERR_PTR(ssp->irq);
1503	1624
1504	1625	ssp->type = type;
1505		- ssp->pdev = pdev;
1506		- ssp->port_id = pxa2xx_spi_get_port_id(adev);
	1626	+ ssp->dev = &pdev->dev;
	1627	+ ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
1507	1628
	1629	+ pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
1508	1630	pdata->num_chipselect = 1;
1509	1631	pdata->enable_dma = true;
	1632	+ pdata->dma_burst_size = 1;
1510	1633
1511	1634	return pdata;
1512	1635	}
1513	1636
1514		-#else /* !CONFIG_PCI */
1515		-static inline struct pxa2xx_spi_master *
1516		-pxa2xx_spi_init_pdata(struct platform_device *pdev)
1517		-{
1518		- return NULL;
1519		-}
1520		-#endif
1521		-
1522		-static int pxa2xx_spi_fw_translate_cs(struct spi_controller *master,
	1637	+static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1523	1638	unsigned int cs)
1524	1639	{
1525		- struct driver_data *drv_data = spi_controller_get_devdata(master);
	1640	+ struct driver_data *drv_data = spi_controller_get_devdata(controller);
1526	1641
1527	1642	if (has_acpi_companion(&drv_data->pdev->dev)) {
1528	1643	switch (drv_data->ssp_type) {
..	..	@@ -1543,11 +1658,16 @@
1543	1658	return cs;
1544	1659	}
1545	1660
	1661	+static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
	1662	+{
	1663	+ return MAX_DMA_LEN;
	1664	+}
	1665	+
1546	1666	static int pxa2xx_spi_probe(struct platform_device *pdev)
1547	1667	{
1548	1668	struct device *dev = &pdev->dev;
1549		- struct pxa2xx_spi_master *platform_info;
1550		- struct spi_controller *master;
	1669	+ struct pxa2xx_spi_controller *platform_info;
	1670	+ struct spi_controller *controller;
1551	1671	struct driver_data *drv_data;
1552	1672	struct ssp_device *ssp;
1553	1673	const struct lpss_config *config;
..	..	@@ -1557,9 +1677,9 @@
1557	1677	platform_info = dev_get_platdata(dev);
1558	1678	if (!platform_info) {
1559	1679	platform_info = pxa2xx_spi_init_pdata(pdev);
1560		- if (!platform_info) {
	1680	+ if (IS_ERR(platform_info)) {
1561	1681	dev_err(&pdev->dev, "missing platform data\n");
1562		- return -ENODEV;
	1682	+ return PTR_ERR(platform_info);
1563	1683	}
1564	1684	}
1565	1685
..	..	@@ -1572,33 +1692,38 @@
1572	1692	return -ENODEV;
1573	1693	}
1574	1694
1575		- master = devm_spi_alloc_master(dev, sizeof(*drv_data));
1576		- if (!master) {
1577		- dev_err(&pdev->dev, "cannot alloc spi_master\n");
	1695	+ if (platform_info->is_slave)
	1696	+ controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
	1697	+ else
	1698	+ controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
	1699	+
	1700	+ if (!controller) {
	1701	+ dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1578	1702	pxa_ssp_free(ssp);
1579	1703	return -ENOMEM;
1580	1704	}
1581		- drv_data = spi_controller_get_devdata(master);
1582		- drv_data->master = master;
1583		- drv_data->master_info = platform_info;
	1705	+ drv_data = spi_controller_get_devdata(controller);
	1706	+ drv_data->controller = controller;
	1707	+ drv_data->controller_info = platform_info;
1584	1708	drv_data->pdev = pdev;
1585	1709	drv_data->ssp = ssp;
1586	1710
1587		- master->dev.of_node = pdev->dev.of_node;
	1711	+ controller->dev.of_node = pdev->dev.of_node;
1588	1712	/* the spi->mode bits understood by this driver: */
1589		- master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_LOOP;
	1713	+ controller->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_LOOP;
1590	1714
1591		- master->bus_num = ssp->port_id;
1592		- master->dma_alignment = DMA_ALIGNMENT;
1593		- master->cleanup = cleanup;
1594		- master->setup = setup;
1595		- master->set_cs = pxa2xx_spi_set_cs;
1596		- master->transfer_one = pxa2xx_spi_transfer_one;
1597		- master->handle_err = pxa2xx_spi_handle_err;
1598		- master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1599		- master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1600		- master->auto_runtime_pm = true;
1601		- master->flags = SPI_CONTROLLER_MUST_RX \| SPI_CONTROLLER_MUST_TX;
	1715	+ controller->bus_num = ssp->port_id;
	1716	+ controller->dma_alignment = DMA_ALIGNMENT;
	1717	+ controller->cleanup = cleanup;
	1718	+ controller->setup = setup;
	1719	+ controller->set_cs = pxa2xx_spi_set_cs;
	1720	+ controller->transfer_one = pxa2xx_spi_transfer_one;
	1721	+ controller->slave_abort = pxa2xx_spi_slave_abort;
	1722	+ controller->handle_err = pxa2xx_spi_handle_err;
	1723	+ controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
	1724	+ controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
	1725	+ controller->auto_runtime_pm = true;
	1726	+ controller->flags = SPI_CONTROLLER_MUST_RX \| SPI_CONTROLLER_MUST_TX;
1602	1727
1603	1728	drv_data->ssp_type = ssp->type;
1604	1729
..	..	@@ -1607,10 +1732,10 @@
1607	1732	if (pxa25x_ssp_comp(drv_data)) {
1608	1733	switch (drv_data->ssp_type) {
1609	1734	case QUARK_X1000_SSP:
1610		- master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
	1735	+ controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1611	1736	break;
1612	1737	default:
1613		- master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
	1738	+ controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1614	1739	break;
1615	1740	}
1616	1741
..	..	@@ -1619,29 +1744,32 @@
1619	1744	drv_data->clear_sr = SSSR_ROR;
1620	1745	drv_data->mask_sr = SSSR_RFS \| SSSR_TFS \| SSSR_ROR;
1621	1746	} else {
1622		- master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
	1747	+ controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1623	1748	drv_data->int_cr1 = SSCR1_TIE \| SSCR1_RIE \| SSCR1_TINTE;
1624	1749	drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1625	1750	drv_data->clear_sr = SSSR_ROR \| SSSR_TINT;
1626		- drv_data->mask_sr = SSSR_TINT \| SSSR_RFS \| SSSR_TFS \| SSSR_ROR;
	1751	+ drv_data->mask_sr = SSSR_TINT \| SSSR_RFS \| SSSR_TFS
	1752	+ \| SSSR_ROR \| SSSR_TUR;
1627	1753	}
1628	1754
1629	1755	status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1630	1756	drv_data);
1631	1757	if (status < 0) {
1632	1758	dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1633		- goto out_error_master_alloc;
	1759	+ goto out_error_controller_alloc;
1634	1760	}
1635	1761
1636	1762	/* Setup DMA if requested */
1637	1763	if (platform_info->enable_dma) {
1638	1764	status = pxa2xx_spi_dma_setup(drv_data);
1639	1765	if (status) {
1640		- dev_dbg(dev, "no DMA channels available, using PIO\n");
	1766	+ dev_warn(dev, "no DMA channels available, using PIO\n");
1641	1767	platform_info->enable_dma = false;
1642	1768	} else {
1643		- master->can_dma = pxa2xx_spi_can_dma;
1644		- master->max_dma_len = MAX_DMA_LEN;
	1769	+ controller->can_dma = pxa2xx_spi_can_dma;
	1770	+ controller->max_dma_len = MAX_DMA_LEN;
	1771	+ controller->max_transfer_size =
	1772	+ pxa2xx_spi_max_dma_transfer_size;
1645	1773	}
1646	1774	}
1647	1775
..	..	@@ -1650,7 +1778,17 @@
1650	1778	if (status)
1651	1779	goto out_error_dma_irq_alloc;
1652	1780
1653		- master->max_speed_hz = clk_get_rate(ssp->clk);
	1781	+ controller->max_speed_hz = clk_get_rate(ssp->clk);
	1782	+ /*
	1783	+ * Set minimum speed for all other platforms than Intel Quark which is
	1784	+ * able do under 1 Hz transfers.
	1785	+ */
	1786	+ if (!pxa25x_ssp_comp(drv_data))
	1787	+ controller->min_speed_hz =
	1788	+ DIV_ROUND_UP(controller->max_speed_hz, 4096);
	1789	+ else if (!is_quark_x1000_ssp(drv_data))
	1790	+ controller->min_speed_hz =
	1791	+ DIV_ROUND_UP(controller->max_speed_hz, 512);
1654	1792
1655	1793	/* Load default SSP configuration */
1656	1794	pxa2xx_spi_write(drv_data, SSCR0, 0);
..	..	@@ -1672,10 +1810,22 @@
1672	1810	pxa2xx_spi_write(drv_data, SSCR0, tmp);
1673	1811	break;
1674	1812	default:
1675		- tmp = SSCR1_RxTresh(RX_THRESH_DFLT) \|
1676		- SSCR1_TxTresh(TX_THRESH_DFLT);
	1813	+
	1814	+ if (spi_controller_is_slave(controller)) {
	1815	+ tmp = SSCR1_SCFR \|
	1816	+ SSCR1_SCLKDIR \|
	1817	+ SSCR1_SFRMDIR \|
	1818	+ SSCR1_RxTresh(2) \|
	1819	+ SSCR1_TxTresh(1) \|
	1820	+ SSCR1_SPH;
	1821	+ } else {
	1822	+ tmp = SSCR1_RxTresh(RX_THRESH_DFLT) \|
	1823	+ SSCR1_TxTresh(TX_THRESH_DFLT);
	1824	+ }
1677	1825	pxa2xx_spi_write(drv_data, SSCR1, tmp);
1678		- tmp = SSCR0_SCR(2) \| SSCR0_Motorola \| SSCR0_DataSize(8);
	1826	+ tmp = SSCR0_Motorola \| SSCR0_DataSize(8);
	1827	+ if (!spi_controller_is_slave(controller))
	1828	+ tmp \|= SSCR0_SCR(2);
1679	1829	pxa2xx_spi_write(drv_data, SSCR0, tmp);
1680	1830	break;
1681	1831	}
..	..	@@ -1699,24 +1849,24 @@
1699	1849	platform_info->num_chipselect = config->cs_num;
1700	1850	}
1701	1851	}
1702		- master->num_chipselect = platform_info->num_chipselect;
	1852	+ controller->num_chipselect = platform_info->num_chipselect;
1703	1853
1704	1854	count = gpiod_count(&pdev->dev, "cs");
1705	1855	if (count > 0) {
1706	1856	int i;
1707	1857
1708		- master->num_chipselect = max_t(int, count,
1709		- master->num_chipselect);
	1858	+ controller->num_chipselect = max_t(int, count,
	1859	+ controller->num_chipselect);
1710	1860
1711	1861	drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1712		- master->num_chipselect, sizeof(struct gpio_desc *),
	1862	+ controller->num_chipselect, sizeof(struct gpio_desc *),
1713	1863	GFP_KERNEL);
1714	1864	if (!drv_data->cs_gpiods) {
1715	1865	status = -ENOMEM;
1716	1866	goto out_error_clock_enabled;
1717	1867	}
1718	1868
1719		- for (i = 0; i < master->num_chipselect; i++) {
	1869	+ for (i = 0; i < controller->num_chipselect; i++) {
1720	1870	struct gpio_desc *gpiod;
1721	1871
1722	1872	gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
..	..	@@ -1725,11 +1875,20 @@
1725	1875	if (PTR_ERR(gpiod) == -ENOENT)
1726	1876	continue;
1727	1877
1728		- status = (int)PTR_ERR(gpiod);
	1878	+ status = PTR_ERR(gpiod);
1729	1879	goto out_error_clock_enabled;
1730	1880	} else {
1731	1881	drv_data->cs_gpiods[i] = gpiod;
1732	1882	}
	1883	+ }
	1884	+ }
	1885	+
	1886	+ if (platform_info->is_slave) {
	1887	+ drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
	1888	+ "ready", GPIOD_OUT_LOW);
	1889	+ if (IS_ERR(drv_data->gpiod_ready)) {
	1890	+ status = PTR_ERR(drv_data->gpiod_ready);
	1891	+ goto out_error_clock_enabled;
1733	1892	}
1734	1893	}
1735	1894
..	..	@@ -1740,9 +1899,9 @@
1740	1899
1741	1900	/* Register with the SPI framework */
1742	1901	platform_set_drvdata(pdev, drv_data);
1743		- status = spi_register_controller(master);
	1902	+ status = spi_register_controller(controller);
1744	1903	if (status != 0) {
1745		- dev_err(&pdev->dev, "problem registering spi master\n");
	1904	+ dev_err(&pdev->dev, "problem registering spi controller\n");
1746	1905	goto out_error_pm_runtime_enabled;
1747	1906	}
1748	1907
..	..	@@ -1758,7 +1917,7 @@
1758	1917	pxa2xx_spi_dma_release(drv_data);
1759	1918	free_irq(ssp->irq, drv_data);
1760	1919
1761		-out_error_master_alloc:
	1920	+out_error_controller_alloc:
1762	1921	pxa_ssp_free(ssp);
1763	1922	return status;
1764	1923	}
..	..	@@ -1766,22 +1925,18 @@
1766	1925	static int pxa2xx_spi_remove(struct platform_device *pdev)
1767	1926	{
1768	1927	struct driver_data *drv_data = platform_get_drvdata(pdev);
1769		- struct ssp_device *ssp;
1770		-
1771		- if (!drv_data)
1772		- return 0;
1773		- ssp = drv_data->ssp;
	1928	+ struct ssp_device *ssp = drv_data->ssp;
1774	1929
1775	1930	pm_runtime_get_sync(&pdev->dev);
1776	1931
1777		- spi_unregister_controller(drv_data->master);
	1932	+ spi_unregister_controller(drv_data->controller);
1778	1933
1779	1934	/* Disable the SSP at the peripheral and SOC level */
1780	1935	pxa2xx_spi_write(drv_data, SSCR0, 0);
1781	1936	clk_disable_unprepare(ssp->clk);
1782	1937
1783	1938	/* Release DMA */
1784		- if (drv_data->master_info->enable_dma)
	1939	+ if (drv_data->controller_info->enable_dma)
1785	1940	pxa2xx_spi_dma_release(drv_data);
1786	1941
1787	1942	pm_runtime_put_noidle(&pdev->dev);
..	..	@@ -1796,14 +1951,6 @@
1796	1951	return 0;
1797	1952	}
1798	1953
1799		-static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1800		-{
1801		- int status = 0;
1802		-
1803		- if ((status = pxa2xx_spi_remove(pdev)) != 0)
1804		- dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1805		-}
1806		-
1807	1954	#ifdef CONFIG_PM_SLEEP
1808	1955	static int pxa2xx_spi_suspend(struct device *dev)
1809	1956	{
..	..	@@ -1811,7 +1958,7 @@
1811	1958	struct ssp_device *ssp = drv_data->ssp;
1812	1959	int status;
1813	1960
1814		- status = spi_controller_suspend(drv_data->master);
	1961	+ status = spi_controller_suspend(drv_data->controller);
1815	1962	if (status != 0)
1816	1963	return status;
1817	1964	pxa2xx_spi_write(drv_data, SSCR0, 0);
..	..	@@ -1835,18 +1982,8 @@
1835	1982	return status;
1836	1983	}
1837	1984
1838		- /* Restore LPSS private register bits */
1839		- if (is_lpss_ssp(drv_data))
1840		- lpss_ssp_setup(drv_data);
1841		-
1842	1985	/* Start the queue running */
1843		- status = spi_controller_resume(drv_data->master);
1844		- if (status != 0) {
1845		- dev_err(dev, "problem starting queue (%d)\n", status);
1846		- return status;
1847		- }
1848		-
1849		- return 0;
	1986	+ return spi_controller_resume(drv_data->controller);
1850	1987	}
1851	1988	#endif
1852	1989
..	..	@@ -1880,10 +2017,10 @@
1880	2017	.name = "pxa2xx-spi",
1881	2018	.pm = &pxa2xx_spi_pm_ops,
1882	2019	.acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
	2020	+ .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1883	2021	},
1884	2022	.probe = pxa2xx_spi_probe,
1885	2023	.remove = pxa2xx_spi_remove,
1886		- .shutdown = pxa2xx_spi_shutdown,
1887	2024	};
1888	2025
1889	2026	static int __init pxa2xx_spi_init(void)
..	..	@@ -1897,3 +2034,5 @@
1897	2034	platform_driver_unregister(&driver);
1898	2035	}
1899	2036	module_exit(pxa2xx_spi_exit);
	2037	+
	2038	+MODULE_SOFTDEP("pre: dw_dmac");