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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/spi/spi-pxa2xx-dma.c
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@@ -1,12 +1,9 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * PXA2xx SPI DMA engine support.
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  *
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  * Copyright (C) 2013, Intel Corporation
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  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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8
 
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 #include <linux/device.h>
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@@ -23,7 +20,7 @@
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 static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
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 					     bool error)
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 {
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-	struct spi_message *msg = drv_data->master->cur_msg;
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+	struct spi_message *msg = drv_data->controller->cur_msg;
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 	/*
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 	 * It is possible that one CPU is handling ROR interrupt and other
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@@ -59,7 +56,7 @@
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 			msg->status = -EIO;
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 		}
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-		spi_finalize_current_transfer(drv_data->master);
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+		spi_finalize_current_transfer(drv_data->controller);
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 	}
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 }
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@@ -74,7 +71,7 @@
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 			   struct spi_transfer *xfer)
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 {
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 	struct chip_data *chip =
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-		spi_get_ctldata(drv_data->master->cur_msg->spi);
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+		spi_get_ctldata(drv_data->controller->cur_msg->spi);
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 	enum dma_slave_buswidth width;
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 	struct dma_slave_config cfg;
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 	struct dma_chan *chan;
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@@ -102,14 +99,14 @@
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 		cfg.dst_maxburst = chip->dma_burst_size;
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 		sgt = &xfer->tx_sg;
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-		chan = drv_data->master->dma_tx;
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+		chan = drv_data->controller->dma_tx;
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 	} else {
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 		cfg.src_addr = drv_data->ssdr_physical;
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 		cfg.src_addr_width = width;
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 		cfg.src_maxburst = chip->dma_burst_size;
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 		sgt = &xfer->rx_sg;
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-		chan = drv_data->master->dma_rx;
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+		chan = drv_data->controller->dma_rx;
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 	}
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 	ret = dmaengine_slave_config(chan, &cfg);
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@@ -130,8 +127,8 @@
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 	if (status & SSSR_ROR) {
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 		dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
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-		dmaengine_terminate_async(drv_data->master->dma_rx);
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-		dmaengine_terminate_async(drv_data->master->dma_tx);
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+		dmaengine_terminate_async(drv_data->controller->dma_rx);
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+		dmaengine_terminate_async(drv_data->controller->dma_tx);
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 		pxa2xx_spi_dma_transfer_complete(drv_data, true);
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 		return IRQ_HANDLED;
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@@ -171,15 +168,15 @@
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 	return 0;
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 err_rx:
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-	dmaengine_terminate_async(drv_data->master->dma_tx);
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+	dmaengine_terminate_async(drv_data->controller->dma_tx);
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 err_tx:
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 	return err;
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 }
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 void pxa2xx_spi_dma_start(struct driver_data *drv_data)
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 {
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-	dma_async_issue_pending(drv_data->master->dma_rx);
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-	dma_async_issue_pending(drv_data->master->dma_tx);
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+	dma_async_issue_pending(drv_data->controller->dma_rx);
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+	dma_async_issue_pending(drv_data->controller->dma_tx);
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 	atomic_set(&drv_data->dma_running, 1);
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 }
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@@ -187,30 +184,30 @@
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 void pxa2xx_spi_dma_stop(struct driver_data *drv_data)
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 {
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 	atomic_set(&drv_data->dma_running, 0);
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-	dmaengine_terminate_sync(drv_data->master->dma_rx);
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-	dmaengine_terminate_sync(drv_data->master->dma_tx);
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+	dmaengine_terminate_sync(drv_data->controller->dma_rx);
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+	dmaengine_terminate_sync(drv_data->controller->dma_tx);
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 }
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 int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
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 {
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-	struct pxa2xx_spi_master *pdata = drv_data->master_info;
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+	struct pxa2xx_spi_controller *pdata = drv_data->controller_info;
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 	struct device *dev = &drv_data->pdev->dev;
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-	struct spi_controller *master = drv_data->master;
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+	struct spi_controller *controller = drv_data->controller;
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 	dma_cap_mask_t mask;
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 	dma_cap_zero(mask);
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 	dma_cap_set(DMA_SLAVE, mask);
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-	master->dma_tx = dma_request_slave_channel_compat(mask,
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+	controller->dma_tx = dma_request_slave_channel_compat(mask,
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 				pdata->dma_filter, pdata->tx_param, dev, "tx");
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-	if (!master->dma_tx)
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+	if (!controller->dma_tx)
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 		return -ENODEV;
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-	master->dma_rx = dma_request_slave_channel_compat(mask,
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+	controller->dma_rx = dma_request_slave_channel_compat(mask,
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 				pdata->dma_filter, pdata->rx_param, dev, "rx");
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-	if (!master->dma_rx) {
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-		dma_release_channel(master->dma_tx);
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-		master->dma_tx = NULL;
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+	if (!controller->dma_rx) {
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+		dma_release_channel(controller->dma_tx);
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+		controller->dma_tx = NULL;
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 		return -ENODEV;
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 	}
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@@ -219,17 +216,17 @@
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 void pxa2xx_spi_dma_release(struct driver_data *drv_data)
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 {
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-	struct spi_controller *master = drv_data->master;
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+	struct spi_controller *controller = drv_data->controller;
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-	if (master->dma_rx) {
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-		dmaengine_terminate_sync(master->dma_rx);
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-		dma_release_channel(master->dma_rx);
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-		master->dma_rx = NULL;
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+	if (controller->dma_rx) {
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+		dmaengine_terminate_sync(controller->dma_rx);
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+		dma_release_channel(controller->dma_rx);
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+		controller->dma_rx = NULL;
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 	}
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-	if (master->dma_tx) {
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-		dmaengine_terminate_sync(master->dma_tx);
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-		dma_release_channel(master->dma_tx);
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-		master->dma_tx = NULL;
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+	if (controller->dma_tx) {
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+		dmaengine_terminate_sync(controller->dma_tx);
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+		dma_release_channel(controller->dma_tx);
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+		controller->dma_tx = NULL;
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 	}
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 }
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@@ -239,13 +236,15 @@
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 					   u32 *threshold)
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 {
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 	struct pxa2xx_spi_chip *chip_info = spi->controller_data;
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+	struct driver_data *drv_data = spi_controller_get_devdata(spi->controller);
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+	u32 dma_burst_size = drv_data->controller_info->dma_burst_size;
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 	/*
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 	 * If the DMA burst size is given in chip_info we use that,
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 	 * otherwise we use the default. Also we use the default FIFO
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 	 * thresholds for now.
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 	 */
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-	*burst_code = chip_info ? chip_info->dma_burst_size : 1;
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+	*burst_code = chip_info ? chip_info->dma_burst_size : dma_burst_size;
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 	*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
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 		   | SSCR1_TxTresh(TX_THRESH_DFLT);
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