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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/spi/spi-orion.c
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@@ -1,12 +1,9 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Marvell Orion SPI controller driver
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  *
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  * Author: Shadi Ammouri <shadi@marvell.com>
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  * Copyright (C) 2007-2008 Marvell Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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8
 
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 #include <linux/interrupt.h>
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@@ -20,10 +17,8 @@
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 #include <linux/of.h>
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 #include <linux/of_address.h>
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 #include <linux/of_device.h>
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-#include <linux/of_gpio.h>
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 #include <linux/clk.h>
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 #include <linux/sizes.h>
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-#include <linux/gpio.h>
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 #include <asm/unaligned.h>
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 #define DRIVER_NAME			"orion_spi"
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@@ -101,7 +96,6 @@
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 	struct clk              *clk;
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 	struct clk              *axi_clk;
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 	const struct orion_spi_dev *devdata;
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-	int			unused_hw_gpio;
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 	struct orion_child_options	child[ORION_NUM_CHIPSELECTS];
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 };
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@@ -328,20 +322,27 @@
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 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
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 {
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 	struct orion_spi *orion_spi;
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-	int cs;
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 	orion_spi = spi_master_get_devdata(spi->master);
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-	if (gpio_is_valid(spi->cs_gpio))
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-		cs = orion_spi->unused_hw_gpio;
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-	else
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-		cs = spi->chip_select;
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-
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+	/*
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+	 * If this line is using a GPIO to control chip select, this internal
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+	 * .set_cs() function will still be called, so we clear any previous
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+	 * chip select. The CS we activate will not have any elecrical effect,
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+	 * as it is handled by a GPIO, but that doesn't matter. What we need
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+	 * is to deassert the old chip select and assert some other chip select.
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+	 */
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 	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
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 	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
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-				ORION_SPI_CS(cs));
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+			  ORION_SPI_CS(spi->chip_select));
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-	/* Chip select logic is inverted from spi_set_cs */
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+	/*
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+	 * Chip select logic is inverted from spi_set_cs(). For lines using a
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+	 * GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens
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+	 * in the GPIO library, but we don't care about that, because in those
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+	 * cases we are dealing with an unused native CS anyways so the polarity
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+	 * doesn't matter.
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+	 */
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 	if (!enable)
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 		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
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 	else
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@@ -431,6 +432,7 @@
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 	int word_len;
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 	struct orion_spi *orion_spi;
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 	int cs = spi->chip_select;
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+	void __iomem *vaddr;
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 	word_len = spi->bits_per_word;
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 	count = xfer->len;
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@@ -441,8 +443,9 @@
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 	 * Use SPI direct write mode if base address is available. Otherwise
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 	 * fall back to PIO mode for this transfer.
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 	 */
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-	if ((orion_spi->child[cs].direct_access.vaddr) && (xfer->tx_buf) &&
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-	    (word_len == 8)) {
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+	vaddr = orion_spi->child[cs].direct_access.vaddr;
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+
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+	if (vaddr && xfer->tx_buf && word_len == 8) {
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 		unsigned int cnt = count / 4;
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 		unsigned int rem = count % 4;
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@@ -450,13 +453,11 @@
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 		 * Send the TX-data to the SPI device via the direct
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 		 * mapped address window
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 		 */
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-		iowrite32_rep(orion_spi->child[cs].direct_access.vaddr,
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-			      xfer->tx_buf, cnt);
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+		iowrite32_rep(vaddr, xfer->tx_buf, cnt);
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 		if (rem) {
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 			u32 *buf = (u32 *)xfer->tx_buf;
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-			iowrite8_rep(orion_spi->child[cs].direct_access.vaddr,
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-				     &buf[cnt], rem);
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+			iowrite8_rep(vaddr, &buf[cnt], rem);
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 		}
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 		return count;
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@@ -470,6 +471,7 @@
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 			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
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 				goto out;
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 			count--;
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+			spi_delay_exec(&xfer->word_delay, xfer);
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 		} while (count);
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 	} else if (word_len == 16) {
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 		const u16 *tx = xfer->tx_buf;
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@@ -479,6 +481,7 @@
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 			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
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 				goto out;
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 			count -= 2;
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+			spi_delay_exec(&xfer->word_delay, xfer);
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 		} while (count);
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 	}
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@@ -504,9 +507,6 @@
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 static int orion_spi_setup(struct spi_device *spi)
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 {
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-	if (gpio_is_valid(spi->cs_gpio)) {
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-		gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
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-	}
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 	return orion_spi_setup_transfer(spi, NULL);
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 }
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@@ -623,13 +623,13 @@
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 	master->setup = orion_spi_setup;
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 	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
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 	master->auto_runtime_pm = true;
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+	master->use_gpio_descriptors = true;
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 	master->flags = SPI_MASTER_GPIO_SS;
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 	platform_set_drvdata(pdev, master);
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 	spi = spi_master_get_devdata(master);
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 	spi->master = master;
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-	spi->unused_hw_gpio = -1;
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 	of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
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 	devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
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@@ -647,8 +647,7 @@
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 	/* The following clock is only used by some SoCs */
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 	spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
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-	if (IS_ERR(spi->axi_clk) &&
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-	    PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
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+	if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
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 		status = -EPROBE_DEFER;
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 		goto out_rel_clk;
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 	}
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@@ -683,8 +682,8 @@
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 	}
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 	for_each_available_child_of_node(pdev->dev.of_node, np) {
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+		struct orion_direct_acc *dir_acc;
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 		u32 cs;
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-		int cs_gpio;
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 		/* Get chip-select number from the "reg" property */
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 		status = of_property_read_u32(np, "reg", &cs);
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@@ -693,44 +692,6 @@
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 				"%pOF has no valid 'reg' property (%d)\n",
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 				np, status);
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 			continue;
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-		}
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-
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-		/*
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-		 * Initialize the CS GPIO:
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-		 * - properly request the actual GPIO signal
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-		 * - de-assert the logical signal so that all GPIO CS lines
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-		 *   are inactive when probing for slaves
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-		 * - find an unused physical CS which will be driven for any
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-		 *   slave which uses a CS GPIO
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-		 */
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-		cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", cs);
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-		if (cs_gpio > 0) {
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-			char *gpio_name;
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-			int cs_flags;
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-
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-			if (spi->unused_hw_gpio == -1) {
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-				dev_info(&pdev->dev,
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-					"Selected unused HW CS#%d for any GPIO CSes\n",
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-					cs);
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-				spi->unused_hw_gpio = cs;
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-			}
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-
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-			gpio_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
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-					"%s-CS%d", dev_name(&pdev->dev), cs);
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-			if (!gpio_name) {
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-				status = -ENOMEM;
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-				goto out_rel_axi_clk;
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-			}
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-
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-			cs_flags = of_property_read_bool(np, "spi-cs-high") ?
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-				GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
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-			status = devm_gpio_request_one(&pdev->dev, cs_gpio,
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-					cs_flags, gpio_name);
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-			if (status) {
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-				dev_err(&pdev->dev,
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-					"Can't request GPIO for CS %d\n", cs);
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-				goto out_rel_axi_clk;
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-			}
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 		}
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 		/*
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@@ -747,17 +708,16 @@
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 		/*
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 		 * Only map one page for direct access. This is enough for the
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 		 * simple TX transfer which only writes to the first word.
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-		 * This needs to get extended for the direct SPI-NOR / SPI-NAND
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+		 * This needs to get extended for the direct SPI NOR / SPI NAND
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 		 * support, once this gets implemented.
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 		 */
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-		spi->child[cs].direct_access.vaddr = devm_ioremap(&pdev->dev,
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-							    r->start,
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-							    PAGE_SIZE);
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-		if (!spi->child[cs].direct_access.vaddr) {
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+		dir_acc = &spi->child[cs].direct_access;
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+		dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
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+		if (!dir_acc->vaddr) {
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 			status = -ENOMEM;
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 			goto out_rel_axi_clk;
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 		}
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-		spi->child[cs].direct_access.size = PAGE_SIZE;
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+		dir_acc->size = PAGE_SIZE;
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 		dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
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 	}
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@@ -770,9 +730,6 @@
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 	status = orion_spi_reset(spi);
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 	if (status < 0)
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 		goto out_rel_pm;
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-
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-	pm_runtime_mark_last_busy(&pdev->dev);
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-	pm_runtime_put_autosuspend(&pdev->dev);
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 	master->dev.of_node = pdev->dev.of_node;
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 	status = spi_register_master(master);