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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/spi/spi-omap2-mcspi.c
....@@ -1,19 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * OMAP2 McSPI controller driver
34  *
45  * Copyright (C) 2005, 2006 Nokia Corporation
56  * Author:	Samuel Ortiz <samuel.ortiz@nokia.com> and
67  *		Juha Yrj�l� <juha.yrjola@nokia.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16
- * GNU General Public License for more details.
178  */
189 
1910 #include <linux/kernel.h>
....@@ -35,7 +26,6 @@
3526 #include <linux/gcd.h>
3627 
3728 #include <linux/spi/spi.h>
38
-#include <linux/gpio.h>
3929 
4030 #include <linux/platform_data/spi-omap2-mcspi.h>
4131 
....@@ -126,6 +116,7 @@
126116 };
127117 
128118 struct omap2_mcspi {
119
+	struct completion	txdone;
129120 	struct spi_master	*master;
130121 	/* Virtual base address of the controller */
131122 	void __iomem		*base;
....@@ -135,7 +126,9 @@
135126 	struct device		*dev;
136127 	struct omap2_mcspi_regs ctx;
137128 	int			fifo_depth;
129
+	bool			slave_aborted;
138130 	unsigned int		pin_dir:1;
131
+	size_t			max_xfer_len;
139132 };
140133 
141134 struct omap2_mcspi_cs {
....@@ -274,19 +267,23 @@
274267 	}
275268 }
276269 
277
-static void omap2_mcspi_set_master_mode(struct spi_master *master)
270
+static void omap2_mcspi_set_mode(struct spi_master *master)
278271 {
279272 	struct omap2_mcspi	*mcspi = spi_master_get_devdata(master);
280273 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
281274 	u32 l;
282275 
283276 	/*
284
-	 * Setup when switching from (reset default) slave mode
285
-	 * to single-channel master mode
277
+	 * Choose master or slave mode
286278 	 */
287279 	l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
288
-	l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
289
-	l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
280
+	l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
281
+	if (spi_controller_is_slave(master)) {
282
+		l |= (OMAP2_MCSPI_MODULCTRL_MS);
283
+	} else {
284
+		l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
285
+		l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
286
+	}
290287 	mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
291288 
292289 	ctx->modulctrl = l;
....@@ -365,6 +362,20 @@
365362 	return 0;
366363 }
367364 
365
+static int mcspi_wait_for_completion(struct  omap2_mcspi *mcspi,
366
+				     struct completion *x)
367
+{
368
+	if (spi_controller_is_slave(mcspi->master)) {
369
+		if (wait_for_completion_interruptible(x) ||
370
+		    mcspi->slave_aborted)
371
+			return -EINTR;
372
+	} else {
373
+		wait_for_completion(x);
374
+	}
375
+
376
+	return 0;
377
+}
378
+
368379 static void omap2_mcspi_rx_callback(void *data)
369380 {
370381 	struct spi_device *spi = data;
....@@ -395,30 +406,26 @@
395406 {
396407 	struct omap2_mcspi	*mcspi;
397408 	struct omap2_mcspi_dma  *mcspi_dma;
409
+	struct dma_async_tx_descriptor *tx;
398410 
399411 	mcspi = spi_master_get_devdata(spi->master);
400412 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
401413 
402
-	if (mcspi_dma->dma_tx) {
403
-		struct dma_async_tx_descriptor *tx;
414
+	dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
404415 
405
-		dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
406
-
407
-		tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
408
-					     xfer->tx_sg.nents,
409
-					     DMA_MEM_TO_DEV,
410
-					     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
411
-		if (tx) {
412
-			tx->callback = omap2_mcspi_tx_callback;
413
-			tx->callback_param = spi;
414
-			dmaengine_submit(tx);
415
-		} else {
416
-			/* FIXME: fall back to PIO? */
417
-		}
416
+	tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
417
+				     xfer->tx_sg.nents,
418
+				     DMA_MEM_TO_DEV,
419
+				     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
420
+	if (tx) {
421
+		tx->callback = omap2_mcspi_tx_callback;
422
+		tx->callback_param = spi;
423
+		dmaengine_submit(tx);
424
+	} else {
425
+		/* FIXME: fall back to PIO? */
418426 	}
419427 	dma_async_issue_pending(mcspi_dma->dma_tx);
420428 	omap2_mcspi_set_dma_req(spi, 0, 1);
421
-
422429 }
423430 
424431 static unsigned
....@@ -437,6 +444,7 @@
437444 	int			word_len, element_count;
438445 	struct omap2_mcspi_cs	*cs = spi->controller_state;
439446 	void __iomem		*chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
447
+	struct dma_async_tx_descriptor *tx;
440448 
441449 	mcspi = spi_master_get_devdata(spi->master);
442450 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
....@@ -460,61 +468,58 @@
460468 	else /* word_len <= 32 */
461469 		element_count = count >> 2;
462470 
463
-	if (mcspi_dma->dma_rx) {
464
-		struct dma_async_tx_descriptor *tx;
465471 
466
-		dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
472
+	dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
467473 
474
+	/*
475
+	 *  Reduce DMA transfer length by one more if McSPI is
476
+	 *  configured in turbo mode.
477
+	 */
478
+	if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
479
+		transfer_reduction += es;
480
+
481
+	if (transfer_reduction) {
482
+		/* Split sgl into two. The second sgl won't be used. */
483
+		sizes[0] = count - transfer_reduction;
484
+		sizes[1] = transfer_reduction;
485
+		nb_sizes = 2;
486
+	} else {
468487 		/*
469
-		 *  Reduce DMA transfer length by one more if McSPI is
470
-		 *  configured in turbo mode.
488
+		 * Don't bother splitting the sgl. This essentially
489
+		 * clones the original sgl.
471490 		 */
472
-		if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
473
-			transfer_reduction += es;
491
+		sizes[0] = count;
492
+		nb_sizes = 1;
493
+	}
474494 
475
-		if (transfer_reduction) {
476
-			/* Split sgl into two. The second sgl won't be used. */
477
-			sizes[0] = count - transfer_reduction;
478
-			sizes[1] = transfer_reduction;
479
-			nb_sizes = 2;
480
-		} else {
481
-			/*
482
-			 * Don't bother splitting the sgl. This essentially
483
-			 * clones the original sgl.
484
-			 */
485
-			sizes[0] = count;
486
-			nb_sizes = 1;
487
-		}
495
+	ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes,
496
+		       sizes, sg_out, out_mapped_nents, GFP_KERNEL);
488497 
489
-		ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
490
-			       0, nb_sizes,
491
-			       sizes,
492
-			       sg_out, out_mapped_nents,
493
-			       GFP_KERNEL);
498
+	if (ret < 0) {
499
+		dev_err(&spi->dev, "sg_split failed\n");
500
+		return 0;
501
+	}
494502 
495
-		if (ret < 0) {
496
-			dev_err(&spi->dev, "sg_split failed\n");
497
-			return 0;
498
-		}
499
-
500
-		tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
501
-					     sg_out[0],
502
-					     out_mapped_nents[0],
503
-					     DMA_DEV_TO_MEM,
504
-					     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
505
-		if (tx) {
506
-			tx->callback = omap2_mcspi_rx_callback;
507
-			tx->callback_param = spi;
508
-			dmaengine_submit(tx);
509
-		} else {
510
-				/* FIXME: fall back to PIO? */
511
-		}
503
+	tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0],
504
+				     out_mapped_nents[0], DMA_DEV_TO_MEM,
505
+				     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
506
+	if (tx) {
507
+		tx->callback = omap2_mcspi_rx_callback;
508
+		tx->callback_param = spi;
509
+		dmaengine_submit(tx);
510
+	} else {
511
+		/* FIXME: fall back to PIO? */
512512 	}
513513 
514514 	dma_async_issue_pending(mcspi_dma->dma_rx);
515515 	omap2_mcspi_set_dma_req(spi, 1, 1);
516516 
517
-	wait_for_completion(&mcspi_dma->dma_rx_completion);
517
+	ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
518
+	if (ret || mcspi->slave_aborted) {
519
+		dmaengine_terminate_sync(mcspi_dma->dma_rx);
520
+		omap2_mcspi_set_dma_req(spi, 1, 0);
521
+		return 0;
522
+	}
518523 
519524 	for (x = 0; x < nb_sizes; x++)
520525 		kfree(sg_out[x]);
....@@ -613,14 +618,37 @@
613618 	rx = xfer->rx_buf;
614619 	tx = xfer->tx_buf;
615620 
616
-	if (tx != NULL)
621
+	mcspi->slave_aborted = false;
622
+	reinit_completion(&mcspi_dma->dma_tx_completion);
623
+	reinit_completion(&mcspi_dma->dma_rx_completion);
624
+	reinit_completion(&mcspi->txdone);
625
+	if (tx) {
626
+		/* Enable EOW IRQ to know end of tx in slave mode */
627
+		if (spi_controller_is_slave(spi->master))
628
+			mcspi_write_reg(spi->master,
629
+					OMAP2_MCSPI_IRQENABLE,
630
+					OMAP2_MCSPI_IRQSTATUS_EOW);
617631 		omap2_mcspi_tx_dma(spi, xfer, cfg);
632
+	}
618633 
619634 	if (rx != NULL)
620635 		count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
621636 
622637 	if (tx != NULL) {
623
-		wait_for_completion(&mcspi_dma->dma_tx_completion);
638
+		int ret;
639
+
640
+		ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
641
+		if (ret || mcspi->slave_aborted) {
642
+			dmaengine_terminate_sync(mcspi_dma->dma_tx);
643
+			omap2_mcspi_set_dma_req(spi, 0, 0);
644
+			return 0;
645
+		}
646
+
647
+		if (spi_controller_is_slave(mcspi->master)) {
648
+			ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
649
+			if (ret || mcspi->slave_aborted)
650
+				return 0;
651
+		}
624652 
625653 		if (mcspi->fifo_depth > 0) {
626654 			irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
....@@ -955,20 +983,12 @@
955983  * Note that we currently allow DMA only if we get a channel
956984  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
957985  */
958
-static int omap2_mcspi_request_dma(struct spi_device *spi)
986
+static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
987
+				   struct omap2_mcspi_dma *mcspi_dma)
959988 {
960
-	struct spi_master	*master = spi->master;
961
-	struct omap2_mcspi	*mcspi;
962
-	struct omap2_mcspi_dma	*mcspi_dma;
963989 	int ret = 0;
964990 
965
-	mcspi = spi_master_get_devdata(master);
966
-	mcspi_dma = mcspi->dma_channels + spi->chip_select;
967
-
968
-	init_completion(&mcspi_dma->dma_rx_completion);
969
-	init_completion(&mcspi_dma->dma_tx_completion);
970
-
971
-	mcspi_dma->dma_rx = dma_request_chan(&master->dev,
991
+	mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
972992 					     mcspi_dma->dma_rx_ch_name);
973993 	if (IS_ERR(mcspi_dma->dma_rx)) {
974994 		ret = PTR_ERR(mcspi_dma->dma_rx);
....@@ -976,7 +996,7 @@
976996 		goto no_dma;
977997 	}
978998 
979
-	mcspi_dma->dma_tx = dma_request_chan(&master->dev,
999
+	mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
9801000 					     mcspi_dma->dma_tx_ch_name);
9811001 	if (IS_ERR(mcspi_dma->dma_tx)) {
9821002 		ret = PTR_ERR(mcspi_dma->dma_tx);
....@@ -985,19 +1005,53 @@
9851005 		mcspi_dma->dma_rx = NULL;
9861006 	}
9871007 
1008
+	init_completion(&mcspi_dma->dma_rx_completion);
1009
+	init_completion(&mcspi_dma->dma_tx_completion);
1010
+
9881011 no_dma:
9891012 	return ret;
9901013 }
9911014 
1015
+static void omap2_mcspi_release_dma(struct spi_master *master)
1016
+{
1017
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1018
+	struct omap2_mcspi_dma	*mcspi_dma;
1019
+	int i;
1020
+
1021
+	for (i = 0; i < master->num_chipselect; i++) {
1022
+		mcspi_dma = &mcspi->dma_channels[i];
1023
+
1024
+		if (mcspi_dma->dma_rx) {
1025
+			dma_release_channel(mcspi_dma->dma_rx);
1026
+			mcspi_dma->dma_rx = NULL;
1027
+		}
1028
+		if (mcspi_dma->dma_tx) {
1029
+			dma_release_channel(mcspi_dma->dma_tx);
1030
+			mcspi_dma->dma_tx = NULL;
1031
+		}
1032
+	}
1033
+}
1034
+
1035
+static void omap2_mcspi_cleanup(struct spi_device *spi)
1036
+{
1037
+	struct omap2_mcspi_cs	*cs;
1038
+
1039
+	if (spi->controller_state) {
1040
+		/* Unlink controller state from context save list */
1041
+		cs = spi->controller_state;
1042
+		list_del(&cs->node);
1043
+
1044
+		kfree(cs);
1045
+	}
1046
+}
1047
+
9921048 static int omap2_mcspi_setup(struct spi_device *spi)
9931049 {
1050
+	bool			initial_setup = false;
9941051 	int			ret;
9951052 	struct omap2_mcspi	*mcspi = spi_master_get_devdata(spi->master);
9961053 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
997
-	struct omap2_mcspi_dma	*mcspi_dma;
9981054 	struct omap2_mcspi_cs	*cs = spi->controller_state;
999
-
1000
-	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
10011055 
10021056 	if (!cs) {
10031057 		cs = kzalloc(sizeof *cs, GFP_KERNEL);
....@@ -1011,70 +1065,56 @@
10111065 		spi->controller_state = cs;
10121066 		/* Link this to context save list */
10131067 		list_add_tail(&cs->node, &ctx->cs);
1014
-
1015
-		if (gpio_is_valid(spi->cs_gpio)) {
1016
-			ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1017
-			if (ret) {
1018
-				dev_err(&spi->dev, "failed to request gpio\n");
1019
-				return ret;
1020
-			}
1021
-			gpio_direction_output(spi->cs_gpio,
1022
-					 !(spi->mode & SPI_CS_HIGH));
1023
-		}
1024
-	}
1025
-
1026
-	if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1027
-		ret = omap2_mcspi_request_dma(spi);
1028
-		if (ret)
1029
-			dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1030
-				 ret);
1068
+		initial_setup = true;
10311069 	}
10321070 
10331071 	ret = pm_runtime_get_sync(mcspi->dev);
10341072 	if (ret < 0) {
10351073 		pm_runtime_put_noidle(mcspi->dev);
1074
+		if (initial_setup)
1075
+			omap2_mcspi_cleanup(spi);
10361076 
10371077 		return ret;
10381078 	}
10391079 
10401080 	ret = omap2_mcspi_setup_transfer(spi, NULL);
1081
+	if (ret && initial_setup)
1082
+		omap2_mcspi_cleanup(spi);
1083
+
10411084 	pm_runtime_mark_last_busy(mcspi->dev);
10421085 	pm_runtime_put_autosuspend(mcspi->dev);
10431086 
10441087 	return ret;
10451088 }
10461089 
1047
-static void omap2_mcspi_cleanup(struct spi_device *spi)
1090
+static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
10481091 {
1049
-	struct omap2_mcspi	*mcspi;
1050
-	struct omap2_mcspi_dma	*mcspi_dma;
1051
-	struct omap2_mcspi_cs	*cs;
1092
+	struct omap2_mcspi *mcspi = data;
1093
+	u32 irqstat;
10521094 
1053
-	mcspi = spi_master_get_devdata(spi->master);
1095
+	irqstat	= mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
1096
+	if (!irqstat)
1097
+		return IRQ_NONE;
10541098 
1055
-	if (spi->controller_state) {
1056
-		/* Unlink controller state from context save list */
1057
-		cs = spi->controller_state;
1058
-		list_del(&cs->node);
1099
+	/* Disable IRQ and wakeup slave xfer task */
1100
+	mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0);
1101
+	if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
1102
+		complete(&mcspi->txdone);
10591103 
1060
-		kfree(cs);
1061
-	}
1104
+	return IRQ_HANDLED;
1105
+}
10621106 
1063
-	if (spi->chip_select < spi->master->num_chipselect) {
1064
-		mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1107
+static int omap2_mcspi_slave_abort(struct spi_master *master)
1108
+{
1109
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1110
+	struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
10651111 
1066
-		if (mcspi_dma->dma_rx) {
1067
-			dma_release_channel(mcspi_dma->dma_rx);
1068
-			mcspi_dma->dma_rx = NULL;
1069
-		}
1070
-		if (mcspi_dma->dma_tx) {
1071
-			dma_release_channel(mcspi_dma->dma_tx);
1072
-			mcspi_dma->dma_tx = NULL;
1073
-		}
1074
-	}
1112
+	mcspi->slave_aborted = true;
1113
+	complete(&mcspi_dma->dma_rx_completion);
1114
+	complete(&mcspi_dma->dma_tx_completion);
1115
+	complete(&mcspi->txdone);
10751116 
1076
-	if (gpio_is_valid(spi->cs_gpio))
1077
-		gpio_free(spi->cs_gpio);
1117
+	return 0;
10781118 }
10791119 
10801120 static int omap2_mcspi_transfer_one(struct spi_master *master,
....@@ -1114,7 +1154,7 @@
11141154 
11151155 	omap2_mcspi_set_enable(spi, 0);
11161156 
1117
-	if (gpio_is_valid(spi->cs_gpio))
1157
+	if (spi->cs_gpiod)
11181158 		omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
11191159 
11201160 	if (par_override ||
....@@ -1203,7 +1243,7 @@
12031243 
12041244 	omap2_mcspi_set_enable(spi, 0);
12051245 
1206
-	if (gpio_is_valid(spi->cs_gpio))
1246
+	if (spi->cs_gpiod)
12071247 		omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
12081248 
12091249 	if (mcspi->fifo_depth > 0 && t)
....@@ -1243,10 +1283,35 @@
12431283 				struct spi_device *spi,
12441284 				struct spi_transfer *xfer)
12451285 {
1286
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1287
+	struct omap2_mcspi_dma *mcspi_dma =
1288
+		&mcspi->dma_channels[spi->chip_select];
1289
+
1290
+	if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
1291
+		return false;
1292
+
1293
+	if (spi_controller_is_slave(master))
1294
+		return true;
1295
+
1296
+	master->dma_rx = mcspi_dma->dma_rx;
1297
+	master->dma_tx = mcspi_dma->dma_tx;
1298
+
12461299 	return (xfer->len >= DMA_MIN_BYTES);
12471300 }
12481301 
1249
-static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1302
+static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
1303
+{
1304
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1305
+	struct omap2_mcspi_dma *mcspi_dma =
1306
+		&mcspi->dma_channels[spi->chip_select];
1307
+
1308
+	if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
1309
+		return mcspi->max_xfer_len;
1310
+
1311
+	return SIZE_MAX;
1312
+}
1313
+
1314
+static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
12501315 {
12511316 	struct spi_master	*master = mcspi->master;
12521317 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
....@@ -1263,7 +1328,7 @@
12631328 			OMAP2_MCSPI_WAKEUPENABLE_WKEN);
12641329 	ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
12651330 
1266
-	omap2_mcspi_set_master_mode(master);
1331
+	omap2_mcspi_set_mode(master);
12671332 	pm_runtime_mark_last_busy(mcspi->dev);
12681333 	pm_runtime_put_autosuspend(mcspi->dev);
12691334 	return 0;
....@@ -1314,6 +1379,11 @@
13141379 	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
13151380 };
13161381 
1382
+static struct omap2_mcspi_platform_config am654_pdata = {
1383
+	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
1384
+	.max_xfer_len = SZ_4K - 1,
1385
+};
1386
+
13171387 static const struct of_device_id omap_mcspi_of_match[] = {
13181388 	{
13191389 		.compatible = "ti,omap2-mcspi",
....@@ -1322,6 +1392,10 @@
13221392 	{
13231393 		.compatible = "ti,omap4-mcspi",
13241394 		.data = &omap4_pdata,
1395
+	},
1396
+	{
1397
+		.compatible = "ti,am654-mcspi",
1398
+		.data = &am654_pdata,
13251399 	},
13261400 	{ },
13271401 };
....@@ -1338,11 +1412,12 @@
13381412 	struct device_node	*node = pdev->dev.of_node;
13391413 	const struct of_device_id *match;
13401414 
1341
-	master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1342
-	if (master == NULL) {
1343
-		dev_dbg(&pdev->dev, "master allocation failed\n");
1415
+	if (of_property_read_bool(node, "spi-slave"))
1416
+		master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi));
1417
+	else
1418
+		master = spi_alloc_master(&pdev->dev, sizeof(*mcspi));
1419
+	if (!master)
13441420 		return -ENOMEM;
1345
-	}
13461421 
13471422 	/* the spi->mode bits understood by this driver: */
13481423 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
....@@ -1354,9 +1429,11 @@
13541429 	master->transfer_one = omap2_mcspi_transfer_one;
13551430 	master->set_cs = omap2_mcspi_set_cs;
13561431 	master->cleanup = omap2_mcspi_cleanup;
1432
+	master->slave_abort = omap2_mcspi_slave_abort;
13571433 	master->dev.of_node = node;
13581434 	master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
13591435 	master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1436
+	master->use_gpio_descriptors = true;
13601437 
13611438 	platform_set_drvdata(pdev, master);
13621439 
....@@ -1378,6 +1455,10 @@
13781455 		mcspi->pin_dir = pdata->pin_dir;
13791456 	}
13801457 	regs_offset = pdata->regs_offset;
1458
+	if (pdata->max_xfer_len) {
1459
+		mcspi->max_xfer_len = pdata->max_xfer_len;
1460
+		master->max_transfer_size = omap2_mcspi_max_xfer_size;
1461
+	}
13811462 
13821463 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
13831464 	mcspi->base = devm_ioremap_resource(&pdev->dev, r);
....@@ -1403,17 +1484,38 @@
14031484 	for (i = 0; i < master->num_chipselect; i++) {
14041485 		sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
14051486 		sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1487
+
1488
+		status = omap2_mcspi_request_dma(mcspi,
1489
+						 &mcspi->dma_channels[i]);
1490
+		if (status == -EPROBE_DEFER)
1491
+			goto free_master;
1492
+	}
1493
+
1494
+	status = platform_get_irq(pdev, 0);
1495
+	if (status == -EPROBE_DEFER)
1496
+		goto free_master;
1497
+	if (status < 0) {
1498
+		dev_err(&pdev->dev, "no irq resource found\n");
1499
+		goto free_master;
1500
+	}
1501
+	init_completion(&mcspi->txdone);
1502
+	status = devm_request_irq(&pdev->dev, status,
1503
+				  omap2_mcspi_irq_handler, 0, pdev->name,
1504
+				  mcspi);
1505
+	if (status) {
1506
+		dev_err(&pdev->dev, "Cannot request IRQ");
1507
+		goto free_master;
14061508 	}
14071509 
14081510 	pm_runtime_use_autosuspend(&pdev->dev);
14091511 	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
14101512 	pm_runtime_enable(&pdev->dev);
14111513 
1412
-	status = omap2_mcspi_master_setup(mcspi);
1514
+	status = omap2_mcspi_controller_setup(mcspi);
14131515 	if (status < 0)
14141516 		goto disable_pm;
14151517 
1416
-	status = devm_spi_register_master(&pdev->dev, master);
1518
+	status = devm_spi_register_controller(&pdev->dev, master);
14171519 	if (status < 0)
14181520 		goto disable_pm;
14191521 
....@@ -1424,6 +1526,7 @@
14241526 	pm_runtime_put_sync(&pdev->dev);
14251527 	pm_runtime_disable(&pdev->dev);
14261528 free_master:
1529
+	omap2_mcspi_release_dma(master);
14271530 	spi_master_put(master);
14281531 	return status;
14291532 }
....@@ -1433,6 +1536,8 @@
14331536 	struct spi_master *master = platform_get_drvdata(pdev);
14341537 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
14351538 
1539
+	omap2_mcspi_release_dma(master);
1540
+
14361541 	pm_runtime_dont_use_autosuspend(mcspi->dev);
14371542 	pm_runtime_put_sync(mcspi->dev);
14381543 	pm_runtime_disable(&pdev->dev);