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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/spi/spi-dw.h
....@@ -2,19 +2,23 @@
22 #ifndef DW_SPI_HEADER_H
33 #define DW_SPI_HEADER_H
44 
5
+#include <linux/bits.h>
6
+#include <linux/completion.h>
7
+#include <linux/debugfs.h>
8
+#include <linux/irqreturn.h>
59 #include <linux/io.h>
610 #include <linux/scatterlist.h>
7
-#include <linux/gpio.h>
11
+#include <linux/spi/spi-mem.h>
812 
913 /* Register offsets */
10
-#define DW_SPI_CTRL0			0x00
11
-#define DW_SPI_CTRL1			0x04
14
+#define DW_SPI_CTRLR0			0x00
15
+#define DW_SPI_CTRLR1			0x04
1216 #define DW_SPI_SSIENR			0x08
1317 #define DW_SPI_MWCR			0x0c
1418 #define DW_SPI_SER			0x10
1519 #define DW_SPI_BAUDR			0x14
16
-#define DW_SPI_TXFLTR			0x18
17
-#define DW_SPI_RXFLTR			0x1c
20
+#define DW_SPI_TXFTLR			0x18
21
+#define DW_SPI_RXFTLR			0x1c
1822 #define DW_SPI_TXFLR			0x20
1923 #define DW_SPI_RXFLR			0x24
2024 #define DW_SPI_SR			0x28
....@@ -32,6 +36,8 @@
3236 #define DW_SPI_IDR			0x58
3337 #define DW_SPI_VERSION			0x5c
3438 #define DW_SPI_DR			0x60
39
+#define DW_SPI_RX_SAMPLE_DLY		0xf0
40
+#define DW_SPI_CS_OVERRIDE		0xf4
3541 
3642 /* Bit fields in CTRLR0 */
3743 #define SPI_DFS_OFFSET			0
....@@ -57,6 +63,25 @@
5763 #define SPI_SRL_OFFSET			11
5864 #define SPI_CFS_OFFSET			12
5965 
66
+/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
67
+#define DWC_SSI_CTRLR0_SRL_OFFSET	13
68
+#define DWC_SSI_CTRLR0_TMOD_OFFSET	10
69
+#define DWC_SSI_CTRLR0_TMOD_MASK	GENMASK(11, 10)
70
+#define DWC_SSI_CTRLR0_SCPOL_OFFSET	9
71
+#define DWC_SSI_CTRLR0_SCPH_OFFSET	8
72
+#define DWC_SSI_CTRLR0_FRF_OFFSET	6
73
+#define DWC_SSI_CTRLR0_DFS_OFFSET	0
74
+
75
+/*
76
+ * For Keem Bay, CTRLR0[31] is used to select controller mode.
77
+ * 0: SSI is slave
78
+ * 1: SSI is master
79
+ */
80
+#define DWC_SSI_CTRLR0_KEEMBAY_MST	BIT(31)
81
+
82
+/* Bit fields in CTRLR1 */
83
+#define SPI_NDF_MASK			GENMASK(15, 0)
84
+
6085 /* Bit fields in SR, 7 bits */
6186 #define SR_MASK				0x7f		/* cover 7 bits */
6287 #define SR_BUSY				(1 << 0)
....@@ -79,8 +104,12 @@
79104 #define SPI_DMA_RDMAE			(1 << 0)
80105 #define SPI_DMA_TDMAE			(1 << 1)
81106 
82
-/* TX RX interrupt level threshold, max can be 256 */
83
-#define SPI_INT_THRESHOLD		32
107
+#define SPI_WAIT_RETRIES		5
108
+#define SPI_BUF_SIZE \
109
+	(sizeof_field(struct spi_mem_op, cmd.opcode) + \
110
+	 sizeof_field(struct spi_mem_op, addr.val) + 256)
111
+#define SPI_GET_BYTE(_val, _idx) \
112
+	((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
84113 
85114 enum dw_ssi_type {
86115 	SSI_MOTO_SPI = 0,
....@@ -88,9 +117,22 @@
88117 	SSI_NS_MICROWIRE,
89118 };
90119 
120
+/* DW SPI capabilities */
121
+#define DW_SPI_CAP_CS_OVERRIDE		BIT(0)
122
+#define DW_SPI_CAP_KEEMBAY_MST		BIT(1)
123
+#define DW_SPI_CAP_DWC_SSI		BIT(2)
124
+
125
+/* Slave spi_transfer/spi_mem_op related */
126
+struct dw_spi_cfg {
127
+	u8 tmode;
128
+	u8 dfs;
129
+	u32 ndf;
130
+	u32 freq;
131
+};
132
+
91133 struct dw_spi;
92134 struct dw_spi_dma_ops {
93
-	int (*dma_init)(struct dw_spi *dws);
135
+	int (*dma_init)(struct device *dev, struct dw_spi *dws);
94136 	void (*dma_exit)(struct dw_spi *dws);
95137 	int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
96138 	bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
....@@ -101,13 +143,15 @@
101143 
102144 struct dw_spi {
103145 	struct spi_controller	*master;
104
-	enum dw_ssi_type	type;
105146 
106147 	void __iomem		*regs;
107148 	unsigned long		paddr;
108149 	int			irq;
109150 	u32			fifo_len;	/* depth of the FIFO buffer */
151
+	u32			max_mem_freq;	/* max mem-ops bus freq */
110152 	u32			max_freq;	/* max bus freq supported */
153
+
154
+	u32			caps;		/* DW SPI capabilities */
111155 
112156 	u32			reg_io_width;	/* DR I/O width in bytes */
113157 	u16			bus_num;
....@@ -115,32 +159,35 @@
115159 	void (*set_cs)(struct spi_device *spi, bool enable);
116160 
117161 	/* Current message transfer state info */
118
-	size_t			len;
119162 	void			*tx;
120
-	void			*tx_end;
121
-	spinlock_t		buf_lock;
163
+	unsigned int		tx_len;
122164 	void			*rx;
123
-	void			*rx_end;
165
+	unsigned int		rx_len;
166
+	u8			buf[SPI_BUF_SIZE];
124167 	int			dma_mapped;
125168 	u8			n_bytes;	/* current is a 1/2 bytes op */
126
-	u32			dma_width;
127169 	irqreturn_t		(*transfer_handler)(struct dw_spi *dws);
128170 	u32			current_freq;	/* frequency in hz */
171
+	u32			cur_rx_sample_dly;
172
+	u32			def_rx_sample_dly_ns;
173
+
174
+	/* Custom memory operations */
175
+	struct spi_controller_mem_ops mem_ops;
129176 
130177 	/* DMA info */
131
-	int			dma_inited;
132178 	struct dma_chan		*txchan;
179
+	u32			txburst;
133180 	struct dma_chan		*rxchan;
181
+	u32			rxburst;
182
+	u32			dma_sg_burst;
134183 	unsigned long		dma_chan_busy;
135184 	dma_addr_t		dma_addr; /* phy address of the Data register */
136185 	const struct dw_spi_dma_ops *dma_ops;
137
-	void			*dma_tx;
138
-	void			*dma_rx;
186
+	struct completion	dma_completion;
139187 
140
-	/* Bus interface info */
141
-	void			*priv;
142188 #ifdef CONFIG_DEBUG_FS
143189 	struct dentry *debugfs;
190
+	struct debugfs_regset32 regset;
144191 #endif
145192 };
146193 
....@@ -149,29 +196,19 @@
149196 	return __raw_readl(dws->regs + offset);
150197 }
151198 
152
-static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
153
-{
154
-	return __raw_readw(dws->regs + offset);
155
-}
156
-
157199 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
158200 {
159201 	__raw_writel(val, dws->regs + offset);
160
-}
161
-
162
-static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
163
-{
164
-	__raw_writew(val, dws->regs + offset);
165202 }
166203 
167204 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
168205 {
169206 	switch (dws->reg_io_width) {
170207 	case 2:
171
-		return dw_readw(dws, offset);
208
+		return readw_relaxed(dws->regs + offset);
172209 	case 4:
173210 	default:
174
-		return dw_readl(dws, offset);
211
+		return readl_relaxed(dws->regs + offset);
175212 	}
176213 }
177214 
....@@ -179,11 +216,11 @@
179216 {
180217 	switch (dws->reg_io_width) {
181218 	case 2:
182
-		dw_writew(dws, offset, val);
219
+		writew_relaxed(val, dws->regs + offset);
183220 		break;
184221 	case 4:
185222 	default:
186
-		dw_writel(dws, offset, val);
223
+		writel_relaxed(val, dws->regs + offset);
187224 		break;
188225 	}
189226 }
....@@ -217,14 +254,16 @@
217254 }
218255 
219256 /*
220
- * This does disable the SPI controller, interrupts, and re-enable the
221
- * controller back. Transmit and receive FIFO buffers are cleared when the
222
- * device is disabled.
257
+ * This disables the SPI controller, interrupts, clears the interrupts status
258
+ * and CS, then re-enables the controller back. Transmit and receive FIFO
259
+ * buffers are cleared when the device is disabled.
223260  */
224261 static inline void spi_reset_chip(struct dw_spi *dws)
225262 {
226263 	spi_enable_chip(dws, 0);
227264 	spi_mask_intr(dws, 0xff);
265
+	dw_readl(dws, DW_SPI_ICR);
266
+	dw_writel(dws, DW_SPI_SER, 0);
228267 	spi_enable_chip(dws, 1);
229268 }
230269 
....@@ -234,24 +273,25 @@
234273 	spi_set_clk(dws, 0);
235274 }
236275 
237
-/*
238
- * Each SPI slave device to work with dw_api controller should
239
- * has such a structure claiming its working mode (poll or PIO/DMA),
240
- * which can be save in the "controller_data" member of the
241
- * struct spi_device.
242
- */
243
-struct dw_spi_chip {
244
-	u8 poll_mode;	/* 1 for controller polling mode */
245
-	u8 type;	/* SPI/SSP/MicroWire */
246
-	void (*cs_control)(u32 command);
247
-};
248
-
249276 extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
277
+extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
278
+				 struct dw_spi_cfg *cfg);
279
+extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
250280 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
251281 extern void dw_spi_remove_host(struct dw_spi *dws);
252282 extern int dw_spi_suspend_host(struct dw_spi *dws);
253283 extern int dw_spi_resume_host(struct dw_spi *dws);
254284 
255
-/* platform related setup */
256
-extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
285
+#ifdef CONFIG_SPI_DW_DMA
286
+
287
+extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
288
+extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
289
+
290
+#else
291
+
292
+static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
293
+static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
294
+
295
+#endif /* !CONFIG_SPI_DW_DMA */
296
+
257297 #endif /* DW_SPI_HEADER_H */