forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/spi/spi-dw-pci.c
....@@ -1,20 +1,12 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * PCI interface driver for DW SPI Core
34  *
45  * Copyright (c) 2009, 2014 Intel Corporation.
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms and conditions of the GNU General Public License,
8
- * version 2, as published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
- * more details.
146  */
157 
16
-#include <linux/interrupt.h>
178 #include <linux/pci.h>
9
+#include <linux/pm_runtime.h>
1810 #include <linux/slab.h>
1911 #include <linux/spi/spi.h>
2012 #include <linux/module.h>
....@@ -23,22 +15,68 @@
2315 
2416 #define DRIVER_NAME "dw_spi_pci"
2517 
18
+/* HW info for MRST Clk Control Unit, 32b reg per controller */
19
+#define MRST_SPI_CLK_BASE	100000000	/* 100m */
20
+#define MRST_CLK_SPI_REG	0xff11d86c
21
+#define CLK_SPI_BDIV_OFFSET	0
22
+#define CLK_SPI_BDIV_MASK	0x00000007
23
+#define CLK_SPI_CDIV_OFFSET	9
24
+#define CLK_SPI_CDIV_MASK	0x00000e00
25
+#define CLK_SPI_DISABLE_OFFSET	8
26
+
2627 struct spi_pci_desc {
2728 	int	(*setup)(struct dw_spi *);
2829 	u16	num_cs;
2930 	u16	bus_num;
31
+	u32	max_freq;
3032 };
3133 
34
+static int spi_mid_init(struct dw_spi *dws)
35
+{
36
+	void __iomem *clk_reg;
37
+	u32 clk_cdiv;
38
+
39
+	clk_reg = ioremap(MRST_CLK_SPI_REG, 16);
40
+	if (!clk_reg)
41
+		return -ENOMEM;
42
+
43
+	/* Get SPI controller operating freq info */
44
+	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
45
+	clk_cdiv &= CLK_SPI_CDIV_MASK;
46
+	clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
47
+	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
48
+
49
+	iounmap(clk_reg);
50
+
51
+	dw_spi_dma_setup_mfld(dws);
52
+
53
+	return 0;
54
+}
55
+
56
+static int spi_generic_init(struct dw_spi *dws)
57
+{
58
+	dw_spi_dma_setup_generic(dws);
59
+
60
+	return 0;
61
+}
62
+
3263 static struct spi_pci_desc spi_pci_mid_desc_1 = {
33
-	.setup = dw_spi_mid_init,
64
+	.setup = spi_mid_init,
3465 	.num_cs = 5,
3566 	.bus_num = 0,
3667 };
3768 
3869 static struct spi_pci_desc spi_pci_mid_desc_2 = {
39
-	.setup = dw_spi_mid_init,
70
+	.setup = spi_mid_init,
4071 	.num_cs = 2,
4172 	.bus_num = 1,
73
+};
74
+
75
+static struct spi_pci_desc spi_pci_ehl_desc = {
76
+	.setup = spi_generic_init,
77
+	.num_cs = 2,
78
+	.bus_num = -1,
79
+	.max_freq = 100000000,
4280 };
4381 
4482 static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
....@@ -58,13 +96,18 @@
5896 
5997 	/* Get basic io resource and map it */
6098 	dws->paddr = pci_resource_start(pdev, pci_bar);
99
+	pci_set_master(pdev);
61100 
62101 	ret = pcim_iomap_regions(pdev, 1 << pci_bar, pci_name(pdev));
63102 	if (ret)
64103 		return ret;
65104 
105
+	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
106
+	if (ret < 0)
107
+		return ret;
108
+
66109 	dws->regs = pcim_iomap_table(pdev)[pci_bar];
67
-	dws->irq = pdev->irq;
110
+	dws->irq = pci_irq_vector(pdev, 0);
68111 
69112 	/*
70113 	 * Specific handling for platforms, like dma setup,
....@@ -73,19 +116,21 @@
73116 	if (desc) {
74117 		dws->num_cs = desc->num_cs;
75118 		dws->bus_num = desc->bus_num;
119
+		dws->max_freq = desc->max_freq;
76120 
77121 		if (desc->setup) {
78122 			ret = desc->setup(dws);
79123 			if (ret)
80
-				return ret;
124
+				goto err_free_irq_vectors;
81125 		}
82126 	} else {
83
-		return -ENODEV;
127
+		ret = -ENODEV;
128
+		goto err_free_irq_vectors;
84129 	}
85130 
86131 	ret = dw_spi_add_host(&pdev->dev, dws);
87132 	if (ret)
88
-		return ret;
133
+		goto err_free_irq_vectors;
89134 
90135 	/* PCI hook and SPI hook use the same drv data */
91136 	pci_set_drvdata(pdev, dws);
....@@ -93,29 +138,40 @@
93138 	dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
94139 		pdev->vendor, pdev->device);
95140 
141
+	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
142
+	pm_runtime_use_autosuspend(&pdev->dev);
143
+	pm_runtime_put_autosuspend(&pdev->dev);
144
+	pm_runtime_allow(&pdev->dev);
145
+
96146 	return 0;
147
+
148
+err_free_irq_vectors:
149
+	pci_free_irq_vectors(pdev);
150
+	return ret;
97151 }
98152 
99153 static void spi_pci_remove(struct pci_dev *pdev)
100154 {
101155 	struct dw_spi *dws = pci_get_drvdata(pdev);
102156 
157
+	pm_runtime_forbid(&pdev->dev);
158
+	pm_runtime_get_noresume(&pdev->dev);
159
+
103160 	dw_spi_remove_host(dws);
161
+	pci_free_irq_vectors(pdev);
104162 }
105163 
106164 #ifdef CONFIG_PM_SLEEP
107165 static int spi_suspend(struct device *dev)
108166 {
109
-	struct pci_dev *pdev = to_pci_dev(dev);
110
-	struct dw_spi *dws = pci_get_drvdata(pdev);
167
+	struct dw_spi *dws = dev_get_drvdata(dev);
111168 
112169 	return dw_spi_suspend_host(dws);
113170 }
114171 
115172 static int spi_resume(struct device *dev)
116173 {
117
-	struct pci_dev *pdev = to_pci_dev(dev);
118
-	struct dw_spi *dws = pci_get_drvdata(pdev);
174
+	struct dw_spi *dws = dev_get_drvdata(dev);
119175 
120176 	return dw_spi_resume_host(dws);
121177 }
....@@ -133,8 +189,14 @@
133189 	{ PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc_1},
134190 	/* Intel MID platform SPI controller 2 */
135191 	{ PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&spi_pci_mid_desc_2},
192
+	/* Intel Elkhart Lake PSE SPI controllers */
193
+	{ PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&spi_pci_ehl_desc},
194
+	{ PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&spi_pci_ehl_desc},
195
+	{ PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&spi_pci_ehl_desc},
196
+	{ PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&spi_pci_ehl_desc},
136197 	{},
137198 };
199
+MODULE_DEVICE_TABLE(pci, pci_ids);
138200 
139201 static struct pci_driver dw_spi_driver = {
140202 	.name =		DRIVER_NAME,