hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c
kernel/drivers/spi/spi-bcm63xx-hsspi.c
....@@ -20,6 +20,8 @@
2020 #include <linux/spi/spi.h>
2121 #include <linux/mutex.h>
2222 #include <linux/of.h>
23
+#include <linux/reset.h>
24
+#include <linux/pm_runtime.h>
2325
2426 #define HSSPI_GLOBAL_CTRL_REG 0x0
2527 #define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
....@@ -161,6 +163,7 @@
161163 int step_size = HSSPI_BUFFER_LEN;
162164 const u8 *tx = t->tx_buf;
163165 u8 *rx = t->rx_buf;
166
+ u32 val = 0;
164167
165168 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
166169 bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
....@@ -176,11 +179,16 @@
176179 step_size -= HSSPI_OPCODE_LEN;
177180
178181 if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
179
- (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
182
+ (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) {
180183 opcode |= HSSPI_OP_MULTIBIT;
181184
182
- __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
183
- 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
185
+ if (t->rx_nbits == SPI_NBITS_DUAL)
186
+ val |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT;
187
+ if (t->tx_nbits == SPI_NBITS_DUAL)
188
+ val |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT;
189
+ }
190
+
191
+ __raw_writel(val | 0xff,
184192 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
185193
186194 while (pending > 0) {
....@@ -291,8 +299,7 @@
291299
292300 msg->actual_length += t->len;
293301
294
- if (t->delay_usecs)
295
- udelay(t->delay_usecs);
302
+ spi_transfer_delay_exec(t);
296303
297304 if (t->cs_change)
298305 bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
....@@ -330,21 +337,18 @@
330337 {
331338 struct spi_master *master;
332339 struct bcm63xx_hsspi *bs;
333
- struct resource *res_mem;
334340 void __iomem *regs;
335341 struct device *dev = &pdev->dev;
336342 struct clk *clk, *pll_clk = NULL;
337343 int irq, ret;
338344 u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
345
+ struct reset_control *reset;
339346
340347 irq = platform_get_irq(pdev, 0);
341
- if (irq < 0) {
342
- dev_err(dev, "no irq: %d\n", irq);
348
+ if (irq < 0)
343349 return irq;
344
- }
345350
346
- res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
347
- regs = devm_ioremap_resource(dev, res_mem);
351
+ regs = devm_platform_ioremap_resource(pdev, 0);
348352 if (IS_ERR(regs))
349353 return PTR_ERR(regs);
350354
....@@ -353,9 +357,19 @@
353357 if (IS_ERR(clk))
354358 return PTR_ERR(clk);
355359
360
+ reset = devm_reset_control_get_optional_exclusive(dev, NULL);
361
+ if (IS_ERR(reset))
362
+ return PTR_ERR(reset);
363
+
356364 ret = clk_prepare_enable(clk);
357365 if (ret)
358366 return ret;
367
+
368
+ ret = reset_control_reset(reset);
369
+ if (ret) {
370
+ dev_err(dev, "unable to reset device: %d\n", ret);
371
+ goto out_disable_clk;
372
+ }
359373
360374 rate = clk_get_rate(clk);
361375 if (!rate) {
....@@ -432,13 +446,17 @@
432446 if (ret)
433447 goto out_put_master;
434448
449
+ pm_runtime_enable(&pdev->dev);
450
+
435451 /* register and we are done */
436452 ret = devm_spi_register_master(dev, master);
437453 if (ret)
438
- goto out_put_master;
454
+ goto out_pm_disable;
439455
440456 return 0;
441457
458
+out_pm_disable:
459
+ pm_runtime_disable(&pdev->dev);
442460 out_put_master:
443461 spi_master_put(master);
444462 out_disable_pll_clk: