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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/spi/spi-bcm-qspi.c
....@@ -1,19 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Driver for Broadcom BRCMSTB, NSP,  NS2, Cygnus SPI Controllers
34  *
45  * Copyright 2016 Broadcom
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License, version 2, as
8
- * published by the Free Software Foundation (the "GPL").
9
- *
10
- * This program is distributed in the hope that it will be useful, but
11
- * WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13
- * General Public License version 2 (GPLv2) for more details.
14
- *
15
- * You should have received a copy of the GNU General Public License
16
- * version 2 (GPLv2) along with this source code.
176  */
187 
198 #include <linux/clk.h>
....@@ -102,6 +91,7 @@
10291 #define MSPI_MSPI_STATUS			0x020
10392 #define MSPI_CPTQP				0x024
10493 #define MSPI_SPCR3				0x028
94
+#define MSPI_REV				0x02c
10595 #define MSPI_TXRAM				0x040
10696 #define MSPI_RXRAM				0x0c0
10797 #define MSPI_CDRAM				0x140
....@@ -117,14 +107,22 @@
117107 #define MSPI_SPCR2_SPE				BIT(6)
118108 #define MSPI_SPCR2_CONT_AFTER_CMD		BIT(7)
119109 
110
+#define MSPI_SPCR3_FASTBR			BIT(0)
111
+#define MSPI_SPCR3_FASTDT			BIT(1)
112
+#define MSPI_SPCR3_SYSCLKSEL_MASK		GENMASK(11, 10)
113
+#define MSPI_SPCR3_SYSCLKSEL_27			(MSPI_SPCR3_SYSCLKSEL_MASK & \
114
+						 ~(BIT(10) | BIT(11)))
115
+#define MSPI_SPCR3_SYSCLKSEL_108		(MSPI_SPCR3_SYSCLKSEL_MASK & \
116
+						 BIT(11))
117
+
120118 #define MSPI_MSPI_STATUS_SPIF			BIT(0)
121119 
122120 #define INTR_BASE_BIT_SHIFT			0x02
123121 #define INTR_COUNT				0x07
124122 
125123 #define NUM_CHIPSELECT				4
126
-#define QSPI_SPBR_MIN				8U
127124 #define QSPI_SPBR_MAX				255U
125
+#define MSPI_BASE_FREQ				27000000UL
128126 
129127 #define OPCODE_DIOR				0xBB
130128 #define OPCODE_QIOR				0xEB
....@@ -228,11 +226,44 @@
228226 	struct bcm_qspi_dev_id *dev_ids;
229227 	struct completion mspi_done;
230228 	struct completion bspi_done;
229
+	u8 mspi_maj_rev;
230
+	u8 mspi_min_rev;
231
+	bool mspi_spcr3_sysclk;
231232 };
232233 
233234 static inline bool has_bspi(struct bcm_qspi *qspi)
234235 {
235236 	return qspi->bspi_mode;
237
+}
238
+
239
+/* hardware supports spcr3 and fast baud-rate  */
240
+static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
241
+{
242
+	if (!has_bspi(qspi) &&
243
+	    ((qspi->mspi_maj_rev >= 1) &&
244
+	     (qspi->mspi_min_rev >= 5)))
245
+		return true;
246
+
247
+	return false;
248
+}
249
+
250
+/* hardware supports sys clk 108Mhz  */
251
+static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
252
+{
253
+	if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk ||
254
+	    ((qspi->mspi_maj_rev >= 1) &&
255
+	     (qspi->mspi_min_rev >= 6))))
256
+		return true;
257
+
258
+	return false;
259
+}
260
+
261
+static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
262
+{
263
+	if (bcm_qspi_has_fastbr(qspi))
264
+		return 1;
265
+	else
266
+		return 8;
236267 }
237268 
238269 /* Read qspi controller register*/
....@@ -542,15 +573,38 @@
542573 	if (xp->speed_hz)
543574 		spbr = qspi->base_clk / (2 * xp->speed_hz);
544575 
545
-	spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
576
+	spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
546577 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
547578 
548
-	spcr = MSPI_MASTER_BIT;
579
+	if (!qspi->mspi_maj_rev)
580
+		/* legacy controller */
581
+		spcr = MSPI_MASTER_BIT;
582
+	else
583
+		spcr = 0;
584
+
549585 	/* for 16 bit the data should be zero */
550586 	if (xp->bits_per_word != 16)
551587 		spcr |= xp->bits_per_word << 2;
552588 	spcr |= xp->mode & 3;
589
+
553590 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
591
+
592
+	if (bcm_qspi_has_fastbr(qspi)) {
593
+		spcr = 0;
594
+
595
+		/* enable fastbr */
596
+		spcr |=	MSPI_SPCR3_FASTBR;
597
+
598
+		if (bcm_qspi_has_sysclk_108(qspi)) {
599
+			/* SYSCLK_108 */
600
+			spcr |= MSPI_SPCR3_SYSCLKSEL_108;
601
+			qspi->base_clk = MSPI_BASE_FREQ * 4;
602
+			/* Change spbr as we changed sysclk */
603
+			bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4);
604
+		}
605
+
606
+		bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
607
+	}
554608 
555609 	qspi->last_parms = *xp;
556610 }
....@@ -623,19 +677,15 @@
623677 		if (qt->trans->cs_change &&
624678 		    (flags & TRANS_STATUS_BREAK_CS_CHANGE))
625679 			ret |= TRANS_STATUS_BREAK_CS_CHANGE;
626
-		if (ret)
627
-			goto done;
628680 
629
-		dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
630681 		if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
631
-			ret = TRANS_STATUS_BREAK_EOM;
682
+			ret |= TRANS_STATUS_BREAK_EOM;
632683 		else
633
-			ret = TRANS_STATUS_BREAK_NO_BYTES;
684
+			ret |= TRANS_STATUS_BREAK_NO_BYTES;
634685 
635686 		qt->trans = NULL;
636687 	}
637688 
638
-done:
639689 	dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
640690 		qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
641691 	return ret;
....@@ -782,7 +832,16 @@
782832 	bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
783833 	bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
784834 
785
-	if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
835
+	/*
836
+	 *  case 1) EOM =1, cs_change =0: SSb inactive
837
+	 *  case 2) EOM =1, cs_change =1: SSb stay active
838
+	 *  case 3) EOM =0, cs_change =0: SSb stay active
839
+	 *  case 4) EOM =0, cs_change =1: SSb inactive
840
+	 */
841
+	if (((tstatus & TRANS_STATUS_BREAK_DESELECT)
842
+	     == TRANS_STATUS_BREAK_CS_CHANGE) ||
843
+	    ((tstatus & TRANS_STATUS_BREAK_DESELECT)
844
+	     == TRANS_STATUS_BREAK_EOM)) {
786845 		mspi_cdram = read_cdram_slot(qspi, slot - 1) &
787846 			~MSPI_CDRAM_CONT_BIT;
788847 		write_cdram_slot(qspi, slot - 1, mspi_cdram);
....@@ -814,7 +873,8 @@
814873 			return -EIO;
815874 
816875 	from = op->addr.val;
817
-	bcm_qspi_chip_select(qspi, spi->chip_select);
876
+	if (!spi->cs_gpiod)
877
+		bcm_qspi_chip_select(qspi, spi->chip_select);
818878 	bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
819879 
820880 	/*
....@@ -893,7 +953,8 @@
893953 	int slots;
894954 	unsigned long timeo = msecs_to_jiffies(100);
895955 
896
-	bcm_qspi_chip_select(qspi, spi->chip_select);
956
+	if (!spi->cs_gpiod)
957
+		bcm_qspi_chip_select(qspi, spi->chip_select);
897958 	qspi->trans_pos.trans = trans;
898959 	qspi->trans_pos.byte = 0;
899960 
....@@ -908,6 +969,7 @@
908969 
909970 		read_from_hw(qspi, slots);
910971 	}
972
+	bcm_qspi_enable_bspi(qspi);
911973 
912974 	return 0;
913975 }
....@@ -970,7 +1032,7 @@
9701032 	addr = op->addr.val;
9711033 	len = op->data.nbytes;
9721034 
973
-	if (bcm_qspi_bspi_ver_three(qspi) == true) {
1035
+	if (has_bspi(qspi) && bcm_qspi_bspi_ver_three(qspi) == true) {
9741036 		/*
9751037 		 * The address coming into this function is a raw flash offset.
9761038 		 * But for BSPI <= V3, we need to convert it to a remapped BSPI
....@@ -989,7 +1051,7 @@
9891051 	    len < 4)
9901052 		mspi_read = true;
9911053 
992
-	if (mspi_read)
1054
+	if (!has_bspi(qspi) || mspi_read)
9931055 		return bcm_qspi_mspi_exec_mem_op(spi, op);
9941056 
9951057 	ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
....@@ -1188,18 +1250,58 @@
11881250 
11891251 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
11901252 {
1253
+	u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1254
+
11911255 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
11921256 	if (has_bspi(qspi))
11931257 		bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
11941258 
1259
+	/* clear interrupt */
1260
+	bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
11951261 }
11961262 
11971263 static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
11981264 	.exec_op = bcm_qspi_exec_mem_op,
11991265 };
12001266 
1267
+struct bcm_qspi_data {
1268
+	bool	has_mspi_rev;
1269
+	bool	has_spcr3_sysclk;
1270
+};
1271
+
1272
+static const struct bcm_qspi_data bcm_qspi_no_rev_data = {
1273
+	.has_mspi_rev	= false,
1274
+	.has_spcr3_sysclk = false,
1275
+};
1276
+
1277
+static const struct bcm_qspi_data bcm_qspi_rev_data = {
1278
+	.has_mspi_rev	= true,
1279
+	.has_spcr3_sysclk = false,
1280
+};
1281
+
1282
+static const struct bcm_qspi_data bcm_qspi_spcr3_data = {
1283
+	.has_mspi_rev	= true,
1284
+	.has_spcr3_sysclk = true,
1285
+};
1286
+
12011287 static const struct of_device_id bcm_qspi_of_match[] = {
1202
-	{ .compatible = "brcm,spi-bcm-qspi" },
1288
+	{
1289
+		.compatible = "brcm,spi-bcm7445-qspi",
1290
+		.data = &bcm_qspi_rev_data,
1291
+
1292
+	},
1293
+	{
1294
+		.compatible = "brcm,spi-bcm-qspi",
1295
+		.data = &bcm_qspi_no_rev_data,
1296
+	},
1297
+	{
1298
+		.compatible = "brcm,spi-bcm7216-qspi",
1299
+		.data = &bcm_qspi_spcr3_data,
1300
+	},
1301
+	{
1302
+		.compatible = "brcm,spi-bcm7278-qspi",
1303
+		.data = &bcm_qspi_spcr3_data,
1304
+	},
12031305 	{},
12041306 };
12051307 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
....@@ -1207,12 +1309,15 @@
12071309 int bcm_qspi_probe(struct platform_device *pdev,
12081310 		   struct bcm_qspi_soc_intc *soc_intc)
12091311 {
1312
+	const struct of_device_id *of_id = NULL;
1313
+	const struct bcm_qspi_data *data;
12101314 	struct device *dev = &pdev->dev;
12111315 	struct bcm_qspi *qspi;
12121316 	struct spi_master *master;
12131317 	struct resource *res;
12141318 	int irq, ret = 0, num_ints = 0;
12151319 	u32 val;
1320
+	u32 rev = 0;
12161321 	const char *name = NULL;
12171322 	int num_irqs = ARRAY_SIZE(qspi_irq_tab);
12181323 
....@@ -1220,8 +1325,11 @@
12201325 	if (!dev->of_node)
12211326 		return -ENODEV;
12221327 
1223
-	if (!of_match_node(bcm_qspi_of_match, dev->of_node))
1328
+	of_id = of_match_node(bcm_qspi_of_match, dev->of_node);
1329
+	if (!of_id)
12241330 		return -ENODEV;
1331
+
1332
+	data = of_id->data;
12251333 
12261334 	master = devm_spi_alloc_master(dev, sizeof(struct bcm_qspi));
12271335 	if (!master) {
....@@ -1230,6 +1338,11 @@
12301338 	}
12311339 
12321340 	qspi = spi_master_get_devdata(master);
1341
+
1342
+	qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
1343
+	if (IS_ERR(qspi->clk))
1344
+		return PTR_ERR(qspi->clk);
1345
+
12331346 	qspi->pdev = pdev;
12341347 	qspi->trans_pos.trans = NULL;
12351348 	qspi->trans_pos.byte = 0;
....@@ -1244,6 +1357,7 @@
12441357 	master->cleanup = bcm_qspi_cleanup;
12451358 	master->dev.of_node = dev->of_node;
12461359 	master->num_chipselect = NUM_CHIPSELECT;
1360
+	master->use_gpio_descriptors = true;
12471361 
12481362 	qspi->big_endian = of_device_is_big_endian(dev->of_node);
12491363 
....@@ -1255,13 +1369,9 @@
12551369 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
12561370 						   "mspi");
12571371 
1258
-	if (res) {
1259
-		qspi->base[MSPI]  = devm_ioremap_resource(dev, res);
1260
-		if (IS_ERR(qspi->base[MSPI]))
1261
-			return PTR_ERR(qspi->base[MSPI]);
1262
-	} else {
1263
-		return 0;
1264
-	}
1372
+	qspi->base[MSPI]  = devm_ioremap_resource(dev, res);
1373
+	if (IS_ERR(qspi->base[MSPI]))
1374
+		return PTR_ERR(qspi->base[MSPI]);
12651375 
12661376 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
12671377 	if (res) {
....@@ -1287,12 +1397,53 @@
12871397 	if (!qspi->dev_ids)
12881398 		return -ENOMEM;
12891399 
1400
+	/*
1401
+	 * Some SoCs integrate spi controller (e.g., its interrupt bits)
1402
+	 * in specific ways
1403
+	 */
1404
+	if (soc_intc) {
1405
+		qspi->soc_intc = soc_intc;
1406
+		soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1407
+	} else {
1408
+		qspi->soc_intc = NULL;
1409
+	}
1410
+
1411
+	if (qspi->clk) {
1412
+		ret = clk_prepare_enable(qspi->clk);
1413
+		if (ret) {
1414
+			dev_err(dev, "failed to prepare clock\n");
1415
+			goto qspi_probe_err;
1416
+		}
1417
+		qspi->base_clk = clk_get_rate(qspi->clk);
1418
+	} else {
1419
+		qspi->base_clk = MSPI_BASE_FREQ;
1420
+	}
1421
+
1422
+	if (data->has_mspi_rev) {
1423
+		rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
1424
+		/* some older revs do not have a MSPI_REV register */
1425
+		if ((rev & 0xff) == 0xff)
1426
+			rev = 0;
1427
+	}
1428
+
1429
+	qspi->mspi_maj_rev = (rev >> 4) & 0xf;
1430
+	qspi->mspi_min_rev = rev & 0xf;
1431
+	qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk;
1432
+
1433
+	qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
1434
+
1435
+	/*
1436
+	 * On SW resets it is possible to have the mask still enabled
1437
+	 * Need to disable the mask and clear the status while we init
1438
+	 */
1439
+	bcm_qspi_hw_uninit(qspi);
1440
+
12901441 	for (val = 0; val < num_irqs; val++) {
12911442 		irq = -1;
12921443 		name = qspi_irq_tab[val].irq_name;
12931444 		if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
12941445 			/* get the l2 interrupts */
1295
-			irq = platform_get_irq_byname(pdev, name);
1446
+			irq = platform_get_irq_byname_optional(pdev, name);
12961447 		} else if (!num_ints && soc_intc) {
12971448 			/* all mspi, bspi intrs muxed to one L1 intr */
12981449 			irq = platform_get_irq(pdev, 0);
....@@ -1322,33 +1473,6 @@
13221473 		ret = -EINVAL;
13231474 		goto qspi_unprepare_err;
13241475 	}
1325
-
1326
-	/*
1327
-	 * Some SoCs integrate spi controller (e.g., its interrupt bits)
1328
-	 * in specific ways
1329
-	 */
1330
-	if (soc_intc) {
1331
-		qspi->soc_intc = soc_intc;
1332
-		soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1333
-	} else {
1334
-		qspi->soc_intc = NULL;
1335
-	}
1336
-
1337
-	qspi->clk = devm_clk_get(&pdev->dev, NULL);
1338
-	if (IS_ERR(qspi->clk)) {
1339
-		dev_warn(dev, "unable to get clock\n");
1340
-		ret = PTR_ERR(qspi->clk);
1341
-		goto qspi_probe_err;
1342
-	}
1343
-
1344
-	ret = clk_prepare_enable(qspi->clk);
1345
-	if (ret) {
1346
-		dev_err(dev, "failed to prepare clock\n");
1347
-		goto qspi_probe_err;
1348
-	}
1349
-
1350
-	qspi->base_clk = clk_get_rate(qspi->clk);
1351
-	qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
13521476 
13531477 	bcm_qspi_hw_init(qspi);
13541478 	init_completion(&qspi->mspi_done);
....@@ -1404,7 +1528,7 @@
14041528 			bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
14051529 
14061530 	spi_master_suspend(qspi->master);
1407
-	clk_disable(qspi->clk);
1531
+	clk_disable_unprepare(qspi->clk);
14081532 	bcm_qspi_hw_uninit(qspi);
14091533 
14101534 	return 0;
....@@ -1422,7 +1546,7 @@
14221546 		qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
14231547 						 true);
14241548 
1425
-	ret = clk_enable(qspi->clk);
1549
+	ret = clk_prepare_enable(qspi->clk);
14261550 	if (!ret)
14271551 		spi_master_resume(qspi->master);
14281552