.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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1 | 2 | /* |
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2 | 3 | * pmcraid.c -- driver for PMC Sierra MaxRAID controller adapters |
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3 | 4 | * |
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.. | .. |
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5 | 6 | * PMC-Sierra Inc |
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6 | 7 | * |
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7 | 8 | * Copyright (C) 2008, 2009 PMC Sierra Inc |
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8 | | - * |
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9 | | - * This program is free software; you can redistribute it and/or modify |
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10 | | - * it under the terms of the GNU General Public License as published by |
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11 | | - * the Free Software Foundation; either version 2 of the License, or |
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12 | | - * (at your option) any later version. |
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13 | | - * |
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14 | | - * This program is distributed in the hope that it will be useful, |
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15 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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17 | | - * GNU General Public License for more details. |
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18 | | - * |
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19 | | - * You should have received a copy of the GNU General Public License |
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20 | | - * along with this program; if not, write to the Free Software |
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21 | | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, |
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22 | | - * USA |
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23 | | - * |
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24 | 9 | */ |
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25 | 10 | #include <linux/fs.h> |
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26 | 11 | #include <linux/init.h> |
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.. | .. |
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846 | 831 | cmd->ioa_cb->ioarcb.cdb[0], ioasc); |
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847 | 832 | } |
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848 | 833 | |
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849 | | - /* if we had allocated sense buffers for request sense, copy the sense |
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850 | | - * release the buffers |
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851 | | - */ |
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852 | | - if (cmd->sense_buffer != NULL) { |
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853 | | - memcpy(scsi_cmd->sense_buffer, |
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854 | | - cmd->sense_buffer, |
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855 | | - SCSI_SENSE_BUFFERSIZE); |
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856 | | - pci_free_consistent(pinstance->pdev, |
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857 | | - SCSI_SENSE_BUFFERSIZE, |
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858 | | - cmd->sense_buffer, cmd->sense_buffer_dma); |
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| 834 | + if (cmd->sense_buffer) { |
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| 835 | + dma_unmap_single(&pinstance->pdev->dev, cmd->sense_buffer_dma, |
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| 836 | + SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); |
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859 | 837 | cmd->sense_buffer = NULL; |
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860 | 838 | cmd->sense_buffer_dma = 0; |
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861 | 839 | } |
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.. | .. |
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2444 | 2422 | { |
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2445 | 2423 | struct pmcraid_ioarcb *ioarcb = &cmd->ioa_cb->ioarcb; |
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2446 | 2424 | struct pmcraid_ioadl_desc *ioadl = ioarcb->add_data.u.ioadl; |
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| 2425 | + struct device *dev = &cmd->drv_inst->pdev->dev; |
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2447 | 2426 | |
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2448 | | - /* allocate DMAable memory for sense buffers */ |
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2449 | | - cmd->sense_buffer = pci_alloc_consistent(cmd->drv_inst->pdev, |
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2450 | | - SCSI_SENSE_BUFFERSIZE, |
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2451 | | - &cmd->sense_buffer_dma); |
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2452 | | - |
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2453 | | - if (cmd->sense_buffer == NULL) { |
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| 2427 | + cmd->sense_buffer = cmd->scsi_cmd->sense_buffer; |
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| 2428 | + cmd->sense_buffer_dma = dma_map_single(dev, cmd->sense_buffer, |
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| 2429 | + SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); |
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| 2430 | + if (dma_mapping_error(dev, cmd->sense_buffer_dma)) { |
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2454 | 2431 | pmcraid_err |
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2455 | 2432 | ("couldn't allocate sense buffer for request sense\n"); |
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2456 | 2433 | pmcraid_erp_done(cmd); |
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.. | .. |
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2491 | 2468 | /** |
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2492 | 2469 | * pmcraid_cancel_all - cancel all outstanding IOARCBs as part of error recovery |
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2493 | 2470 | * @cmd: command that failed |
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2494 | | - * @sense: true if request_sense is required after cancel all |
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| 2471 | + * @need_sense: true if request_sense is required after cancel all |
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2495 | 2472 | * |
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2496 | 2473 | * This function sends a cancel all to a device to clear the queue. |
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2497 | 2474 | */ |
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2498 | | -static void pmcraid_cancel_all(struct pmcraid_cmd *cmd, u32 sense) |
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| 2475 | +static void pmcraid_cancel_all(struct pmcraid_cmd *cmd, bool need_sense) |
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2499 | 2476 | { |
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2500 | 2477 | struct scsi_cmnd *scsi_cmd = cmd->scsi_cmd; |
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2501 | 2478 | struct pmcraid_ioarcb *ioarcb = &cmd->ioa_cb->ioarcb; |
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2502 | 2479 | struct pmcraid_resource_entry *res = scsi_cmd->device->hostdata; |
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2503 | | - void (*cmd_done) (struct pmcraid_cmd *) = sense ? pmcraid_erp_done |
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2504 | | - : pmcraid_request_sense; |
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2505 | 2480 | |
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2506 | 2481 | memset(ioarcb->cdb, 0, PMCRAID_MAX_CDB_LEN); |
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2507 | 2482 | ioarcb->request_flags0 = SYNC_OVERRIDE; |
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.. | .. |
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2519 | 2494 | /* writing to IOARRIN must be protected by host_lock, as mid-layer |
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2520 | 2495 | * schedule queuecommand while we are doing this |
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2521 | 2496 | */ |
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2522 | | - pmcraid_send_cmd(cmd, cmd_done, |
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| 2497 | + pmcraid_send_cmd(cmd, need_sense ? |
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| 2498 | + pmcraid_erp_done : pmcraid_request_sense, |
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2523 | 2499 | PMCRAID_REQUEST_SENSE_TIMEOUT, |
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2524 | 2500 | pmcraid_timeout_handler); |
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2525 | 2501 | } |
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.. | .. |
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2612 | 2588 | struct pmcraid_ioasa *ioasa = &cmd->ioa_cb->ioasa; |
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2613 | 2589 | u32 ioasc = le32_to_cpu(ioasa->ioasc); |
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2614 | 2590 | u32 masked_ioasc = ioasc & PMCRAID_IOASC_SENSE_MASK; |
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2615 | | - u32 sense_copied = 0; |
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| 2591 | + bool sense_copied = false; |
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2616 | 2592 | |
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2617 | 2593 | if (!res) { |
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2618 | 2594 | pmcraid_info("resource pointer is NULL\n"); |
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.. | .. |
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2684 | 2660 | memcpy(scsi_cmd->sense_buffer, |
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2685 | 2661 | ioasa->sense_data, |
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2686 | 2662 | data_size); |
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2687 | | - sense_copied = 1; |
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| 2663 | + sense_copied = true; |
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2688 | 2664 | } |
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2689 | 2665 | |
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2690 | 2666 | if (RES_IS_GSCSI(res->cfg_entry)) |
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.. | .. |
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2884 | 2860 | { |
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2885 | 2861 | struct pmcraid_cmd *cancel_cmd; |
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2886 | 2862 | struct pmcraid_instance *pinstance; |
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2887 | | - struct pmcraid_resource_entry *res; |
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2888 | 2863 | |
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2889 | 2864 | pinstance = (struct pmcraid_instance *)cmd->drv_inst; |
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2890 | | - res = cmd->scsi_cmd->device->hostdata; |
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2891 | 2865 | |
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2892 | 2866 | cancel_cmd = pmcraid_get_free_cmd(pinstance); |
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2893 | 2867 | |
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.. | .. |
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3279 | 3253 | int direction |
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3280 | 3254 | ) |
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3281 | 3255 | { |
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3282 | | - struct scatterlist *scatterlist; |
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| 3256 | + struct scatterlist *sg; |
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3283 | 3257 | void *kaddr; |
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3284 | 3258 | int bsize_elem; |
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3285 | 3259 | int i; |
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.. | .. |
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3288 | 3262 | /* Determine the actual number of bytes per element */ |
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3289 | 3263 | bsize_elem = PAGE_SIZE * (1 << sglist->order); |
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3290 | 3264 | |
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3291 | | - scatterlist = sglist->scatterlist; |
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| 3265 | + sg = sglist->scatterlist; |
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3292 | 3266 | |
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3293 | | - for (i = 0; i < (len / bsize_elem); i++, buffer += bsize_elem) { |
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3294 | | - struct page *page = sg_page(&scatterlist[i]); |
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| 3267 | + for (i = 0; i < (len / bsize_elem); i++, sg = sg_next(sg), buffer += bsize_elem) { |
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| 3268 | + struct page *page = sg_page(sg); |
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3295 | 3269 | |
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3296 | 3270 | kaddr = kmap(page); |
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3297 | 3271 | if (direction == DMA_TO_DEVICE) |
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.. | .. |
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3306 | 3280 | return -EFAULT; |
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3307 | 3281 | } |
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3308 | 3282 | |
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3309 | | - scatterlist[i].length = bsize_elem; |
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| 3283 | + sg->length = bsize_elem; |
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3310 | 3284 | } |
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3311 | 3285 | |
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3312 | 3286 | if (len % bsize_elem) { |
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3313 | | - struct page *page = sg_page(&scatterlist[i]); |
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| 3287 | + struct page *page = sg_page(sg); |
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3314 | 3288 | |
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3315 | 3289 | kaddr = kmap(page); |
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3316 | 3290 | |
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.. | .. |
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3321 | 3295 | |
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3322 | 3296 | kunmap(page); |
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3323 | 3297 | |
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3324 | | - scatterlist[i].length = len % bsize_elem; |
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| 3298 | + sg->length = len % bsize_elem; |
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3325 | 3299 | } |
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3326 | 3300 | |
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3327 | 3301 | if (rc) { |
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.. | .. |
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3523 | 3497 | return -ENOMEM; |
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3524 | 3498 | } |
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3525 | 3499 | |
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3526 | | - sglist->num_dma_sg = pci_map_sg(cmd->drv_inst->pdev, |
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| 3500 | + sglist->num_dma_sg = dma_map_sg(&cmd->drv_inst->pdev->dev, |
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3527 | 3501 | sglist->scatterlist, |
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3528 | 3502 | sglist->num_sg, direction); |
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3529 | 3503 | |
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.. | .. |
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3572 | 3546 | struct pmcraid_sglist *sglist = cmd->sglist; |
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3573 | 3547 | |
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3574 | 3548 | if (buflen > 0) { |
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3575 | | - pci_unmap_sg(cmd->drv_inst->pdev, |
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| 3549 | + dma_unmap_sg(&cmd->drv_inst->pdev->dev, |
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3576 | 3550 | sglist->scatterlist, |
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3577 | 3551 | sglist->num_sg, |
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3578 | 3552 | direction); |
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.. | .. |
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3609 | 3583 | u32 ioasc; |
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3610 | 3584 | int request_size; |
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3611 | 3585 | int buffer_size; |
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3612 | | - u8 access, direction; |
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| 3586 | + u8 direction; |
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3613 | 3587 | int rc = 0; |
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3614 | 3588 | |
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3615 | 3589 | /* If IOA reset is in progress, wait 10 secs for reset to complete */ |
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.. | .. |
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3658 | 3632 | request_size = le32_to_cpu(buffer->ioarcb.data_transfer_length); |
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3659 | 3633 | |
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3660 | 3634 | if (buffer->ioarcb.request_flags0 & TRANSFER_DIR_WRITE) { |
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3661 | | - access = VERIFY_READ; |
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3662 | 3635 | direction = DMA_TO_DEVICE; |
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3663 | 3636 | } else { |
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3664 | | - access = VERIFY_WRITE; |
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3665 | 3637 | direction = DMA_FROM_DEVICE; |
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3666 | 3638 | } |
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3667 | 3639 | |
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.. | .. |
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3999 | 3971 | .open = pmcraid_chr_open, |
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4000 | 3972 | .fasync = pmcraid_chr_fasync, |
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4001 | 3973 | .unlocked_ioctl = pmcraid_chr_ioctl, |
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4002 | | -#ifdef CONFIG_COMPAT |
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4003 | | - .compat_ioctl = pmcraid_chr_ioctl, |
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4004 | | -#endif |
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| 3974 | + .compat_ioctl = compat_ptr_ioctl, |
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4005 | 3975 | .llseek = noop_llseek, |
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4006 | 3976 | }; |
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4007 | 3977 | |
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.. | .. |
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4158 | 4128 | .max_sectors = PMCRAID_IOA_MAX_SECTORS, |
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4159 | 4129 | .no_write_same = 1, |
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4160 | 4130 | .cmd_per_lun = PMCRAID_MAX_CMD_PER_LUN, |
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4161 | | - .use_clustering = ENABLE_CLUSTERING, |
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4162 | 4131 | .shost_attrs = pmcraid_host_attrs, |
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4163 | 4132 | .proc_name = PMCRAID_DRIVER_NAME, |
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4164 | 4133 | }; |
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.. | .. |
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4559 | 4528 | return 0; |
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4560 | 4529 | |
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4561 | 4530 | out_unwind: |
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4562 | | - while (--i > 0) |
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| 4531 | + while (--i >= 0) |
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4563 | 4532 | free_irq(pci_irq_vector(pdev, i), &pinstance->hrrq_vector[i]); |
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4564 | 4533 | pci_free_irq_vectors(pdev); |
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4565 | 4534 | return rc; |
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.. | .. |
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4681 | 4650 | |
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4682 | 4651 | for (i = 0; i < PMCRAID_MAX_CMD; i++) { |
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4683 | 4652 | pinstance->cmd_list[i]->ioa_cb = |
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4684 | | - dma_pool_alloc( |
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| 4653 | + dma_pool_zalloc( |
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4685 | 4654 | pinstance->control_pool, |
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4686 | 4655 | GFP_KERNEL, |
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4687 | 4656 | &(pinstance->cmd_list[i]->ioa_cb_bus_addr)); |
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.. | .. |
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4690 | 4659 | pmcraid_release_control_blocks(pinstance, i); |
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4691 | 4660 | return -ENOMEM; |
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4692 | 4661 | } |
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4693 | | - memset(pinstance->cmd_list[i]->ioa_cb, 0, |
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4694 | | - sizeof(struct pmcraid_control_block)); |
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4695 | 4662 | } |
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4696 | 4663 | return 0; |
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4697 | 4664 | } |
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.. | .. |
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4708 | 4675 | pmcraid_release_host_rrqs(struct pmcraid_instance *pinstance, int maxindex) |
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4709 | 4676 | { |
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4710 | 4677 | int i; |
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4711 | | - for (i = 0; i < maxindex; i++) { |
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4712 | 4678 | |
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4713 | | - pci_free_consistent(pinstance->pdev, |
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| 4679 | + for (i = 0; i < maxindex; i++) { |
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| 4680 | + dma_free_coherent(&pinstance->pdev->dev, |
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4714 | 4681 | HRRQ_ENTRY_SIZE * PMCRAID_MAX_CMD, |
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4715 | 4682 | pinstance->hrrq_start[i], |
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4716 | 4683 | pinstance->hrrq_start_bus_addr[i]); |
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.. | .. |
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4737 | 4704 | |
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4738 | 4705 | for (i = 0; i < pinstance->num_hrrq; i++) { |
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4739 | 4706 | pinstance->hrrq_start[i] = |
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4740 | | - pci_alloc_consistent( |
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4741 | | - pinstance->pdev, |
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4742 | | - buffer_size, |
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4743 | | - &(pinstance->hrrq_start_bus_addr[i])); |
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4744 | | - |
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| 4707 | + dma_alloc_coherent(&pinstance->pdev->dev, buffer_size, |
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| 4708 | + &pinstance->hrrq_start_bus_addr[i], |
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| 4709 | + GFP_KERNEL); |
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4745 | 4710 | if (!pinstance->hrrq_start[i]) { |
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4746 | 4711 | pmcraid_err("pci_alloc failed for hrrq vector : %d\n", |
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4747 | 4712 | i); |
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.. | .. |
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4749 | 4714 | return -ENOMEM; |
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4750 | 4715 | } |
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4751 | 4716 | |
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4752 | | - memset(pinstance->hrrq_start[i], 0, buffer_size); |
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4753 | 4717 | pinstance->hrrq_curr[i] = pinstance->hrrq_start[i]; |
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4754 | 4718 | pinstance->hrrq_end[i] = |
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4755 | 4719 | pinstance->hrrq_start[i] + PMCRAID_MAX_CMD - 1; |
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.. | .. |
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4770 | 4734 | static void pmcraid_release_hcams(struct pmcraid_instance *pinstance) |
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4771 | 4735 | { |
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4772 | 4736 | if (pinstance->ccn.msg != NULL) { |
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4773 | | - pci_free_consistent(pinstance->pdev, |
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| 4737 | + dma_free_coherent(&pinstance->pdev->dev, |
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4774 | 4738 | PMCRAID_AEN_HDR_SIZE + |
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4775 | 4739 | sizeof(struct pmcraid_hcam_ccn_ext), |
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4776 | 4740 | pinstance->ccn.msg, |
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.. | .. |
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4782 | 4746 | } |
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4783 | 4747 | |
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4784 | 4748 | if (pinstance->ldn.msg != NULL) { |
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4785 | | - pci_free_consistent(pinstance->pdev, |
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| 4749 | + dma_free_coherent(&pinstance->pdev->dev, |
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4786 | 4750 | PMCRAID_AEN_HDR_SIZE + |
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4787 | 4751 | sizeof(struct pmcraid_hcam_ldn), |
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4788 | 4752 | pinstance->ldn.msg, |
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.. | .. |
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4803 | 4767 | */ |
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4804 | 4768 | static int pmcraid_allocate_hcams(struct pmcraid_instance *pinstance) |
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4805 | 4769 | { |
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4806 | | - pinstance->ccn.msg = pci_alloc_consistent( |
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4807 | | - pinstance->pdev, |
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| 4770 | + pinstance->ccn.msg = dma_alloc_coherent(&pinstance->pdev->dev, |
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4808 | 4771 | PMCRAID_AEN_HDR_SIZE + |
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4809 | 4772 | sizeof(struct pmcraid_hcam_ccn_ext), |
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4810 | | - &(pinstance->ccn.baddr)); |
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| 4773 | + &pinstance->ccn.baddr, GFP_KERNEL); |
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4811 | 4774 | |
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4812 | | - pinstance->ldn.msg = pci_alloc_consistent( |
---|
4813 | | - pinstance->pdev, |
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| 4775 | + pinstance->ldn.msg = dma_alloc_coherent(&pinstance->pdev->dev, |
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4814 | 4776 | PMCRAID_AEN_HDR_SIZE + |
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4815 | 4777 | sizeof(struct pmcraid_hcam_ldn), |
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4816 | | - &(pinstance->ldn.baddr)); |
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| 4778 | + &pinstance->ldn.baddr, GFP_KERNEL); |
---|
4817 | 4779 | |
---|
4818 | 4780 | if (pinstance->ldn.msg == NULL || pinstance->ccn.msg == NULL) { |
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4819 | 4781 | pmcraid_release_hcams(pinstance); |
---|
.. | .. |
---|
4841 | 4803 | { |
---|
4842 | 4804 | if (pinstance->cfg_table != NULL && |
---|
4843 | 4805 | pinstance->cfg_table_bus_addr != 0) { |
---|
4844 | | - pci_free_consistent(pinstance->pdev, |
---|
| 4806 | + dma_free_coherent(&pinstance->pdev->dev, |
---|
4845 | 4807 | sizeof(struct pmcraid_config_table), |
---|
4846 | 4808 | pinstance->cfg_table, |
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4847 | 4809 | pinstance->cfg_table_bus_addr); |
---|
.. | .. |
---|
4886 | 4848 | list_add_tail(&pinstance->res_entries[i].queue, |
---|
4887 | 4849 | &pinstance->free_res_q); |
---|
4888 | 4850 | |
---|
4889 | | - pinstance->cfg_table = |
---|
4890 | | - pci_alloc_consistent(pinstance->pdev, |
---|
| 4851 | + pinstance->cfg_table = dma_alloc_coherent(&pinstance->pdev->dev, |
---|
4891 | 4852 | sizeof(struct pmcraid_config_table), |
---|
4892 | | - &pinstance->cfg_table_bus_addr); |
---|
| 4853 | + &pinstance->cfg_table_bus_addr, |
---|
| 4854 | + GFP_KERNEL); |
---|
4893 | 4855 | |
---|
4894 | 4856 | if (NULL == pinstance->cfg_table) { |
---|
4895 | 4857 | pmcraid_err("couldn't alloc DMA memory for config table\n"); |
---|
.. | .. |
---|
4954 | 4916 | pmcraid_release_host_rrqs(pinstance, pinstance->num_hrrq); |
---|
4955 | 4917 | |
---|
4956 | 4918 | if (pinstance->inq_data != NULL) { |
---|
4957 | | - pci_free_consistent(pinstance->pdev, |
---|
| 4919 | + dma_free_coherent(&pinstance->pdev->dev, |
---|
4958 | 4920 | sizeof(struct pmcraid_inquiry_data), |
---|
4959 | 4921 | pinstance->inq_data, |
---|
4960 | 4922 | pinstance->inq_data_baddr); |
---|
.. | .. |
---|
4964 | 4926 | } |
---|
4965 | 4927 | |
---|
4966 | 4928 | if (pinstance->timestamp_data != NULL) { |
---|
4967 | | - pci_free_consistent(pinstance->pdev, |
---|
| 4929 | + dma_free_coherent(&pinstance->pdev->dev, |
---|
4968 | 4930 | sizeof(struct pmcraid_timestamp_data), |
---|
4969 | 4931 | pinstance->timestamp_data, |
---|
4970 | 4932 | pinstance->timestamp_data_baddr); |
---|
.. | .. |
---|
4981 | 4943 | * This routine pre-allocates memory based on the type of block as below: |
---|
4982 | 4944 | * cmdblocks(PMCRAID_MAX_CMD): kernel memory using kernel's slab_allocator, |
---|
4983 | 4945 | * IOARCBs(PMCRAID_MAX_CMD) : DMAable memory, using pci pool allocator |
---|
4984 | | - * config-table entries : DMAable memory using pci_alloc_consistent |
---|
4985 | | - * HostRRQs : DMAable memory, using pci_alloc_consistent |
---|
| 4946 | + * config-table entries : DMAable memory using dma_alloc_coherent |
---|
| 4947 | + * HostRRQs : DMAable memory, using dma_alloc_coherent |
---|
4986 | 4948 | * |
---|
4987 | 4949 | * Return Value |
---|
4988 | 4950 | * 0 in case all of the blocks are allocated, -ENOMEM otherwise. |
---|
.. | .. |
---|
5019 | 4981 | } |
---|
5020 | 4982 | |
---|
5021 | 4983 | /* allocate DMAable memory for page D0 INQUIRY buffer */ |
---|
5022 | | - pinstance->inq_data = pci_alloc_consistent( |
---|
5023 | | - pinstance->pdev, |
---|
| 4984 | + pinstance->inq_data = dma_alloc_coherent(&pinstance->pdev->dev, |
---|
5024 | 4985 | sizeof(struct pmcraid_inquiry_data), |
---|
5025 | | - &pinstance->inq_data_baddr); |
---|
5026 | | - |
---|
| 4986 | + &pinstance->inq_data_baddr, GFP_KERNEL); |
---|
5027 | 4987 | if (pinstance->inq_data == NULL) { |
---|
5028 | 4988 | pmcraid_err("couldn't allocate DMA memory for INQUIRY\n"); |
---|
5029 | 4989 | pmcraid_release_buffers(pinstance); |
---|
.. | .. |
---|
5031 | 4991 | } |
---|
5032 | 4992 | |
---|
5033 | 4993 | /* allocate DMAable memory for set timestamp data buffer */ |
---|
5034 | | - pinstance->timestamp_data = pci_alloc_consistent( |
---|
5035 | | - pinstance->pdev, |
---|
| 4994 | + pinstance->timestamp_data = dma_alloc_coherent(&pinstance->pdev->dev, |
---|
5036 | 4995 | sizeof(struct pmcraid_timestamp_data), |
---|
5037 | | - &pinstance->timestamp_data_baddr); |
---|
5038 | | - |
---|
| 4996 | + &pinstance->timestamp_data_baddr, |
---|
| 4997 | + GFP_KERNEL); |
---|
5039 | 4998 | if (pinstance->timestamp_data == NULL) { |
---|
5040 | 4999 | pmcraid_err("couldn't allocate DMA memory for \ |
---|
5041 | 5000 | set time_stamp \n"); |
---|
.. | .. |
---|
5324 | 5283 | |
---|
5325 | 5284 | pci_set_master(pdev); |
---|
5326 | 5285 | |
---|
5327 | | - if ((sizeof(dma_addr_t) == 4) || |
---|
5328 | | - pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) |
---|
5329 | | - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
---|
| 5286 | + if (sizeof(dma_addr_t) == 4 || |
---|
| 5287 | + dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) |
---|
| 5288 | + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
---|
5330 | 5289 | |
---|
5331 | 5290 | if (rc == 0) |
---|
5332 | | - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
---|
| 5291 | + rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
---|
5333 | 5292 | |
---|
5334 | 5293 | if (rc != 0) { |
---|
5335 | 5294 | dev_err(&pdev->dev, "resume: Failed to set PCI DMA mask\n"); |
---|
.. | .. |
---|
5733 | 5692 | /* Firmware requires the system bus address of IOARCB to be within |
---|
5734 | 5693 | * 32-bit addressable range though it has 64-bit IOARRIN register. |
---|
5735 | 5694 | * However, firmware supports 64-bit streaming DMA buffers, whereas |
---|
5736 | | - * coherent buffers are to be 32-bit. Since pci_alloc_consistent always |
---|
| 5695 | + * coherent buffers are to be 32-bit. Since dma_alloc_coherent always |
---|
5737 | 5696 | * returns memory within 4GB (if not, change this logic), coherent |
---|
5738 | 5697 | * buffers are within firmware acceptable address ranges. |
---|
5739 | 5698 | */ |
---|
5740 | | - if ((sizeof(dma_addr_t) == 4) || |
---|
5741 | | - pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) |
---|
5742 | | - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
---|
| 5699 | + if (sizeof(dma_addr_t) == 4 || |
---|
| 5700 | + dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) |
---|
| 5701 | + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
---|
5743 | 5702 | |
---|
5744 | 5703 | /* firmware expects 32-bit DMA addresses for IOARRIN register; set 32 |
---|
5745 | | - * bit mask for pci_alloc_consistent to return addresses within 4GB |
---|
| 5704 | + * bit mask for dma_alloc_coherent to return addresses within 4GB |
---|
5746 | 5705 | */ |
---|
5747 | 5706 | if (rc == 0) |
---|
5748 | | - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
---|
| 5707 | + rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
---|
5749 | 5708 | |
---|
5750 | 5709 | if (rc != 0) { |
---|
5751 | 5710 | dev_err(&pdev->dev, "Failed to set PCI DMA mask\n"); |
---|
.. | .. |
---|
5875 | 5834 | } |
---|
5876 | 5835 | |
---|
5877 | 5836 | /* |
---|
5878 | | - * PCI driver structure of pcmraid driver |
---|
| 5837 | + * PCI driver structure of pmcraid driver |
---|
5879 | 5838 | */ |
---|
5880 | 5839 | static struct pci_driver pmcraid_driver = { |
---|
5881 | 5840 | .name = PMCRAID_DRIVER_NAME, |
---|