forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/scsi/mac_scsi.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Generic Macintosh NCR5380 driver
34  *
....@@ -24,6 +25,7 @@
2425 
2526 #include <asm/hwtest.h>
2627 #include <asm/io.h>
28
+#include <asm/macintosh.h>
2729 #include <asm/macints.h>
2830 #include <asm/setup.h>
2931 
....@@ -262,11 +264,22 @@
262264 	return addr - start;
263265 }
264266 
267
+/* The "SCSI DMA" chip on the IIfx implements this register. */
268
+#define CTRL_REG                0x8
269
+#define CTRL_INTERRUPTS_ENABLE  BIT(1)
270
+#define CTRL_HANDSHAKE_MODE     BIT(3)
271
+
272
+static inline void write_ctrl_reg(struct NCR5380_hostdata *hostdata, u32 value)
273
+{
274
+	out_be32(hostdata->io + (CTRL_REG << 4), value);
275
+}
276
+
265277 static inline int macscsi_pread(struct NCR5380_hostdata *hostdata,
266278                                 unsigned char *dst, int len)
267279 {
268280 	u8 __iomem *s = hostdata->pdma_io + (INPUT_DATA_REG << 4);
269281 	unsigned char *d = dst;
282
+	int result = 0;
270283 
271284 	hostdata->pdma_residual = len;
272285 
....@@ -274,6 +287,10 @@
274287 	                              BASR_DRQ | BASR_PHASE_MATCH,
275288 	                              BASR_DRQ | BASR_PHASE_MATCH, HZ / 64)) {
276289 		int bytes;
290
+
291
+		if (macintosh_config->ident == MAC_MODEL_IIFX)
292
+			write_ctrl_reg(hostdata, CTRL_HANDSHAKE_MODE |
293
+			                         CTRL_INTERRUPTS_ENABLE);
277294 
278295 		bytes = mac_pdma_recv(s, d, min(hostdata->pdma_residual, 512));
279296 
....@@ -283,7 +300,7 @@
283300 		}
284301 
285302 		if (hostdata->pdma_residual == 0)
286
-			return 0;
303
+			goto out;
287304 
288305 		if (NCR5380_poll_politely2(hostdata, STATUS_REG, SR_REQ, SR_REQ,
289306 		                           BUS_AND_STATUS_REG, BASR_ACK,
....@@ -291,7 +308,7 @@
291308 			scmd_printk(KERN_DEBUG, hostdata->connected,
292309 			            "%s: !REQ and !ACK\n", __func__);
293310 		if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH))
294
-			return 0;
311
+			goto out;
295312 
296313 		if (bytes == 0)
297314 			udelay(MAC_PDMA_DELAY);
....@@ -302,13 +319,18 @@
302319 		dsprintk(NDEBUG_PSEUDO_DMA, hostdata->host,
303320 		         "%s: bus error (%d/%d)\n", __func__, d - dst, len);
304321 		NCR5380_dprint(NDEBUG_PSEUDO_DMA, hostdata->host);
305
-		return -1;
322
+		result = -1;
323
+		goto out;
306324 	}
307325 
308326 	scmd_printk(KERN_ERR, hostdata->connected,
309327 	            "%s: phase mismatch or !DRQ\n", __func__);
310328 	NCR5380_dprint(NDEBUG_PSEUDO_DMA, hostdata->host);
311
-	return -1;
329
+	result = -1;
330
+out:
331
+	if (macintosh_config->ident == MAC_MODEL_IIFX)
332
+		write_ctrl_reg(hostdata, CTRL_INTERRUPTS_ENABLE);
333
+	return result;
312334 }
313335 
314336 static inline int macscsi_pwrite(struct NCR5380_hostdata *hostdata,
....@@ -316,6 +338,7 @@
316338 {
317339 	unsigned char *s = src;
318340 	u8 __iomem *d = hostdata->pdma_io + (OUTPUT_DATA_REG << 4);
341
+	int result = 0;
319342 
320343 	hostdata->pdma_residual = len;
321344 
....@@ -323,6 +346,10 @@
323346 	                              BASR_DRQ | BASR_PHASE_MATCH,
324347 	                              BASR_DRQ | BASR_PHASE_MATCH, HZ / 64)) {
325348 		int bytes;
349
+
350
+		if (macintosh_config->ident == MAC_MODEL_IIFX)
351
+			write_ctrl_reg(hostdata, CTRL_HANDSHAKE_MODE |
352
+			                         CTRL_INTERRUPTS_ENABLE);
326353 
327354 		bytes = mac_pdma_send(s, d, min(hostdata->pdma_residual, 512));
328355 
....@@ -334,10 +361,13 @@
334361 		if (hostdata->pdma_residual == 0) {
335362 			if (NCR5380_poll_politely(hostdata, TARGET_COMMAND_REG,
336363 			                          TCR_LAST_BYTE_SENT,
337
-			                          TCR_LAST_BYTE_SENT, HZ / 64) < 0)
364
+			                          TCR_LAST_BYTE_SENT,
365
+			                          HZ / 64) < 0) {
338366 				scmd_printk(KERN_ERR, hostdata->connected,
339367 				            "%s: Last Byte Sent timeout\n", __func__);
340
-			return 0;
368
+				result = -1;
369
+			}
370
+			goto out;
341371 		}
342372 
343373 		if (NCR5380_poll_politely2(hostdata, STATUS_REG, SR_REQ, SR_REQ,
....@@ -346,7 +376,7 @@
346376 			scmd_printk(KERN_DEBUG, hostdata->connected,
347377 			            "%s: !REQ and !ACK\n", __func__);
348378 		if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH))
349
-			return 0;
379
+			goto out;
350380 
351381 		if (bytes == 0)
352382 			udelay(MAC_PDMA_DELAY);
....@@ -357,13 +387,18 @@
357387 		dsprintk(NDEBUG_PSEUDO_DMA, hostdata->host,
358388 		         "%s: bus error (%d/%d)\n", __func__, s - src, len);
359389 		NCR5380_dprint(NDEBUG_PSEUDO_DMA, hostdata->host);
360
-		return -1;
390
+		result = -1;
391
+		goto out;
361392 	}
362393 
363394 	scmd_printk(KERN_ERR, hostdata->connected,
364395 	            "%s: phase mismatch or !DRQ\n", __func__);
365396 	NCR5380_dprint(NDEBUG_PSEUDO_DMA, hostdata->host);
366
-	return -1;
397
+	result = -1;
398
+out:
399
+	if (macintosh_config->ident == MAC_MODEL_IIFX)
400
+		write_ctrl_reg(hostdata, CTRL_INTERRUPTS_ENABLE);
401
+	return result;
367402 }
368403 
369404 static int macscsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
....@@ -398,7 +433,7 @@
398433 	.this_id		= 7,
399434 	.sg_tablesize		= 1,
400435 	.cmd_per_lun		= 2,
401
-	.use_clustering		= DISABLE_CLUSTERING,
436
+	.dma_boundary		= PAGE_SIZE - 1,
402437 	.cmd_size		= NCR5380_CMD_SIZE,
403438 	.max_sectors		= 128,
404439 };