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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/rtc/rtc-mc146818-lib.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 #include <linux/bcd.h>
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 #include <linux/delay.h>
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 #include <linux/export.h>
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@@ -8,40 +9,143 @@
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 #endif
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10
 
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 /*
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- * Returns true if a clock update is in progress
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+ * Execute a function while the UIP (Update-in-progress) bit of the RTC is
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+ * unset.
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+ *
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+ * Warning: callback may be executed more then once.
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  */
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-static inline unsigned char mc146818_is_updating(void)
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+bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param),
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+			void *param)
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 {
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-	unsigned char uip;
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+	int i;
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+	unsigned long flags;
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+	unsigned char seconds;
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+
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+	for (i = 0; i < 10; i++) {
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+		spin_lock_irqsave(&rtc_lock, flags);
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+
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+		/*
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+		 * Check whether there is an update in progress during which the
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+		 * readout is unspecified. The maximum update time is ~2ms. Poll
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+		 * every msec for completion.
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+		 *
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+		 * Store the second value before checking UIP so a long lasting
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+		 * NMI which happens to hit after the UIP check cannot make
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+		 * an update cycle invisible.
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+		 */
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+		seconds = CMOS_READ(RTC_SECONDS);
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+
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+		if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) {
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+			spin_unlock_irqrestore(&rtc_lock, flags);
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+			mdelay(1);
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+			continue;
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+		}
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+
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+		/* Revalidate the above readout */
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+		if (seconds != CMOS_READ(RTC_SECONDS)) {
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+			spin_unlock_irqrestore(&rtc_lock, flags);
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+			continue;
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+		}
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+
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+		if (callback)
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+			callback(seconds, param);
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+
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+		/*
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+		 * Check for the UIP bit again. If it is set now then
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+		 * the above values may contain garbage.
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+		 */
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+		if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) {
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+			spin_unlock_irqrestore(&rtc_lock, flags);
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+			mdelay(1);
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+			continue;
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+		}
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+
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+		/*
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+		 * A NMI might have interrupted the above sequence so check
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+		 * whether the seconds value has changed which indicates that
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+		 * the NMI took longer than the UIP bit was set. Unlikely, but
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+		 * possible and there is also virt...
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+		 */
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+		if (seconds != CMOS_READ(RTC_SECONDS)) {
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+			spin_unlock_irqrestore(&rtc_lock, flags);
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+			continue;
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+		}
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+		spin_unlock_irqrestore(&rtc_lock, flags);
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+
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+		return true;
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+	}
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+	return false;
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+}
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+EXPORT_SYMBOL_GPL(mc146818_avoid_UIP);
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+
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+/*
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+ * If the UIP (Update-in-progress) bit of the RTC is set for more then
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+ * 10ms, the RTC is apparently broken or not present.
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+ */
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+bool mc146818_does_rtc_work(void)
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+{
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+	int i;
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+	unsigned char val;
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 	unsigned long flags;
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-	spin_lock_irqsave(&rtc_lock, flags);
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-	uip = (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
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-	spin_unlock_irqrestore(&rtc_lock, flags);
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-	return uip;
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-}
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+	for (i = 0; i < 10; i++) {
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+		spin_lock_irqsave(&rtc_lock, flags);
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+		val = CMOS_READ(RTC_FREQ_SELECT);
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+		spin_unlock_irqrestore(&rtc_lock, flags);
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95
 
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-unsigned int mc146818_get_time(struct rtc_time *time)
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+		if ((val & RTC_UIP) == 0)
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+			return true;
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+
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+		mdelay(1);
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+	}
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+
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+	return false;
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+}
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+EXPORT_SYMBOL_GPL(mc146818_does_rtc_work);
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+
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+int mc146818_get_time(struct rtc_time *time)
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 {
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 	unsigned char ctrl;
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 	unsigned long flags;
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+	unsigned int iter_count = 0;
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 	unsigned char century = 0;
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+	bool retry;
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113
 
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 #ifdef CONFIG_MACH_DECSTATION
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 	unsigned int real_year;
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 #endif
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117
 
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+again:
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+	if (iter_count > 10) {
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+		memset(time, 0, sizeof(*time));
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+		return -EIO;
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+	}
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+	iter_count++;
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+
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+	spin_lock_irqsave(&rtc_lock, flags);
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+
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 	/*
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-	 * read RTC once any update in progress is done. The update
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-	 * can take just over 2ms. We wait 20ms. There is no need to
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-	 * to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP.
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-	 * If you need to know *exactly* when a second has started, enable
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-	 * periodic update complete interrupts, (via ioctl) and then
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-	 * immediately read /dev/rtc which will block until you get the IRQ.
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-	 * Once the read clears, read the RTC time (again via ioctl). Easy.
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+	 * Check whether there is an update in progress during which the
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+	 * readout is unspecified. The maximum update time is ~2ms. Poll
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+	 * every msec for completion.
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+	 *
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+	 * Store the second value before checking UIP so a long lasting NMI
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+	 * which happens to hit after the UIP check cannot make an update
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+	 * cycle invisible.
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 	 */
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-	if (mc146818_is_updating())
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-		mdelay(20);
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+	time->tm_sec = CMOS_READ(RTC_SECONDS);
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+
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+	if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) {
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+		spin_unlock_irqrestore(&rtc_lock, flags);
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+		mdelay(1);
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+		goto again;
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+	}
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+
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+	/* Revalidate the above readout */
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+	if (time->tm_sec != CMOS_READ(RTC_SECONDS)) {
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+		spin_unlock_irqrestore(&rtc_lock, flags);
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+		goto again;
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+	}
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 	/*
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 	 * Only the values that we read from the RTC are set. We leave
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..
@@ -49,8 +153,6 @@
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 	 * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated
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 	 * by the RTC when initially set to a non-zero value.
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 	 */
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-	spin_lock_irqsave(&rtc_lock, flags);
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-	time->tm_sec = CMOS_READ(RTC_SECONDS);
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 	time->tm_min = CMOS_READ(RTC_MINUTES);
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 	time->tm_hour = CMOS_READ(RTC_HOURS);
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 	time->tm_mday = CMOS_READ(RTC_DAY_OF_MONTH);
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@@ -65,7 +167,23 @@
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 		century = CMOS_READ(acpi_gbl_FADT.century);
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 #endif
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 	ctrl = CMOS_READ(RTC_CONTROL);
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+	/*
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+	 * Check for the UIP bit again. If it is set now then
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+	 * the above values may contain garbage.
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+	 */
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+	retry = CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP;
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+	/*
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+	 * A NMI might have interrupted the above sequence so check whether
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+	 * the seconds value has changed which indicates that the NMI took
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+	 * longer than the UIP bit was set. Unlikely, but possible and
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+	 * there is also virt...
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+	 */
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+	retry |= time->tm_sec != CMOS_READ(RTC_SECONDS);
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+
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 	spin_unlock_irqrestore(&rtc_lock, flags);
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+
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+	if (retry)
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+		goto again;
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 	if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
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 	{
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@@ -94,9 +212,20 @@
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212
 
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 	time->tm_mon--;
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214
 
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-	return RTC_24H;
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+	return 0;
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 }
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 EXPORT_SYMBOL_GPL(mc146818_get_time);
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+
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+/* AMD systems don't allow access to AltCentury with DV1 */
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+static bool apply_amd_register_a_behavior(void)
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+{
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+#ifdef CONFIG_X86
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+	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
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+	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
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+		return true;
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+#endif
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+	return false;
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+}
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 /* Set the current date and time in the real time clock. */
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 int mc146818_set_time(struct rtc_time *time)
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@@ -120,7 +249,6 @@
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 	if (yrs > 255)	/* They are unsigned */
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 		return -EINVAL;
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-	spin_lock_irqsave(&rtc_lock, flags);
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 #ifdef CONFIG_MACH_DECSTATION
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 	real_yrs = yrs;
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 	leap_yr = ((!((yrs + 1900) % 4) && ((yrs + 1900) % 100)) ||
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@@ -149,16 +277,16 @@
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 	/* These limits and adjustments are independent of
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 	 * whether the chip is in binary mode or not.
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 	 */
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-	if (yrs > 169) {
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-		spin_unlock_irqrestore(&rtc_lock, flags);
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+	if (yrs > 169)
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 		return -EINVAL;
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-	}
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282
 
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 	if (yrs >= 100)
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 		yrs -= 100;
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-	if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
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-	    || RTC_ALWAYS_BCD) {
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+	spin_lock_irqsave(&rtc_lock, flags);
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+	save_control = CMOS_READ(RTC_CONTROL);
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+	spin_unlock_irqrestore(&rtc_lock, flags);
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+	if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
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 		sec = bin2bcd(sec);
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 		min = bin2bcd(min);
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 		hrs = bin2bcd(hrs);
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@@ -168,10 +296,14 @@
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 		century = bin2bcd(century);
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 	}
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+	spin_lock_irqsave(&rtc_lock, flags);
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 	save_control = CMOS_READ(RTC_CONTROL);
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 	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
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 	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
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-	CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
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+	if (apply_amd_register_a_behavior())
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+		CMOS_WRITE((save_freq_select & ~RTC_AMD_BANK_SELECT), RTC_FREQ_SELECT);
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+	else
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+		CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
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 #ifdef CONFIG_MACH_DECSTATION
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 	CMOS_WRITE(real_yrs, RTC_DEC_YEAR);