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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/rtc/rtc-jz4740.c
....@@ -1,17 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0+
12 /*
23  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
34  *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
45  *	 JZ4740 SoC RTC driver
5
- *
6
- *  This program is free software; you can redistribute it and/or modify it
7
- *  under  the terms of  the GNU General Public License as published by the
8
- *  Free Software Foundation;  either version 2 of the License, or (at your
9
- *  option) any later version.
10
- *
11
- *  You should have received a copy of the GNU General Public License along
12
- *  with this program; if not, write to the Free Software Foundation, Inc.,
13
- *  675 Mass Ave, Cambridge, MA 02139, USA.
14
- *
156  */
167 
178 #include <linux/clk.h>
....@@ -20,6 +11,7 @@
2011 #include <linux/module.h>
2112 #include <linux/of_device.h>
2213 #include <linux/platform_device.h>
14
+#include <linux/pm_wakeirq.h>
2315 #include <linux/reboot.h>
2416 #include <linux/rtc.h>
2517 #include <linux/slab.h>
....@@ -54,6 +46,7 @@
5446 
5547 enum jz4740_rtc_type {
5648 	ID_JZ4740,
49
+	ID_JZ4760,
5750 	ID_JZ4780,
5851 };
5952 
....@@ -62,14 +55,8 @@
6255 	enum jz4740_rtc_type type;
6356 
6457 	struct rtc_device *rtc;
65
-	struct clk *clk;
66
-
67
-	int irq;
6858 
6959 	spinlock_t lock;
70
-
71
-	unsigned int min_wakeup_pin_assert_time;
72
-	unsigned int reset_pin_assert_time;
7360 };
7461 
7562 static struct device *dev_for_power_off;
....@@ -114,7 +101,7 @@
114101 {
115102 	int ret = 0;
116103 
117
-	if (rtc->type >= ID_JZ4780)
104
+	if (rtc->type >= ID_JZ4760)
118105 		ret = jz4780_rtc_enable_write(rtc);
119106 	if (ret == 0)
120107 		ret = jz4740_rtc_wait_write_ready(rtc);
....@@ -156,6 +143,9 @@
156143 	uint32_t secs, secs2;
157144 	int timeout = 5;
158145 
146
+	if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
147
+		return -EINVAL;
148
+
159149 	/* If the seconds register is read while it is updated, it can contain a
160150 	 * bogus value. This can be avoided by making sure that two consecutive
161151 	 * reads have the same value.
....@@ -171,16 +161,21 @@
171161 	if (timeout == 0)
172162 		return -EIO;
173163 
174
-	rtc_time_to_tm(secs, time);
164
+	rtc_time64_to_tm(secs, time);
175165 
176166 	return 0;
177167 }
178168 
179
-static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
169
+static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
180170 {
181171 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
172
+	int ret;
182173 
183
-	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
174
+	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
175
+	if (ret)
176
+		return ret;
177
+
178
+	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
184179 }
185180 
186181 static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
....@@ -196,18 +191,16 @@
196191 	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
197192 	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
198193 
199
-	rtc_time_to_tm(secs, &alrm->time);
194
+	rtc_time64_to_tm(secs, &alrm->time);
200195 
201
-	return rtc_valid_tm(&alrm->time);
196
+	return 0;
202197 }
203198 
204199 static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
205200 {
206201 	int ret;
207202 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
208
-	unsigned long secs;
209
-
210
-	rtc_tm_to_time(&alrm->time, &secs);
203
+	uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
211204 
212205 	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
213206 	if (!ret)
....@@ -225,7 +218,7 @@
225218 
226219 static const struct rtc_class_ops jz4740_rtc_ops = {
227220 	.read_time	= jz4740_rtc_read_time,
228
-	.set_mmss	= jz4740_rtc_set_mmss,
221
+	.set_time	= jz4740_rtc_set_time,
229222 	.read_alarm	= jz4740_rtc_read_alarm,
230223 	.set_alarm	= jz4740_rtc_set_alarm,
231224 	.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
....@@ -260,187 +253,157 @@
260253 
261254 static void jz4740_rtc_power_off(void)
262255 {
263
-	struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
264
-	unsigned long rtc_rate;
265
-	unsigned long wakeup_filter_ticks;
266
-	unsigned long reset_counter_ticks;
267
-
268
-	clk_prepare_enable(rtc->clk);
269
-
270
-	rtc_rate = clk_get_rate(rtc->clk);
271
-
272
-	/*
273
-	 * Set minimum wakeup pin assertion time: 100 ms.
274
-	 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
275
-	 */
276
-	wakeup_filter_ticks =
277
-		(rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
278
-	if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
279
-		wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
280
-	else
281
-		wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
282
-	jz4740_rtc_reg_write(rtc,
283
-			     JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
284
-
285
-	/*
286
-	 * Set reset pin low-level assertion time after wakeup: 60 ms.
287
-	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
288
-	 */
289
-	reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
290
-	if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
291
-		reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
292
-	else
293
-		reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
294
-	jz4740_rtc_reg_write(rtc,
295
-			     JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
296
-
297256 	jz4740_rtc_poweroff(dev_for_power_off);
298257 	kernel_halt();
299258 }
300259 
260
+static void jz4740_rtc_clk_disable(void *data)
261
+{
262
+	clk_disable_unprepare(data);
263
+}
264
+
301265 static const struct of_device_id jz4740_rtc_of_match[] = {
302266 	{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
267
+	{ .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
303268 	{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
304269 	{},
305270 };
306271 MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
307272 
273
+static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,
274
+					 struct device_node *np,
275
+					 unsigned long rate)
276
+{
277
+	unsigned long wakeup_ticks, reset_ticks;
278
+	unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */
279
+	unsigned int reset_pin_assert_time = 100; /* Default: 100ms */
280
+
281
+	of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",
282
+			     &reset_pin_assert_time);
283
+	of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",
284
+			     &min_wakeup_pin_assert_time);
285
+
286
+	/*
287
+	 * Set minimum wakeup pin assertion time: 100 ms.
288
+	 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
289
+	 */
290
+	wakeup_ticks = (min_wakeup_pin_assert_time * rate) / 1000;
291
+	if (wakeup_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
292
+		wakeup_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
293
+	else
294
+		wakeup_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
295
+	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);
296
+
297
+	/*
298
+	 * Set reset pin low-level assertion time after wakeup: 60 ms.
299
+	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
300
+	 */
301
+	reset_ticks = (reset_pin_assert_time * rate) / 1000;
302
+	if (reset_ticks < JZ_RTC_RESET_COUNTER_MASK)
303
+		reset_ticks &= JZ_RTC_RESET_COUNTER_MASK;
304
+	else
305
+		reset_ticks = JZ_RTC_RESET_COUNTER_MASK;
306
+	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);
307
+}
308
+
308309 static int jz4740_rtc_probe(struct platform_device *pdev)
309310 {
310
-	int ret;
311
+	struct device *dev = &pdev->dev;
312
+	struct device_node *np = dev->of_node;
311313 	struct jz4740_rtc *rtc;
312
-	uint32_t scratchpad;
313
-	struct resource *mem;
314
-	const struct platform_device_id *id = platform_get_device_id(pdev);
315
-	const struct of_device_id *of_id = of_match_device(
316
-			jz4740_rtc_of_match, &pdev->dev);
317
-	struct device_node *np = pdev->dev.of_node;
314
+	unsigned long rate;
315
+	struct clk *clk;
316
+	int ret, irq;
318317 
319
-	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
318
+	rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
320319 	if (!rtc)
321320 		return -ENOMEM;
322321 
323
-	if (of_id)
324
-		rtc->type = (enum jz4740_rtc_type)of_id->data;
325
-	else
326
-		rtc->type = id->driver_data;
322
+	rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev);
327323 
328
-	rtc->irq = platform_get_irq(pdev, 0);
329
-	if (rtc->irq < 0) {
330
-		dev_err(&pdev->dev, "Failed to get platform irq\n");
331
-		return -ENOENT;
332
-	}
324
+	irq = platform_get_irq(pdev, 0);
325
+	if (irq < 0)
326
+		return irq;
333327 
334
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
335
-	rtc->base = devm_ioremap_resource(&pdev->dev, mem);
328
+	rtc->base = devm_platform_ioremap_resource(pdev, 0);
336329 	if (IS_ERR(rtc->base))
337330 		return PTR_ERR(rtc->base);
338331 
339
-	rtc->clk = devm_clk_get(&pdev->dev, "rtc");
340
-	if (IS_ERR(rtc->clk)) {
341
-		dev_err(&pdev->dev, "Failed to get RTC clock\n");
342
-		return PTR_ERR(rtc->clk);
332
+	clk = devm_clk_get(dev, "rtc");
333
+	if (IS_ERR(clk)) {
334
+		dev_err(dev, "Failed to get RTC clock\n");
335
+		return PTR_ERR(clk);
336
+	}
337
+
338
+	ret = clk_prepare_enable(clk);
339
+	if (ret) {
340
+		dev_err(dev, "Failed to enable clock\n");
341
+		return ret;
342
+	}
343
+
344
+	ret = devm_add_action_or_reset(dev, jz4740_rtc_clk_disable, clk);
345
+	if (ret) {
346
+		dev_err(dev, "Failed to register devm action\n");
347
+		return ret;
343348 	}
344349 
345350 	spin_lock_init(&rtc->lock);
346351 
347352 	platform_set_drvdata(pdev, rtc);
348353 
349
-	device_init_wakeup(&pdev->dev, 1);
354
+	device_init_wakeup(dev, 1);
350355 
351
-	rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
352
-					&jz4740_rtc_ops, THIS_MODULE);
356
+	ret = dev_pm_set_wake_irq(dev, irq);
357
+	if (ret) {
358
+		dev_err(dev, "Failed to set wake irq: %d\n", ret);
359
+		return ret;
360
+	}
361
+
362
+	rtc->rtc = devm_rtc_allocate_device(dev);
353363 	if (IS_ERR(rtc->rtc)) {
354364 		ret = PTR_ERR(rtc->rtc);
355
-		dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
365
+		dev_err(dev, "Failed to allocate rtc device: %d\n", ret);
356366 		return ret;
357367 	}
358368 
359
-	ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
360
-				pdev->name, rtc);
369
+	rtc->rtc->ops = &jz4740_rtc_ops;
370
+	rtc->rtc->range_max = U32_MAX;
371
+
372
+	rate = clk_get_rate(clk);
373
+	jz4740_rtc_set_wakeup_params(rtc, np, rate);
374
+
375
+	/* Each 1 Hz pulse should happen after (rate) ticks */
376
+	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);
377
+
378
+	ret = rtc_register_device(rtc->rtc);
379
+	if (ret)
380
+		return ret;
381
+
382
+	ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,
383
+			       pdev->name, rtc);
361384 	if (ret) {
362
-		dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
385
+		dev_err(dev, "Failed to request rtc irq: %d\n", ret);
363386 		return ret;
364387 	}
365388 
366
-	scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
367
-	if (scratchpad != 0x12345678) {
368
-		ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
369
-		ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
370
-		if (ret) {
371
-			dev_err(&pdev->dev, "Could not write to RTC registers\n");
372
-			return ret;
373
-		}
374
-	}
389
+	if (of_device_is_system_power_controller(np)) {
390
+		dev_for_power_off = dev;
375391 
376
-	if (np && of_device_is_system_power_controller(np)) {
377
-		if (!pm_power_off) {
378
-			/* Default: 60ms */
379
-			rtc->reset_pin_assert_time = 60;
380
-			of_property_read_u32(np, "reset-pin-assert-time-ms",
381
-					     &rtc->reset_pin_assert_time);
382
-
383
-			/* Default: 100ms */
384
-			rtc->min_wakeup_pin_assert_time = 100;
385
-			of_property_read_u32(np,
386
-					     "min-wakeup-pin-assert-time-ms",
387
-					     &rtc->min_wakeup_pin_assert_time);
388
-
389
-			dev_for_power_off = &pdev->dev;
392
+		if (!pm_power_off)
390393 			pm_power_off = jz4740_rtc_power_off;
391
-		} else {
392
-			dev_warn(&pdev->dev,
393
-				 "Poweroff handler already present!\n");
394
-		}
394
+		else
395
+			dev_warn(dev, "Poweroff handler already present!\n");
395396 	}
396397 
397398 	return 0;
398399 }
399
-
400
-#ifdef CONFIG_PM
401
-static int jz4740_rtc_suspend(struct device *dev)
402
-{
403
-	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
404
-
405
-	if (device_may_wakeup(dev))
406
-		enable_irq_wake(rtc->irq);
407
-	return 0;
408
-}
409
-
410
-static int jz4740_rtc_resume(struct device *dev)
411
-{
412
-	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
413
-
414
-	if (device_may_wakeup(dev))
415
-		disable_irq_wake(rtc->irq);
416
-	return 0;
417
-}
418
-
419
-static const struct dev_pm_ops jz4740_pm_ops = {
420
-	.suspend = jz4740_rtc_suspend,
421
-	.resume  = jz4740_rtc_resume,
422
-};
423
-#define JZ4740_RTC_PM_OPS (&jz4740_pm_ops)
424
-
425
-#else
426
-#define JZ4740_RTC_PM_OPS NULL
427
-#endif  /* CONFIG_PM */
428
-
429
-static const struct platform_device_id jz4740_rtc_ids[] = {
430
-	{ "jz4740-rtc", ID_JZ4740 },
431
-	{ "jz4780-rtc", ID_JZ4780 },
432
-	{}
433
-};
434
-MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids);
435400 
436401 static struct platform_driver jz4740_rtc_driver = {
437402 	.probe	 = jz4740_rtc_probe,
438403 	.driver	 = {
439404 		.name  = "jz4740-rtc",
440
-		.pm    = JZ4740_RTC_PM_OPS,
441
-		.of_match_table = of_match_ptr(jz4740_rtc_of_match),
405
+		.of_match_table = jz4740_rtc_of_match,
442406 	},
443
-	.id_table = jz4740_rtc_ids,
444407 };
445408 
446409 module_platform_driver(jz4740_rtc_driver);