add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/rk_nand/rk_ftl_arm_v7.S
..
..
@@ -5,10 +5,9 @@
5
5
  * it under the terms of the GNU General Public License as published by
6
6
  * the Free Software Foundation; either version 2 of the License, or
7
7
  * (at your option) any later version.
8
- * date: 2020-09-23
8
+ * date: 2021-07-26
9
9
  */
10
10
 	.arch armv7-a
11
-	.fpu softvfp
12
11
 	.eabi_attribute 20, 1
13
12
 	.eabi_attribute 21, 1
14
13
 	.eabi_attribute 23, 3
..
..
@@ -17,139 +16,246 @@
17
16
 	.eabi_attribute 26, 2
18
17
 	.eabi_attribute 30, 4
19
18
 	.eabi_attribute 34, 1
20
-	.eabi_attribute 18, 4
21
-	.file	"rk_ftl_arm_v7.S"
22
-#APP
19
+	.file	"rk_ftl_arm_v7.c"
23
20
 	.syntax unified
24
21
 	.text
25
22
 	.align	2
23
+	.fpu softvfp
24
+	.type	ndelay, %function
25
+ndelay:
26
+	.fnstart
27
+	@ args = 0, pretend = 0, frame = 0
28
+	@ frame_needed = 0, uses_anonymous_args = 0
29
+	@ link register save eliminated.
30
+	ldr	r3, .L2
31
+	add	r0, r0, #996
32
+	add	r0, r0, #3
33
+	umull	r0, r1, r0, r3
34
+	ldr	r3, .L2+4
35
+	ldr	r3, [r3, #8]
36
+	lsr	r0, r1, #6
37
+	bx	r3	@ indirect register sibling call
38
+.L3:
39
+	.align	2
40
+.L2:
41
+	.word	274877907
42
+	.word	arm_delay_ops
43
+	.fnend
44
+	.size	ndelay, .-ndelay
45
+	.align	2
46
+	.syntax unified
47
+	.arm
48
+	.fpu softvfp
49
+	.type	flash_read_ecc, %function
50
+flash_read_ecc:
51
+	.fnstart
52
+	@ args = 0, pretend = 0, frame = 0
53
+	@ frame_needed = 0, uses_anonymous_args = 0
54
+	ldr	r3, .L6
55
+	push	{r4, lr}
56
+	.save {r4, lr}
57
+	ldr	r4, [r3, r0, lsl #3]
58
+	add	r3, r3, r0, lsl #3
59
+	mov	r0, #80
60
+	ldrb	r3, [r3, #4]	@ zero_extendqisi2
61
+	add	r4, r4, r3, lsl #8
62
+	mov	r3, #122
63
+	str	r3, [r4, #2056]
64
+	bl	ndelay
65
+	ldr	r3, [r4, #2048]
66
+	ldr	r0, [r4, #2048]
67
+	and	r3, r3, #15
68
+	and	r0, r0, #15
69
+	cmp	r0, r3
70
+	movcc	r0, r3
71
+	ldr	r3, [r4, #2048]
72
+	and	r3, r3, #15
73
+	cmp	r3, r0
74
+	movcc	r3, r0
75
+	ldr	r0, [r4, #2048]
76
+	and	r0, r0, #15
77
+	cmp	r0, r3
78
+	movcc	r0, r3
79
+	pop	{r4, pc}
80
+.L7:
81
+	.align	2
82
+.L6:
83
+	.word	.LANCHOR0
84
+	.fnend
85
+	.size	flash_read_ecc, .-flash_read_ecc
86
+	.align	2
87
+	.syntax unified
88
+	.arm
89
+	.fpu softvfp
90
+	.type	ftl_set_blk_mode.part.9, %function
91
+ftl_set_blk_mode.part.9:
92
+	.fnstart
93
+	@ args = 0, pretend = 0, frame = 0
94
+	@ frame_needed = 0, uses_anonymous_args = 0
95
+	@ link register save eliminated.
96
+	ldr	r3, .L9
97
+	lsr	r1, r0, #5
98
+	mov	ip, #1
99
+	and	r0, r0, #31
100
+	ldr	r2, [r3, #32]
101
+	ldr	r3, [r2, r1, lsl #2]
102
+	orr	r0, r3, ip, lsl r0
103
+	str	r0, [r2, r1, lsl #2]
104
+	bx	lr
105
+.L10:
106
+	.align	2
107
+.L9:
108
+	.word	.LANCHOR0
109
+	.fnend
110
+	.size	ftl_set_blk_mode.part.9, .-ftl_set_blk_mode.part.9
111
+	.align	2
26
112
 	.global	FlashMemCmp8
113
+	.syntax unified
114
+	.arm
115
+	.fpu softvfp
27
116
 	.type	FlashMemCmp8, %function
28
117
 FlashMemCmp8:
29
118
 	.fnstart
30
119
 	@ args = 0, pretend = 0, frame = 0
31
120
 	@ frame_needed = 0, uses_anonymous_args = 0
32
-	ldr	r3, .L11
33
-	str	lr, [sp, #-4]!
34
-	.save {lr}
35
-	ldrb	r3, [r3]	@ zero_extendqisi2
121
+	ldr	r3, .L25
122
+	ldrb	r3, [r3, #36]	@ zero_extendqisi2
36
123
 	cmp	r3, #0
37
-	beq	.L4
124
+	beq	.L20
38
125
 	ldrb	r3, [r1, #1]	@ zero_extendqisi2
39
126
 	ldrb	ip, [r0, #1]	@ zero_extendqisi2
40
127
 	cmp	ip, r3
41
128
 	movne	r3, #0
42
-	beq	.L8
43
-.L4:
129
+	bne	.L20
130
+.L24:
131
+	mov	r0, #0
132
+	bx	lr
133
+.L14:
44
134
 	cmp	r3, r2
45
-	beq	.L8
135
+	bne	.L16
136
+	mov	r0, #0
137
+	ldr	pc, [sp], #4
138
+.L20:
139
+	cmp	r3, r2
140
+	beq	.L24
141
+	str	lr, [sp, #-4]!
142
+	.save {lr}
143
+.L16:
46
144
 	ldrb	lr, [r0, r3]	@ zero_extendqisi2
47
145
 	ldrb	ip, [r1, r3]	@ zero_extendqisi2
48
146
 	add	r3, r3, #1
49
147
 	cmp	lr, ip
50
-	beq	.L4
148
+	beq	.L14
51
149
 	mov	r0, r3
52
150
 	ldr	pc, [sp], #4
53
-.L8:
54
-	mov	r0, #0
55
-	ldr	pc, [sp], #4
56
-.L12:
151
+.L26:
57
152
 	.align	2
58
-.L11:
153
+.L25:
59
154
 	.word	.LANCHOR0
60
155
 	.fnend
61
156
 	.size	FlashMemCmp8, .-FlashMemCmp8
62
157
 	.align	2
63
158
 	.global	FlashRsvdBlkChk
159
+	.syntax unified
160
+	.arm
161
+	.fpu softvfp
64
162
 	.type	FlashRsvdBlkChk, %function
65
163
 FlashRsvdBlkChk:
66
164
 	.fnstart
67
165
 	@ args = 0, pretend = 0, frame = 0
68
166
 	@ frame_needed = 0, uses_anonymous_args = 0
69
167
 	@ link register save eliminated.
70
-	ldr	r3, .L14
71
-	ldrb	r2, [r3, #1]	@ zero_extendqisi2
72
-	ldr	r3, [r3, #4]
73
-	mul	r3, r3, r2
74
-	cmp	r1, r3
75
-	movcs	r2, #0
76
-	movcc	r2, #1
168
+	ldr	r2, .L28
169
+	ldrb	ip, [r2, #37]	@ zero_extendqisi2
170
+	ldr	r3, [r2, #40]
171
+	mul	r3, r3, ip
172
+	cmp	r3, r1
173
+	movls	r2, #0
174
+	movhi	r2, #1
77
175
 	cmp	r0, #0
78
176
 	movne	r2, #0
79
177
 	eor	r0, r2, #1
80
178
 	bx	lr
81
-.L15:
179
+.L29:
82
180
 	.align	2
83
-.L14:
181
+.L28:
84
182
 	.word	.LANCHOR0
85
183
 	.fnend
86
184
 	.size	FlashRsvdBlkChk, .-FlashRsvdBlkChk
87
185
 	.align	2
88
186
 	.global	FlashGetRandomizer
187
+	.syntax unified
188
+	.arm
189
+	.fpu softvfp
89
190
 	.type	FlashGetRandomizer, %function
90
191
 FlashGetRandomizer:
91
192
 	.fnstart
92
193
 	@ args = 0, pretend = 0, frame = 0
93
194
 	@ frame_needed = 0, uses_anonymous_args = 0
94
195
 	and	r3, r1, #127
95
-	ldr	r2, .L25
96
-	stmfd	sp!, {r4, lr}
196
+	ldr	r2, .L39
197
+	lsl	r3, r3, #1
198
+	push	{r4, lr}
97
199
 	.save {r4, lr}
98
-	mov	r3, r3, asl #1
99
200
 	ldrh	r4, [r2, r3]
100
-	ldr	r3, .L25+4
101
-	ldrb	r3, [r3, #8]	@ zero_extendqisi2
201
+	ldr	r3, .L39+4
202
+	ldrb	r3, [r3, #44]	@ zero_extendqisi2
102
203
 	cmp	r3, #0
103
-	beq	.L17
204
+	beq	.L30
104
205
 	bl	FlashRsvdBlkChk
105
206
 	cmp	r0, #0
106
207
 	orrne	r4, r4, #-1073741824
107
-.L17:
208
+.L30:
108
209
 	mov	r0, r4
109
-	ldmfd	sp!, {r4, pc}
110
-.L26:
210
+	pop	{r4, pc}
211
+.L40:
111
212
 	.align	2
112
-.L25:
213
+.L39:
113
214
 	.word	.LANCHOR1
114
215
 	.word	.LANCHOR0
115
216
 	.fnend
116
217
 	.size	FlashGetRandomizer, .-FlashGetRandomizer
117
218
 	.align	2
118
219
 	.global	FlashSetRandomizer
220
+	.syntax unified
221
+	.arm
222
+	.fpu softvfp
119
223
 	.type	FlashSetRandomizer, %function
120
224
 FlashSetRandomizer:
121
225
 	.fnstart
122
226
 	@ args = 0, pretend = 0, frame = 0
123
227
 	@ frame_needed = 0, uses_anonymous_args = 0
228
+	ldr	r2, .L50
124
229
 	and	r3, r1, #127
125
-	ldr	r2, .L36
126
-	stmfd	sp!, {r4, r5, r6, lr}
230
+	lsl	r3, r3, #1
231
+	push	{r4, r5, r6, lr}
127
232
 	.save {r4, r5, r6, lr}
128
-	mov	r3, r3, asl #1
129
233
 	mov	r6, r0
130
234
 	ldrh	r5, [r2, r3]
131
-	ldr	r3, .L36+4
132
-	ldrb	r2, [r3, #8]	@ zero_extendqisi2
235
+	ldr	r3, .L50+4
236
+	ldrb	r2, [r3, #44]	@ zero_extendqisi2
133
237
 	mov	r4, r3
134
238
 	cmp	r2, #0
135
-	beq	.L28
239
+	beq	.L42
136
240
 	bl	FlashRsvdBlkChk
137
241
 	cmp	r0, #0
138
242
 	orrne	r5, r5, #-1073741824
139
-.L28:
140
-	add	r4, r4, r6, asl #3
141
-	ldr	r3, [r4, #12]
243
+.L42:
244
+	ldr	r3, [r4, r6, lsl #3]
142
245
 	str	r5, [r3, #336]
143
-	ldmfd	sp!, {r4, r5, r6, pc}
144
-.L37:
246
+	pop	{r4, r5, r6, pc}
247
+.L51:
145
248
 	.align	2
146
-.L36:
249
+.L50:
147
250
 	.word	.LANCHOR1
148
251
 	.word	.LANCHOR0
149
252
 	.fnend
150
253
 	.size	FlashSetRandomizer, .-FlashSetRandomizer
151
254
 	.align	2
152
255
 	.global	FlashBlockAlignInit
256
+	.syntax unified
257
+	.arm
258
+	.fpu softvfp
153
259
 	.type	FlashBlockAlignInit, %function
154
260
 FlashBlockAlignInit:
155
261
 	.fnstart
..
..
@@ -157,45 +263,49 @@
157
263
 	@ frame_needed = 0, uses_anonymous_args = 0
158
264
 	@ link register save eliminated.
159
265
 	cmp	r0, #512
160
-	ldr	r3, .L44
266
+	ldr	r3, .L58
161
267
 	movhi	r2, #1024
162
-	bhi	.L43
268
+	bhi	.L57
163
269
 	cmp	r0, #256
164
270
 	movhi	r2, #512
165
-	bhi	.L43
271
+	bhi	.L57
166
272
 	cmp	r0, #128
167
-	strls	r0, [r3, #4]
168
-	bxls	lr
169
-	mov	r2, #256
170
-.L43:
171
-	str	r2, [r3, #4]
273
+	movhi	r2, #256
274
+	bhi	.L57
275
+	str	r0, [r3, #40]
172
276
 	bx	lr
173
-.L45:
277
+.L57:
278
+	str	r2, [r3, #40]
279
+	bx	lr
280
+.L59:
174
281
 	.align	2
175
-.L44:
282
+.L58:
176
283
 	.word	.LANCHOR0
177
284
 	.fnend
178
285
 	.size	FlashBlockAlignInit, .-FlashBlockAlignInit
179
286
 	.align	2
180
287
 	.global	FlashReadCmd
288
+	.syntax unified
289
+	.arm
290
+	.fpu softvfp
181
291
 	.type	FlashReadCmd, %function
182
292
 FlashReadCmd:
183
293
 	.fnstart
184
294
 	@ args = 0, pretend = 0, frame = 0
185
295
 	@ frame_needed = 0, uses_anonymous_args = 0
186
-	ldr	ip, .L49
296
+	ldr	ip, .L63
187
297
 	str	lr, [sp, #-4]!
188
298
 	.save {lr}
189
-	add	r3, ip, r0, asl #3
190
-	ldr	ip, [ip, #44]
191
-	ldr	r2, [r3, #12]
192
-	ldrb	r3, [r3, #16]	@ zero_extendqisi2
299
+	add	r2, ip, r0, lsl #3
300
+	ldr	r3, [ip, r0, lsl #3]
301
+	ldr	ip, [ip, #48]
302
+	ldrb	r2, [r2, #4]	@ zero_extendqisi2
193
303
 	ldrb	ip, [ip, #7]	@ zero_extendqisi2
194
-	mov	r3, r3, asl #8
304
+	lsl	r2, r2, #8
195
305
 	cmp	ip, #1
196
-	addeq	ip, r2, r3
197
-	add	r3, r2, r3
306
+	addeq	ip, r3, r2
198
307
 	moveq	lr, #38
308
+	add	r3, r3, r2
199
309
 	mov	r2, #0
200
310
 	streq	lr, [ip, #2056]
201
311
 	str	r2, [r3, #2056]
..
..
@@ -203,41 +313,44 @@
203
313
 	str	r2, [r3, #2052]
204
314
 	uxtb	r2, r1
205
315
 	str	r2, [r3, #2052]
206
-	mov	r2, r1, lsr #8
316
+	lsr	r2, r1, #8
207
317
 	str	r2, [r3, #2052]
208
-	mov	r2, r1, lsr #16
318
+	lsr	r2, r1, #16
209
319
 	str	r2, [r3, #2052]
210
320
 	mov	r2, #48
211
321
 	str	r2, [r3, #2056]
212
322
 	ldr	lr, [sp], #4
213
323
 	b	FlashSetRandomizer
214
-.L50:
324
+.L64:
215
325
 	.align	2
216
-.L49:
326
+.L63:
217
327
 	.word	.LANCHOR0
218
328
 	.fnend
219
329
 	.size	FlashReadCmd, .-FlashReadCmd
220
330
 	.align	2
221
331
 	.global	FlashReadDpDataOutCmd
332
+	.syntax unified
333
+	.arm
334
+	.fpu softvfp
222
335
 	.type	FlashReadDpDataOutCmd, %function
223
336
 FlashReadDpDataOutCmd:
224
337
 	.fnstart
225
338
 	@ args = 0, pretend = 0, frame = 0
226
339
 	@ frame_needed = 0, uses_anonymous_args = 0
227
-	ldr	ip, .L56
228
-	stmfd	sp!, {r4, lr}
340
+	ldr	ip, .L70
341
+	push	{r4, lr}
229
342
 	.save {r4, lr}
230
-	add	r3, ip, r0, asl #3
231
-	ldrb	ip, [ip, #64]	@ zero_extendqisi2
232
343
 	uxtb	r4, r1
233
-	ldr	r2, [r3, #12]
234
-	mov	lr, r1, lsr #8
235
-	ldrb	r3, [r3, #16]	@ zero_extendqisi2
344
+	lsr	lr, r1, #8
345
+	add	r2, ip, r0, lsl #3
346
+	ldr	r3, [ip, r0, lsl #3]
347
+	ldrb	ip, [ip, #68]	@ zero_extendqisi2
348
+	ldrb	r2, [r2, #4]	@ zero_extendqisi2
236
349
 	cmp	ip, #1
237
-	mov	ip, r1, lsr #16
238
-	mov	r3, r3, asl #8
239
-	add	r3, r2, r3
240
-	bne	.L52
350
+	lsr	ip, r1, #16
351
+	lsl	r2, r2, #8
352
+	add	r3, r3, r2
353
+	bne	.L66
241
354
 	mov	r2, #6
242
355
 	str	r2, [r3, #2056]
243
356
 	mov	r2, #0
..
..
@@ -246,8 +359,12 @@
246
359
 	str	r4, [r3, #2052]
247
360
 	str	lr, [r3, #2052]
248
361
 	str	ip, [r3, #2052]
249
-	b	.L55
250
-.L52:
362
+.L69:
363
+	mov	r2, #224
364
+	str	r2, [r3, #2056]
365
+	pop	{r4, lr}
366
+	b	FlashSetRandomizer
367
+.L66:
251
368
 	mov	r2, #0
252
369
 	str	r2, [r3, #2056]
253
370
 	str	r2, [r3, #2052]
..
..
@@ -259,31 +376,31 @@
259
376
 	str	ip, [r3, #2056]
260
377
 	str	r2, [r3, #2052]
261
378
 	str	r2, [r3, #2052]
262
-.L55:
263
-	mov	r2, #224
264
-	str	r2, [r3, #2056]
265
-	ldmfd	sp!, {r4, lr}
266
-	b	FlashSetRandomizer
267
-.L57:
379
+	b	.L69
380
+.L71:
268
381
 	.align	2
269
-.L56:
382
+.L70:
270
383
 	.word	.LANCHOR0
271
384
 	.fnend
272
385
 	.size	FlashReadDpDataOutCmd, .-FlashReadDpDataOutCmd
273
386
 	.align	2
274
387
 	.global	FlashProgFirstCmd
388
+	.syntax unified
389
+	.arm
390
+	.fpu softvfp
275
391
 	.type	FlashProgFirstCmd, %function
276
392
 FlashProgFirstCmd:
277
393
 	.fnstart
278
394
 	@ args = 0, pretend = 0, frame = 0
279
395
 	@ frame_needed = 0, uses_anonymous_args = 0
280
-	@ link register save eliminated.
281
-	ldr	ip, .L59
282
-	mov	r2, r1, lsr #16
283
-	add	ip, ip, r0, asl #3
284
-	ldr	r3, [ip, #12]
285
-	ldrb	ip, [ip, #16]	@ zero_extendqisi2
286
-	add	r3, r3, ip, asl #8
396
+	ldr	ip, .L74
397
+	lsr	r2, r1, #16
398
+	str	lr, [sp, #-4]!
399
+	.save {lr}
400
+	ldr	r3, [ip, r0, lsl #3]
401
+	add	ip, ip, r0, lsl #3
402
+	ldrb	ip, [ip, #4]	@ zero_extendqisi2
403
+	add	r3, r3, ip, lsl #8
287
404
 	mov	ip, #128
288
405
 	str	ip, [r3, #2056]
289
406
 	mov	ip, #0
..
..
@@ -291,176 +408,225 @@
291
408
 	str	ip, [r3, #2052]
292
409
 	uxtb	ip, r1
293
410
 	str	ip, [r3, #2052]
294
-	mov	ip, r1, lsr #8
411
+	lsr	ip, r1, #8
295
412
 	str	ip, [r3, #2052]
296
413
 	str	r2, [r3, #2052]
414
+	ldr	lr, [sp], #4
297
415
 	b	FlashSetRandomizer
298
-.L60:
416
+.L75:
299
417
 	.align	2
300
-.L59:
418
+.L74:
301
419
 	.word	.LANCHOR0
302
420
 	.fnend
303
421
 	.size	FlashProgFirstCmd, .-FlashProgFirstCmd
304
422
 	.align	2
305
423
 	.global	FlashEraseCmd
424
+	.syntax unified
425
+	.arm
426
+	.fpu softvfp
306
427
 	.type	FlashEraseCmd, %function
307
428
 FlashEraseCmd:
308
429
 	.fnstart
309
430
 	@ args = 0, pretend = 0, frame = 0
310
431
 	@ frame_needed = 0, uses_anonymous_args = 0
432
+	ldr	ip, .L82
433
+	cmp	r2, #0
311
434
 	str	lr, [sp, #-4]!
312
435
 	.save {lr}
313
-	cmp	r2, #0
314
-	ldr	lr, .L67
315
-	add	r0, lr, r0, asl #3
316
-	ldrb	r3, [r0, #16]	@ zero_extendqisi2
317
-	ldr	ip, [r0, #12]
318
-	mov	r3, r3, asl #8
319
-	beq	.L62
320
-	add	r2, ip, r3
321
-	mov	r0, #96
322
-	str	r0, [r2, #2056]
323
-	uxtb	r0, r1
324
-	str	r0, [r2, #2052]
325
-	mov	r0, r1, lsr #8
326
-	str	r0, [r2, #2052]
327
-	mov	r0, r1, lsr #16
328
-	str	r0, [r2, #2052]
329
-	ldr	r2, [lr, #4]
436
+	ldr	r3, [ip, r0, lsl #3]
437
+	add	r0, ip, r0, lsl #3
438
+	ldrb	r0, [r0, #4]	@ zero_extendqisi2
439
+	lsl	r0, r0, #8
440
+	beq	.L77
441
+	add	r2, r3, r0
442
+	mov	lr, #96
443
+	str	lr, [r2, #2056]
444
+	uxtb	lr, r1
445
+	str	lr, [r2, #2052]
446
+	lsr	lr, r1, #8
447
+	str	lr, [r2, #2052]
448
+	lsr	lr, r1, #16
449
+	str	lr, [r2, #2052]
450
+	ldr	r2, [ip, #40]
330
451
 	add	r1, r1, r2
331
-.L62:
332
-	add	r3, ip, r3
452
+.L77:
453
+	add	r3, r3, r0
333
454
 	mov	r2, #96
334
455
 	str	r2, [r3, #2056]
335
456
 	uxtb	r2, r1
336
457
 	str	r2, [r3, #2052]
337
-	mov	r2, r1, lsr #8
338
-	mov	r1, r1, lsr #16
458
+	lsr	r2, r1, #8
459
+	lsr	r1, r1, #16
339
460
 	str	r2, [r3, #2052]
340
-	str	r1, [r3, #2052]
341
461
 	mov	r2, #208
462
+	str	r1, [r3, #2052]
342
463
 	str	r2, [r3, #2056]
343
464
 	ldr	pc, [sp], #4
344
-.L68:
465
+.L83:
345
466
 	.align	2
346
-.L67:
467
+.L82:
347
468
 	.word	.LANCHOR0
348
469
 	.fnend
349
470
 	.size	FlashEraseCmd, .-FlashEraseCmd
350
471
 	.align	2
351
472
 	.global	FlashProgDpSecondCmd
473
+	.syntax unified
474
+	.arm
475
+	.fpu softvfp
352
476
 	.type	FlashProgDpSecondCmd, %function
353
477
 FlashProgDpSecondCmd:
354
478
 	.fnstart
355
479
 	@ args = 0, pretend = 0, frame = 0
356
480
 	@ frame_needed = 0, uses_anonymous_args = 0
357
-	ldr	ip, .L71
358
-	mov	r2, r1, lsr #16
359
-	str	lr, [sp, #-4]!
360
-	.save {lr}
361
-	add	lr, ip, r0, asl #3
362
-	ldrb	ip, [ip, #59]	@ zero_extendqisi2
363
-	ldr	r3, [lr, #12]
364
-	ldrb	lr, [lr, #16]	@ zero_extendqisi2
365
-	add	r3, r3, lr, asl #8
481
+	push	{r4, lr}
482
+	.save {r4, lr}
483
+	lsr	r2, r1, #16
484
+	ldr	lr, .L86
485
+	ldr	r3, [lr, r0, lsl #3]
486
+	add	ip, lr, r0, lsl #3
487
+	ldrb	r4, [ip, #4]	@ zero_extendqisi2
488
+	ldrb	ip, [lr, #63]	@ zero_extendqisi2
489
+	add	r3, r3, r4, lsl #8
366
490
 	str	ip, [r3, #2056]
367
491
 	mov	ip, #0
368
492
 	str	ip, [r3, #2052]
369
493
 	str	ip, [r3, #2052]
370
494
 	uxtb	ip, r1
371
495
 	str	ip, [r3, #2052]
372
-	mov	ip, r1, lsr #8
496
+	lsr	ip, r1, #8
373
497
 	str	ip, [r3, #2052]
374
498
 	str	r2, [r3, #2052]
375
-	ldr	lr, [sp], #4
499
+	pop	{r4, lr}
376
500
 	b	FlashSetRandomizer
377
-.L72:
501
+.L87:
378
502
 	.align	2
379
-.L71:
503
+.L86:
380
504
 	.word	.LANCHOR0
381
505
 	.fnend
382
506
 	.size	FlashProgDpSecondCmd, .-FlashProgDpSecondCmd
383
507
 	.align	2
384
508
 	.global	FlashProgSecondCmd
509
+	.syntax unified
510
+	.arm
511
+	.fpu softvfp
385
512
 	.type	FlashProgSecondCmd, %function
386
513
 FlashProgSecondCmd:
387
514
 	.fnstart
388
515
 	@ args = 0, pretend = 0, frame = 0
389
516
 	@ frame_needed = 0, uses_anonymous_args = 0
390
-	stmfd	sp!, {r3, r4, r5, lr}
391
-	.save {r3, r4, r5, lr}
392
-	ldr	r3, .L75
393
-	add	r0, r3, r0, asl #3
394
-	ldr	r3, .L75+4
395
-	ldrb	r5, [r0, #16]	@ zero_extendqisi2
396
-	ldr	r4, [r0, #12]
517
+	ldr	r3, .L90
518
+	push	{r4, r5, r6, lr}
519
+	.save {r4, r5, r6, lr}
520
+	ldr	r4, [r3, r0, lsl #3]
521
+	add	r3, r3, r0, lsl #3
522
+	ldr	r0, .L90+4
523
+	ldrb	r5, [r3, #4]	@ zero_extendqisi2
524
+	ldr	r3, .L90+8
525
+	add	r4, r4, r5, lsl #8
397
526
 	ldr	r3, [r3, #4]
398
-	add	r4, r4, r5, asl #8
399
-	ldr	r0, .L75+8
400
527
 	blx	r3
401
528
 	mov	r3, #16
402
529
 	str	r3, [r4, #2056]
403
-	ldmfd	sp!, {r3, r4, r5, pc}
404
-.L76:
530
+	pop	{r4, r5, r6, pc}
531
+.L91:
405
532
 	.align	2
406
-.L75:
533
+.L90:
407
534
 	.word	.LANCHOR0
535
+	.word	64424500
408
536
 	.word	arm_delay_ops
409
-	.word	214748300
410
537
 	.fnend
411
538
 	.size	FlashProgSecondCmd, .-FlashProgSecondCmd
412
539
 	.align	2
413
540
 	.global	FlashProgDpFirstCmd
541
+	.syntax unified
542
+	.arm
543
+	.fpu softvfp
414
544
 	.type	FlashProgDpFirstCmd, %function
415
545
 FlashProgDpFirstCmd:
416
546
 	.fnstart
417
547
 	@ args = 0, pretend = 0, frame = 0
418
548
 	@ frame_needed = 0, uses_anonymous_args = 0
419
549
 	@ link register save eliminated.
420
-	ldr	r2, .L78
421
-	add	r0, r2, r0, asl #3
422
-	ldrb	r2, [r2, #58]	@ zero_extendqisi2
423
-	ldrb	r1, [r0, #16]	@ zero_extendqisi2
424
-	ldr	r3, [r0, #12]
425
-	add	r3, r3, r1, asl #8
550
+	ldr	r2, .L93
551
+	ldr	r3, [r2, r0, lsl #3]
552
+	add	r0, r2, r0, lsl #3
553
+	ldrb	r2, [r2, #62]	@ zero_extendqisi2
554
+	ldrb	r1, [r0, #4]	@ zero_extendqisi2
555
+	add	r3, r3, r1, lsl #8
426
556
 	str	r2, [r3, #2056]
427
557
 	bx	lr
428
-.L79:
558
+.L94:
429
559
 	.align	2
430
-.L78:
560
+.L93:
431
561
 	.word	.LANCHOR0
432
562
 	.fnend
433
563
 	.size	FlashProgDpFirstCmd, .-FlashProgDpFirstCmd
434
564
 	.align	2
565
+	.global	FlashReadStatus
566
+	.syntax unified
567
+	.arm
568
+	.fpu softvfp
569
+	.type	FlashReadStatus, %function
570
+FlashReadStatus:
571
+	.fnstart
572
+	@ args = 0, pretend = 0, frame = 0
573
+	@ frame_needed = 0, uses_anonymous_args = 0
574
+	ldr	r3, .L97
575
+	mov	r2, #112
576
+	push	{r4, r5, r6, lr}
577
+	.save {r4, r5, r6, lr}
578
+	ldr	r5, [r3, r0, lsl #3]
579
+	add	r3, r3, r0, lsl #3
580
+	mov	r0, #80
581
+	ldrb	r4, [r3, #4]	@ zero_extendqisi2
582
+	add	r3, r5, r4, lsl #8
583
+	add	r4, r4, #8
584
+	str	r2, [r3, #2056]
585
+	bl	ndelay
586
+	ldr	r0, [r5, r4, lsl #8]
587
+	pop	{r4, r5, r6, pc}
588
+.L98:
589
+	.align	2
590
+.L97:
591
+	.word	.LANCHOR0
592
+	.fnend
593
+	.size	FlashReadStatus, .-FlashReadStatus
594
+	.align	2
435
595
 	.global	js_hash
596
+	.syntax unified
597
+	.arm
598
+	.fpu softvfp
436
599
 	.type	js_hash, %function
437
600
 js_hash:
438
601
 	.fnstart
439
602
 	@ args = 0, pretend = 0, frame = 0
440
603
 	@ frame_needed = 0, uses_anonymous_args = 0
441
604
 	@ link register save eliminated.
442
-	ldr	r3, .L84
605
+	ldr	r3, .L102
443
606
 	add	r1, r0, r1
444
-.L81:
607
+.L100:
445
608
 	cmp	r0, r1
446
-	beq	.L83
447
-	mov	r2, r3, asl #5
448
-	ldrb	ip, [r0], #1	@ zero_extendqisi2
449
-	add	r2, r2, r3, lsr #2
450
-	add	r2, r2, ip
451
-	eor	r3, r3, r2
452
-	b	.L81
453
-.L83:
609
+	bne	.L101
454
610
 	mov	r0, r3
455
611
 	bx	lr
456
-.L85:
612
+.L101:
613
+	lsr	r2, r3, #2
614
+	ldrb	ip, [r0], #1	@ zero_extendqisi2
615
+	add	r2, r2, r3, lsl #5
616
+	add	r2, r2, ip
617
+	eor	r3, r3, r2
618
+	b	.L100
619
+.L103:
457
620
 	.align	2
458
-.L84:
621
+.L102:
459
622
 	.word	1204201446
460
623
 	.fnend
461
624
 	.size	js_hash, .-js_hash
462
625
 	.align	2
463
626
 	.global	FlashLoadIdbInfo
627
+	.syntax unified
628
+	.arm
629
+	.fpu softvfp
464
630
 	.type	FlashLoadIdbInfo, %function
465
631
 FlashLoadIdbInfo:
466
632
 	.fnstart
..
..
@@ -473,6 +639,9 @@
473
639
 	.size	FlashLoadIdbInfo, .-FlashLoadIdbInfo
474
640
 	.align	2
475
641
 	.global	FlashPrintInfo
642
+	.syntax unified
643
+	.arm
644
+	.fpu softvfp
476
645
 	.type	FlashPrintInfo, %function
477
646
 FlashPrintInfo:
478
647
 	.fnstart
..
..
@@ -483,148 +652,350 @@
483
652
 	.fnend
484
653
 	.size	FlashPrintInfo, .-FlashPrintInfo
485
654
 	.align	2
655
+	.global	ToshibaSetRRPara
656
+	.syntax unified
657
+	.arm
658
+	.fpu softvfp
659
+	.type	ToshibaSetRRPara, %function
660
+ToshibaSetRRPara:
661
+	.fnstart
662
+	@ args = 0, pretend = 0, frame = 0
663
+	@ frame_needed = 0, uses_anonymous_args = 0
664
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
665
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
666
+	add	r9, r1, r1, lsl #2
667
+	ldr	r7, .L114
668
+	mov	r6, r0
669
+	mov	r5, #0
670
+	add	r7, r1, r7
671
+.L107:
672
+	ldr	r8, .L114+4
673
+	ldrb	r3, [r8, #85]	@ zero_extendqisi2
674
+	cmp	r5, r3
675
+	bcc	.L111
676
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
677
+.L111:
678
+	ldr	r4, .L114+8
679
+	mov	r3, #85
680
+	str	r3, [r6, #8]
681
+	mov	r0, #200
682
+	ldrsb	r3, [r5, r4]
683
+	str	r3, [r6, #4]
684
+	bl	ndelay
685
+	ldrb	r3, [r8, #84]	@ zero_extendqisi2
686
+	cmp	r3, #34
687
+	addeq	r3, r5, r9
688
+	addeq	r4, r4, r3
689
+	ldrsbeq	r3, [r4, #5]
690
+	beq	.L113
691
+	cmp	r3, #35
692
+	addeq	r3, r5, r9
693
+	ldrsbne	r3, [r7]
694
+	addeq	r4, r4, r3
695
+	ldrsbeq	r3, [r4, #50]
696
+.L113:
697
+	str	r3, [r6]
698
+	add	r5, r5, #1
699
+	b	.L107
700
+.L115:
701
+	.align	2
702
+.L114:
703
+	.word	.LANCHOR1+396
704
+	.word	.LANCHOR0
705
+	.word	.LANCHOR1+256
706
+	.fnend
707
+	.size	ToshibaSetRRPara, .-ToshibaSetRRPara
708
+	.align	2
709
+	.global	SamsungSetRRPara
710
+	.syntax unified
711
+	.arm
712
+	.fpu softvfp
713
+	.type	SamsungSetRRPara, %function
714
+SamsungSetRRPara:
715
+	.fnstart
716
+	@ args = 0, pretend = 0, frame = 0
717
+	@ frame_needed = 0, uses_anonymous_args = 0
718
+	ldr	r3, .L120
719
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
720
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
721
+	mov	r4, #0
722
+	ldr	r8, .L120+4
723
+	mov	r6, r0
724
+	mov	r7, r3
725
+	mov	r9, #161
726
+	add	r1, r3, r1, lsl #2
727
+	mov	r10, r4
728
+	add	r5, r1, #3
729
+.L117:
730
+	ldrb	r3, [r8, #85]	@ zero_extendqisi2
731
+	cmp	r4, r3
732
+	bcc	.L118
733
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
734
+.L118:
735
+	str	r9, [r6, #8]
736
+	mov	r0, #300
737
+	str	r10, [r6]
738
+	ldrsb	r3, [r7, r4]
739
+	add	r4, r4, #1
740
+	str	r3, [r6]
741
+	ldrsb	r3, [r5, #1]!
742
+	str	r3, [r6]
743
+	bl	ndelay
744
+	b	.L117
745
+.L121:
746
+	.align	2
747
+.L120:
748
+	.word	.LANCHOR1+404
749
+	.word	.LANCHOR0
750
+	.fnend
751
+	.size	SamsungSetRRPara, .-SamsungSetRRPara
752
+	.align	2
486
753
 	.global	ftl_flash_suspend
754
+	.syntax unified
755
+	.arm
756
+	.fpu softvfp
487
757
 	.type	ftl_flash_suspend, %function
488
758
 ftl_flash_suspend:
489
759
 	.fnstart
490
760
 	@ args = 0, pretend = 0, frame = 0
491
761
 	@ frame_needed = 0, uses_anonymous_args = 0
492
762
 	@ link register save eliminated.
493
-	ldr	r3, .L89
494
-	ldr	r2, [r3, #80]
763
+	ldr	r3, .L123
764
+	ldr	r2, [r3, #88]
495
765
 	ldr	r1, [r2]
496
-	str	r1, [r3, #84]
497
-	ldr	r1, [r2, #4]
498
-	str	r1, [r3, #88]
499
-	ldr	r1, [r2, #8]
500
766
 	str	r1, [r3, #92]
501
-	ldr	r1, [r2, #12]
767
+	ldr	r1, [r2, #4]
502
768
 	str	r1, [r3, #96]
503
-	ldr	r1, [r2, #304]
769
+	ldr	r1, [r2, #8]
504
770
 	str	r1, [r3, #100]
505
-	ldr	r1, [r2, #308]
771
+	ldr	r1, [r2, #12]
506
772
 	str	r1, [r3, #104]
773
+	ldr	r1, [r2, #304]
774
+	str	r1, [r3, #108]
775
+	ldr	r1, [r2, #308]
776
+	str	r1, [r3, #112]
507
777
 	ldr	r1, [r2, #336]
508
778
 	ldr	r2, [r2, #344]
509
-	str	r1, [r3, #108]
510
-	str	r2, [r3, #112]
779
+	str	r1, [r3, #116]
780
+	str	r2, [r3, #120]
511
781
 	bx	lr
512
-.L90:
782
+.L124:
513
783
 	.align	2
514
-.L89:
784
+.L123:
515
785
 	.word	.LANCHOR0
516
786
 	.fnend
517
787
 	.size	ftl_flash_suspend, .-ftl_flash_suspend
518
788
 	.global	__aeabi_uidiv
789
+	.global	__aeabi_uidivmod
519
790
 	.align	2
520
791
 	.global	LogAddr2PhyAddr
792
+	.syntax unified
793
+	.arm
794
+	.fpu softvfp
521
795
 	.type	LogAddr2PhyAddr, %function
522
796
 LogAddr2PhyAddr:
523
797
 	.fnstart
524
798
 	@ args = 4, pretend = 0, frame = 8
525
799
 	@ frame_needed = 0, uses_anonymous_args = 0
526
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
800
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
527
801
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
528
802
 	.pad #12
529
-	mov	r5, r0
530
-	ldr	r0, .L97
531
-	mov	r8, r3
532
-	ldr	ip, [r5, #4]
533
-	mov	r9, r1
534
-	mov	r7, r2
535
-	ldrh	r3, [r0, #130]
536
-	bic	ip, ip, #-2147483648
537
-	ldrh	r4, [r0, #128]
538
-	ubfx	r6, ip, #10, #16
539
-	ldrh	r10, [r0, #4]
540
-	mov	fp, r0
541
-	str	ip, [sp, #4]
542
-	smulbb	r4, r4, r3
543
-	ldrb	r3, [r0]	@ zero_extendqisi2
544
-	mov	r0, r6
545
-	cmp	r3, #1
546
-	moveq	r10, r10, asl #1
547
-	uxth	r4, r4
548
-	uxtheq	r10, r10
549
-	mov	r1, r4
803
+	mov	r9, r2
804
+	ldr	r4, .L131
805
+	mov	fp, r3
806
+	mov	r10, r1
807
+	mov	r7, r0
808
+	ldr	r5, [r0, #4]
809
+	ldrh	r2, [r4, #136]
810
+	ldrh	r3, [r4, #138]
811
+	ldrh	r6, [r4, #40]
812
+	smulbb	r3, r3, r2
813
+	ldrb	r2, [r4, #36]	@ zero_extendqisi2
814
+	uxth	r3, r3
815
+	cmp	r2, #1
816
+	lsleq	r6, r6, #1
817
+	ubfx	r2, r5, #10, #16
818
+	mov	r1, r3
819
+	str	r3, [sp, #4]
820
+	mov	r0, r2
821
+	uxtheq	r6, r6
822
+	str	r2, [sp]
550
823
 	bl	__aeabi_uidiv
551
-	cmp	r9, #1
552
-	uxth	r0, r0
553
-	ldr	ip, [sp, #4]
554
-	smulbb	r4, r0, r4
555
-	rsb	r6, r4, r6
556
-	ubfx	r4, ip, #0, #10
557
-	uxth	r6, r6
558
-	bne	.L93
559
-	ldrb	r3, [fp, #144]	@ zero_extendqisi2
824
+	ldr	r3, [sp, #4]
825
+	uxth	r8, r0
826
+	ldr	r2, [sp]
827
+	mov	r1, r3
828
+	mov	r0, r2
829
+	bl	__aeabi_uidivmod
830
+	cmp	r10, #1
831
+	uxth	r1, r1
832
+	ubfx	r0, r5, #0, #10
833
+	bne	.L127
834
+	ldrb	r3, [r4, #152]	@ zero_extendqisi2
560
835
 	cmp	r3, #0
561
-	ldreq	r3, .L97
562
-	addeq	r4, r3, r4, asl #1
563
-	ldreqh	r4, [r4, #148]
564
-.L93:
565
-	add	ip, fp, r0, asl #2
836
+	addeq	r0, r4, r0, lsl #1
837
+	ldrheq	r0, [r0, #156]
838
+.L127:
839
+	add	r4, r4, r8, lsl #2
840
+	ldr	r3, [r4, #1180]
841
+	mla	r6, r6, r1, r3
566
842
 	ldrb	r3, [sp, #48]	@ zero_extendqisi2
567
-	ldr	r1, [ip, #1172]
568
843
 	cmp	r3, #1
569
-	mla	r1, r10, r6, r1
570
-	add	r4, r1, r4
571
-	str	r4, [r7]
572
-	str	r0, [r8]
844
+	add	r0, r6, r0
845
+	str	r0, [r9]
573
846
 	movls	r0, #0
574
-	ldrhi	r0, [r5, #4]
575
-	ldrhi	r3, [r5, #40]
847
+	str	r8, [fp]
848
+	ldrhi	r0, [r7, #4]
849
+	ldrhi	r3, [r7, #40]
576
850
 	addhi	r0, r0, #1024
577
-	rsbhi	r0, r3, r0
851
+	subhi	r0, r0, r3
578
852
 	clzhi	r0, r0
579
-	movhi	r0, r0, lsr #5
853
+	lsrhi	r0, r0, #5
580
854
 	add	sp, sp, #12
581
855
 	@ sp needed
582
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
583
-.L98:
856
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
857
+.L132:
584
858
 	.align	2
585
-.L97:
859
+.L131:
586
860
 	.word	.LANCHOR0
587
861
 	.fnend
588
862
 	.size	LogAddr2PhyAddr, .-LogAddr2PhyAddr
589
863
 	.align	2
864
+	.global	FlashReadStatusEN
865
+	.syntax unified
866
+	.arm
867
+	.fpu softvfp
868
+	.type	FlashReadStatusEN, %function
869
+FlashReadStatusEN:
870
+	.fnstart
871
+	@ args = 0, pretend = 0, frame = 0
872
+	@ frame_needed = 0, uses_anonymous_args = 0
873
+	ldr	r3, .L146
874
+	push	{r4, r5, r6, lr}
875
+	.save {r4, r5, r6, lr}
876
+	ldr	r4, [r3, r0, lsl #3]
877
+	add	r0, r3, r0, lsl #3
878
+	ldrb	r5, [r0, #4]	@ zero_extendqisi2
879
+	ldr	r0, [r3, #48]
880
+	ldrb	r0, [r0, #8]	@ zero_extendqisi2
881
+	cmp	r0, #2
882
+	mov	r0, r3
883
+	lsl	r3, r5, #8
884
+	movne	r2, #112
885
+	add	r5, r5, #8
886
+	addne	r3, r4, r3
887
+	strne	r2, [r3, #2056]
888
+	bne	.L139
889
+	cmp	r2, #0
890
+	add	r3, r4, r3
891
+	ldrbne	r2, [r0, #66]	@ zero_extendqisi2
892
+	ldrbeq	r2, [r0, #65]	@ zero_extendqisi2
893
+	str	r2, [r3, #2056]
894
+	ldrb	r0, [r0, #67]	@ zero_extendqisi2
895
+	cmp	r0, #0
896
+	movne	r2, #0
897
+	addne	ip, r4, r5, lsl #8
898
+	bne	.L138
899
+.L139:
900
+	mov	r0, #80
901
+	bl	ndelay
902
+	ldr	r0, [r4, r5, lsl #8]
903
+	uxtb	r0, r0
904
+	pop	{r4, r5, r6, pc}
905
+.L140:
906
+	lsl	r3, r2, #3
907
+	add	r2, r2, #1
908
+	lsr	r3, r1, r3
909
+	uxtb	r3, r3
910
+	str	r3, [ip, #4]
911
+.L138:
912
+	cmp	r2, r0
913
+	bcc	.L140
914
+	b	.L139
915
+.L147:
916
+	.align	2
917
+.L146:
918
+	.word	.LANCHOR0
919
+	.fnend
920
+	.size	FlashReadStatusEN, .-FlashReadStatusEN
921
+	.align	2
922
+	.global	FlashWaitReadyEN
923
+	.syntax unified
924
+	.arm
925
+	.fpu softvfp
926
+	.type	FlashWaitReadyEN, %function
927
+FlashWaitReadyEN:
928
+	.fnstart
929
+	@ args = 0, pretend = 0, frame = 0
930
+	@ frame_needed = 0, uses_anonymous_args = 0
931
+	push	{r4, r5, r6, lr}
932
+	.save {r4, r5, r6, lr}
933
+	mov	r4, r0
934
+	mov	r5, r1
935
+	mov	r6, r2
936
+.L149:
937
+	mov	r2, r6
938
+	mov	r1, r5
939
+	mov	r0, r4
940
+	bl	FlashReadStatusEN
941
+	cmp	r0, #255
942
+	beq	.L149
943
+	tst	r0, #64
944
+	popne	{r4, r5, r6, pc}
945
+	mov	r1, #3
946
+	mov	r0, #1
947
+	bl	usleep_range
948
+	b	.L149
949
+	.fnend
950
+	.size	FlashWaitReadyEN, .-FlashWaitReadyEN
951
+	.align	2
590
952
 	.global	FlashScheduleEnSet
953
+	.syntax unified
954
+	.arm
955
+	.fpu softvfp
591
956
 	.type	FlashScheduleEnSet, %function
592
957
 FlashScheduleEnSet:
593
958
 	.fnstart
594
959
 	@ args = 0, pretend = 0, frame = 0
595
960
 	@ frame_needed = 0, uses_anonymous_args = 0
596
961
 	@ link register save eliminated.
597
-	ldr	r3, .L100
598
-	ldr	r2, [r3, #1204]
599
-	str	r0, [r3, #1204]
962
+	ldr	r3, .L156
963
+	ldr	r2, [r3, #1212]
964
+	str	r0, [r3, #1212]
600
965
 	mov	r0, r2
601
966
 	bx	lr
602
-.L101:
967
+.L157:
603
968
 	.align	2
604
-.L100:
969
+.L156:
605
970
 	.word	.LANCHOR0
606
971
 	.fnend
607
972
 	.size	FlashScheduleEnSet, .-FlashScheduleEnSet
608
973
 	.align	2
609
974
 	.global	FlashGetPageSize
975
+	.syntax unified
976
+	.arm
977
+	.fpu softvfp
610
978
 	.type	FlashGetPageSize, %function
611
979
 FlashGetPageSize:
612
980
 	.fnstart
613
981
 	@ args = 0, pretend = 0, frame = 0
614
982
 	@ frame_needed = 0, uses_anonymous_args = 0
615
983
 	@ link register save eliminated.
616
-	ldr	r3, .L103
617
-	ldr	r3, [r3, #44]
984
+	ldr	r3, .L159
985
+	ldr	r3, [r3, #48]
618
986
 	ldrb	r0, [r3, #9]	@ zero_extendqisi2
619
987
 	bx	lr
620
-.L104:
988
+.L160:
621
989
 	.align	2
622
-.L103:
990
+.L159:
623
991
 	.word	.LANCHOR0
624
992
 	.fnend
625
993
 	.size	FlashGetPageSize, .-FlashGetPageSize
626
994
 	.align	2
627
995
 	.global	NandcReadDontCaseBusyEn
996
+	.syntax unified
997
+	.arm
998
+	.fpu softvfp
628
999
 	.type	NandcReadDontCaseBusyEn, %function
629
1000
 NandcReadDontCaseBusyEn:
630
1001
 	.fnstart
..
..
@@ -636,107 +1007,122 @@
636
1007
 	.size	NandcReadDontCaseBusyEn, .-NandcReadDontCaseBusyEn
637
1008
 	.align	2
638
1009
 	.global	NandcGetChipIf
1010
+	.syntax unified
1011
+	.arm
1012
+	.fpu softvfp
639
1013
 	.type	NandcGetChipIf, %function
640
1014
 NandcGetChipIf:
641
1015
 	.fnstart
642
1016
 	@ args = 0, pretend = 0, frame = 0
643
1017
 	@ frame_needed = 0, uses_anonymous_args = 0
644
1018
 	@ link register save eliminated.
645
-	ldr	r3, .L107
646
-	add	r0, r3, r0, asl #3
647
-	ldrb	r2, [r0, #16]	@ zero_extendqisi2
648
-	ldr	r0, [r0, #12]
649
-	add	r2, r2, #8
650
-	add	r0, r0, r2, asl #8
1019
+	ldr	r2, .L163
1020
+	add	r3, r2, r0, lsl #3
1021
+	ldr	r0, [r2, r0, lsl #3]
1022
+	ldrb	r3, [r3, #4]	@ zero_extendqisi2
1023
+	add	r3, r3, #8
1024
+	add	r0, r0, r3, lsl #8
651
1025
 	bx	lr
652
-.L108:
1026
+.L164:
653
1027
 	.align	2
654
-.L107:
1028
+.L163:
655
1029
 	.word	.LANCHOR0
656
1030
 	.fnend
657
1031
 	.size	NandcGetChipIf, .-NandcGetChipIf
658
1032
 	.align	2
659
1033
 	.global	NandcSetDdrPara
1034
+	.syntax unified
1035
+	.arm
1036
+	.fpu softvfp
660
1037
 	.type	NandcSetDdrPara, %function
661
1038
 NandcSetDdrPara:
662
1039
 	.fnstart
663
1040
 	@ args = 0, pretend = 0, frame = 0
664
1041
 	@ frame_needed = 0, uses_anonymous_args = 0
665
1042
 	@ link register save eliminated.
666
-	ldr	r3, .L110
667
-	ldr	r2, [r3, #80]
668
-	mov	r3, r0, asl #8
669
-	orr	r0, r3, r0, asl #16
670
-	orr	r3, r0, #1
671
-	str	r3, [r2, #304]
1043
+	ldr	r3, .L166
1044
+	ldr	r2, [r3, #88]
1045
+	lsl	r3, r0, #8
1046
+	orr	r0, r3, r0, lsl #16
1047
+	orr	r0, r0, #1
1048
+	str	r0, [r2, #304]
672
1049
 	bx	lr
673
-.L111:
1050
+.L167:
674
1051
 	.align	2
675
-.L110:
1052
+.L166:
676
1053
 	.word	.LANCHOR0
677
1054
 	.fnend
678
1055
 	.size	NandcSetDdrPara, .-NandcSetDdrPara
679
1056
 	.align	2
680
1057
 	.global	NandcSetDdrDiv
1058
+	.syntax unified
1059
+	.arm
1060
+	.fpu softvfp
681
1061
 	.type	NandcSetDdrDiv, %function
682
1062
 NandcSetDdrDiv:
683
1063
 	.fnstart
684
1064
 	@ args = 0, pretend = 0, frame = 0
685
1065
 	@ frame_needed = 0, uses_anonymous_args = 0
686
1066
 	@ link register save eliminated.
687
-	ldr	r3, .L113
1067
+	ldr	r3, .L169
688
1068
 	orr	r0, r0, #16640
689
-	ldr	r3, [r3, #80]
1069
+	ldr	r3, [r3, #88]
690
1070
 	str	r0, [r3, #344]
691
1071
 	bx	lr
692
-.L114:
1072
+.L170:
693
1073
 	.align	2
694
-.L113:
1074
+.L169:
695
1075
 	.word	.LANCHOR0
696
1076
 	.fnend
697
1077
 	.size	NandcSetDdrDiv, .-NandcSetDdrDiv
698
1078
 	.align	2
699
1079
 	.global	NandcSetDdrMode
1080
+	.syntax unified
1081
+	.arm
1082
+	.fpu softvfp
700
1083
 	.type	NandcSetDdrMode, %function
701
1084
 NandcSetDdrMode:
702
1085
 	.fnstart
703
1086
 	@ args = 0, pretend = 0, frame = 0
704
1087
 	@ frame_needed = 0, uses_anonymous_args = 0
705
1088
 	@ link register save eliminated.
706
-	ldr	r3, .L118
1089
+	ldr	r3, .L174
707
1090
 	cmp	r0, #0
708
-	ldr	r2, [r3, #80]
1091
+	ldr	r2, [r3, #88]
709
1092
 	ldr	r3, [r2]
710
1093
 	bfieq	r3, r0, #13, #1
711
1094
 	orrne	r3, r3, #253952
712
1095
 	str	r3, [r2]
713
1096
 	bx	lr
714
-.L119:
1097
+.L175:
715
1098
 	.align	2
716
-.L118:
1099
+.L174:
717
1100
 	.word	.LANCHOR0
718
1101
 	.fnend
719
1102
 	.size	NandcSetDdrMode, .-NandcSetDdrMode
720
1103
 	.align	2
721
1104
 	.global	NandcSetMode
1105
+	.syntax unified
1106
+	.arm
1107
+	.fpu softvfp
722
1108
 	.type	NandcSetMode, %function
723
1109
 NandcSetMode:
724
1110
 	.fnstart
725
1111
 	@ args = 0, pretend = 0, frame = 0
726
1112
 	@ frame_needed = 0, uses_anonymous_args = 0
727
1113
 	@ link register save eliminated.
728
-	ldr	r3, .L127
1114
+	ldr	r3, .L183
729
1115
 	ands	r1, r0, #6
730
-	ldr	r2, [r3, #80]
1116
+	ldr	r2, [r3, #88]
731
1117
 	ldr	r3, [r2]
732
1118
 	bfieq	r3, r1, #13, #1
733
-	beq	.L123
734
-	orr	r3, r3, #24576
1119
+	beq	.L179
735
1120
 	movw	r1, #8322
736
-	bfc	r3, #15, #1
1121
+	orr	r3, r3, #24576
737
1122
 	str	r1, [r2, #344]
1123
+	bfc	r3, #15, #1
1124
+	ldr	r1, .L183+4
738
1125
 	orr	r3, r3, #196608
739
-	ldr	r1, .L127+4
740
1126
 	tst	r0, #4
741
1127
 	orrne	r3, r3, #32768
742
1128
 	str	r1, [r2, #304]
..
..
@@ -744,642 +1130,416 @@
744
1130
 	str	r1, [r2, #308]
745
1131
 	mov	r1, #39
746
1132
 	str	r1, [r2, #308]
747
-.L123:
1133
+.L179:
748
1134
 	str	r3, [r2]
749
1135
 	mov	r0, #0
750
1136
 	bx	lr
751
-.L128:
1137
+.L184:
752
1138
 	.align	2
753
-.L127:
1139
+.L183:
754
1140
 	.word	.LANCHOR0
755
1141
 	.word	1052675
756
1142
 	.fnend
757
1143
 	.size	NandcSetMode, .-NandcSetMode
758
1144
 	.align	2
759
1145
 	.global	NandcFlashCs
1146
+	.syntax unified
1147
+	.arm
1148
+	.fpu softvfp
760
1149
 	.type	NandcFlashCs, %function
761
1150
 NandcFlashCs:
762
1151
 	.fnstart
763
1152
 	@ args = 0, pretend = 0, frame = 0
764
1153
 	@ frame_needed = 0, uses_anonymous_args = 0
765
1154
 	@ link register save eliminated.
766
-	ldr	r2, .L130
767
-	add	r0, r2, r0, asl #3
1155
+	ldr	r3, .L186
768
1156
 	mov	r2, #1
769
-	ldr	r1, [r0, #12]
770
-	ldrb	r0, [r0, #16]	@ zero_extendqisi2
1157
+	ldr	r1, [r3, r0, lsl #3]
1158
+	add	r0, r3, r0, lsl #3
1159
+	ldrb	r0, [r0, #4]	@ zero_extendqisi2
771
1160
 	ldr	r3, [r1]
772
-	mov	r2, r2, asl r0
1161
+	lsl	r2, r2, r0
773
1162
 	bfi	r3, r2, #0, #8
774
1163
 	str	r3, [r1]
775
1164
 	bx	lr
776
-.L131:
1165
+.L187:
777
1166
 	.align	2
778
-.L130:
1167
+.L186:
779
1168
 	.word	.LANCHOR0
780
1169
 	.fnend
781
1170
 	.size	NandcFlashCs, .-NandcFlashCs
782
1171
 	.align	2
783
1172
 	.global	NandcFlashDeCs
1173
+	.syntax unified
1174
+	.arm
1175
+	.fpu softvfp
784
1176
 	.type	NandcFlashDeCs, %function
785
1177
 NandcFlashDeCs:
786
1178
 	.fnstart
787
1179
 	@ args = 0, pretend = 0, frame = 0
788
1180
 	@ frame_needed = 0, uses_anonymous_args = 0
789
1181
 	@ link register save eliminated.
790
-	ldr	r3, .L133
791
-	add	r0, r3, r0, asl #3
792
-	ldr	r2, [r0, #12]
1182
+	ldr	r3, .L189
1183
+	ldr	r2, [r3, r0, lsl #3]
793
1184
 	ldr	r3, [r2]
794
1185
 	bfc	r3, #0, #8
795
1186
 	bfc	r3, #17, #1
796
1187
 	str	r3, [r2]
797
1188
 	bx	lr
798
-.L134:
1189
+.L190:
799
1190
 	.align	2
800
-.L133:
1191
+.L189:
801
1192
 	.word	.LANCHOR0
802
1193
 	.fnend
803
1194
 	.size	NandcFlashDeCs, .-NandcFlashDeCs
804
1195
 	.align	2
805
-	.global	NandcDelayns
806
-	.type	NandcDelayns, %function
807
-NandcDelayns:
808
-	.fnstart
809
-	@ args = 0, pretend = 0, frame = 0
810
-	@ frame_needed = 0, uses_anonymous_args = 0
811
-	stmfd	sp!, {r3, lr}
812
-	.save {r3, lr}
813
-	add	r0, r0, #996
814
-	ldr	r3, .L137
815
-	add	r0, r0, #3
816
-	umull	r0, r1, r0, r3
817
-	ldr	r3, .L137+4
818
-	ldr	r3, [r3, #8]
819
-	mov	r0, r1, lsr #6
820
-	blx	r3
821
-	mov	r0, #0
822
-	ldmfd	sp!, {r3, pc}
823
-.L138:
824
-	.align	2
825
-.L137:
826
-	.word	274877907
827
-	.word	arm_delay_ops
828
-	.fnend
829
-	.size	NandcDelayns, .-NandcDelayns
830
-	.align	2
831
-	.global	FlashReadStatus
832
-	.type	FlashReadStatus, %function
833
-FlashReadStatus:
834
-	.fnstart
835
-	@ args = 0, pretend = 0, frame = 0
836
-	@ frame_needed = 0, uses_anonymous_args = 0
837
-	stmfd	sp!, {r3, r4, r5, lr}
838
-	.save {r3, r4, r5, lr}
839
-	mov	r2, #112
840
-	ldr	r3, .L141
841
-	add	r0, r3, r0, asl #3
842
-	ldrb	r4, [r0, #16]	@ zero_extendqisi2
843
-	ldr	r5, [r0, #12]
844
-	mov	r0, #80
845
-	add	r3, r5, r4, asl #8
846
-	add	r4, r4, #8
847
-	str	r2, [r3, #2056]
848
-	bl	NandcDelayns
849
-	ldr	r0, [r5, r4, asl #8]
850
-	ldmfd	sp!, {r3, r4, r5, pc}
851
-.L142:
852
-	.align	2
853
-.L141:
854
-	.word	.LANCHOR0
855
-	.fnend
856
-	.size	FlashReadStatus, .-FlashReadStatus
857
-	.align	2
858
-	.global	ToshibaSetRRPara
859
-	.type	ToshibaSetRRPara, %function
860
-ToshibaSetRRPara:
861
-	.fnstart
862
-	@ args = 0, pretend = 0, frame = 0
863
-	@ frame_needed = 0, uses_anonymous_args = 0
864
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
865
-	.save {r4, r5, r6, r7, r8, r9, r10, lr}
866
-	add	r8, r1, r1, asl #2
867
-	ldr	r9, .L153
868
-	mov	r5, r0
869
-	ldr	r7, .L153+4
870
-	mov	r6, r1
871
-	add	r10, r9, #256
872
-	mov	r4, #0
873
-.L144:
874
-	ldrb	r3, [r7, #1209]	@ zero_extendqisi2
875
-	cmp	r4, r3
876
-	bcs	.L152
877
-	mov	r3, #85
878
-	str	r3, [r5, #8]
879
-	ldrsb	r3, [r4, r10]
880
-	mov	r0, #200
881
-	str	r3, [r5, #4]
882
-	bl	NandcDelayns
883
-	ldrb	r3, [r7, #1208]	@ zero_extendqisi2
884
-	cmp	r3, #34
885
-	addeq	r3, r4, r8
886
-	addeq	r3, r10, r3
887
-	beq	.L151
888
-	cmp	r3, #35
889
-	addne	r3, r9, r6
890
-	addne	r3, r3, #400
891
-	ldrnesb	r3, [r3]
892
-	bne	.L150
893
-	ldr	r3, .L153+8
894
-	add	r2, r4, r8
895
-	add	r3, r3, r2
896
-.L151:
897
-	ldrsb	r3, [r3, #5]
898
-.L150:
899
-	str	r3, [r5]
900
-	add	r4, r4, #1
901
-	b	.L144
902
-.L152:
903
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
904
-.L154:
905
-	.align	2
906
-.L153:
907
-	.word	.LANCHOR1
908
-	.word	.LANCHOR0
909
-	.word	.LANCHOR1+304
910
-	.fnend
911
-	.size	ToshibaSetRRPara, .-ToshibaSetRRPara
912
-	.align	2
913
-	.global	SamsungSetRRPara
914
-	.type	SamsungSetRRPara, %function
915
-SamsungSetRRPara:
916
-	.fnstart
917
-	@ args = 0, pretend = 0, frame = 0
918
-	@ frame_needed = 0, uses_anonymous_args = 0
919
-	ldr	r3, .L160
920
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
921
-	.save {r4, r5, r6, r7, r8, r9, r10, lr}
922
-	add	r1, r3, r1, asl #2
923
-	ldr	r8, .L160+4
924
-	mov	r4, #0
925
-	add	r5, r1, #3
926
-	mov	r6, r0
927
-	mov	r7, r3
928
-	mov	r9, #161
929
-	mov	r10, r4
930
-.L156:
931
-	ldrb	r3, [r8, #1209]	@ zero_extendqisi2
932
-	cmp	r4, r3
933
-	bcs	.L159
934
-	str	r9, [r6, #8]
935
-	mov	r0, #300
936
-	str	r10, [r6]
937
-	ldrsb	r3, [r7, r4]
938
-	add	r4, r4, #1
939
-	str	r3, [r6]
940
-	ldrsb	r3, [r5, #1]!
941
-	str	r3, [r6]
942
-	bl	NandcDelayns
943
-	b	.L156
944
-.L159:
945
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
946
-.L161:
947
-	.align	2
948
-.L160:
949
-	.word	.LANCHOR1+408
950
-	.word	.LANCHOR0
951
-	.fnend
952
-	.size	SamsungSetRRPara, .-SamsungSetRRPara
953
-	.align	2
954
1196
 	.global	HynixSetRRPara
1197
+	.syntax unified
1198
+	.arm
1199
+	.fpu softvfp
955
1200
 	.type	HynixSetRRPara, %function
956
1201
 HynixSetRRPara:
957
1202
 	.fnstart
958
1203
 	@ args = 0, pretend = 0, frame = 8
959
1204
 	@ frame_needed = 0, uses_anonymous_args = 0
960
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
1205
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
961
1206
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
962
1207
 	.pad #12
963
-	mov	r6, r3
964
-	ldr	r5, .L171
965
-	mov	r9, r2
966
-	ldr	r4, .L171+4
967
-	mov	r7, r0
1208
+	mov	r6, r0
1209
+	ldr	r0, .L200
1210
+	mov	r7, r3
968
1211
 	mov	r8, r1
969
-	ldr	r3, [r5, #44]
970
-	ldrb	r2, [r3, #19]	@ zero_extendqisi2
971
-	mov	r3, r0, asl #3
972
-	cmp	r2, #6
973
-	addeq	r4, r4, r0, asl #6
974
-	addeq	r4, r4, #20
975
-	addeq	r4, r4, r6, asl #2
976
-	beq	.L164
977
-	cmp	r2, #7
978
-	bne	.L165
979
-	mov	r2, #160
980
-	mla	r4, r2, r0, r4
981
-	add	r2, r6, r6, asl #2
982
-	add	r4, r4, #28
983
-	add	r4, r4, r2, asl #1
984
-	b	.L164
985
-.L165:
986
-	cmp	r2, #8
987
-	addne	r2, r6, r3
988
-	addeq	r2, r6, r6, asl #2
989
-	ldreq	r4, .L171+8
990
-	addne	r4, r4, r2, asl #3
991
-	addeq	r4, r4, r2
992
-	addne	r4, r4, #20
993
-.L164:
994
-	add	r3, r5, r3
995
-	mov	r0, r7
1212
+	mov	r10, r2
1213
+	ldr	r3, [r0, #48]
1214
+	mov	r5, r0
1215
+	add	r4, r0, #1216
1216
+	ldrb	r3, [r3, #19]	@ zero_extendqisi2
1217
+	cmp	r3, #6
1218
+	moveq	r3, #20
1219
+	addeq	r3, r3, r6, lsl #6
1220
+	addeq	r3, r3, r7, lsl #2
1221
+	beq	.L199
1222
+	cmp	r3, #7
1223
+	bne	.L194
1224
+	mov	r3, #160
1225
+	mov	r2, #28
1226
+	smlabb	r2, r3, r6, r2
1227
+	mov	r3, #10
1228
+	smlabb	r3, r3, r7, r2
1229
+.L199:
1230
+	add	r4, r4, r3
1231
+.L193:
1232
+	add	r3, r5, r6, lsl #3
1233
+	ldr	r9, [r5, r6, lsl #3]
1234
+	mov	r0, r6
1235
+	ldrb	fp, [r3, #4]	@ zero_extendqisi2
996
1236
 	sub	r8, r8, #1
997
-	sub	r4, r4, #1
998
-	ldrb	fp, [r3, #16]	@ zero_extendqisi2
999
-	ldr	r10, [r3, #12]
1000
1237
 	bl	NandcFlashCs
1001
-	sub	ip, r9, #1
1002
-	add	r9, r9, r8
1003
-	mov	r3, fp, asl #8
1004
-	mov	r2, #54
1005
-	add	fp, r10, r3
1006
-	str	r2, [fp, #2056]
1007
-.L167:
1008
-	cmp	ip, r9
1009
-	beq	.L170
1010
-	ldrb	r2, [ip, #1]!	@ zero_extendqisi2
1011
-	mov	r0, #200
1012
-	str	r3, [sp, #4]
1013
-	str	r2, [fp, #2052]
1014
-	str	ip, [sp]
1015
-	bl	NandcDelayns
1016
-	ldrsb	r2, [r4, #1]!
1017
-	str	r2, [fp, #2048]
1018
-	ldr	r3, [sp, #4]
1019
-	ldr	ip, [sp]
1020
-	b	.L167
1021
-.L170:
1022
-	add	r10, r10, r3
1023
-	mov	r0, r7
1238
+	mov	r3, #54
1239
+	add	r8, r10, r8
1240
+	sub	r4, r4, #1
1241
+	lsl	fp, fp, #8
1242
+	add	r0, r9, fp
1243
+	str	r3, [r0, #2056]
1244
+	sub	r3, r10, #1
1245
+	mov	r10, r0
1246
+.L196:
1247
+	cmp	r3, r8
1248
+	bne	.L197
1024
1249
 	mov	r3, #22
1025
-	add	r5, r5, r7
1026
-	str	r3, [r10, #2056]
1250
+	add	r9, r9, fp
1251
+	mov	r0, r6
1252
+	str	r3, [r9, #2056]
1027
1253
 	bl	NandcFlashDeCs
1028
-	strb	r6, [r5, #2064]
1254
+	add	r0, r5, r6
1255
+	strb	r7, [r0, #2068]
1029
1256
 	add	sp, sp, #12
1030
1257
 	@ sp needed
1031
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
1032
-.L172:
1258
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
1259
+.L194:
1260
+	cmp	r3, #8
1261
+	addeq	r4, r4, #28
1262
+	addeq	r3, r7, r7, lsl #2
1263
+	beq	.L199
1264
+	add	r3, r7, #2
1265
+	add	r3, r3, r6, lsl #3
1266
+	add	r4, r4, r3, lsl #3
1267
+	add	r4, r4, #4
1268
+	b	.L193
1269
+.L197:
1270
+	ldrb	r2, [r3, #1]!	@ zero_extendqisi2
1271
+	mov	r0, #200
1272
+	str	r2, [r10, #2052]
1273
+	str	r3, [sp, #4]
1274
+	bl	ndelay
1275
+	ldrsb	r2, [r4, #1]!
1276
+	ldr	r3, [sp, #4]
1277
+	str	r2, [r10, #2048]
1278
+	b	.L196
1279
+.L201:
1033
1280
 	.align	2
1034
-.L171:
1281
+.L200:
1035
1282
 	.word	.LANCHOR0
1036
-	.word	.LANCHOR0+1210
1037
-	.word	.LANCHOR0+1238
1038
1283
 	.fnend
1039
1284
 	.size	HynixSetRRPara, .-HynixSetRRPara
1040
1285
 	.align	2
1041
1286
 	.global	FlashSetReadRetryDefault
1287
+	.syntax unified
1288
+	.arm
1289
+	.fpu softvfp
1042
1290
 	.type	FlashSetReadRetryDefault, %function
1043
1291
 FlashSetReadRetryDefault:
1044
1292
 	.fnstart
1045
1293
 	@ args = 0, pretend = 0, frame = 0
1046
1294
 	@ frame_needed = 0, uses_anonymous_args = 0
1047
-	ldr	r3, .L181
1048
-	ldr	r2, [r3, #44]
1049
-	ldrb	r2, [r2, #19]	@ zero_extendqisi2
1050
-	sub	r2, r2, #1
1051
-	cmp	r2, #7
1052
-	bxhi	lr
1053
-	stmfd	sp!, {r4, r5, r6, lr}
1054
-	.save {r4, r5, r6, lr}
1295
+	push	{r4, r5, r6, r7, r8, lr}
1296
+	.save {r4, r5, r6, r7, r8, lr}
1297
+	ldr	r5, .L209
1298
+	ldr	r3, [r5, #48]
1299
+	ldrb	r3, [r3, #19]	@ zero_extendqisi2
1300
+	sub	r3, r3, #1
1301
+	cmp	r3, #7
1302
+	pophi	{r4, r5, r6, r7, r8, pc}
1303
+	ldr	r7, .L209+4
1304
+	add	r6, r5, #1216
1055
1305
 	mov	r4, #0
1056
-	ldr	r6, .L181+4
1057
-	mov	r5, r3
1058
-.L174:
1059
-	ldrb	r3, [r6, r4, asl #3]	@ zero_extendqisi2
1306
+	add	r6, r6, #4
1307
+.L205:
1308
+	ldrb	r3, [r7, r4, lsl #3]	@ zero_extendqisi2
1060
1309
 	uxtb	r0, r4
1061
1310
 	cmp	r3, #173
1062
-	bne	.L175
1063
-	ldrb	r1, [r5, #1211]	@ zero_extendqisi2
1311
+	bne	.L204
1064
1312
 	mov	r3, #0
1065
-	ldr	r2, .L181+8
1313
+	mov	r2, r6
1314
+	ldrb	r1, [r5, #1217]	@ zero_extendqisi2
1066
1315
 	bl	HynixSetRRPara
1067
-.L175:
1316
+.L204:
1068
1317
 	add	r4, r4, #1
1069
1318
 	cmp	r4, #4
1070
-	bne	.L174
1071
-	ldmfd	sp!, {r4, r5, r6, pc}
1072
-.L182:
1319
+	bne	.L205
1320
+	pop	{r4, r5, r6, r7, r8, pc}
1321
+.L210:
1073
1322
 	.align	2
1074
-.L181:
1323
+.L209:
1075
1324
 	.word	.LANCHOR0
1076
-	.word	.LANCHOR0+2068
1077
-	.word	.LANCHOR0+1214
1325
+	.word	.LANCHOR0+2072
1078
1326
 	.fnend
1079
1327
 	.size	FlashSetReadRetryDefault, .-FlashSetReadRetryDefault
1080
1328
 	.align	2
1081
-	.global	FlashReadStatusEN
1082
-	.type	FlashReadStatusEN, %function
1083
-FlashReadStatusEN:
1084
-	.fnstart
1085
-	@ args = 0, pretend = 0, frame = 0
1086
-	@ frame_needed = 0, uses_anonymous_args = 0
1087
-	ldr	ip, .L194
1088
-	stmfd	sp!, {r3, r4, r5, lr}
1089
-	.save {r3, r4, r5, lr}
1090
-	add	r0, ip, r0, asl #3
1091
-	ldr	r3, [ip, #44]
1092
-	ldrb	r5, [r0, #16]	@ zero_extendqisi2
1093
-	ldr	r4, [r0, #12]
1094
-	ldrb	r3, [r3, #8]	@ zero_extendqisi2
1095
-	cmp	r3, #2
1096
-	mov	r3, r5, asl #8
1097
-	addne	r3, r4, r3
1098
-	add	r5, r5, #8
1099
-	movne	r2, #112
1100
-	strne	r2, [r3, #2056]
1101
-	bne	.L188
1102
-	cmp	r2, #0
1103
-	add	r3, r4, r3
1104
-	ldrneb	r2, [ip, #62]	@ zero_extendqisi2
1105
-	ldreqb	r2, [ip, #61]	@ zero_extendqisi2
1106
-	str	r2, [r3, #2056]
1107
-	ldrb	r0, [ip, #63]	@ zero_extendqisi2
1108
-	cmp	r0, #0
1109
-	addne	ip, r4, r5, asl #8
1110
-	movne	r2, #0
1111
-	beq	.L188
1112
-.L187:
1113
-	cmp	r2, r0
1114
-	bcs	.L188
1115
-	mov	r3, r2, asl #3
1116
-	add	r2, r2, #1
1117
-	mov	r3, r1, lsr r3
1118
-	uxtb	r3, r3
1119
-	str	r3, [ip, #4]
1120
-	b	.L187
1121
-.L188:
1122
-	mov	r0, #80
1123
-	bl	NandcDelayns
1124
-	ldr	r0, [r4, r5, asl #8]
1125
-	uxtb	r0, r0
1126
-	ldmfd	sp!, {r3, r4, r5, pc}
1127
-.L195:
1128
-	.align	2
1129
-.L194:
1130
-	.word	.LANCHOR0
1131
-	.fnend
1132
-	.size	FlashReadStatusEN, .-FlashReadStatusEN
1133
-	.align	2
1134
-	.global	FlashWaitReadyEN
1135
-	.type	FlashWaitReadyEN, %function
1136
-FlashWaitReadyEN:
1137
-	.fnstart
1138
-	@ args = 0, pretend = 0, frame = 0
1139
-	@ frame_needed = 0, uses_anonymous_args = 0
1140
-	stmfd	sp!, {r4, r5, r6, lr}
1141
-	.save {r4, r5, r6, lr}
1142
-	mov	r4, r0
1143
-	mov	r5, r1
1144
-	mov	r6, r2
1145
-.L197:
1146
-	mov	r0, r4
1147
-	mov	r1, r5
1148
-	mov	r2, r6
1149
-	bl	FlashReadStatusEN
1150
-	cmp	r0, #255
1151
-	beq	.L197
1152
-	tst	r0, #64
1153
-	ldmnefd	sp!, {r4, r5, r6, pc}
1154
-	mov	r0, #1
1155
-	mov	r1, #3
1156
-	bl	usleep_range
1157
-	b	.L197
1158
-	.fnend
1159
-	.size	FlashWaitReadyEN, .-FlashWaitReadyEN
1160
-	.align	2
1161
1329
 	.global	FlashWaitCmdDone
1330
+	.syntax unified
1331
+	.arm
1332
+	.fpu softvfp
1162
1333
 	.type	FlashWaitCmdDone, %function
1163
1334
 FlashWaitCmdDone:
1164
1335
 	.fnstart
1165
1336
 	@ args = 0, pretend = 0, frame = 0
1166
1337
 	@ frame_needed = 0, uses_anonymous_args = 0
1167
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
1168
-	.save {r3, r4, r5, r6, r7, lr}
1169
-	ldr	r5, .L211
1170
-	add	r4, r5, r0, asl #4
1171
-	ldr	r3, [r4, #2108]
1172
-	ldrb	r7, [r4, #2100]	@ zero_extendqisi2
1338
+	push	{r4, r5, r6, r7, r8, lr}
1339
+	.save {r4, r5, r6, r7, r8, lr}
1340
+	ldr	r5, .L219
1341
+	add	r4, r5, r0, lsl #4
1342
+	ldr	r3, [r4, #2112]
1173
1343
 	cmp	r3, #0
1174
-	beq	.L205
1344
+	beq	.L213
1345
+	ldrb	r7, [r4, #2104]	@ zero_extendqisi2
1175
1346
 	mov	r6, r0
1347
+	add	r5, r5, r6, lsl #2
1176
1348
 	mov	r0, r7
1177
-	add	r5, r5, r6, asl #2
1178
1349
 	bl	NandcFlashCs
1179
-	ldr	r1, [r4, #2104]
1350
+	ldr	r2, [r5, #1180]
1180
1351
 	mov	r0, r7
1181
-	ldr	r2, [r5, #1172]
1352
+	ldr	r1, [r4, #2108]
1182
1353
 	adds	r2, r2, #0
1183
1354
 	movne	r2, #1
1184
1355
 	bl	FlashWaitReadyEN
1185
-	mov	r5, r0
1356
+	mov	r1, r0
1186
1357
 	mov	r0, r7
1187
1358
 	bl	NandcFlashDeCs
1188
-	ldr	r2, [r4, #2108]
1189
-	sbfx	r3, r5, #0, #1
1190
-	str	r3, [r2]
1191
-	mov	r2, #0
1192
-	ldr	r1, [r4, #2112]
1193
-	str	r2, [r4, #2108]
1194
-	cmp	r1, r2
1195
-	strne	r3, [r1]
1196
-	strne	r2, [r4, #2112]
1197
-.L205:
1359
+	ldr	r3, [r4, #2112]
1360
+	sbfx	r0, r1, #0, #1
1361
+	str	r0, [r3]
1362
+	mov	r3, #0
1363
+	ldr	r2, [r4, #2116]
1364
+	str	r3, [r4, #2112]
1365
+	cmp	r2, r3
1366
+	strne	r0, [r2]
1367
+	strne	r3, [r4, #2116]
1368
+.L213:
1198
1369
 	mov	r0, #0
1199
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
1200
-.L212:
1370
+	pop	{r4, r5, r6, r7, r8, pc}
1371
+.L220:
1201
1372
 	.align	2
1202
-.L211:
1373
+.L219:
1203
1374
 	.word	.LANCHOR0
1204
1375
 	.fnend
1205
1376
 	.size	FlashWaitCmdDone, .-FlashWaitCmdDone
1206
1377
 	.align	2
1207
-	.type	flash_read_ecc, %function
1208
-flash_read_ecc:
1378
+	.global	NandcDelayns
1379
+	.syntax unified
1380
+	.arm
1381
+	.fpu softvfp
1382
+	.type	NandcDelayns, %function
1383
+NandcDelayns:
1209
1384
 	.fnstart
1210
1385
 	@ args = 0, pretend = 0, frame = 0
1211
1386
 	@ frame_needed = 0, uses_anonymous_args = 0
1212
-	ldr	r2, .L215
1213
-	stmfd	sp!, {r4, lr}
1387
+	push	{r4, lr}
1214
1388
 	.save {r4, lr}
1215
-	add	r0, r2, r0, asl #3
1216
-	ldrb	r4, [r0, #16]	@ zero_extendqisi2
1217
-	ldr	r3, [r0, #12]
1218
-	mov	r0, #80
1219
-	add	r4, r3, r4, asl #8
1220
-	mov	r3, #122
1221
-	str	r3, [r4, #2056]
1222
-	bl	NandcDelayns
1223
-	ldr	r3, [r4, #2048]
1224
-	ldr	r0, [r4, #2048]
1225
-	and	r3, r3, #15
1226
-	and	r0, r0, #15
1227
-	cmp	r0, r3
1228
-	movcc	r0, r3
1229
-	ldr	r3, [r4, #2048]
1230
-	and	r3, r3, #15
1231
-	cmp	r0, r3
1232
-	movcc	r0, r3
1233
-	ldr	r3, [r4, #2048]
1234
-	and	r3, r3, #15
1235
-	cmp	r0, r3
1236
-	movcc	r0, r3
1237
-	ldmfd	sp!, {r4, pc}
1238
-.L216:
1239
-	.align	2
1240
-.L215:
1241
-	.word	.LANCHOR0
1389
+	bl	ndelay
1390
+	mov	r0, #0
1391
+	pop	{r4, pc}
1242
1392
 	.fnend
1243
-	.size	flash_read_ecc, .-flash_read_ecc
1393
+	.size	NandcDelayns, .-NandcDelayns
1244
1394
 	.align	2
1245
1395
 	.global	NandcWaitFlashReadyNoDelay
1396
+	.syntax unified
1397
+	.arm
1398
+	.fpu softvfp
1246
1399
 	.type	NandcWaitFlashReadyNoDelay, %function
1247
1400
 NandcWaitFlashReadyNoDelay:
1248
1401
 	.fnstart
1249
1402
 	@ args = 0, pretend = 0, frame = 8
1250
1403
 	@ frame_needed = 0, uses_anonymous_args = 0
1251
-	ldr	r3, .L223
1252
-	stmfd	sp!, {r0, r1, r2, r4, r5, lr}
1404
+	ldr	r3, .L229
1405
+	push	{r0, r1, r2, r4, r5, lr}
1253
1406
 	.save {r4, r5, lr}
1254
1407
 	.pad #12
1255
-	add	r0, r3, r0, asl #3
1256
-	ldr	r4, .L223+4
1257
-	ldr	r5, [r0, #12]
1258
-.L219:
1408
+	ldr	r4, .L229+4
1409
+	ldr	r5, [r3, r0, lsl #3]
1410
+.L225:
1259
1411
 	ldr	r3, [r5]
1260
1412
 	str	r3, [sp, #4]
1261
1413
 	ldr	r3, [sp, #4]
1262
1414
 	tst	r3, #512
1263
-	bne	.L220
1415
+	bne	.L226
1264
1416
 	mov	r0, #10
1265
-	bl	NandcDelayns
1417
+	bl	ndelay
1266
1418
 	subs	r4, r4, #1
1267
-	bne	.L219
1419
+	bne	.L225
1268
1420
 	mvn	r0, #0
1269
-	b	.L218
1270
-.L220:
1271
-	mov	r0, #0
1272
-.L218:
1421
+.L223:
1273
1422
 	add	sp, sp, #12
1274
1423
 	@ sp needed
1275
-	ldmfd	sp!, {r4, r5, pc}
1276
-.L224:
1424
+	pop	{r4, r5, pc}
1425
+.L226:
1426
+	mov	r0, #0
1427
+	b	.L223
1428
+.L230:
1277
1429
 	.align	2
1278
-.L223:
1430
+.L229:
1279
1431
 	.word	.LANCHOR0
1280
1432
 	.word	100000
1281
1433
 	.fnend
1282
1434
 	.size	NandcWaitFlashReadyNoDelay, .-NandcWaitFlashReadyNoDelay
1283
1435
 	.align	2
1284
1436
 	.global	NandcWaitFlashReady
1437
+	.syntax unified
1438
+	.arm
1439
+	.fpu softvfp
1285
1440
 	.type	NandcWaitFlashReady, %function
1286
1441
 NandcWaitFlashReady:
1287
1442
 	.fnstart
1288
1443
 	@ args = 0, pretend = 0, frame = 8
1289
1444
 	@ frame_needed = 0, uses_anonymous_args = 0
1290
-	ldr	r3, .L231
1291
-	stmfd	sp!, {r0, r1, r2, r4, r5, lr}
1445
+	push	{r0, r1, r2, r4, r5, lr}
1292
1446
 	.save {r4, r5, lr}
1293
1447
 	.pad #12
1294
-	add	r0, r3, r0, asl #3
1295
-	ldr	r4, .L231+4
1296
-	ldr	r5, [r0, #12]
1448
+	ldr	r3, .L237
1449
+	ldr	r4, .L237+4
1450
+	ldr	r5, [r3, r0, lsl #3]
1297
1451
 	mov	r0, #130
1298
-	bl	NandcDelayns
1299
-.L227:
1452
+	bl	ndelay
1453
+.L233:
1300
1454
 	ldr	r3, [r5]
1301
1455
 	str	r3, [sp, #4]
1302
1456
 	ldr	r3, [sp, #4]
1303
1457
 	tst	r3, #512
1304
-	bne	.L228
1305
-	mov	r0, #1
1458
+	bne	.L234
1306
1459
 	mov	r1, #2
1460
+	mov	r0, #1
1307
1461
 	bl	usleep_range
1308
1462
 	subs	r4, r4, #1
1309
-	bne	.L227
1463
+	bne	.L233
1310
1464
 	mvn	r0, #0
1311
-	b	.L226
1312
-.L228:
1313
-	mov	r0, #0
1314
-.L226:
1465
+.L231:
1315
1466
 	add	sp, sp, #12
1316
1467
 	@ sp needed
1317
-	ldmfd	sp!, {r4, r5, pc}
1318
-.L232:
1468
+	pop	{r4, r5, pc}
1469
+.L234:
1470
+	mov	r0, #0
1471
+	b	.L231
1472
+.L238:
1319
1473
 	.align	2
1320
-.L231:
1474
+.L237:
1321
1475
 	.word	.LANCHOR0
1322
1476
 	.word	100000
1323
1477
 	.fnend
1324
1478
 	.size	NandcWaitFlashReady, .-NandcWaitFlashReady
1325
1479
 	.align	2
1326
1480
 	.global	FlashReset
1481
+	.syntax unified
1482
+	.arm
1483
+	.fpu softvfp
1327
1484
 	.type	FlashReset, %function
1328
1485
 FlashReset:
1329
1486
 	.fnstart
1330
1487
 	@ args = 0, pretend = 0, frame = 0
1331
1488
 	@ frame_needed = 0, uses_anonymous_args = 0
1332
-	ldr	r3, .L235
1333
-	stmfd	sp!, {r4, r5, r6, lr}
1489
+	ldr	r3, .L241
1490
+	push	{r4, r5, r6, lr}
1334
1491
 	.save {r4, r5, r6, lr}
1335
-	add	r3, r3, r0, asl #3
1336
1492
 	mov	r4, r0
1337
-	ldrb	r6, [r3, #16]	@ zero_extendqisi2
1338
-	ldr	r5, [r3, #12]
1493
+	ldr	r5, [r3, r0, lsl #3]
1494
+	add	r3, r3, r0, lsl #3
1495
+	ldrb	r6, [r3, #4]	@ zero_extendqisi2
1339
1496
 	bl	NandcFlashCs
1340
1497
 	mov	r3, #255
1341
1498
 	mov	r0, r4
1342
-	add	r5, r5, r6, asl #8
1499
+	add	r5, r5, r6, lsl #8
1343
1500
 	str	r3, [r5, #2056]
1344
1501
 	bl	NandcWaitFlashReady
1345
1502
 	mov	r0, r4
1346
-	ldmfd	sp!, {r4, r5, r6, lr}
1503
+	pop	{r4, r5, r6, lr}
1347
1504
 	b	NandcFlashDeCs
1348
-.L236:
1505
+.L242:
1349
1506
 	.align	2
1350
-.L235:
1507
+.L241:
1351
1508
 	.word	.LANCHOR0
1352
1509
 	.fnend
1353
1510
 	.size	FlashReset, .-FlashReset
1354
1511
 	.align	2
1355
1512
 	.global	flash_enter_slc_mode
1513
+	.syntax unified
1514
+	.arm
1515
+	.fpu softvfp
1356
1516
 	.type	flash_enter_slc_mode, %function
1357
1517
 flash_enter_slc_mode:
1358
1518
 	.fnstart
1359
1519
 	@ args = 0, pretend = 0, frame = 0
1360
1520
 	@ frame_needed = 0, uses_anonymous_args = 0
1361
-	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
1521
+	push	{r4, r5, r6, r7, r8, lr}
1362
1522
 	.save {r4, r5, r6, r7, r8, lr}
1363
-	ldr	r5, .L244
1364
-	ldrb	r3, [r5, #144]	@ zero_extendqisi2
1523
+	ldr	r5, .L250
1524
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
1365
1525
 	cmp	r3, #0
1366
-	ldmeqfd	sp!, {r4, r5, r6, r7, r8, pc}
1526
+	popeq	{r4, r5, r6, r7, r8, pc}
1367
1527
 	mov	r6, r0
1368
1528
 	bl	NandcFlashCs
1369
-	add	r4, r5, r6, asl #3
1370
-	ldrb	r3, [r4, #2068]	@ zero_extendqisi2
1371
-	ldrb	r8, [r4, #16]	@ zero_extendqisi2
1529
+	add	r3, r5, r6, lsl #3
1530
+	ldr	r7, [r5, r6, lsl #3]
1531
+	ldrb	r8, [r3, #4]	@ zero_extendqisi2
1532
+	ldrb	r3, [r3, #2072]	@ zero_extendqisi2
1372
1533
 	cmp	r3, #44
1373
-	ldr	r7, [r4, #12]
1374
-	mov	r8, r8, asl #8
1375
-	bne	.L239
1534
+	lsl	r8, r8, #8
1535
+	bne	.L245
1376
1536
 	add	r4, r7, r8
1377
1537
 	mov	r3, #239
1378
-	mov	r0, #50
1379
1538
 	str	r3, [r4, #2056]
1380
1539
 	mov	r3, #145
1381
1540
 	str	r3, [r4, #2052]
1382
-	bl	NandcDelayns
1541
+	mov	r0, #50
1542
+	bl	ndelay
1383
1543
 	mov	r3, #0
1384
1544
 	mov	r2, #1
1385
1545
 	str	r3, [r4, #2048]
..
..
@@ -1387,53 +1547,56 @@
1387
1547
 	str	r2, [r4, #2048]
1388
1548
 	str	r3, [r4, #2048]
1389
1549
 	str	r3, [r4, #2048]
1390
-	bl	NandcDelayns
1391
-.L239:
1392
-	add	r7, r7, r8
1550
+	bl	ndelay
1551
+.L245:
1393
1552
 	mov	r0, r6
1553
+	add	r7, r7, r8
1394
1554
 	bl	NandcWaitFlashReadyNoDelay
1395
1555
 	mov	r3, #218
1396
1556
 	mov	r0, r6
1397
1557
 	str	r3, [r7, #2056]
1398
1558
 	bl	NandcWaitFlashReady
1399
1559
 	mov	r3, #2
1400
-	strb	r3, [r5, #2228]
1401
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
1402
-.L245:
1560
+	strb	r3, [r5, #2232]
1561
+	pop	{r4, r5, r6, r7, r8, pc}
1562
+.L251:
1403
1563
 	.align	2
1404
-.L244:
1564
+.L250:
1405
1565
 	.word	.LANCHOR0
1406
1566
 	.fnend
1407
1567
 	.size	flash_enter_slc_mode, .-flash_enter_slc_mode
1408
1568
 	.align	2
1409
1569
 	.global	flash_exit_slc_mode
1570
+	.syntax unified
1571
+	.arm
1572
+	.fpu softvfp
1410
1573
 	.type	flash_exit_slc_mode, %function
1411
1574
 flash_exit_slc_mode:
1412
1575
 	.fnstart
1413
1576
 	@ args = 0, pretend = 0, frame = 0
1414
1577
 	@ frame_needed = 0, uses_anonymous_args = 0
1415
-	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
1578
+	push	{r4, r5, r6, r7, r8, lr}
1416
1579
 	.save {r4, r5, r6, r7, r8, lr}
1417
-	ldr	r5, .L253
1418
-	ldrb	r3, [r5, #144]	@ zero_extendqisi2
1580
+	ldr	r5, .L259
1581
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
1419
1582
 	cmp	r3, #0
1420
-	ldmeqfd	sp!, {r4, r5, r6, r7, r8, pc}
1583
+	popeq	{r4, r5, r6, r7, r8, pc}
1421
1584
 	mov	r6, r0
1422
1585
 	bl	NandcFlashCs
1423
-	add	r4, r5, r6, asl #3
1424
-	ldrb	r3, [r4, #2068]	@ zero_extendqisi2
1425
-	ldrb	r8, [r4, #16]	@ zero_extendqisi2
1586
+	add	r3, r5, r6, lsl #3
1587
+	ldr	r7, [r5, r6, lsl #3]
1588
+	ldrb	r8, [r3, #4]	@ zero_extendqisi2
1589
+	ldrb	r3, [r3, #2072]	@ zero_extendqisi2
1426
1590
 	cmp	r3, #44
1427
-	ldr	r7, [r4, #12]
1428
-	mov	r8, r8, asl #8
1429
-	bne	.L248
1591
+	lsl	r8, r8, #8
1592
+	bne	.L254
1430
1593
 	add	r4, r7, r8
1431
1594
 	mov	r3, #239
1432
-	mov	r0, #50
1433
1595
 	str	r3, [r4, #2056]
1434
1596
 	mov	r3, #145
1435
1597
 	str	r3, [r4, #2052]
1436
-	bl	NandcDelayns
1598
+	mov	r0, #50
1599
+	bl	ndelay
1437
1600
 	mov	r3, #2
1438
1601
 	mov	r0, #100
1439
1602
 	str	r3, [r4, #2048]
..
..
@@ -1442,32 +1605,35 @@
1442
1605
 	mov	r3, #0
1443
1606
 	str	r3, [r4, #2048]
1444
1607
 	str	r3, [r4, #2048]
1445
-	bl	NandcDelayns
1446
-.L248:
1447
-	add	r7, r7, r8
1608
+	bl	ndelay
1609
+.L254:
1448
1610
 	mov	r0, r6
1611
+	add	r7, r7, r8
1449
1612
 	bl	NandcWaitFlashReadyNoDelay
1450
1613
 	mov	r3, #223
1451
1614
 	mov	r0, r6
1452
1615
 	str	r3, [r7, #2056]
1453
1616
 	bl	NandcWaitFlashReady
1454
1617
 	mov	r3, #0
1455
-	strb	r3, [r5, #2228]
1456
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
1457
-.L254:
1618
+	strb	r3, [r5, #2232]
1619
+	pop	{r4, r5, r6, r7, r8, pc}
1620
+.L260:
1458
1621
 	.align	2
1459
-.L253:
1622
+.L259:
1460
1623
 	.word	.LANCHOR0
1461
1624
 	.fnend
1462
1625
 	.size	flash_exit_slc_mode, .-flash_exit_slc_mode
1463
1626
 	.align	2
1464
1627
 	.global	FlashEraseBlock
1628
+	.syntax unified
1629
+	.arm
1630
+	.fpu softvfp
1465
1631
 	.type	FlashEraseBlock, %function
1466
1632
 FlashEraseBlock:
1467
1633
 	.fnstart
1468
1634
 	@ args = 0, pretend = 0, frame = 0
1469
1635
 	@ frame_needed = 0, uses_anonymous_args = 0
1470
-	stmfd	sp!, {r4, r5, r6, lr}
1636
+	push	{r4, r5, r6, lr}
1471
1637
 	.save {r4, r5, r6, lr}
1472
1638
 	mov	r4, r0
1473
1639
 	mov	r5, r1
..
..
@@ -1484,138 +1650,140 @@
1484
1650
 	mov	r1, r5
1485
1651
 	mov	r0, r4
1486
1652
 	bl	FlashReadStatus
1487
-	mov	r5, r0
1653
+	mov	r1, r0
1488
1654
 	mov	r0, r4
1489
1655
 	bl	NandcFlashDeCs
1490
-	and	r0, r5, #1
1491
-	ldmfd	sp!, {r4, r5, r6, pc}
1656
+	and	r0, r1, #1
1657
+	pop	{r4, r5, r6, pc}
1492
1658
 	.fnend
1493
1659
 	.size	FlashEraseBlock, .-FlashEraseBlock
1494
1660
 	.align	2
1495
1661
 	.global	FlashSetInterfaceMode
1662
+	.syntax unified
1663
+	.arm
1664
+	.fpu softvfp
1496
1665
 	.type	FlashSetInterfaceMode, %function
1497
1666
 FlashSetInterfaceMode:
1498
1667
 	.fnstart
1499
-	@ args = 0, pretend = 0, frame = 16
1668
+	@ args = 0, pretend = 0, frame = 8
1500
1669
 	@ frame_needed = 0, uses_anonymous_args = 0
1501
-	ldr	r1, .L280
1502
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
1670
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
1503
1671
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
1504
-	.pad #20
1505
-	sub	sp, sp, #20
1506
-	ldrb	fp, [r1, #2229]	@ zero_extendqisi2
1672
+	.pad #12
1507
1673
 	mov	lr, #0
1508
-	ldr	r7, .L280+4
1509
-	mov	r4, #239
1510
-	and	r2, fp, #4
1511
-	and	r3, fp, #1
1512
-	mov	r5, #128
1513
-	str	r3, [sp, #8]
1514
-	mov	r6, #1
1515
-	uxtb	r3, r2
1674
+	ldr	r4, .L286
1675
+	mov	r5, #239
1676
+	mov	r6, #128
1677
+	mov	r7, #1
1516
1678
 	mov	r8, #35
1517
-	mov	r2, lr
1518
1679
 	mov	r9, #32
1680
+	ldrb	r3, [r4, #2233]	@ zero_extendqisi2
1519
1681
 	mov	r10, #5
1520
-	str	r3, [sp, #4]
1521
-	add	r3, r1, #12
1522
-	str	r3, [sp, #12]
1523
-.L267:
1524
-	ldr	r3, [sp, #12]
1525
-	ldrb	ip, [lr, r7]	@ zero_extendqisi2
1526
-	ldr	r1, [r3, lr]!
1682
+	and	r2, r3, #4
1683
+	and	r3, r3, #1
1684
+	str	r2, [sp, #4]
1685
+	mov	r2, lr
1686
+	str	r3, [sp]
1687
+.L273:
1688
+	ldr	r1, .L286+4
1689
+	add	r3, r4, lr
1690
+	ldrb	r3, [r3, #4]	@ zero_extendqisi2
1691
+	ldrb	ip, [lr, r1]	@ zero_extendqisi2
1527
1692
 	cmp	ip, #69
1528
1693
 	cmpne	ip, #152
1529
-	ldrb	r3, [r3, #4]	@ zero_extendqisi2
1530
-	beq	.L258
1694
+	beq	.L264
1531
1695
 	cmp	ip, #44
1532
1696
 	cmpne	ip, #173
1533
-	bne	.L259
1534
-.L258:
1697
+	bne	.L265
1698
+.L264:
1535
1699
 	cmp	r0, #1
1536
-	bne	.L260
1537
-	ldr	fp, [sp, #8]
1700
+	ldr	r1, [r4, lr]
1701
+	bne	.L266
1702
+	ldr	fp, [sp]
1538
1703
 	cmp	fp, #0
1539
-	beq	.L259
1540
-	mov	r3, r3, asl #8
1704
+	beq	.L265
1705
+	lsl	r3, r3, #8
1541
1706
 	cmp	ip, #173
1542
1707
 	add	fp, r1, r3
1543
-	str	r4, [fp, #2056]
1708
+	str	r5, [fp, #2056]
1544
1709
 	streq	r0, [fp, #2052]
1545
-	beq	.L279
1710
+	beq	.L285
1546
1711
 	cmp	ip, #44
1547
1712
 	streq	r0, [fp, #2052]
1548
-	strne	r5, [fp, #2052]
1713
+	strne	r6, [fp, #2052]
1549
1714
 	streq	r10, [fp, #2048]
1550
1715
 	strne	r0, [fp, #2048]
1551
-	b	.L265
1552
-.L260:
1553
-	ldr	fp, [sp, #4]
1554
-	cmp	fp, #0
1555
-	beq	.L259
1556
-	mov	r3, r3, asl #8
1557
-	cmp	ip, #173
1558
-	add	fp, r1, r3
1559
-	str	r4, [fp, #2056]
1560
-	streq	r6, [fp, #2052]
1561
-	streq	r9, [fp, #2048]
1562
-	beq	.L265
1563
-	cmp	ip, #44
1564
-	streq	r6, [fp, #2052]
1565
-	streq	r8, [fp, #2048]
1566
-	beq	.L265
1567
-	str	r5, [fp, #2052]
1568
-.L279:
1569
-	str	r2, [fp, #2048]
1570
-.L265:
1716
+.L271:
1571
1717
 	add	r3, r1, r3
1572
1718
 	str	r2, [r3, #2048]
1573
1719
 	str	r2, [r3, #2048]
1574
1720
 	str	r2, [r3, #2048]
1575
-.L259:
1721
+.L265:
1576
1722
 	add	lr, lr, #8
1577
1723
 	cmp	lr, #32
1578
-	bne	.L267
1724
+	bne	.L273
1579
1725
 	mov	r0, #0
1580
1726
 	bl	NandcWaitFlashReady
1581
1727
 	mov	r0, #0
1582
-	add	sp, sp, #20
1728
+	add	sp, sp, #12
1583
1729
 	@ sp needed
1584
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
1585
-.L281:
1730
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
1731
+.L266:
1732
+	ldr	fp, [sp, #4]
1733
+	cmp	fp, #0
1734
+	beq	.L265
1735
+	lsl	r3, r3, #8
1736
+	cmp	ip, #173
1737
+	add	fp, r1, r3
1738
+	str	r5, [fp, #2056]
1739
+	streq	r7, [fp, #2052]
1740
+	streq	r9, [fp, #2048]
1741
+	beq	.L271
1742
+	cmp	ip, #44
1743
+	streq	r7, [fp, #2052]
1744
+	streq	r8, [fp, #2048]
1745
+	beq	.L271
1746
+	str	r6, [fp, #2052]
1747
+.L285:
1748
+	str	r2, [fp, #2048]
1749
+	b	.L271
1750
+.L287:
1586
1751
 	.align	2
1587
-.L280:
1752
+.L286:
1588
1753
 	.word	.LANCHOR0
1589
-	.word	.LANCHOR0+2068
1754
+	.word	.LANCHOR0+2072
1590
1755
 	.fnend
1591
1756
 	.size	FlashSetInterfaceMode, .-FlashSetInterfaceMode
1592
1757
 	.align	2
1593
1758
 	.global	FlashReadSpare
1759
+	.syntax unified
1760
+	.arm
1761
+	.fpu softvfp
1594
1762
 	.type	FlashReadSpare, %function
1595
1763
 FlashReadSpare:
1596
1764
 	.fnstart
1597
1765
 	@ args = 0, pretend = 0, frame = 0
1598
1766
 	@ frame_needed = 0, uses_anonymous_args = 0
1599
-	ldr	ip, .L284
1600
-	stmfd	sp!, {r3, r4, r5, lr}
1601
-	.save {r3, r4, r5, lr}
1602
-	add	ip, ip, r0, asl #3
1603
-	ldr	r3, .L284+4
1767
+	ldr	ip, .L290
1768
+	ldr	r3, .L290+4
1769
+	push	{r4, r5, r6, lr}
1770
+	.save {r4, r5, r6, lr}
1604
1771
 	mov	r5, r2
1605
-	ldrb	r2, [ip, #16]	@ zero_extendqisi2
1606
-	ldr	r4, [ip, #12]
1607
-	ldrb	r3, [r3, #481]	@ zero_extendqisi2
1608
-	add	r4, r4, r2, asl #8
1772
+	ldr	r4, [ip, r0, lsl #3]
1773
+	add	ip, ip, r0, lsl #3
1774
+	ldrb	r3, [r3, #477]	@ zero_extendqisi2
1775
+	ldrb	r2, [ip, #4]	@ zero_extendqisi2
1776
+	lsl	r3, r3, #9
1777
+	add	r4, r4, r2, lsl #8
1609
1778
 	mov	r2, #0
1610
-	mov	r3, r3, asl #9
1611
1779
 	str	r2, [r4, #2056]
1612
1780
 	str	r3, [r4, #2052]
1613
-	mov	r3, r3, lsr #8
1781
+	lsr	r3, r3, #8
1614
1782
 	str	r3, [r4, #2052]
1615
1783
 	uxtb	r3, r1
1616
1784
 	str	r3, [r4, #2052]
1617
-	mov	r3, r1, lsr #8
1618
-	mov	r1, r1, lsr #16
1785
+	lsr	r3, r1, #8
1786
+	lsr	r1, r1, #16
1619
1787
 	str	r3, [r4, #2052]
1620
1788
 	mov	r3, #48
1621
1789
 	str	r1, [r4, #2052]
..
..
@@ -1623,28 +1791,31 @@
1623
1791
 	bl	NandcWaitFlashReady
1624
1792
 	ldr	r3, [r4, #2048]
1625
1793
 	strb	r3, [r5]
1626
-	ldmfd	sp!, {r3, r4, r5, pc}
1627
-.L285:
1794
+	pop	{r4, r5, r6, pc}
1795
+.L291:
1628
1796
 	.align	2
1629
-.L284:
1797
+.L290:
1630
1798
 	.word	.LANCHOR0
1631
1799
 	.word	.LANCHOR1
1632
1800
 	.fnend
1633
1801
 	.size	FlashReadSpare, .-FlashReadSpare
1634
1802
 	.align	2
1635
1803
 	.global	SandiskProgTestBadBlock
1804
+	.syntax unified
1805
+	.arm
1806
+	.fpu softvfp
1636
1807
 	.type	SandiskProgTestBadBlock, %function
1637
1808
 SandiskProgTestBadBlock:
1638
1809
 	.fnstart
1639
1810
 	@ args = 0, pretend = 0, frame = 0
1640
1811
 	@ frame_needed = 0, uses_anonymous_args = 0
1641
-	ldr	r2, .L288
1642
-	stmfd	sp!, {r4, lr}
1812
+	ldr	r3, .L294
1813
+	push	{r4, lr}
1643
1814
 	.save {r4, lr}
1644
-	add	r2, r2, r0, asl #3
1645
-	ldrb	r4, [r2, #16]	@ zero_extendqisi2
1646
-	ldr	r3, [r2, #12]
1647
-	add	r4, r3, r4, asl #8
1815
+	ldr	r4, [r3, r0, lsl #3]
1816
+	add	r3, r3, r0, lsl #3
1817
+	ldrb	r3, [r3, #4]	@ zero_extendqisi2
1818
+	add	r4, r4, r3, lsl #8
1648
1819
 	mov	r3, #162
1649
1820
 	str	r3, [r4, #2056]
1650
1821
 	mov	r3, #128
..
..
@@ -1654,163 +1825,177 @@
1654
1825
 	str	r3, [r4, #2052]
1655
1826
 	uxtb	r3, r1
1656
1827
 	str	r3, [r4, #2052]
1657
-	mov	r3, r1, lsr #8
1658
-	mov	r1, r1, lsr #16
1828
+	lsr	r3, r1, #8
1829
+	lsr	r1, r1, #16
1659
1830
 	str	r3, [r4, #2052]
1660
-	str	r1, [r4, #2052]
1661
1831
 	mov	r3, #16
1832
+	str	r1, [r4, #2052]
1662
1833
 	str	r3, [r4, #2056]
1663
1834
 	bl	NandcWaitFlashReady
1664
1835
 	mov	r3, #112
1665
1836
 	mov	r0, #80
1666
1837
 	str	r3, [r4, #2056]
1667
-	bl	NandcDelayns
1838
+	bl	ndelay
1668
1839
 	ldr	r0, [r4, #2048]
1669
1840
 	and	r0, r0, #1
1670
-	ldmfd	sp!, {r4, pc}
1671
-.L289:
1841
+	pop	{r4, pc}
1842
+.L295:
1672
1843
 	.align	2
1673
-.L288:
1844
+.L294:
1674
1845
 	.word	.LANCHOR0
1675
1846
 	.fnend
1676
1847
 	.size	SandiskProgTestBadBlock, .-SandiskProgTestBadBlock
1677
1848
 	.align	2
1678
1849
 	.global	SandiskSetRRPara
1850
+	.syntax unified
1851
+	.arm
1852
+	.fpu softvfp
1679
1853
 	.type	SandiskSetRRPara, %function
1680
1854
 SandiskSetRRPara:
1681
1855
 	.fnstart
1682
1856
 	@ args = 0, pretend = 0, frame = 0
1683
1857
 	@ frame_needed = 0, uses_anonymous_args = 0
1684
-	stmfd	sp!, {r3, r4, r5, lr}
1685
-	.save {r3, r4, r5, lr}
1686
1858
 	mov	r3, #239
1687
-	mov	r5, r0
1859
+	push	{r4, r5, r6, lr}
1860
+	.save {r4, r5, r6, lr}
1688
1861
 	str	r3, [r0, #8]
1689
1862
 	mov	r3, #17
1863
+	mov	r5, r0
1864
+	mov	r4, r1
1690
1865
 	str	r3, [r0, #4]
1691
1866
 	mov	r0, #200
1692
-	mov	r4, r1
1693
-	bl	NandcDelayns
1694
-	ldr	r0, .L298
1695
-	ldr	r1, .L298+4
1696
-	add	r4, r4, r4, asl #2
1697
-	sub	ip, r0, #48
1867
+	bl	ndelay
1868
+	ldr	r0, .L303
1869
+	add	r4, r4, r4, lsl #2
1870
+	ldr	r1, .L303+4
1698
1871
 	mov	r2, #0
1699
-.L291:
1700
-	ldrb	r3, [r1, #1209]	@ zero_extendqisi2
1872
+	sub	ip, r0, #45
1873
+.L297:
1874
+	ldrb	r3, [r1, #85]	@ zero_extendqisi2
1701
1875
 	cmp	r2, r3
1702
-	bcs	.L297
1703
-	ldrb	r3, [r1, #1208]	@ zero_extendqisi2
1876
+	bcc	.L300
1877
+	mov	r0, #0
1878
+	pop	{r4, r5, r6, lr}
1879
+	b	NandcWaitFlashReady
1880
+.L300:
1881
+	ldrb	r3, [r1, #84]	@ zero_extendqisi2
1704
1882
 	cmp	r3, #67
1705
1883
 	add	r3, r2, r4
1706
1884
 	addeq	r3, ip, r3
1707
1885
 	addne	r3, r0, r3
1708
-	add	r2, r2, #1
1709
1886
 	ldrsb	r3, [r3, #5]
1887
+	add	r2, r2, #1
1710
1888
 	str	r3, [r5]
1711
-	b	.L291
1712
-.L297:
1713
-	mov	r0, #0
1714
-	ldmfd	sp!, {r3, r4, r5, lr}
1715
-	b	NandcWaitFlashReady
1716
-.L299:
1889
+	b	.L297
1890
+.L304:
1717
1891
 	.align	2
1718
-.L298:
1719
-	.word	.LANCHOR1+304
1892
+.L303:
1893
+	.word	.LANCHOR1+301
1720
1894
 	.word	.LANCHOR0
1721
1895
 	.fnend
1722
1896
 	.size	SandiskSetRRPara, .-SandiskSetRRPara
1723
1897
 	.align	2
1724
1898
 	.global	micron_auto_read_calibration_config
1899
+	.syntax unified
1900
+	.arm
1901
+	.fpu softvfp
1725
1902
 	.type	micron_auto_read_calibration_config, %function
1726
1903
 micron_auto_read_calibration_config:
1727
1904
 	.fnstart
1728
1905
 	@ args = 0, pretend = 0, frame = 0
1729
1906
 	@ frame_needed = 0, uses_anonymous_args = 0
1730
-	stmfd	sp!, {r3, r4, r5, lr}
1731
-	.save {r3, r4, r5, lr}
1732
-	mov	r4, r0
1733
-	mov	r5, r1
1907
+	push	{r4, r5, r6, lr}
1908
+	.save {r4, r5, r6, lr}
1909
+	mov	r5, r0
1910
+	mov	r6, r1
1734
1911
 	bl	NandcWaitFlashReady
1735
-	ldr	r3, .L302
1912
+	ldr	r0, .L307
1913
+	ldr	r4, [r0, r5, lsl #3]
1914
+	add	r0, r0, r5, lsl #3
1915
+	ldrb	r3, [r0, #4]	@ zero_extendqisi2
1736
1916
 	mov	r0, #200
1737
-	add	r2, r3, r4, asl #3
1738
-	ldrb	r4, [r2, #16]	@ zero_extendqisi2
1739
-	ldr	r3, [r2, #12]
1740
-	add	r4, r3, r4, asl #8
1917
+	add	r4, r4, r3, lsl #8
1741
1918
 	mov	r3, #239
1742
1919
 	str	r3, [r4, #2056]
1743
1920
 	mov	r3, #150
1744
1921
 	str	r3, [r4, #2052]
1745
-	bl	NandcDelayns
1746
-	str	r5, [r4, #2048]
1922
+	bl	ndelay
1747
1923
 	mov	r3, #0
1924
+	str	r6, [r4, #2048]
1748
1925
 	str	r3, [r4, #2048]
1749
1926
 	str	r3, [r4, #2048]
1750
1927
 	str	r3, [r4, #2048]
1751
-	ldmfd	sp!, {r3, r4, r5, pc}
1752
-.L303:
1928
+	pop	{r4, r5, r6, pc}
1929
+.L308:
1753
1930
 	.align	2
1754
-.L302:
1931
+.L307:
1755
1932
 	.word	.LANCHOR0
1756
1933
 	.fnend
1757
1934
 	.size	micron_auto_read_calibration_config, .-micron_auto_read_calibration_config
1758
1935
 	.align	2
1759
1936
 	.global	FlashEraseSLc2KBlocks
1937
+	.syntax unified
1938
+	.arm
1939
+	.fpu softvfp
1760
1940
 	.type	FlashEraseSLc2KBlocks, %function
1761
1941
 FlashEraseSLc2KBlocks:
1762
1942
 	.fnstart
1763
1943
 	@ args = 0, pretend = 0, frame = 8
1764
1944
 	@ frame_needed = 0, uses_anonymous_args = 0
1765
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, lr}
1766
-	.save {r4, r5, r6, r7, r8, r9, lr}
1945
+	push	{r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, lr}
1946
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
1947
+	.pad #16
1767
1948
 	mov	r5, #0
1768
-	ldr	r8, .L316
1769
-	.pad #20
1770
-	sub	sp, sp, #20
1949
+	ldr	r8, .L320
1771
1950
 	mov	r6, r0
1772
1951
 	mov	r9, r1
1773
1952
 	mov	r7, r5
1774
-.L305:
1953
+	ldr	r10, .L320+4
1954
+.L310:
1775
1955
 	cmp	r7, r9
1776
-	beq	.L315
1777
-	rsb	r3, r7, r9
1956
+	bne	.L315
1957
+	mov	r0, #0
1958
+	add	sp, sp, #16
1959
+	@ sp needed
1960
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
1961
+.L315:
1962
+	sub	r3, r9, r7
1778
1963
 	add	r2, sp, #8
1779
-	add	r0, r6, r5
1780
-	mov	r1, #0
1781
1964
 	uxtb	r3, r3
1965
+	mov	r1, #0
1966
+	add	r0, r6, r5
1782
1967
 	str	r3, [sp]
1783
1968
 	add	r3, sp, #12
1784
1969
 	bl	LogAddr2PhyAddr
1785
-	ldrb	r2, [r8, #2230]	@ zero_extendqisi2
1970
+	ldrb	r2, [r8, #2234]	@ zero_extendqisi2
1786
1971
 	ldr	r3, [sp, #12]
1787
-	cmp	r3, r2
1788
-	mvncs	r3, #0
1789
-	strcs	r3, [r6, r5]
1790
-	bcs	.L307
1972
+	cmp	r2, r3
1973
+	mvnls	r3, #0
1974
+	strls	r3, [r6, r5]
1975
+	bls	.L312
1791
1976
 	add	r2, r8, r3
1792
-	add	r3, r8, r3, asl #4
1793
-	ldrb	r4, [r2, #2232]	@ zero_extendqisi2
1794
-	strb	r4, [r3, #2100]
1977
+	add	r3, r8, r3, lsl #4
1978
+	ldrb	r4, [r2, #2236]	@ zero_extendqisi2
1979
+	strb	r4, [r3, #2104]
1795
1980
 	mov	r0, r4
1796
1981
 	bl	NandcWaitFlashReady
1797
1982
 	mov	r0, r4
1798
1983
 	bl	NandcFlashCs
1799
1984
 	mov	r2, #0
1800
-	mov	r0, r4
1801
1985
 	ldr	r1, [sp, #8]
1986
+	mov	r0, r4
1802
1987
 	bl	FlashEraseCmd
1803
1988
 	mov	r0, r4
1804
1989
 	bl	NandcWaitFlashReady
1805
1990
 	mov	r0, r4
1806
1991
 	ldr	r1, [sp, #8]
1807
1992
 	bl	FlashReadStatus
1808
-	mov	r2, #0
1809
-	ldr	r3, [sp, #8]
1810
1993
 	sbfx	r0, r0, #0, #1
1994
+	ldr	r1, [sp, #8]
1811
1995
 	str	r0, [r6, r5]
1996
+	mov	r2, #0
1997
+	ldr	r3, [r8, #40]
1812
1998
 	mov	r0, r4
1813
-	ldr	r1, [r8, #4]
1814
1999
 	add	r1, r1, r3
1815
2000
 	bl	FlashEraseCmd
1816
2001
 	mov	r0, r4
..
..
@@ -1823,249 +2008,244 @@
1823
2008
 	strne	r3, [r6, r5]
1824
2009
 	ldr	r3, [r6, r5]
1825
2010
 	cmn	r3, #1
1826
-	bne	.L309
1827
-	ldr	r0, .L316+4
2011
+	bne	.L314
1828
2012
 	ldr	r1, [sp, #8]
2013
+	mov	r0, r10
1829
2014
 	bl	printk
1830
-.L309:
2015
+.L314:
1831
2016
 	mov	r0, r4
1832
2017
 	bl	NandcFlashDeCs
1833
-.L307:
2018
+.L312:
1834
2019
 	add	r7, r7, #1
1835
2020
 	add	r5, r5, #36
1836
-	b	.L305
1837
-.L315:
1838
-	mov	r0, #0
1839
-	add	sp, sp, #20
1840
-	@ sp needed
1841
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, pc}
1842
-.L317:
2021
+	b	.L310
2022
+.L321:
1843
2023
 	.align	2
1844
-.L316:
2024
+.L320:
1845
2025
 	.word	.LANCHOR0
1846
2026
 	.word	.LC1
1847
2027
 	.fnend
1848
2028
 	.size	FlashEraseSLc2KBlocks, .-FlashEraseSLc2KBlocks
1849
2029
 	.align	2
1850
2030
 	.global	FlashEraseBlocks
2031
+	.syntax unified
2032
+	.arm
2033
+	.fpu softvfp
1851
2034
 	.type	FlashEraseBlocks, %function
1852
2035
 FlashEraseBlocks:
1853
2036
 	.fnstart
1854
-	@ args = 0, pretend = 0, frame = 16
2037
+	@ args = 0, pretend = 0, frame = 8
1855
2038
 	@ frame_needed = 0, uses_anonymous_args = 0
1856
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2039
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
1857
2040
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
1858
2041
 	mov	r8, r2
1859
-	ldr	r4, .L354
1860
-	.pad #28
1861
-	sub	sp, sp, #28
1862
-	ldrb	r5, [r4]	@ zero_extendqisi2
2042
+	ldr	r4, .L355
2043
+	.pad #20
2044
+	sub	sp, sp, #20
2045
+	ldrb	r5, [r4, #36]	@ zero_extendqisi2
1863
2046
 	cmp	r5, #0
1864
2047
 	moveq	r9, r0
1865
2048
 	moveq	r10, r1
1866
-	moveq	fp, r4
1867
-	beq	.L319
2049
+	beq	.L324
1868
2050
 	mov	r1, r2
1869
2051
 	bl	FlashEraseSLc2KBlocks
1870
-	b	.L320
1871
-.L328:
1872
-	mov	r3, #36
1873
-	mov	r1, #0
1874
-	mul	r6, r3, r5
1875
-	add	r2, sp, #16
1876
-	add	r3, r9, r6
1877
-	str	r3, [sp, #12]
1878
-	rsb	r3, r5, r8
1879
-	ldr	r0, [sp, #12]
1880
-	uxtb	r3, r3
1881
-	str	r3, [sp]
1882
-	add	r3, sp, #20
1883
-	bl	LogAddr2PhyAddr
1884
-	ldrb	r3, [r4, #2230]	@ zero_extendqisi2
1885
-	mov	r7, r0
1886
-	ldr	r0, [sp, #20]
1887
-	cmp	r0, r3
1888
-	mvncs	r3, #0
1889
-	strcs	r3, [r9, r6]
1890
-	bcc	.L351
1891
2052
 .L322:
1892
-	add	r5, r5, #1
1893
-.L319:
1894
-	cmp	r5, r8
1895
-	bcc	.L328
1896
-	b	.L352
1897
-.L351:
1898
-	ldrb	r3, [fp, #2240]	@ zero_extendqisi2
2053
+	add	sp, sp, #20
2054
+	@ sp needed
2055
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
2056
+.L333:
2057
+	mov	r3, #36
2058
+	add	r2, sp, #8
2059
+	mul	r6, r3, r5
2060
+	sub	r3, r8, r5
2061
+	uxtb	r3, r3
2062
+	mov	r1, #0
2063
+	str	r3, [sp]
2064
+	add	r3, sp, #12
2065
+	add	fp, r9, r6
2066
+	mov	r0, fp
2067
+	bl	LogAddr2PhyAddr
2068
+	ldrb	r3, [r4, #2234]	@ zero_extendqisi2
2069
+	mov	r7, r0
2070
+	ldr	r0, [sp, #12]
2071
+	cmp	r3, r0
2072
+	mvnls	r3, #0
2073
+	strls	r3, [r9, r6]
2074
+	bls	.L327
2075
+	ldrb	r3, [r4, #2244]	@ zero_extendqisi2
1899
2076
 	cmp	r3, #0
1900
-	add	r3, r4, r0, asl #4
1901
-	ldr	r3, [r3, #2108]
2077
+	add	r3, r4, r0, lsl #4
1902
2078
 	moveq	r7, #0
2079
+	ldr	r3, [r3, #2112]
1903
2080
 	cmp	r3, #0
1904
-	beq	.L324
2081
+	beq	.L329
1905
2082
 	uxtb	r0, r0
1906
2083
 	bl	FlashWaitCmdDone
1907
-.L324:
1908
-	ldr	r2, [sp, #20]
2084
+.L329:
2085
+	ldr	r2, [sp, #12]
1909
2086
 	cmp	r7, #0
1910
-	ldr	r0, [sp, #12]
1911
-	addne	ip, r6, #36
1912
-	addne	ip, r9, ip
1913
-	mov	r3, r2, asl #4
2087
+	addne	r6, r6, #36
2088
+	mov	r0, #0
2089
+	addne	r6, r9, r6
2090
+	lsl	r3, r2, #4
1914
2091
 	add	r2, r4, r2
1915
2092
 	add	r1, r4, r3
1916
2093
 	add	r3, r4, r3
1917
-	ldrb	r6, [r2, #2232]	@ zero_extendqisi2
2094
+	str	r0, [r1, #2116]
2095
+	ldr	r0, [sp, #8]
2096
+	strne	r6, [r1, #2116]
2097
+	ldrb	r6, [r2, #2236]	@ zero_extendqisi2
1918
2098
 	str	r0, [r1, #2108]
1919
-	mov	r0, #0
1920
-	str	r0, [r1, #2112]
1921
-	ldr	r0, [sp, #16]
1922
-	strne	ip, [r1, #2112]
1923
-	strb	r6, [r3, #2100]
1924
-	str	r0, [r1, #2104]
2099
+	str	fp, [r1, #2112]
1925
2100
 	mov	r0, r6
2101
+	strb	r6, [r3, #2104]
1926
2102
 	bl	NandcFlashCs
1927
2103
 	cmp	r10, #1
1928
2104
 	mov	r0, r6
1929
-	bne	.L326
1930
-	ldrb	r3, [fp, #144]	@ zero_extendqisi2
2105
+	bne	.L331
2106
+	ldrb	r3, [r4, #152]	@ zero_extendqisi2
1931
2107
 	cmp	r3, #0
1932
-	beq	.L326
2108
+	beq	.L331
1933
2109
 	bl	flash_enter_slc_mode
1934
-	b	.L327
1935
-.L326:
1936
-	bl	flash_exit_slc_mode
1937
-.L327:
1938
-	ldr	r3, [sp, #20]
2110
+.L332:
2111
+	ldr	r3, [sp, #12]
1939
2112
 	mov	r0, r6
1940
-	ldr	r1, [sp, #16]
2113
+	ldr	r1, [sp, #8]
1941
2114
 	add	r5, r5, r7
1942
-	add	r3, r4, r3, asl #2
1943
-	ldr	r2, [r3, #1172]
2115
+	add	r3, r4, r3, lsl #2
2116
+	ldr	r2, [r3, #1180]
1944
2117
 	adds	r2, r2, #0
1945
2118
 	movne	r2, #1
1946
2119
 	bl	FlashWaitReadyEN
1947
-	mov	r0, r6
1948
2120
 	mov	r2, r7
1949
-	ldr	r1, [sp, #16]
2121
+	ldr	r1, [sp, #8]
2122
+	mov	r0, r6
1950
2123
 	bl	FlashEraseCmd
1951
2124
 	mov	r0, r6
1952
2125
 	bl	NandcFlashDeCs
1953
-	b	.L322
1954
-.L352:
1955
-	ldr	r6, .L354
2126
+.L327:
2127
+	add	r5, r5, #1
2128
+.L324:
2129
+	cmp	r5, r8
2130
+	bcc	.L333
2131
+	ldr	r6, .L355+4
1956
2132
 	mov	r5, #0
1957
-	ldr	r7, .L354+4
1958
-.L329:
1959
-	ldrb	r2, [r4, #2230]	@ zero_extendqisi2
1960
-	ldr	r3, .L354
1961
-	cmp	r5, r2
1962
-	bcs	.L353
2133
+.L334:
2134
+	ldrb	r3, [r4, #2234]	@ zero_extendqisi2
2135
+	cmp	r5, r3
2136
+	bcc	.L336
2137
+	ldr	r3, [r4, #2248]
2138
+	cmp	r3, #0
2139
+	bne	.L337
2140
+.L338:
2141
+	mov	r0, #0
2142
+	b	.L322
2143
+.L331:
2144
+	bl	flash_exit_slc_mode
2145
+	b	.L332
2146
+.L336:
1963
2147
 	uxtb	r0, r5
1964
2148
 	bl	FlashWaitCmdDone
1965
2149
 	cmp	r10, #1
1966
-	bne	.L330
1967
-	ldrb	r3, [r6, #144]	@ zero_extendqisi2
2150
+	bne	.L335
2151
+	ldrb	r3, [r4, #152]	@ zero_extendqisi2
1968
2152
 	cmp	r3, #0
1969
-	beq	.L330
1970
-	ldrb	r0, [r7, r5, asl #4]	@ zero_extendqisi2
2153
+	beq	.L335
2154
+	ldrb	r0, [r6, r5, lsl #4]	@ zero_extendqisi2
1971
2155
 	bl	flash_exit_slc_mode
1972
-.L330:
2156
+.L335:
1973
2157
 	add	r5, r5, #1
1974
-	b	.L329
1975
-.L353:
1976
-	ldr	r2, [r3, #2244]
1977
-	cmp	r2, #0
1978
-	bne	.L332
1979
-.L334:
1980
-	mov	r0, #0
1981
-	b	.L320
1982
-.L332:
1983
-	ldrb	r3, [r3, #2068]	@ zero_extendqisi2
2158
+	b	.L334
2159
+.L337:
2160
+	ldrb	r3, [r4, #2072]	@ zero_extendqisi2
1984
2161
 	cmp	r3, #69
1985
-	bne	.L334
1986
-	mov	r3, #0
1987
-	mov	r2, #36
1988
-	mov	r1, r3
1989
-.L333:
2162
+	moveq	r3, #0
2163
+	moveq	r2, #36
2164
+	moveq	r1, r3
2165
+	bne	.L338
2166
+.L339:
1990
2167
 	cmp	r3, r8
1991
-	beq	.L334
2168
+	beq	.L338
1992
2169
 	mul	r0, r2, r3
1993
2170
 	add	r3, r3, #1
1994
2171
 	str	r1, [r9, r0]
1995
-	b	.L333
1996
-.L320:
1997
-	add	sp, sp, #28
1998
-	@ sp needed
1999
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
2000
-.L355:
2172
+	b	.L339
2173
+.L356:
2001
2174
 	.align	2
2002
-.L354:
2175
+.L355:
2003
2176
 	.word	.LANCHOR0
2004
-	.word	.LANCHOR0+2100
2177
+	.word	.LANCHOR0+2104
2005
2178
 	.fnend
2006
2179
 	.size	FlashEraseBlocks, .-FlashEraseBlocks
2007
2180
 	.align	2
2008
2181
 	.global	FlashReadDpCmd
2182
+	.syntax unified
2183
+	.arm
2184
+	.fpu softvfp
2009
2185
 	.type	FlashReadDpCmd, %function
2010
2186
 FlashReadDpCmd:
2011
2187
 	.fnstart
2012
2188
 	@ args = 0, pretend = 0, frame = 0
2013
2189
 	@ frame_needed = 0, uses_anonymous_args = 0
2014
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
2190
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
2015
2191
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
2016
-	mov	r8, r0
2017
-	ldr	r0, .L362
2018
-	mov	r7, r1
2192
+	mov	r7, r0
2193
+	ldr	r0, .L363
2194
+	mov	r8, r1
2019
2195
 	uxtb	r10, r2
2020
-	mov	r9, r2, lsr #8
2021
-	add	r3, r0, r8, asl #3
2022
-	mov	r5, r2, lsr #16
2023
-	ldrb	r1, [r0, #64]	@ zero_extendqisi2
2024
-	uxtb	lr, r7
2025
-	ldr	r4, [r3, #12]
2026
-	mov	ip, r7, lsr #8
2027
-	ldrb	r3, [r3, #16]	@ zero_extendqisi2
2028
-	cmp	r1, #1
2029
-	ldr	r2, [r0, #44]
2030
-	mov	r1, r7, lsr #16
2031
-	mov	r3, r3, asl #8
2196
+	lsr	r9, r2, #8
2197
+	lsr	r6, r2, #16
2198
+	uxtb	lr, r8
2199
+	ldr	r2, [r0, #48]
2200
+	lsr	ip, r8, #8
2201
+	add	r1, r0, r7, lsl #3
2202
+	ldr	r3, [r0, r7, lsl #3]
2203
+	ldrb	r4, [r1, #4]	@ zero_extendqisi2
2204
+	ldrb	r1, [r0, #68]	@ zero_extendqisi2
2032
2205
 	ldrb	r2, [r2, #7]	@ zero_extendqisi2
2033
-	bne	.L357
2206
+	cmp	r1, #1
2207
+	lsl	r4, r4, #8
2208
+	lsr	r1, r8, #16
2209
+	bne	.L358
2034
2210
 	cmp	r2, #1
2035
-	addeq	r2, r4, r3
2036
-	add	r4, r4, r3
2037
-	moveq	r6, #38
2038
-	streq	r6, [r2, #2056]
2039
-	mov	r6, #0
2040
-	ldrb	r3, [r0, #57]	@ zero_extendqisi2
2041
-	ldrb	r2, [r0, #56]	@ zero_extendqisi2
2042
-	mov	r0, r8
2211
+	addeq	r2, r3, r4
2212
+	moveq	r5, #38
2213
+	add	r4, r3, r4
2214
+	streq	r5, [r2, #2056]
2215
+	ldrb	r3, [r0, #61]	@ zero_extendqisi2
2216
+	mov	r5, #0
2217
+	ldrb	r2, [r0, #60]	@ zero_extendqisi2
2218
+	mov	r0, r7
2043
2219
 	str	r2, [r4, #2056]
2044
-	str	r6, [r4, #2052]
2045
-	str	r6, [r4, #2052]
2220
+	str	r5, [r4, #2052]
2221
+	str	r5, [r4, #2052]
2046
2222
 	str	lr, [r4, #2052]
2047
2223
 	str	ip, [r4, #2052]
2048
2224
 	str	r1, [r4, #2052]
2049
2225
 	str	r3, [r4, #2056]
2050
2226
 	bl	NandcWaitFlashReady
2051
-	str	r6, [r4, #2056]
2052
2227
 	mov	r3, #48
2053
-	str	r6, [r4, #2052]
2054
-	str	r6, [r4, #2052]
2228
+	str	r5, [r4, #2056]
2229
+	str	r5, [r4, #2052]
2230
+	str	r5, [r4, #2052]
2055
2231
 	str	r10, [r4, #2052]
2056
2232
 	str	r9, [r4, #2052]
2057
-	str	r5, [r4, #2052]
2233
+	str	r6, [r4, #2052]
2058
2234
 	str	r3, [r4, #2056]
2059
-	b	.L359
2060
-.L357:
2235
+.L360:
2236
+	mov	r1, r8
2237
+	mov	r0, r7
2238
+	pop	{r4, r5, r6, r7, r8, r9, r10, lr}
2239
+	b	FlashSetRandomizer
2240
+.L358:
2061
2241
 	cmp	r2, #1
2062
-	addeq	r2, r4, r3
2063
-	add	r3, r4, r3
2064
-	moveq	r6, #38
2065
-	streq	r6, [r2, #2056]
2066
-	ldrb	r2, [r0, #56]	@ zero_extendqisi2
2242
+	addeq	r2, r3, r4
2243
+	moveq	r5, #38
2244
+	streq	r5, [r2, #2056]
2245
+	add	r3, r3, r4
2246
+	ldrb	r2, [r0, #60]	@ zero_extendqisi2
2067
2247
 	str	r2, [r3, #2056]
2068
-	ldrb	r2, [r0, #57]	@ zero_extendqisi2
2248
+	ldrb	r2, [r0, #61]	@ zero_extendqisi2
2069
2249
 	str	lr, [r3, #2052]
2070
2250
 	str	ip, [r3, #2052]
2071
2251
 	str	r1, [r3, #2052]
..
..
@@ -2073,132 +2253,140 @@
2073
2253
 	mov	r2, #48
2074
2254
 	str	r10, [r3, #2052]
2075
2255
 	str	r9, [r3, #2052]
2076
-	str	r5, [r3, #2052]
2256
+	str	r6, [r3, #2052]
2077
2257
 	str	r2, [r3, #2056]
2078
-.L359:
2079
-	mov	r0, r8
2080
-	mov	r1, r7
2081
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
2082
-	b	FlashSetRandomizer
2083
-.L363:
2258
+	b	.L360
2259
+.L364:
2084
2260
 	.align	2
2085
-.L362:
2261
+.L363:
2086
2262
 	.word	.LANCHOR0
2087
2263
 	.fnend
2088
2264
 	.size	FlashReadDpCmd, .-FlashReadDpCmd
2089
2265
 	.align	2
2090
2266
 	.global	ftl_flash_de_init
2267
+	.syntax unified
2268
+	.arm
2269
+	.fpu softvfp
2091
2270
 	.type	ftl_flash_de_init, %function
2092
2271
 ftl_flash_de_init:
2093
2272
 	.fnstart
2094
2273
 	@ args = 0, pretend = 0, frame = 0
2095
2274
 	@ frame_needed = 0, uses_anonymous_args = 0
2096
-	stmfd	sp!, {r3, r4, r5, lr}
2097
-	.save {r3, r4, r5, lr}
2275
+	push	{r4, lr}
2276
+	.save {r4, lr}
2098
2277
 	mov	r0, #0
2099
-	ldr	r4, .L375
2278
+	ldr	r4, .L376
2100
2279
 	bl	NandcWaitFlashReady
2101
2280
 	bl	FlashSetReadRetryDefault
2102
-	ldr	r0, [r4, #2248]
2281
+	ldr	r0, [r4, #2252]
2103
2282
 	cmp	r0, #0
2104
-	beq	.L365
2283
+	beq	.L366
2105
2284
 	mov	r0, #0
2106
2285
 	bl	flash_enter_slc_mode
2107
-	b	.L366
2108
-.L365:
2109
-	bl	flash_exit_slc_mode
2110
-.L366:
2111
-	ldrb	r3, [r4, #2252]	@ zero_extendqisi2
2112
-	ldr	r5, .L375
2286
+.L367:
2287
+	ldrb	r3, [r4, #2256]	@ zero_extendqisi2
2113
2288
 	cmp	r3, #0
2114
-	beq	.L367
2115
-	ldrb	r3, [r5, #2229]	@ zero_extendqisi2
2289
+	beq	.L368
2290
+	ldrb	r3, [r4, #2233]	@ zero_extendqisi2
2116
2291
 	tst	r3, #1
2117
-	beq	.L367
2292
+	beq	.L368
2118
2293
 	mov	r0, #1
2119
2294
 	bl	FlashSetInterfaceMode
2120
2295
 	mov	r0, #1
2121
2296
 	bl	NandcSetMode
2122
2297
 	mov	r3, #0
2123
-	strb	r3, [r5, #2252]
2124
-.L367:
2125
-	ldr	r3, [r4, #12]
2298
+	strb	r3, [r4, #2256]
2299
+.L368:
2300
+	ldr	r3, [r4]
2126
2301
 	mov	r0, #0
2127
2302
 	str	r0, [r3, #336]
2128
-	ldmfd	sp!, {r3, r4, r5, pc}
2129
-.L376:
2303
+	pop	{r4, pc}
2304
+.L366:
2305
+	bl	flash_exit_slc_mode
2306
+	b	.L367
2307
+.L377:
2130
2308
 	.align	2
2131
-.L375:
2309
+.L376:
2132
2310
 	.word	.LANCHOR0
2133
2311
 	.fnend
2134
2312
 	.size	ftl_flash_de_init, .-ftl_flash_de_init
2135
2313
 	.align	2
2136
2314
 	.global	NandcRandmzSel
2315
+	.syntax unified
2316
+	.arm
2317
+	.fpu softvfp
2137
2318
 	.type	NandcRandmzSel, %function
2138
2319
 NandcRandmzSel:
2139
2320
 	.fnstart
2140
2321
 	@ args = 0, pretend = 0, frame = 0
2141
2322
 	@ frame_needed = 0, uses_anonymous_args = 0
2142
2323
 	@ link register save eliminated.
2143
-	ldr	r3, .L378
2144
-	add	r0, r3, r0, asl #3
2145
-	ldr	r3, [r0, #12]
2324
+	ldr	r3, .L379
2325
+	ldr	r3, [r3, r0, lsl #3]
2146
2326
 	str	r1, [r3, #336]
2147
2327
 	bx	lr
2148
-.L379:
2328
+.L380:
2149
2329
 	.align	2
2150
-.L378:
2330
+.L379:
2151
2331
 	.word	.LANCHOR0
2152
2332
 	.fnend
2153
2333
 	.size	NandcRandmzSel, .-NandcRandmzSel
2154
2334
 	.global	__aeabi_idiv
2155
2335
 	.align	2
2156
2336
 	.global	NandcTimeCfg
2337
+	.syntax unified
2338
+	.arm
2339
+	.fpu softvfp
2157
2340
 	.type	NandcTimeCfg, %function
2158
2341
 NandcTimeCfg:
2159
2342
 	.fnstart
2160
2343
 	@ args = 0, pretend = 0, frame = 0
2161
2344
 	@ frame_needed = 0, uses_anonymous_args = 0
2162
-	stmfd	sp!, {r4, lr}
2345
+	push	{r4, lr}
2163
2346
 	.save {r4, lr}
2164
2347
 	mov	r4, r0
2165
2348
 	mov	r0, #0
2166
2349
 	bl	rknand_get_clk_rate
2167
-	ldr	r1, .L391
2350
+	ldr	r1, .L392
2168
2351
 	bl	__aeabi_idiv
2169
-	ldr	r3, .L391+4
2170
-	ldr	r3, [r3, #80]
2352
+	ldr	r3, .L392+4
2171
2353
 	cmp	r0, #250
2172
2354
 	movwgt	r2, #8354
2173
-	bgt	.L389
2174
-	cmp	r0, #220
2355
+	ldr	r3, [r3, #88]
2175
2356
 	bgt	.L390
2357
+	cmp	r0, #220
2358
+	ble	.L384
2359
+.L391:
2360
+	movw	r2, #8322
2361
+	b	.L390
2362
+.L384:
2176
2363
 	cmp	r0, #185
2177
2364
 	movwgt	r2, #4226
2178
-	bgt	.L389
2365
+	bgt	.L390
2179
2366
 	cmp	r0, #160
2180
2367
 	movwgt	r2, #4194
2181
-	bgt	.L389
2368
+	bgt	.L390
2182
2369
 	cmp	r4, #35
2183
2370
 	movwls	r2, #4193
2184
-	bls	.L389
2371
+	bls	.L390
2185
2372
 	cmp	r4, #99
2186
2373
 	movwls	r2, #4225
2187
-	bls	.L389
2374
+	bhi	.L391
2188
2375
 .L390:
2189
-	movw	r2, #8322
2190
-.L389:
2191
2376
 	str	r2, [r3, #4]
2192
-	ldmfd	sp!, {r4, pc}
2193
-.L392:
2377
+	pop	{r4, pc}
2378
+.L393:
2194
2379
 	.align	2
2195
-.L391:
2380
+.L392:
2196
2381
 	.word	1000000
2197
2382
 	.word	.LANCHOR0
2198
2383
 	.fnend
2199
2384
 	.size	NandcTimeCfg, .-NandcTimeCfg
2200
2385
 	.align	2
2201
2386
 	.global	FlashTimingCfg
2387
+	.syntax unified
2388
+	.arm
2389
+	.fpu softvfp
2202
2390
 	.type	FlashTimingCfg, %function
2203
2391
 FlashTimingCfg:
2204
2392
 	.fnstart
..
..
@@ -2209,249 +2397,266 @@
2209
2397
 	sub	r3, r3, #33
2210
2398
 	bic	r3, r3, #32
2211
2399
 	cmp	r3, #1
2212
-	bls	.L394
2400
+	bls	.L395
2213
2401
 	movw	r3, #8322
2214
2402
 	cmp	r0, r3
2215
-	bne	.L395
2216
-.L394:
2217
-	ldr	r3, .L396
2218
-	ldr	r3, [r3, #80]
2219
-	str	r0, [r3, #4]
2403
+	bne	.L396
2220
2404
 .L395:
2221
-	ldr	r3, .L396+4
2222
-	ldrb	r0, [r3, #493]	@ zero_extendqisi2
2223
-	b	NandcTimeCfg
2224
-.L397:
2225
-	.align	2
2405
+	ldr	r3, .L397
2406
+	ldr	r3, [r3, #88]
2407
+	str	r0, [r3, #4]
2226
2408
 .L396:
2409
+	ldr	r3, .L397+4
2410
+	ldrb	r0, [r3, #489]	@ zero_extendqisi2
2411
+	b	NandcTimeCfg
2412
+.L398:
2413
+	.align	2
2414
+.L397:
2227
2415
 	.word	.LANCHOR0
2228
2416
 	.word	.LANCHOR1
2229
2417
 	.fnend
2230
2418
 	.size	FlashTimingCfg, .-FlashTimingCfg
2231
2419
 	.align	2
2232
2420
 	.global	NandcInit
2421
+	.syntax unified
2422
+	.arm
2423
+	.fpu softvfp
2233
2424
 	.type	NandcInit, %function
2234
2425
 NandcInit:
2235
2426
 	.fnstart
2236
2427
 	@ args = 0, pretend = 0, frame = 0
2237
2428
 	@ frame_needed = 0, uses_anonymous_args = 0
2238
-	stmfd	sp!, {r3, r4, r5, lr}
2239
-	.save {r3, r4, r5, lr}
2240
-	mov	r1, #0
2241
-	ldr	r3, .L401
2429
+	ldr	r3, .L402
2242
2430
 	mov	r2, #1
2431
+	push	{r4, r5, r6, lr}
2432
+	.save {r4, r5, r6, lr}
2433
+	mov	r1, #0
2243
2434
 	mov	r5, #0
2244
-	str	r1, [r3, #16]
2245
2435
 	mov	r4, r3
2246
-	str	r0, [r3, #12]
2247
-	str	r2, [r3, #24]
2436
+	str	r2, [r3, #12]
2248
2437
 	mov	r2, #2
2249
-	str	r0, [r3, #20]
2250
-	str	r2, [r3, #32]
2438
+	str	r2, [r3, #20]
2251
2439
 	mov	r2, #3
2252
-	str	r0, [r3, #28]
2253
-	str	r0, [r3, #36]
2254
-	str	r0, [r3, #80]
2255
-	str	r2, [r3, #40]
2440
+	stm	r3, {r0, r1}
2441
+	str	r0, [r3, #8]
2442
+	str	r0, [r3, #16]
2443
+	str	r0, [r3, #24]
2444
+	str	r0, [r3, #88]
2445
+	str	r2, [r3, #28]
2256
2446
 	ldr	r2, [r0]
2257
2447
 	and	r2, r2, #253952
2258
2448
 	ubfx	ip, r2, #13, #1
2259
2449
 	bfi	r2, r1, #13, #1
2260
2450
 	ldr	r1, [r0, #352]
2261
2451
 	orr	r2, r2, #256
2262
-	str	ip, [r3, #2256]
2452
+	str	ip, [r3, #2260]
2263
2453
 	movw	ip, #2049
2264
2454
 	ubfx	r1, r1, #16, #4
2265
-	str	r1, [r3, #2260]
2455
+	str	r1, [r3, #2264]
2266
2456
 	ldr	r1, [r0, #352]
2267
2457
 	cmp	r1, ip
2268
-	str	r1, [r3, #2264]
2458
+	str	r1, [r3, #2268]
2269
2459
 	moveq	r3, #8
2270
-	streq	r3, [r4, #2260]
2460
+	streq	r3, [r4, #2264]
2271
2461
 	str	r2, [r0]
2272
2462
 	mov	r0, #40
2273
-	ldr	r3, [r4, #80]
2463
+	ldr	r3, [r4, #88]
2274
2464
 	str	r5, [r3, #336]
2275
2465
 	bl	NandcTimeCfg
2276
-	ldr	r3, [r4, #80]
2466
+	ldr	r3, [r4, #88]
2277
2467
 	movw	r2, #8322
2278
2468
 	mov	r0, #36864
2279
2469
 	str	r2, [r3, #344]
2280
-	ldr	r2, .L401+4
2470
+	ldr	r2, .L402+4
2281
2471
 	str	r2, [r3, #304]
2282
2472
 	bl	ftl_malloc
2283
-	str	r5, [r4, #2296]
2284
-	str	r5, [r4, #2304]
2285
-	str	r0, [r4, #2268]
2286
2473
 	str	r0, [r4, #2272]
2287
-	add	r0, r0, #32768
2288
2474
 	str	r0, [r4, #2276]
2289
-	ldmfd	sp!, {r3, r4, r5, pc}
2290
-.L402:
2475
+	add	r0, r0, #32768
2476
+	str	r0, [r4, #2280]
2477
+	str	r5, [r4, #2300]
2478
+	str	r5, [r4, #2308]
2479
+	pop	{r4, r5, r6, pc}
2480
+.L403:
2291
2481
 	.align	2
2292
-.L401:
2482
+.L402:
2293
2483
 	.word	.LANCHOR0
2294
2484
 	.word	1579009
2295
2485
 	.fnend
2296
2486
 	.size	NandcInit, .-NandcInit
2297
2487
 	.align	2
2298
2488
 	.global	NandcGetTimeCfg
2489
+	.syntax unified
2490
+	.arm
2491
+	.fpu softvfp
2299
2492
 	.type	NandcGetTimeCfg, %function
2300
2493
 NandcGetTimeCfg:
2301
2494
 	.fnstart
2302
2495
 	@ args = 0, pretend = 0, frame = 0
2303
2496
 	@ frame_needed = 0, uses_anonymous_args = 0
2304
-	ldr	ip, .L405
2497
+	ldr	ip, .L406
2305
2498
 	str	lr, [sp, #-4]!
2306
2499
 	.save {lr}
2307
-	ldr	lr, [ip, #80]
2500
+	ldr	lr, [ip, #88]
2308
2501
 	ldr	lr, [lr, #4]
2309
2502
 	str	lr, [r0]
2310
-	ldr	r0, [ip, #80]
2503
+	ldr	r0, [ip, #88]
2311
2504
 	ldr	r0, [r0]
2312
2505
 	str	r0, [r1]
2313
-	ldr	r1, [ip, #80]
2506
+	ldr	r1, [ip, #88]
2314
2507
 	ldr	r1, [r1, #304]
2315
2508
 	str	r1, [r2]
2316
-	ldr	r1, [ip, #80]
2509
+	ldr	r1, [ip, #88]
2317
2510
 	ldr	r2, [r1, #308]
2318
2511
 	ldr	r1, [r1, #344]
2319
2512
 	uxtb	r2, r2
2320
-	orr	r2, r2, r1, asl #16
2513
+	orr	r2, r2, r1, lsl #16
2321
2514
 	str	r2, [r3]
2322
2515
 	ldr	pc, [sp], #4
2323
-.L406:
2516
+.L407:
2324
2517
 	.align	2
2325
-.L405:
2518
+.L406:
2326
2519
 	.word	.LANCHOR0
2327
2520
 	.fnend
2328
2521
 	.size	NandcGetTimeCfg, .-NandcGetTimeCfg
2329
2522
 	.align	2
2330
2523
 	.global	NandcBchSel
2524
+	.syntax unified
2525
+	.arm
2526
+	.fpu softvfp
2331
2527
 	.type	NandcBchSel, %function
2332
2528
 NandcBchSel:
2333
2529
 	.fnstart
2334
2530
 	@ args = 0, pretend = 0, frame = 0
2335
2531
 	@ frame_needed = 0, uses_anonymous_args = 0
2336
2532
 	@ link register save eliminated.
2337
-	ldr	r3, .L415
2338
-	mov	r1, #1
2339
-	ldr	r2, [r3, #80]
2340
-	str	r0, [r3, #2308]
2341
-	mov	r3, #0
2342
-	str	r1, [r2, #8]
2343
-	mov	r1, #16
2344
-	cmp	r0, r1
2345
-	bfi	r3, r1, #8, #8
2346
-	bfc	r3, #18, #1
2347
-	bne	.L408
2348
-.L411:
2533
+	ldr	r3, .L416
2534
+	mov	ip, #1
2535
+	mov	r1, #0
2536
+	ldr	r2, [r3, #88]
2537
+	str	r0, [r3, #2312]
2538
+	mov	r3, r1
2539
+	str	ip, [r2, #8]
2540
+	mov	ip, #16
2541
+	cmp	r0, ip
2542
+	bfi	r3, ip, #8, #8
2543
+	bfi	r3, r1, #18, #1
2544
+	bne	.L409
2545
+.L412:
2349
2546
 	bfc	r3, #4, #1
2350
-	b	.L409
2351
-.L408:
2352
-	cmp	r0, #24
2353
-	orreq	r3, r3, #16
2354
-	beq	.L409
2355
-	cmp	r0, #40
2356
-	orr	r3, r3, #262144
2357
-	orr	r3, r3, #16
2358
-	beq	.L411
2359
-.L409:
2547
+.L410:
2360
2548
 	orr	r3, r3, #1
2361
2549
 	str	r3, [r2, #12]
2362
2550
 	bx	lr
2363
-.L416:
2551
+.L409:
2552
+	cmp	r0, #24
2553
+	orreq	r3, r3, #16
2554
+	beq	.L410
2555
+	cmp	r0, #40
2556
+	orr	r3, r3, #262144
2557
+	orr	r3, r3, #16
2558
+	bne	.L410
2559
+	b	.L412
2560
+.L417:
2364
2561
 	.align	2
2365
-.L415:
2562
+.L416:
2366
2563
 	.word	.LANCHOR0
2367
2564
 	.fnend
2368
2565
 	.size	NandcBchSel, .-NandcBchSel
2369
2566
 	.align	2
2370
2567
 	.global	FlashBchSel
2568
+	.syntax unified
2569
+	.arm
2570
+	.fpu softvfp
2371
2571
 	.type	FlashBchSel, %function
2372
2572
 FlashBchSel:
2373
2573
 	.fnstart
2374
2574
 	@ args = 0, pretend = 0, frame = 0
2375
2575
 	@ frame_needed = 0, uses_anonymous_args = 0
2376
2576
 	@ link register save eliminated.
2377
-	ldr	r3, .L418
2378
-	strb	r0, [r3, #2312]
2577
+	ldr	r3, .L419
2578
+	strb	r0, [r3, #2316]
2379
2579
 	b	NandcBchSel
2380
-.L419:
2580
+.L420:
2381
2581
 	.align	2
2382
-.L418:
2582
+.L419:
2383
2583
 	.word	.LANCHOR0
2384
2584
 	.fnend
2385
2585
 	.size	FlashBchSel, .-FlashBchSel
2386
2586
 	.align	2
2387
2587
 	.global	ftl_flash_resume
2588
+	.syntax unified
2589
+	.arm
2590
+	.fpu softvfp
2388
2591
 	.type	ftl_flash_resume, %function
2389
2592
 ftl_flash_resume:
2390
2593
 	.fnstart
2391
2594
 	@ args = 0, pretend = 0, frame = 0
2392
2595
 	@ frame_needed = 0, uses_anonymous_args = 0
2393
-	ldr	r3, .L429
2394
-	stmfd	sp!, {r4, r5, r6, lr}
2596
+	ldr	r3, .L430
2597
+	push	{r4, r5, r6, lr}
2395
2598
 	.save {r4, r5, r6, lr}
2396
2599
 	mov	r5, #0
2397
-	ldr	r2, [r3, #80]
2600
+	ldr	r6, .L430+4
2398
2601
 	mov	r4, r3
2399
-	ldr	r1, [r3, #84]
2400
-	ldr	r6, .L429+4
2401
-	str	r1, [r2]
2402
-	ldr	r1, [r3, #88]
2403
-	ldr	r2, [r3, #80]
2404
-	str	r1, [r2, #4]
2602
+	ldr	r2, [r3, #88]
2405
2603
 	ldr	r1, [r3, #92]
2406
-	str	r1, [r2, #8]
2604
+	str	r1, [r2]
2407
2605
 	ldr	r1, [r3, #96]
2408
-	str	r1, [r2, #12]
2606
+	ldr	r2, [r3, #88]
2607
+	str	r1, [r2, #4]
2409
2608
 	ldr	r1, [r3, #100]
2410
-	str	r1, [r2, #304]
2609
+	str	r1, [r2, #8]
2411
2610
 	ldr	r1, [r3, #104]
2412
-	str	r1, [r2, #308]
2611
+	str	r1, [r2, #12]
2413
2612
 	ldr	r1, [r3, #108]
2414
-	str	r1, [r2, #336]
2613
+	str	r1, [r2, #304]
2415
2614
 	ldr	r1, [r3, #112]
2615
+	str	r1, [r2, #308]
2616
+	ldr	r1, [r3, #116]
2617
+	str	r1, [r2, #336]
2618
+	ldr	r1, [r3, #120]
2416
2619
 	str	r1, [r2, #344]
2417
-.L422:
2418
-	ldrb	r3, [r6, r5, asl #3]	@ zero_extendqisi2
2620
+.L423:
2621
+	ldrb	r3, [r6, r5, lsl #3]	@ zero_extendqisi2
2419
2622
 	sub	r3, r3, #1
2420
2623
 	uxtb	r3, r3
2421
2624
 	cmp	r3, #253
2422
-	bhi	.L421
2625
+	bhi	.L422
2423
2626
 	uxtb	r0, r5
2424
2627
 	bl	FlashReset
2425
-.L421:
2628
+.L422:
2426
2629
 	add	r5, r5, #1
2427
2630
 	cmp	r5, #4
2428
-	bne	.L422
2429
-	ldrb	r3, [r4, #2252]	@ zero_extendqisi2
2430
-	ldr	r5, .L429
2631
+	bne	.L423
2632
+	ldrb	r3, [r4, #2256]	@ zero_extendqisi2
2431
2633
 	cmp	r3, #0
2432
-	beq	.L423
2634
+	beq	.L424
2433
2635
 	mov	r0, #1
2434
2636
 	bl	NandcSetMode
2435
-	ldrb	r0, [r5, #2229]	@ zero_extendqisi2
2637
+	ldrb	r0, [r4, #2233]	@ zero_extendqisi2
2436
2638
 	bl	FlashSetInterfaceMode
2437
-	ldrb	r0, [r5, #2229]	@ zero_extendqisi2
2639
+	ldrb	r0, [r4, #2233]	@ zero_extendqisi2
2438
2640
 	bl	NandcSetMode
2439
-	ldrb	r0, [r5, #101]	@ zero_extendqisi2
2641
+	ldrb	r0, [r4, #109]	@ zero_extendqisi2
2440
2642
 	bl	NandcSetDdrPara
2441
-.L423:
2442
-	ldr	r3, [r4, #44]
2443
-	ldmfd	sp!, {r4, r5, r6, lr}
2643
+.L424:
2644
+	ldr	r3, [r4, #48]
2645
+	pop	{r4, r5, r6, lr}
2444
2646
 	ldrb	r0, [r3, #20]	@ zero_extendqisi2
2445
2647
 	b	FlashBchSel
2446
-.L430:
2648
+.L431:
2447
2649
 	.align	2
2448
-.L429:
2650
+.L430:
2449
2651
 	.word	.LANCHOR0
2450
-	.word	.LANCHOR0+2068
2652
+	.word	.LANCHOR0+2072
2451
2653
 	.fnend
2452
2654
 	.size	ftl_flash_resume, .-ftl_flash_resume
2453
2655
 	.align	2
2454
2656
 	.global	ftl_nandc_get_irq_status
2657
+	.syntax unified
2658
+	.arm
2659
+	.fpu softvfp
2455
2660
 	.type	ftl_nandc_get_irq_status, %function
2456
2661
 ftl_nandc_get_irq_status:
2457
2662
 	.fnstart
..
..
@@ -2464,6 +2669,9 @@
2464
2669
 	.size	ftl_nandc_get_irq_status, .-ftl_nandc_get_irq_status
2465
2670
 	.align	2
2466
2671
 	.global	rk_nandc_flash_ready
2672
+	.syntax unified
2673
+	.arm
2674
+	.fpu softvfp
2467
2675
 	.type	rk_nandc_flash_ready, %function
2468
2676
 rk_nandc_flash_ready:
2469
2677
 	.fnstart
..
..
@@ -2481,6 +2689,9 @@
2481
2689
 	.size	rk_nandc_flash_ready, .-rk_nandc_flash_ready
2482
2690
 	.align	2
2483
2691
 	.global	NandcIqrWaitFlashReady
2692
+	.syntax unified
2693
+	.arm
2694
+	.fpu softvfp
2484
2695
 	.type	NandcIqrWaitFlashReady, %function
2485
2696
 NandcIqrWaitFlashReady:
2486
2697
 	.fnstart
..
..
@@ -2492,6 +2703,9 @@
2492
2703
 	.size	NandcIqrWaitFlashReady, .-NandcIqrWaitFlashReady
2493
2704
 	.align	2
2494
2705
 	.global	rk_nandc_flash_xfer_completed
2706
+	.syntax unified
2707
+	.arm
2708
+	.fpu softvfp
2495
2709
 	.type	rk_nandc_flash_xfer_completed, %function
2496
2710
 rk_nandc_flash_xfer_completed:
2497
2711
 	.fnstart
..
..
@@ -2509,6 +2723,9 @@
2509
2723
 	.size	rk_nandc_flash_xfer_completed, .-rk_nandc_flash_xfer_completed
2510
2724
 	.align	2
2511
2725
 	.global	NandcSendDumpDataStart
2726
+	.syntax unified
2727
+	.arm
2728
+	.fpu softvfp
2512
2729
 	.type	NandcSendDumpDataStart, %function
2513
2730
 NandcSendDumpDataStart:
2514
2731
 	.fnstart
..
..
@@ -2518,10 +2735,10 @@
2518
2735
 	ldr	r2, [r0, #16]
2519
2736
 	.pad #8
2520
2737
 	sub	sp, sp, #8
2521
-	ldr	r3, .L437
2738
+	ldr	r3, .L438
2522
2739
 	str	r2, [sp, #4]
2523
2740
 	ldr	r2, [sp, #4]
2524
-	bic	r2, r2, #4
2741
+	bfc	r2, #2, #1
2525
2742
 	str	r2, [sp, #4]
2526
2743
 	ldr	r2, [sp, #4]
2527
2744
 	str	r2, [r0, #16]
..
..
@@ -2531,14 +2748,17 @@
2531
2748
 	add	sp, sp, #8
2532
2749
 	@ sp needed
2533
2750
 	bx	lr
2534
-.L438:
2751
+.L439:
2535
2752
 	.align	2
2536
-.L437:
2753
+.L438:
2537
2754
 	.word	538969130
2538
2755
 	.fnend
2539
2756
 	.size	NandcSendDumpDataStart, .-NandcSendDumpDataStart
2540
2757
 	.align	2
2541
2758
 	.global	NandcSendDumpDataDone
2759
+	.syntax unified
2760
+	.arm
2761
+	.fpu softvfp
2542
2762
 	.type	NandcSendDumpDataDone, %function
2543
2763
 NandcSendDumpDataDone:
2544
2764
 	.fnstart
..
..
@@ -2547,12 +2767,12 @@
2547
2767
 	@ link register save eliminated.
2548
2768
 	.pad #8
2549
2769
 	sub	sp, sp, #8
2550
-.L440:
2770
+.L441:
2551
2771
 	ldr	r3, [r0, #8]
2552
2772
 	str	r3, [sp, #4]
2553
2773
 	ldr	r3, [sp, #4]
2554
2774
 	tst	r3, #1048576
2555
-	beq	.L440
2775
+	beq	.L441
2556
2776
 	add	sp, sp, #8
2557
2777
 	@ sp needed
2558
2778
 	bx	lr
..
..
@@ -2560,155 +2780,152 @@
2560
2780
 	.size	NandcSendDumpDataDone, .-NandcSendDumpDataDone
2561
2781
 	.align	2
2562
2782
 	.global	NandcXferStart
2783
+	.syntax unified
2784
+	.arm
2785
+	.fpu softvfp
2563
2786
 	.type	NandcXferStart, %function
2564
2787
 NandcXferStart:
2565
2788
 	.fnstart
2566
-	@ args = 8, pretend = 0, frame = 24
2789
+	@ args = 8, pretend = 0, frame = 16
2567
2790
 	@ frame_needed = 0, uses_anonymous_args = 0
2568
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2791
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
2569
2792
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2570
-	mov	lr, #16
2571
-	ldr	r5, .L462
2572
-	mov	r4, #0
2573
-	.pad #28
2574
-	sub	sp, sp, #28
2575
-	add	r0, r5, r0, asl #3
2576
-	ldr	r8, [sp, #64]
2577
-	ldr	r6, [r0, #12]
2578
-	ldrb	r0, [r0, #16]	@ zero_extendqisi2
2579
-	ldr	ip, [sp, #68]
2793
+	mov	ip, #16
2794
+	ldr	r4, .L463
2795
+	mov	r5, #0
2796
+	.pad #20
2797
+	sub	sp, sp, #20
2798
+	ldr	r8, [sp, #56]
2799
+	ldr	r6, [r4, r0, lsl #3]
2800
+	add	r0, r4, r0, lsl #3
2580
2801
 	ldr	r7, [r6, #12]
2581
-	bfi	r7, lr, #8, #8
2582
-	bfi	r7, r4, #3, #1
2583
-	bfi	r4, r1, #1, #1
2584
-	orr	r4, r4, #8
2802
+	ldrb	r0, [r0, #4]	@ zero_extendqisi2
2803
+	bfi	r7, ip, #8, #8
2804
+	bfi	r7, r5, #3, #1
2805
+	bfi	r5, r1, #1, #1
2585
2806
 	bfi	r7, r0, #5, #3
2807
+	orr	r5, r5, #8
2586
2808
 	mov	r0, #1
2587
-	bfi	r4, r0, #5, #2
2588
-	orr	r4, r4, #536870912
2589
-	mov	r3, r3, lsr r0
2590
-	orr	r4, r4, #1024
2591
-	bfi	r4, r3, #4, #1
2592
-	ldr	r3, [r5, #2260]
2809
+	bfi	r5, r0, #5, #2
2810
+	lsr	r3, r3, r0
2811
+	orr	r5, r5, #536870912
2812
+	orr	r5, r5, #1024
2813
+	bfi	r5, r3, #4, #1
2814
+	ldr	r3, [r4, #2264]
2593
2815
 	cmp	r3, #3
2594
-	bls	.L445
2816
+	bls	.L446
2595
2817
 	ldr	r3, [r6, #16]
2596
-	str	r3, [sp, #20]
2597
-	ldr	r3, [sp, #20]
2598
-	bic	r3, r3, #4
2599
-	str	r3, [sp, #20]
2600
-	adds	r3, ip, #0
2601
-	movne	r3, #1
2602
-	cmp	ip, #0
2603
-	cmpeq	r8, #0
2604
-	str	r3, [sp, #8]
2605
-	beq	.L446
2818
+	str	r3, [sp, #12]
2819
+	ldr	r3, [sp, #12]
2820
+	bfc	r3, #2, #1
2821
+	str	r3, [sp, #12]
2822
+	ldr	r3, [sp, #60]
2823
+	cmp	r8, #0
2824
+	cmpeq	r3, #0
2825
+	beq	.L447
2606
2826
 	cmp	r1, #0
2607
-	bne	.L447
2608
-.L455:
2827
+	bne	.L448
2828
+.L456:
2609
2829
 	add	r2, r2, #1
2610
2830
 	cmp	r8, #0
2611
-	mov	r2, r2, asr #1
2831
+	asr	r2, r2, #1
2612
2832
 	movne	r0, r8
2613
-	bfi	r4, r2, #22, #6
2614
-	ldreq	r0, [r5, #2272]
2615
-	b	.L449
2833
+	bfi	r5, r2, #22, #6
2834
+	ldreq	r0, [r4, #2276]
2835
+.L450:
2836
+	ldr	r3, [r4, #2280]
2837
+	ubfx	r10, r5, #22, #5
2838
+	mov	r9, r1
2839
+	mov	r2, r1
2840
+	lsl	r1, r10, #10
2841
+	str	r0, [r4, #2284]
2842
+	str	r3, [r4, #2288]
2843
+	bl	rknand_dma_map_single
2844
+	mov	r2, r9
2845
+	str	r0, [r4, #2292]
2846
+	lsl	r1, r10, #7
2847
+	ldr	r0, [r4, #2288]
2848
+	bl	rknand_dma_map_single
2849
+	mov	r3, #1
2850
+	str	r0, [r4, #2296]
2851
+	str	r3, [r4, #2300]
2852
+	mov	r2, #16
2853
+	ldr	r3, [r4, #2292]
2854
+	tst	r8, #3
2855
+	clz	r1, r9
2856
+	lsr	r1, r1, #5
2857
+	str	r3, [r6, #20]
2858
+	ldr	r3, [r4, #2296]
2859
+	str	r3, [r6, #24]
2860
+	mov	r3, #0
2861
+	str	r3, [sp, #12]
2862
+	ldr	r3, [sp, #12]
2863
+	bfi	r3, r2, #9, #5
2864
+	moveq	r2, #2
2865
+	str	r3, [sp, #12]
2866
+	ldr	r3, [sp, #12]
2867
+	orr	r3, r3, #448
2868
+	str	r3, [sp, #12]
2869
+	ldreq	r3, [sp, #12]
2870
+	bfieq	r3, r2, #3, #3
2871
+	streq	r3, [sp, #12]
2872
+	ldr	r3, [sp, #12]
2873
+	orr	r3, r3, #4
2874
+	str	r3, [sp, #12]
2875
+	ldr	r3, [sp, #12]
2876
+	bfi	r3, r1, #1, #1
2877
+	str	r3, [sp, #12]
2878
+	ldr	r3, [sp, #12]
2879
+	orr	r3, r3, #1
2880
+	str	r3, [sp, #12]
2616
2881
 .L447:
2617
-	ldr	r3, [r5, #2308]
2618
-	mov	r9, r5
2882
+	ldr	r3, [sp, #12]
2883
+	str	r3, [r6, #16]
2884
+.L446:
2885
+	str	r7, [r6, #12]
2886
+	str	r5, [r6, #8]
2887
+	orr	r5, r5, #4
2888
+	str	r5, [r6, #8]
2889
+	add	sp, sp, #20
2890
+	@ sp needed
2891
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
2892
+.L448:
2893
+	ldr	r3, [r4, #2312]
2894
+	lsr	r10, r2, #1
2895
+	ldr	ip, [sp, #60]
2619
2896
 	cmp	r3, #25
2620
2897
 	movcc	r3, #64
2621
2898
 	movcs	r3, #128
2622
2899
 	str	r3, [sp, #4]
2623
-	mov	r3, r2, lsr #1
2624
-	str	r3, [sp, #12]
2625
2900
 	mov	r3, #0
2626
2901
 	mov	r0, r3
2627
-.L451:
2628
-	ldr	lr, [sp, #12]
2629
-	cmp	r0, lr
2630
-	bcs	.L455
2631
-	ldr	lr, [sp, #8]
2632
-	mov	r10, r3, lsr #2
2902
+.L452:
2903
+	cmp	r0, r10
2904
+	bcs	.L456
2905
+	ldr	lr, [sp, #60]
2633
2906
 	add	r0, r0, #1
2634
2907
 	cmp	lr, #0
2635
-	ldrneh	fp, [ip, #2]
2636
-	mvneq	fp, #0
2637
-	ldrneh	lr, [ip], #4
2638
-	ldreq	lr, [r9, #2276]
2639
-	orrne	lr, lr, fp, asl #16
2640
-	ldrne	fp, [r9, #2276]
2641
-	streq	fp, [lr, r10, asl #2]
2642
-	strne	lr, [fp, r10, asl #2]
2908
+	bic	lr, r3, #3
2909
+	ldrne	fp, [ip], #4	@ unaligned
2910
+	mvneq	r9, #0
2911
+	ldrne	r9, [r4, #2280]
2912
+	ldreq	fp, [r4, #2280]
2913
+	strne	fp, [r9, lr]
2914
+	streq	r9, [fp, lr]
2643
2915
 	ldr	lr, [sp, #4]
2644
2916
 	add	r3, r3, lr
2645
-	b	.L451
2646
-.L449:
2647
-	ldr	r3, [r5, #2276]
2648
-	ubfx	r10, r4, #22, #5
2649
-	mov	r9, r1
2650
-	str	r0, [r5, #2280]
2651
-	mov	r2, r9
2652
-	mov	r1, r10, asl #10
2653
-	str	r3, [r5, #2284]
2654
-	bl	rknand_dma_map_single
2655
-	mov	r2, r9
2656
-	mov	r1, r10, asl #7
2657
-	clz	r9, r9
2658
-	mov	r9, r9, lsr #5
2659
-	str	r0, [r5, #2288]
2660
-	ldr	r0, [r5, #2284]
2661
-	bl	rknand_dma_map_single
2662
-	mov	r3, #1
2663
-	str	r3, [r5, #2296]
2664
-	tst	r8, #3
2665
-	ldr	r3, [r5, #2288]
2666
-	str	r0, [r5, #2292]
2667
-	str	r3, [r6, #20]
2668
-	ldr	r3, [r5, #2292]
2669
-	str	r3, [r6, #24]
2670
-	mov	r3, #0
2671
-	str	r3, [sp, #20]
2672
-	ldr	r3, [sp, #20]
2673
-	bic	r3, r3, #15872
2674
-	orr	r3, r3, #8192
2675
-	str	r3, [sp, #20]
2676
-	ldr	r3, [sp, #20]
2677
-	orr	r3, r3, #448
2678
-	str	r3, [sp, #20]
2679
-	ldreq	r3, [sp, #20]
2680
-	biceq	r3, r3, #56
2681
-	orreq	r3, r3, #16
2682
-	streq	r3, [sp, #20]
2683
-	ldr	r3, [sp, #20]
2684
-	orr	r3, r3, #4
2685
-	str	r3, [sp, #20]
2686
-	ldr	r3, [sp, #20]
2687
-	bic	r3, r3, #2
2688
-	orr	r9, r3, r9, asl #1
2689
-	str	r9, [sp, #20]
2690
-	ldr	r3, [sp, #20]
2691
-	orr	r3, r3, #1
2692
-	str	r3, [sp, #20]
2693
-.L446:
2694
-	ldr	r3, [sp, #20]
2695
-	str	r3, [r6, #16]
2696
-.L445:
2697
-	str	r7, [r6, #12]
2698
-	str	r4, [r6, #8]
2699
-	orr	r4, r4, #4
2700
-	str	r4, [r6, #8]
2701
-	add	sp, sp, #28
2702
-	@ sp needed
2703
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
2704
-.L463:
2917
+	b	.L452
2918
+.L464:
2705
2919
 	.align	2
2706
-.L462:
2920
+.L463:
2707
2921
 	.word	.LANCHOR0
2708
2922
 	.fnend
2709
2923
 	.size	NandcXferStart, .-NandcXferStart
2710
2924
 	.align	2
2711
2925
 	.global	Ftl_log2
2926
+	.syntax unified
2927
+	.arm
2928
+	.fpu softvfp
2712
2929
 	.type	Ftl_log2, %function
2713
2930
 Ftl_log2:
2714
2931
 	.fnstart
..
..
@@ -2717,20 +2934,24 @@
2717
2934
 	@ link register save eliminated.
2718
2935
 	mov	r1, #0
2719
2936
 	mov	r2, #1
2720
-.L465:
2937
+.L466:
2721
2938
 	cmp	r2, r0
2722
2939
 	uxth	r3, r1
2723
2940
 	add	r1, r1, #1
2724
-	movls	r2, r2, asl #1
2725
-	bls	.L465
2726
-.L467:
2941
+	bls	.L467
2727
2942
 	sub	r0, r3, #1
2728
2943
 	uxth	r0, r0
2729
2944
 	bx	lr
2945
+.L467:
2946
+	lsl	r2, r2, #1
2947
+	b	.L466
2730
2948
 	.fnend
2731
2949
 	.size	Ftl_log2, .-Ftl_log2
2732
2950
 	.align	2
2733
2951
 	.global	FtlPrintInfo
2952
+	.syntax unified
2953
+	.arm
2954
+	.fpu softvfp
2734
2955
 	.type	FtlPrintInfo, %function
2735
2956
 FtlPrintInfo:
2736
2957
 	.fnstart
..
..
@@ -2742,507 +2963,534 @@
2742
2963
 	.size	FtlPrintInfo, .-FtlPrintInfo
2743
2964
 	.align	2
2744
2965
 	.global	FtlSysBlkNumInit
2966
+	.syntax unified
2967
+	.arm
2968
+	.fpu softvfp
2745
2969
 	.type	FtlSysBlkNumInit, %function
2746
2970
 FtlSysBlkNumInit:
2747
2971
 	.fnstart
2748
2972
 	@ args = 0, pretend = 0, frame = 0
2749
2973
 	@ frame_needed = 0, uses_anonymous_args = 0
2750
2974
 	@ link register save eliminated.
2751
-	ldr	r3, .L471
2752
-	cmp	r0, #23
2753
-	movw	r1, #2330
2754
-	add	r2, r3, #2320
2755
-	movls	r0, #24
2975
+	ldr	r3, .L470
2976
+	movw	r2, #2324
2977
+	movw	r1, #2334
2978
+	cmp	r0, #24
2979
+	movcc	r0, #24
2980
+	ldrh	r2, [r3, r2]
2756
2981
 	ldrh	r1, [r3, r1]
2757
-	ldrh	r2, [r2]
2758
-	str	r0, [r3, #2316]
2759
-	mul	r2, r2, r0
2760
-	rsb	r0, r0, r1
2761
-	movw	r1, #2328
2982
+	str	r0, [r3, #2320]
2983
+	mul	r2, r0, r2
2984
+	sub	r0, r1, r0
2985
+	movw	r1, #2332
2762
2986
 	strh	r0, [r3, r1]	@ movhi
2763
2987
 	mov	r0, #0
2764
-	ldr	r1, [r3, #2336]
2765
-	str	r2, [r3, #2324]
2766
-	rsb	r2, r2, r1
2767
-	str	r2, [r3, #2332]
2988
+	ldr	r1, [r3, #2340]
2989
+	str	r2, [r3, #2328]
2990
+	sub	r2, r1, r2
2991
+	str	r2, [r3, #2336]
2768
2992
 	bx	lr
2769
-.L472:
2770
-	.align	2
2771
2993
 .L471:
2994
+	.align	2
2995
+.L470:
2772
2996
 	.word	.LANCHOR0
2773
2997
 	.fnend
2774
2998
 	.size	FtlSysBlkNumInit, .-FtlSysBlkNumInit
2775
2999
 	.align	2
2776
3000
 	.global	FtlConstantsInit
3001
+	.syntax unified
3002
+	.arm
3003
+	.fpu softvfp
2777
3004
 	.type	FtlConstantsInit, %function
2778
3005
 FtlConstantsInit:
2779
3006
 	.fnstart
2780
3007
 	@ args = 0, pretend = 0, frame = 16
2781
3008
 	@ frame_needed = 0, uses_anonymous_args = 0
2782
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
3009
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
2783
3010
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2784
-	movw	r3, #2340
2785
-	ldr	r4, .L502
2786
-	movw	r1, #2344
2787
-	ldrh	r6, [r0, #8]
3011
+	movw	r3, #2344
3012
+	ldr	r4, .L500
3013
+	movw	r1, #2348
2788
3014
 	mov	r5, r0
2789
-	ldrh	r2, [r0, #10]
2790
3015
 	.pad #20
2791
3016
 	sub	sp, sp, #20
3017
+	ldrh	r6, [r0, #8]
3018
+	ldrh	r2, [r0, #10]
2792
3019
 	ldrh	lr, [r0, #14]
2793
3020
 	strh	r6, [r4, r3]	@ movhi
2794
-	movw	r3, #2342
3021
+	movw	r3, #2346
2795
3022
 	strh	r2, [r4, r3]	@ movhi
2796
3023
 	ldrh	r3, [r0, #12]
2797
-	ldr	r0, .L502+4
3024
+	ldr	r0, .L500+4
2798
3025
 	strh	r3, [r4, r1]	@ movhi
2799
-	movw	r1, #2330
3026
+	movw	r1, #2334
2800
3027
 	strh	lr, [r4, r1]	@ movhi
2801
3028
 	mov	r1, #0
2802
-.L474:
3029
+.L473:
2803
3030
 	strb	r1, [r1, r0]
2804
3031
 	add	r1, r1, #1
2805
3032
 	cmp	r1, #32
2806
-	bne	.L474
3033
+	bne	.L473
2807
3034
 	ldrh	r0, [r5, #14]
2808
3035
 	ldrh	r1, [r5, #20]
2809
3036
 	cmp	r1, r0, lsr #8
2810
-	bcs	.L475
3037
+	bcs	.L474
2811
3038
 	uxtb	r10, r3
2812
-	ldr	r9, .L502+4
2813
-	mov	r1, r10, asl #1
3039
+	ldr	r9, .L500+4
3040
+	lsl	r1, r10, #1
2814
3041
 	uxtb	r1, r1
2815
-	str	r1, [sp, #4]
3042
+	str	r1, [sp]
2816
3043
 	sub	r1, r2, #1
2817
3044
 	mul	r1, r3, r1
2818
-	str	r1, [sp]
3045
+	str	r1, [sp, #8]
2819
3046
 	mov	r1, #0
2820
-.L476:
3047
+.L475:
2821
3048
 	cmp	r1, r3
2822
-	bcs	.L478
2823
-	ldr	ip, [sp]
2824
-	uxtb	r0, r1
2825
-	rsb	r7, r3, r1
2826
-	add	ip, r1, ip
3049
+	bcs	.L477
3050
+	ldr	ip, [sp, #8]
3051
+	sub	r7, r1, r3
2827
3052
 	add	r7, r9, r7
2828
-	add	ip, r9, ip
2829
-	str	ip, [sp, #8]
2830
-	mov	ip, #0
3053
+	uxtb	r0, r1
2831
3054
 	str	r7, [sp, #12]
3055
+	add	ip, r1, ip
3056
+	add	ip, r9, ip
3057
+	str	ip, [sp, #4]
3058
+	mov	ip, #0
2832
3059
 	mov	r8, ip
2833
-.L479:
2834
-	cmp	r8, r2
2835
-	add	ip, ip, r3
2836
-	bcs	.L501
3060
+	b	.L478
3061
+.L476:
2837
3062
 	ldr	r7, [sp, #12]
2838
-	add	fp, r0, r10
3063
+	add	fp, r10, r0
2839
3064
 	add	r8, r8, #1
2840
3065
 	strb	r0, [r7, ip]
2841
-	ldr	r7, [sp, #8]
2842
-	strb	fp, [r7, ip]
2843
3066
 	ldr	r7, [sp, #4]
2844
-	add	r0, r0, r7
3067
+	strb	fp, [r7, ip]
3068
+	ldr	r7, [sp]
3069
+	add	r0, r7, r0
2845
3070
 	uxtb	r0, r0
2846
-	b	.L479
2847
-.L501:
2848
-	add	r1, r1, #1
2849
-	b	.L476
2850
3071
 .L478:
2851
-	movw	r1, #2342
2852
-	mov	r2, r2, asl #1
3072
+	cmp	r8, r2
3073
+	add	ip, ip, r3
3074
+	bcc	.L476
3075
+	add	r1, r1, #1
3076
+	b	.L475
3077
+.L477:
3078
+	lsl	r2, r2, #1
3079
+	movw	r1, #2346
3080
+	lsr	lr, lr, #1
2853
3081
 	strh	r2, [r4, r1]	@ movhi
2854
-	movw	r2, #2330
2855
-	mov	lr, lr, lsr #1
3082
+	movw	r2, #2334
2856
3083
 	strh	lr, [r4, r2]	@ movhi
2857
-.L475:
2858
-	cmp	r6, #1
2859
-	movw	r2, #2380
3084
+.L474:
3085
+	ldr	fp, .L500+8
3086
+	movw	r2, #2382
3087
+	ldrb	r9, [r4, #36]	@ zero_extendqisi2
2860
3088
 	mov	r1, #5
2861
3089
 	strh	r1, [r4, r2]	@ movhi
2862
-	movw	r1, #2382
2863
-	mov	r0, #0
2864
-	strh	r0, [r4, r1]	@ movhi
2865
-	ldreq	r1, .L502
2866
-	ldrb	r9, [r4]	@ zero_extendqisi2
2867
-	ldr	r8, .L502+8
2868
-	streqh	r6, [r1, r2]	@ movhi
2869
-	movw	r1, #2342
2870
-	ldrh	r7, [r4, r1]
3090
+	cmp	r6, #1
3091
+	mov	r1, #0
3092
+	strheq	r6, [r4, r2]	@ movhi
3093
+	strh	r1, [fp]	@ movhi
2871
3094
 	cmp	r9, #0
2872
-	mov	r2, #4352
2873
-	strh	r2, [r8]	@ movhi
2874
-	movne	r2, #384
2875
-	strneh	r2, [r8]	@ movhi
2876
-	smulbb	r7, r7, r3
2877
-	ldr	r2, .L502
2878
-	ldrh	r10, [r5, #16]
2879
-	add	r1, r2, #2320
2880
-	str	r2, [sp, #8]
2881
-	uxth	r7, r7
2882
-	strh	r7, [r1]	@ movhi
2883
-	movw	r1, #2330
2884
-	ldrh	r6, [r4, r1]
2885
-	movw	r1, #2386
2886
-	smulbb	r0, r7, r10
2887
-	smulbb	r3, r6, r3
2888
-	strh	r3, [r4, r1]	@ movhi
2889
-	movw	r3, #2388
3095
+	mov	r1, #4352
3096
+	movw	r2, #2386
3097
+	strh	r1, [r4, r2]	@ movhi
3098
+	movne	r1, #384
3099
+	strhne	r1, [r4, r2]	@ movhi
3100
+	movw	r2, #2346
3101
+	ldrh	r7, [r4, r2]
3102
+	movw	r2, #2324
3103
+	ldrh	r8, [r5, #16]
2890
3104
 	ldrh	r1, [r5, #18]
2891
-	strh	r10, [r4, r3]	@ movhi
2892
-	movw	r3, #2390
2893
-	strh	r1, [r4, r3]	@ movhi
2894
-	movw	r3, #2392
2895
-	strh	r0, [r4, r3]	@ movhi
2896
-	movw	r0, #2394
2897
-	ldrh	r3, [r5, #20]
3105
+	smulbb	r7, r7, r3
2898
3106
 	str	r1, [sp, #4]
2899
-	strh	r3, [r4, r0]	@ movhi
3107
+	uxth	r7, r7
3108
+	strh	r7, [r4, r2]	@ movhi
3109
+	movw	r2, #2334
3110
+	ldrh	r6, [r4, r2]
3111
+	movw	r2, #2388
3112
+	smulbb	r3, r3, r6
3113
+	strh	r3, [r4, r2]	@ movhi
3114
+	smulbb	r2, r7, r8
3115
+	movw	r3, #2390
3116
+	strh	r8, [r4, r3]	@ movhi
3117
+	movw	r3, #2392
3118
+	strh	r1, [r4, r3]	@ movhi
3119
+	movw	r3, #2394
3120
+	strh	r2, [r4, r3]	@ movhi
3121
+	movw	r2, #2396
3122
+	ldrh	r3, [r5, #20]
2900
3123
 	mov	r0, r3
3124
+	strh	r3, [r4, r2]	@ movhi
2901
3125
 	str	r3, [sp]
2902
3126
 	bl	Ftl_log2
2903
-	movw	ip, #2398
2904
-	cmp	r6, #1024
2905
3127
 	ldr	r3, [sp]
2906
-	mov	fp, r0
2907
-	movw	r0, #2396
2908
-	ldr	r2, [sp, #8]
2909
-	strh	fp, [r4, r0]	@ movhi
2910
-	mov	r0, r3, asl #9
3128
+	movw	r2, #2398
3129
+	strh	r0, [r4, r2]	@ movhi
3130
+	mov	r10, r0
3131
+	ldr	r0, .L500+12
3132
+	cmp	r6, #1024
2911
3133
 	ldr	r1, [sp, #4]
2912
-	uxth	r0, r0
2913
-	strh	r0, [r4, ip]	@ movhi
2914
-	add	ip, r2, #2400
2915
-	mov	r0, r0, lsr #8
2916
-	strh	r0, [ip]	@ movhi
3134
+	lsl	r2, r3, #9
3135
+	uxth	r2, r2
3136
+	mul	r1, r3, r1
3137
+	strh	r2, [r0]	@ movhi
3138
+	lsr	r2, r2, #8
2917
3139
 	movw	r0, #2402
2918
-	ldrh	ip, [r5, #26]
2919
-	mul	r1, r1, r3
2920
-	ldr	r5, .L502
2921
-	strh	ip, [r4, r0]	@ movhi
2922
-	movwhi	ip, #2382
2923
-	mul	r0, r6, r7
2924
-	str	r0, [r4, #2336]
2925
-	uxtbhi	r0, r6
2926
-	strhih	r0, [r2, ip]	@ movhi
2927
-	movw	r2, #2382
2928
-	ldrh	r2, [r4, r2]
2929
-	ldrh	r0, [r8]
2930
-	rsb	r2, r2, r6
2931
-	mov	r6, r6, asl #6
2932
-	mul	r2, r2, r7
2933
-	mov	r0, r0, asl #3
3140
+	strh	r2, [r4, r0]	@ movhi
3141
+	movw	r2, #2404
3142
+	ldrh	r0, [r5, #26]
3143
+	strh	r0, [r4, r2]	@ movhi
3144
+	mul	r2, r6, r7
3145
+	str	r2, [r4, #2340]
3146
+	uxtbhi	r2, r6
3147
+	strhhi	r2, [fp]	@ movhi
3148
+	ldrh	r2, [fp]
3149
+	sub	r2, r6, r2
3150
+	lsl	r6, r6, #6
3151
+	mul	r2, r7, r2
2934
3152
 	mul	r2, r3, r2
2935
-	mul	r10, r10, r2
2936
-	mov	r10, r10, asr #11
2937
-	str	r10, [r4, #2404]
3153
+	mul	r8, r8, r2
3154
+	movw	r2, #2386
3155
+	ldrh	r0, [r4, r2]
3156
+	asr	r8, r8, #11
3157
+	lsl	r0, r0, #3
3158
+	str	r8, [r4, #2408]
2938
3159
 	bl	__aeabi_idiv
2939
-	movw	r3, #2408
2940
-	mov	r1, r7
2941
-	ldr	r10, .L502
2942
3160
 	uxth	r0, r0
3161
+	movw	r3, #2412
3162
+	mov	r1, r7
2943
3163
 	cmp	r0, #4
2944
-	strhih	r0, [r5, r3]	@ movhi
2945
3164
 	movls	r2, #4
2946
-	strlsh	r2, [r5, r3]	@ movhi
3165
+	strhhi	r0, [r4, r3]	@ movhi
3166
+	strhls	r2, [r4, r3]	@ movhi
2947
3167
 	cmp	r9, #0
2948
-	movw	r2, #2410
2949
-	movne	r3, #640
2950
-	strneh	r3, [r8]	@ movhi
2951
-	ldrh	r3, [r8]
2952
-	mov	r3, r3, asr fp
2953
-	add	fp, fp, #9
2954
-	mov	r0, r6, asr fp
3168
+	movne	r2, #640
3169
+	movwne	r3, #2386
3170
+	strhne	r2, [r4, r3]	@ movhi
3171
+	movw	r3, #2386
3172
+	ldrh	r3, [r4, r3]
3173
+	movw	r2, #2414
3174
+	asr	r3, r3, r10
3175
+	add	r10, r10, #9
3176
+	asr	r6, r6, r10
2955
3177
 	add	r3, r3, #2
2956
3178
 	strh	r3, [r4, r2]	@ movhi
3179
+	ldr	r3, .L500+16
3180
+	strh	r6, [r3]	@ movhi
3181
+	uxth	r6, r6
3182
+	mul	r3, r6, r7
3183
+	add	r6, r6, #8
3184
+	str	r3, [r4, #2420]
2957
3185
 	movw	r3, #2412
2958
-	strh	r0, [r4, r3]	@ movhi
2959
-	uxth	r0, r0
2960
-	add	r6, r0, #8
2961
-	mul	r3, r7, r0
2962
-	str	r3, [r4, #2416]
2963
-	movw	r3, #2408
2964
3186
 	ldrh	r0, [r4, r3]
2965
3187
 	bl	__aeabi_uidiv
2966
-	cmp	r7, #1
2967
3188
 	uxtah	r0, r6, r0
2968
-	ldr	r6, .L502
3189
+	cmp	r7, #1
3190
+	add	r3, r4, #2320
2969
3191
 	addeq	r0, r0, #4
2970
-	str	r0, [r10, #2316]
2971
-	ldr	r3, [r4, #2316]
2972
-	uxth	r0, r3
3192
+	str	r0, [r4, #2320]
3193
+	ldrh	r0, [r3]
2973
3194
 	bl	FtlSysBlkNumInit
2974
-	ldr	r3, [r4, #2316]
2975
-	ldr	r2, [r4, #2332]
3195
+	ldr	r5, [r4, #2336]
3196
+	movw	r2, #2390
3197
+	ldr	r3, [r4, #2320]
2976
3198
 	mov	r0, #2048
2977
-	str	r3, [r4, #2420]
2978
-	movw	r3, #2388
2979
-	ldrh	r3, [r4, r3]
2980
-	mov	r2, r2, asl #2
2981
-	mul	r3, r3, r2
2982
-	movw	r2, #2396
3199
+	str	r3, [r4, #2424]
3200
+	lsl	r3, r5, #2
2983
3201
 	ldrh	r5, [r4, r2]
2984
-	add	r5, r5, #9
2985
-	mov	r5, r3, lsr r5
2986
-	movw	r3, #2424
3202
+	mul	r5, r5, r3
3203
+	movw	r3, #2398
3204
+	ldrh	r3, [r4, r3]
3205
+	add	r3, r3, #9
3206
+	lsr	r5, r5, r3
3207
+	movw	r3, #2428
2987
3208
 	add	r5, r5, #2
2988
3209
 	uxth	r5, r5
2989
3210
 	strh	r5, [r4, r3]	@ movhi
2990
-	movw	r3, #2394
2991
-	ldrh	r7, [r4, r3]
2992
-	mov	r1, r7
3211
+	movw	r3, #2396
3212
+	ldrh	r6, [r4, r3]
3213
+	mov	r1, r6
2993
3214
 	bl	__aeabi_idiv
2994
-	movw	r1, #2408
3215
+	movw	r1, #2412
3216
+	movw	r3, #2430
2995
3217
 	ldrh	r2, [r4, r1]
2996
-	movw	r3, #2426
2997
-	ldrb	ip, [r4, #144]	@ zero_extendqisi2
2998
-	cmp	ip, #0
2999
3218
 	strh	r0, [r4, r3]	@ movhi
3000
3219
 	mov	r3, #0
3001
-	str	r3, [r4, #2428]
3220
+	str	r3, [r4, #2432]
3221
+	ldrb	ip, [r4, #152]	@ zero_extendqisi2
3002
3222
 	add	r3, r2, #3
3003
3223
 	strh	r3, [r4, r1]	@ movhi
3224
+	ldr	r3, [r4, #2420]
3225
+	cmp	ip, #0
3004
3226
 	addne	r2, r2, #4
3005
-	ldr	r3, [r4, #2416]
3006
-	strneh	r2, [r6, r1]	@ movhi
3007
3227
 	add	r0, r3, #3
3228
+	strhne	r2, [r4, r1]	@ movhi
3229
+	str	r0, [r4, #2420]
3008
3230
 	addne	r3, r3, #5
3009
-	str	r0, [r4, #2416]
3010
-	bne	.L500
3231
+	bne	.L499
3011
3232
 	cmp	r0, #7
3012
-	bhi	.L489
3233
+	bhi	.L488
3013
3234
 	mov	r3, #8
3014
-.L500:
3015
-	str	r3, [r6, #2416]
3016
-.L489:
3017
-	ldr	r2, .L502+12
3235
+.L499:
3236
+	str	r3, [r4, #2420]
3237
+.L488:
3238
+	movw	r2, #2436
3018
3239
 	mov	r3, #0
3019
-	mov	r0, #0
3020
-	strh	r3, [r2]	@ movhi
3021
-	movw	r3, #2328
3240
+	strh	r3, [r4, r2]	@ movhi
3241
+	movw	r3, #2332
3022
3242
 	ldrh	r1, [r4, r3]
3023
-	mov	r3, r1, lsr #3
3024
-	add	r3, r3, r1, asl #1
3243
+	mov	r0, #0
3244
+	lsr	r3, r1, #3
3245
+	add	r3, r3, r1, lsl #1
3025
3246
 	add	r3, r3, #52
3026
-	add	r5, r3, r5, asl #2
3027
-	cmp	r5, r7, asl #9
3247
+	add	r5, r3, r5, lsl #2
3248
+	cmp	r5, r6, lsl #9
3028
3249
 	movcc	r3, #1
3029
-	strcch	r3, [r2]	@ movhi
3250
+	strhcc	r3, [r4, r2]	@ movhi
3030
3251
 	add	sp, sp, #20
3031
3252
 	@ sp needed
3032
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
3033
-.L503:
3253
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
3254
+.L501:
3034
3255
 	.align	2
3035
-.L502:
3256
+.L500:
3036
3257
 	.word	.LANCHOR0
3037
-	.word	.LANCHOR0+2348
3258
+	.word	.LANCHOR0+2350
3038
3259
 	.word	.LANCHOR0+2384
3039
-	.word	.LANCHOR0+2432
3260
+	.word	.LANCHOR0+2400
3261
+	.word	.LANCHOR0+2416
3040
3262
 	.fnend
3041
3263
 	.size	FtlConstantsInit, .-FtlConstantsInit
3042
3264
 	.align	2
3043
3265
 	.global	IsBlkInVendorPart
3266
+	.syntax unified
3267
+	.arm
3268
+	.fpu softvfp
3044
3269
 	.type	IsBlkInVendorPart, %function
3045
3270
 IsBlkInVendorPart:
3046
3271
 	.fnstart
3047
3272
 	@ args = 0, pretend = 0, frame = 0
3048
3273
 	@ frame_needed = 0, uses_anonymous_args = 0
3049
3274
 	@ link register save eliminated.
3050
-	ldr	r2, .L511
3051
-	movw	r3, #2434
3275
+	ldr	r2, .L509
3276
+	movw	r3, #2438
3052
3277
 	ldrh	r3, [r2, r3]
3053
3278
 	cmp	r3, #0
3054
-	beq	.L510
3055
-	movw	r1, #2408
3056
-	ldr	r3, [r2, #2436]
3279
+	beq	.L508
3280
+	movw	r1, #2412
3281
+	ldr	r3, [r2, #2440]
3057
3282
 	ldrh	r2, [r2, r1]
3058
-	add	r2, r3, r2, asl #1
3059
-.L506:
3283
+	add	r2, r3, r2, lsl #1
3284
+.L504:
3060
3285
 	cmp	r3, r2
3061
-	beq	.L510
3286
+	bne	.L505
3287
+.L508:
3288
+	mov	r0, #0
3289
+	bx	lr
3290
+.L505:
3062
3291
 	ldrh	r1, [r3], #2
3063
-	cmp	r1, r0
3064
-	bne	.L506
3292
+	cmp	r0, r1
3293
+	bne	.L504
3065
3294
 	mov	r0, #1
3066
3295
 	bx	lr
3067
3296
 .L510:
3068
-	mov	r0, #0
3069
-	bx	lr
3070
-.L512:
3071
3297
 	.align	2
3072
-.L511:
3298
+.L509:
3073
3299
 	.word	.LANCHOR0
3074
3300
 	.fnend
3075
3301
 	.size	IsBlkInVendorPart, .-IsBlkInVendorPart
3076
3302
 	.align	2
3077
3303
 	.global	FtlCacheMetchLpa
3304
+	.syntax unified
3305
+	.arm
3306
+	.fpu softvfp
3078
3307
 	.type	FtlCacheMetchLpa, %function
3079
3308
 FtlCacheMetchLpa:
3080
3309
 	.fnstart
3081
3310
 	@ args = 0, pretend = 0, frame = 0
3082
3311
 	@ frame_needed = 0, uses_anonymous_args = 0
3083
-	ldr	r2, .L520
3084
-	ldr	r3, [r2, #2440]
3312
+	ldr	r2, .L521
3313
+	ldr	r3, [r2, #2444]
3085
3314
 	cmp	r3, #0
3086
-	beq	.L516
3087
-	stmfd	sp!, {r4, r5, lr}
3315
+	beq	.L514
3316
+	push	{r4, r5, lr}
3088
3317
 	.save {r4, r5, lr}
3089
3318
 	mov	r5, #36
3090
-	ldr	r4, [r2, #2444]
3319
+	ldr	r4, [r2, #2448]
3091
3320
 	mov	r2, #0
3092
-.L515:
3321
+.L513:
3093
3322
 	mla	ip, r5, r2, r4
3094
3323
 	ldr	lr, [ip, #16]
3095
-	cmp	lr, r0
3096
-	movcc	ip, #0
3097
-	movcs	ip, #1
3098
3324
 	cmp	lr, r1
3099
3325
 	movhi	ip, #0
3326
+	movls	ip, #1
3327
+	cmp	lr, r0
3328
+	movcc	ip, #0
3100
3329
 	cmp	ip, #0
3101
-	bne	.L517
3102
-	add	r2, r2, #1
3103
-	cmp	r2, r3
3104
3330
 	bne	.L515
3331
+	add	r2, r2, #1
3332
+	cmp	r3, r2
3333
+	bne	.L513
3105
3334
 	mov	r0, ip
3106
-	ldmfd	sp!, {r4, r5, pc}
3107
-.L516:
3335
+	pop	{r4, r5, pc}
3336
+.L514:
3108
3337
 	mov	r0, r3
3109
3338
 	bx	lr
3110
-.L517:
3339
+.L515:
3111
3340
 	mov	r0, #1
3112
-	ldmfd	sp!, {r4, r5, pc}
3113
-.L521:
3341
+	pop	{r4, r5, pc}
3342
+.L522:
3114
3343
 	.align	2
3115
-.L520:
3344
+.L521:
3116
3345
 	.word	.LANCHOR0
3117
3346
 	.fnend
3118
3347
 	.size	FtlCacheMetchLpa, .-FtlCacheMetchLpa
3119
3348
 	.align	2
3120
3349
 	.global	FtlGetCap
3350
+	.syntax unified
3351
+	.arm
3352
+	.fpu softvfp
3121
3353
 	.type	FtlGetCap, %function
3122
3354
 FtlGetCap:
3123
3355
 	.fnstart
3124
3356
 	@ args = 0, pretend = 0, frame = 0
3125
3357
 	@ frame_needed = 0, uses_anonymous_args = 0
3126
3358
 	@ link register save eliminated.
3127
-	ldr	r3, .L523
3128
-	ldr	r0, [r3, #2428]
3359
+	ldr	r3, .L524
3360
+	ldr	r0, [r3, #2432]
3129
3361
 	bx	lr
3130
-.L524:
3362
+.L525:
3131
3363
 	.align	2
3132
-.L523:
3364
+.L524:
3133
3365
 	.word	.LANCHOR0
3134
3366
 	.fnend
3135
3367
 	.size	FtlGetCap, .-FtlGetCap
3136
3368
 	.align	2
3137
3369
 	.global	FtlGetCapacity
3370
+	.syntax unified
3371
+	.arm
3372
+	.fpu softvfp
3138
3373
 	.type	FtlGetCapacity, %function
3139
3374
 FtlGetCapacity:
3140
3375
 	.fnstart
3141
3376
 	@ args = 0, pretend = 0, frame = 0
3142
3377
 	@ frame_needed = 0, uses_anonymous_args = 0
3143
3378
 	@ link register save eliminated.
3144
-	ldr	r3, .L526
3145
-	ldr	r0, [r3, #2428]
3379
+	ldr	r3, .L527
3380
+	ldr	r0, [r3, #2432]
3146
3381
 	bx	lr
3147
-.L527:
3382
+.L528:
3148
3383
 	.align	2
3149
-.L526:
3384
+.L527:
3150
3385
 	.word	.LANCHOR0
3151
3386
 	.fnend
3152
3387
 	.size	FtlGetCapacity, .-FtlGetCapacity
3153
3388
 	.align	2
3154
3389
 	.global	ftl_get_density
3390
+	.syntax unified
3391
+	.arm
3392
+	.fpu softvfp
3155
3393
 	.type	ftl_get_density, %function
3156
3394
 ftl_get_density:
3157
3395
 	.fnstart
3158
3396
 	@ args = 0, pretend = 0, frame = 0
3159
3397
 	@ frame_needed = 0, uses_anonymous_args = 0
3160
3398
 	@ link register save eliminated.
3161
-	ldr	r3, .L529
3162
-	ldr	r0, [r3, #2428]
3399
+	ldr	r3, .L530
3400
+	ldr	r0, [r3, #2432]
3163
3401
 	bx	lr
3164
-.L530:
3402
+.L531:
3165
3403
 	.align	2
3166
-.L529:
3404
+.L530:
3167
3405
 	.word	.LANCHOR0
3168
3406
 	.fnend
3169
3407
 	.size	ftl_get_density, .-ftl_get_density
3170
3408
 	.align	2
3171
3409
 	.global	FtlGetLpn
3410
+	.syntax unified
3411
+	.arm
3412
+	.fpu softvfp
3172
3413
 	.type	FtlGetLpn, %function
3173
3414
 FtlGetLpn:
3174
3415
 	.fnstart
3175
3416
 	@ args = 0, pretend = 0, frame = 0
3176
3417
 	@ frame_needed = 0, uses_anonymous_args = 0
3177
3418
 	@ link register save eliminated.
3178
-	ldr	r3, .L532
3179
-	ldr	r0, [r3, #2448]
3419
+	ldr	r3, .L533
3420
+	ldr	r0, [r3, #2452]
3180
3421
 	bx	lr
3181
-.L533:
3422
+.L534:
3182
3423
 	.align	2
3183
-.L532:
3424
+.L533:
3184
3425
 	.word	.LANCHOR0
3185
3426
 	.fnend
3186
3427
 	.size	FtlGetLpn, .-FtlGetLpn
3187
3428
 	.align	2
3188
3429
 	.global	FtlBbmMapBadBlock
3430
+	.syntax unified
3431
+	.arm
3432
+	.fpu softvfp
3189
3433
 	.type	FtlBbmMapBadBlock, %function
3190
3434
 FtlBbmMapBadBlock:
3191
3435
 	.fnstart
3192
3436
 	@ args = 0, pretend = 0, frame = 0
3193
3437
 	@ frame_needed = 0, uses_anonymous_args = 0
3194
-	stmfd	sp!, {r0, r1, r4, r5, r6, lr}
3195
-	.save {r4, r5, r6, lr}
3196
-	.pad #8
3197
-	movw	r3, #2386
3198
-	ldr	r5, .L536
3199
-	mov	r6, r0
3200
-	ldrh	r4, [r5, r3]
3201
-	mov	r1, r4
3438
+	push	{r0, r1, r2, r4, r5, r6, r7, lr}
3439
+	.save {r4, r5, r6, r7, lr}
3440
+	.pad #12
3441
+	movw	r3, #2388
3442
+	ldr	r4, .L537
3443
+	mov	r5, r0
3444
+	ldrh	r7, [r4, r3]
3445
+	mov	r1, r7
3202
3446
 	bl	__aeabi_uidiv
3203
-	uxth	r2, r0
3204
-	smulbb	r3, r2, r4
3205
-	add	r1, r5, r2, asl #2
3206
-	mov	r4, #1
3207
-	ldr	ip, [r1, #2480]
3208
-	rsb	r3, r3, r6
3209
-	uxth	r3, r3
3210
-	and	r1, r3, #31
3211
-	mov	lr, r3, lsr #5
3212
-	ldr	r0, [ip, lr, asl #2]
3213
-	orr	r1, r0, r4, asl r1
3214
-	ldr	r0, .L536+4
3215
-	str	r1, [ip, lr, asl #2]
3216
-	str	r1, [sp]
3217
-	mov	r1, r6
3447
+	uxth	r6, r0
3448
+	mov	r1, r7
3449
+	mov	r0, r5
3450
+	bl	__aeabi_uidivmod
3451
+	add	r2, r4, r6, lsl #2
3452
+	uxth	r3, r1
3453
+	ldr	r2, [r2, #2484]
3454
+	lsr	r1, r3, #5
3455
+	and	ip, r3, #31
3456
+	mov	lr, #1
3457
+	ldr	r0, [r2, r1, lsl #2]
3458
+	orr	r0, r0, lr, lsl ip
3459
+	str	r0, [r2, r1, lsl #2]
3460
+	mov	r2, r6
3461
+	str	r0, [sp]
3462
+	mov	r1, r5
3463
+	ldr	r0, .L537+4
3218
3464
 	bl	printk
3219
-	add	r2, r5, #2448
3465
+	add	r3, r4, #2448
3220
3466
 	mov	r0, #0
3221
-	ldrh	r3, [r2, #10]
3222
-	add	r3, r3, r4
3223
-	strh	r3, [r2, #10]	@ movhi
3224
-	add	sp, sp, #8
3467
+	ldrh	r2, [r3, #14]
3468
+	add	r2, r2, #1
3469
+	strh	r2, [r3, #14]	@ movhi
3470
+	add	sp, sp, #12
3225
3471
 	@ sp needed
3226
-	ldmfd	sp!, {r4, r5, r6, pc}
3227
-.L537:
3472
+	pop	{r4, r5, r6, r7, pc}
3473
+.L538:
3228
3474
 	.align	2
3229
-.L536:
3475
+.L537:
3230
3476
 	.word	.LANCHOR0
3231
3477
 	.word	.LC2
3232
3478
 	.fnend
3233
3479
 	.size	FtlBbmMapBadBlock, .-FtlBbmMapBadBlock
3234
-	.global	__aeabi_uidivmod
3235
3480
 	.align	2
3236
3481
 	.global	FtlBbmIsBadBlock
3482
+	.syntax unified
3483
+	.arm
3484
+	.fpu softvfp
3237
3485
 	.type	FtlBbmIsBadBlock, %function
3238
3486
 FtlBbmIsBadBlock:
3239
3487
 	.fnstart
3240
3488
 	@ args = 0, pretend = 0, frame = 0
3241
3489
 	@ frame_needed = 0, uses_anonymous_args = 0
3242
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
3243
-	.save {r3, r4, r5, r6, r7, lr}
3244
-	movw	r3, #2386
3245
-	ldr	r5, .L540
3490
+	push	{r4, r5, r6, r7, r8, lr}
3491
+	.save {r4, r5, r6, r7, r8, lr}
3492
+	movw	r3, #2388
3493
+	ldr	r5, .L541
3246
3494
 	mov	r7, r0
3247
3495
 	ldrh	r6, [r5, r3]
3248
3496
 	mov	r1, r6
..
..
@@ -3251,23 +3499,26 @@
3251
3499
 	uxth	r4, r1
3252
3500
 	mov	r1, r6
3253
3501
 	bl	__aeabi_uidiv
3254
-	mov	r2, r4, lsr #5
3255
-	and	r4, r4, #31
3256
3502
 	uxth	r0, r0
3257
-	add	r5, r5, r0, asl #2
3258
-	ldr	r3, [r5, #2480]
3259
-	ldr	r0, [r3, r2, asl #2]
3260
-	mov	r0, r0, lsr r4
3503
+	lsr	r2, r4, #5
3504
+	add	r5, r5, r0, lsl #2
3505
+	and	r4, r4, #31
3506
+	ldr	r3, [r5, #2484]
3507
+	ldr	r0, [r3, r2, lsl #2]
3508
+	lsr	r0, r0, r4
3261
3509
 	and	r0, r0, #1
3262
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
3263
-.L541:
3510
+	pop	{r4, r5, r6, r7, r8, pc}
3511
+.L542:
3264
3512
 	.align	2
3265
-.L540:
3513
+.L541:
3266
3514
 	.word	.LANCHOR0
3267
3515
 	.fnend
3268
3516
 	.size	FtlBbmIsBadBlock, .-FtlBbmIsBadBlock
3269
3517
 	.align	2
3270
3518
 	.global	FtlBbtInfoPrint
3519
+	.syntax unified
3520
+	.arm
3521
+	.fpu softvfp
3271
3522
 	.type	FtlBbtInfoPrint, %function
3272
3523
 FtlBbtInfoPrint:
3273
3524
 	.fnstart
..
..
@@ -3279,34 +3530,37 @@
3279
3530
 	.size	FtlBbtInfoPrint, .-FtlBbtInfoPrint
3280
3531
 	.align	2
3281
3532
 	.global	FtlBbtCalcTotleCnt
3533
+	.syntax unified
3534
+	.arm
3535
+	.fpu softvfp
3282
3536
 	.type	FtlBbtCalcTotleCnt, %function
3283
3537
 FtlBbtCalcTotleCnt:
3284
3538
 	.fnstart
3285
3539
 	@ args = 0, pretend = 0, frame = 0
3286
3540
 	@ frame_needed = 0, uses_anonymous_args = 0
3287
-	stmfd	sp!, {r4, r5, r6, lr}
3541
+	ldr	r3, .L552
3542
+	movw	r2, #2388
3543
+	movw	r1, #2346
3544
+	push	{r4, r5, r6, lr}
3288
3545
 	.save {r4, r5, r6, lr}
3289
-	movw	r3, #2386
3290
-	ldr	r4, .L552
3291
3546
 	mov	r5, #0
3292
-	ldrh	r6, [r4, r3]
3293
-	movw	r3, #2342
3294
-	ldrh	r3, [r4, r3]
3295
3547
 	mov	r4, r5
3296
-	mul	r6, r3, r6
3297
-.L544:
3548
+	ldrh	r2, [r3, r2]
3549
+	ldrh	r6, [r3, r1]
3550
+	mul	r6, r6, r2
3551
+.L545:
3298
3552
 	uxth	r0, r5
3299
3553
 	cmp	r0, r6
3300
-	bge	.L551
3554
+	blt	.L547
3555
+	mov	r0, r4
3556
+	pop	{r4, r5, r6, pc}
3557
+.L547:
3301
3558
 	bl	FtlBbmIsBadBlock
3302
-	add	r5, r5, #1
3303
3559
 	cmp	r0, #0
3560
+	add	r5, r5, #1
3304
3561
 	addne	r4, r4, #1
3305
3562
 	uxthne	r4, r4
3306
-	b	.L544
3307
-.L551:
3308
-	mov	r0, r4
3309
-	ldmfd	sp!, {r4, r5, r6, pc}
3563
+	b	.L545
3310
3564
 .L553:
3311
3565
 	.align	2
3312
3566
 .L552:
..
..
@@ -3315,29 +3569,34 @@
3315
3569
 	.size	FtlBbtCalcTotleCnt, .-FtlBbtCalcTotleCnt
3316
3570
 	.align	2
3317
3571
 	.global	V2P_block
3572
+	.syntax unified
3573
+	.arm
3574
+	.fpu softvfp
3318
3575
 	.type	V2P_block, %function
3319
3576
 V2P_block:
3320
3577
 	.fnstart
3321
3578
 	@ args = 0, pretend = 0, frame = 0
3322
3579
 	@ frame_needed = 0, uses_anonymous_args = 0
3323
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
3324
-	.save {r3, r4, r5, r6, r7, lr}
3325
-	movw	r3, #2344
3326
-	ldr	r6, .L556
3327
-	mov	r4, r1
3580
+	push	{r4, r5, r6, r7, r8, lr}
3581
+	.save {r4, r5, r6, r7, r8, lr}
3582
+	movw	r3, #2348
3583
+	ldr	r4, .L556
3584
+	mov	r5, r1
3328
3585
 	mov	r7, r0
3329
-	ldrh	r5, [r6, r3]
3330
-	mov	r1, r5
3331
-	bl	__aeabi_uidivmod
3332
-	mov	r0, r7
3333
-	smlabb	r4, r4, r5, r1
3334
-	mov	r1, r5
3586
+	ldrh	r6, [r4, r3]
3587
+	mov	r1, r6
3335
3588
 	bl	__aeabi_uidiv
3336
-	movw	r3, #2386
3337
-	ldrh	r3, [r6, r3]
3338
-	smlabb	r0, r3, r0, r4
3589
+	movw	r3, #2388
3590
+	smulbb	r5, r6, r5
3591
+	ldrh	r4, [r4, r3]
3592
+	mov	r1, r6
3593
+	smulbb	r4, r4, r0
3594
+	mov	r0, r7
3595
+	bl	__aeabi_uidivmod
3596
+	add	r0, r5, r1
3597
+	add	r0, r4, r0
3339
3598
 	uxth	r0, r0
3340
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
3599
+	pop	{r4, r5, r6, r7, r8, pc}
3341
3600
 .L557:
3342
3601
 	.align	2
3343
3602
 .L556:
..
..
@@ -3346,18 +3605,21 @@
3346
3605
 	.size	V2P_block, .-V2P_block
3347
3606
 	.align	2
3348
3607
 	.global	P2V_plane
3608
+	.syntax unified
3609
+	.arm
3610
+	.fpu softvfp
3349
3611
 	.type	P2V_plane, %function
3350
3612
 P2V_plane:
3351
3613
 	.fnstart
3352
3614
 	@ args = 0, pretend = 0, frame = 0
3353
3615
 	@ frame_needed = 0, uses_anonymous_args = 0
3354
3616
 	ldr	r3, .L560
3355
-	movw	r2, #2344
3356
-	stmfd	sp!, {r4, r5, r6, lr}
3617
+	movw	r2, #2348
3618
+	push	{r4, r5, r6, lr}
3357
3619
 	.save {r4, r5, r6, lr}
3358
3620
 	mov	r6, r0
3359
3621
 	ldrh	r5, [r3, r2]
3360
-	movw	r2, #2386
3622
+	movw	r2, #2388
3361
3623
 	ldrh	r1, [r3, r2]
3362
3624
 	bl	__aeabi_uidiv
3363
3625
 	mov	r1, r5
..
..
@@ -3366,7 +3628,7 @@
3366
3628
 	bl	__aeabi_uidivmod
3367
3629
 	add	r1, r4, r1
3368
3630
 	uxth	r0, r1
3369
-	ldmfd	sp!, {r4, r5, r6, pc}
3631
+	pop	{r4, r5, r6, pc}
3370
3632
 .L561:
3371
3633
 	.align	2
3372
3634
 .L560:
..
..
@@ -3375,23 +3637,26 @@
3375
3637
 	.size	P2V_plane, .-P2V_plane
3376
3638
 	.align	2
3377
3639
 	.global	P2V_block_in_plane
3640
+	.syntax unified
3641
+	.arm
3642
+	.fpu softvfp
3378
3643
 	.type	P2V_block_in_plane, %function
3379
3644
 P2V_block_in_plane:
3380
3645
 	.fnstart
3381
3646
 	@ args = 0, pretend = 0, frame = 0
3382
3647
 	@ frame_needed = 0, uses_anonymous_args = 0
3383
-	stmfd	sp!, {r4, lr}
3648
+	push	{r4, lr}
3384
3649
 	.save {r4, lr}
3385
-	movw	r3, #2386
3650
+	movw	r3, #2388
3386
3651
 	ldr	r4, .L564
3387
3652
 	ldrh	r1, [r4, r3]
3388
3653
 	bl	__aeabi_uidivmod
3389
-	movw	r3, #2344
3654
+	movw	r3, #2348
3390
3655
 	uxth	r0, r1
3391
3656
 	ldrh	r1, [r4, r3]
3392
3657
 	bl	__aeabi_uidiv
3393
3658
 	uxth	r0, r0
3394
-	ldmfd	sp!, {r4, pc}
3659
+	pop	{r4, pc}
3395
3660
 .L565:
3396
3661
 	.align	2
3397
3662
 .L564:
..
..
@@ -3400,6 +3665,9 @@
3400
3665
 	.size	P2V_block_in_plane, .-P2V_block_in_plane
3401
3666
 	.align	2
3402
3667
 	.global	ftl_cmp_data_ver
3668
+	.syntax unified
3669
+	.arm
3670
+	.fpu softvfp
3403
3671
 	.type	ftl_cmp_data_ver, %function
3404
3672
 ftl_cmp_data_ver:
3405
3673
 	.fnstart
..
..
@@ -3408,13 +3676,13 @@
3408
3676
 	@ link register save eliminated.
3409
3677
 	cmp	r0, r1
3410
3678
 	bls	.L567
3411
-	rsb	r0, r1, r0
3679
+	sub	r0, r0, r1
3412
3680
 	cmp	r0, #-2147483648
3413
3681
 	movhi	r0, #0
3414
3682
 	movls	r0, #1
3415
3683
 	bx	lr
3416
3684
 .L567:
3417
-	rsb	r0, r0, r1
3685
+	sub	r0, r1, r0
3418
3686
 	cmp	r0, #-2147483648
3419
3687
 	movls	r0, #0
3420
3688
 	movhi	r0, #1
..
..
@@ -3423,6 +3691,9 @@
3423
3691
 	.size	ftl_cmp_data_ver, .-ftl_cmp_data_ver
3424
3692
 	.align	2
3425
3693
 	.global	FtlFreeSysBlkQueueEmpty
3694
+	.syntax unified
3695
+	.arm
3696
+	.fpu softvfp
3426
3697
 	.type	FtlFreeSysBlkQueueEmpty, %function
3427
3698
 FtlFreeSysBlkQueueEmpty:
3428
3699
 	.fnstart
..
..
@@ -3432,16 +3703,19 @@
3432
3703
 	ldr	r3, .L570
3433
3704
 	ldrh	r0, [r3, #6]
3434
3705
 	clz	r0, r0
3435
-	mov	r0, r0, lsr #5
3706
+	lsr	r0, r0, #5
3436
3707
 	bx	lr
3437
3708
 .L571:
3438
3709
 	.align	2
3439
3710
 .L570:
3440
-	.word	.LANCHOR0+2512
3711
+	.word	.LANCHOR0+2516
3441
3712
 	.fnend
3442
3713
 	.size	FtlFreeSysBlkQueueEmpty, .-FtlFreeSysBlkQueueEmpty
3443
3714
 	.align	2
3444
3715
 	.global	FtlFreeSysBlkQueueFull
3716
+	.syntax unified
3717
+	.arm
3718
+	.fpu softvfp
3445
3719
 	.type	FtlFreeSysBlkQueueFull, %function
3446
3720
 FtlFreeSysBlkQueueFull:
3447
3721
 	.fnstart
..
..
@@ -3452,291 +3726,307 @@
3452
3726
 	ldrh	r0, [r3, #6]
3453
3727
 	sub	r0, r0, #1024
3454
3728
 	clz	r0, r0
3455
-	mov	r0, r0, lsr #5
3729
+	lsr	r0, r0, #5
3456
3730
 	bx	lr
3457
3731
 .L574:
3458
3732
 	.align	2
3459
3733
 .L573:
3460
-	.word	.LANCHOR0+2512
3734
+	.word	.LANCHOR0+2516
3461
3735
 	.fnend
3462
3736
 	.size	FtlFreeSysBlkQueueFull, .-FtlFreeSysBlkQueueFull
3463
3737
 	.align	2
3464
3738
 	.global	FtlFreeSysBlkQueueIn
3739
+	.syntax unified
3740
+	.arm
3741
+	.fpu softvfp
3465
3742
 	.type	FtlFreeSysBlkQueueIn, %function
3466
3743
 FtlFreeSysBlkQueueIn:
3467
3744
 	.fnstart
3468
3745
 	@ args = 0, pretend = 0, frame = 0
3469
3746
 	@ frame_needed = 0, uses_anonymous_args = 0
3470
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
3471
-	.save {r3, r4, r5, r6, r7, lr}
3472
3747
 	sub	r3, r0, #1
3473
3748
 	movw	r2, #65533
3474
-	mov	r7, r0
3475
3749
 	uxth	r3, r3
3476
3750
 	cmp	r3, r2
3477
-	ldmhifd	sp!, {r3, r4, r5, r6, r7, pc}
3478
-	ldr	r4, .L585
3751
+	bxhi	lr
3752
+	push	{r4, r5, r6, r7, r8, lr}
3753
+	.save {r4, r5, r6, r7, r8, lr}
3754
+	ldr	r4, .L588
3479
3755
 	ldrh	r3, [r4, #6]
3480
3756
 	cmp	r3, #1024
3481
-	ldmeqfd	sp!, {r3, r4, r5, r6, r7, pc}
3757
+	popeq	{r4, r5, r6, r7, r8, pc}
3482
3758
 	cmp	r1, #0
3759
+	mov	r5, r0
3483
3760
 	beq	.L577
3484
-	ldr	r5, .L585+4
3485
-	ldr	r3, [r5, #-3616]
3761
+	ldr	r6, .L588+4
3762
+	ldr	r3, [r6, #-3612]
3486
3763
 	cmp	r3, #0
3487
3764
 	bne	.L577
3488
3765
 	bl	P2V_block_in_plane
3489
-	mov	r1, #1
3490
-	mov	r3, r7, asl #10
3491
-	mov	r2, r1
3492
-	mov	r6, r0
3493
-	ldr	r0, [r5, #-3612]
3766
+	mov	r7, r0
3767
+	ldr	r0, [r6, #-3608]
3768
+	lsl	r3, r5, #10
3769
+	mov	r2, #1
3770
+	mov	r1, r2
3494
3771
 	str	r3, [r0, #4]
3495
3772
 	bl	FlashEraseBlocks
3496
-	ldr	r1, [r5, #-3608]
3497
-	mov	r3, r6, asl #1
3498
-	ldrh	r2, [r1, r3]
3499
-	add	r2, r2, #1
3500
-	strh	r2, [r1, r3]	@ movhi
3501
-	ldr	r3, [r5, #-3604]
3773
+	ldr	r2, [r6, #-3604]
3774
+	lsl	r0, r7, #1
3775
+	ldrh	r3, [r2, r0]
3502
3776
 	add	r3, r3, #1
3503
-	str	r3, [r5, #-3604]
3777
+	strh	r3, [r2, r0]	@ movhi
3778
+	ldr	r3, [r6, #-3600]
3779
+	add	r3, r3, #1
3780
+	str	r3, [r6, #-3600]
3504
3781
 .L577:
3505
3782
 	ldrh	r3, [r4, #6]
3506
3783
 	add	r3, r3, #1
3507
3784
 	strh	r3, [r4, #6]	@ movhi
3508
3785
 	ldrh	r3, [r4, #4]
3509
-	add	r2, r4, r3, asl #1
3786
+	add	r2, r4, r3, lsl #1
3510
3787
 	add	r3, r3, #1
3511
3788
 	ubfx	r3, r3, #0, #10
3789
+	strh	r5, [r2, #8]	@ movhi
3512
3790
 	strh	r3, [r4, #4]	@ movhi
3513
-	strh	r7, [r2, #8]	@ movhi
3514
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
3515
-.L586:
3791
+	pop	{r4, r5, r6, r7, r8, pc}
3792
+.L589:
3516
3793
 	.align	2
3517
-.L585:
3518
-	.word	.LANCHOR0+2512
3794
+.L588:
3795
+	.word	.LANCHOR0+2516
3519
3796
 	.word	.LANCHOR2
3520
3797
 	.fnend
3521
3798
 	.size	FtlFreeSysBlkQueueIn, .-FtlFreeSysBlkQueueIn
3522
3799
 	.align	2
3523
3800
 	.global	FtlFreeSysBLkSort
3801
+	.syntax unified
3802
+	.arm
3803
+	.fpu softvfp
3524
3804
 	.type	FtlFreeSysBLkSort, %function
3525
3805
 FtlFreeSysBLkSort:
3526
3806
 	.fnstart
3527
3807
 	@ args = 0, pretend = 0, frame = 0
3528
3808
 	@ frame_needed = 0, uses_anonymous_args = 0
3529
-	ldr	r3, .L600
3530
-	ldrh	ip, [r3, #28]
3531
-	ldr	r3, .L600+4
3809
+	ldr	r3, .L603
3532
3810
 	ldrh	r2, [r3, #6]
3533
3811
 	cmp	r2, #0
3534
3812
 	bxeq	lr
3535
-	stmfd	sp!, {r4, lr}
3536
-	.save {r4, lr}
3813
+	ldr	r2, .L603+4
3537
3814
 	mov	r0, #0
3538
-	ldrh	r1, [r3, #2]
3539
-	and	ip, ip, #31
3540
-	ldrh	r2, [r3, #4]
3815
+	push	{r4, lr}
3816
+	.save {r4, lr}
3541
3817
 	mov	r4, r0
3542
-.L589:
3543
-	uxth	lr, r0
3818
+	ldrh	r1, [r3, #2]
3819
+	ldrh	lr, [r2, #28]
3820
+	ldrh	r2, [r3, #4]
3821
+	and	lr, lr, #31
3822
+.L592:
3823
+	uxth	ip, r0
3544
3824
 	add	r0, r0, #1
3545
3825
 	cmp	lr, ip
3546
-	bge	.L599
3547
-	add	lr, r3, r1, asl #1
3826
+	bgt	.L593
3827
+	cmp	r4, #0
3828
+	strhne	r1, [r3, #2]	@ movhi
3829
+	strhne	r2, [r3, #4]	@ movhi
3830
+	pop	{r4, pc}
3831
+.L593:
3832
+	add	ip, r3, r1, lsl #1
3548
3833
 	add	r1, r1, #1
3549
3834
 	ubfx	r1, r1, #0, #10
3550
-	ldrh	r4, [lr, #8]
3551
-	add	lr, r3, r2, asl #1
3552
-	strh	r4, [lr, #8]	@ movhi
3835
+	ldrh	r4, [ip, #8]
3836
+	add	ip, r3, r2, lsl #1
3837
+	strh	r4, [ip, #8]	@ movhi
3553
3838
 	mov	r4, #1
3554
3839
 	add	r2, r2, r4
3555
3840
 	ubfx	r2, r2, #0, #10
3556
-	b	.L589
3557
-.L599:
3558
-	cmp	r4, #0
3559
-	strneh	r1, [r3, #2]	@ movhi
3560
-	strneh	r2, [r3, #4]	@ movhi
3561
-	ldmfd	sp!, {r4, pc}
3562
-.L601:
3841
+	b	.L592
3842
+.L604:
3563
3843
 	.align	2
3564
-.L600:
3565
-	.word	.LANCHOR2-3600
3566
-	.word	.LANCHOR0+2512
3844
+.L603:
3845
+	.word	.LANCHOR0+2516
3846
+	.word	.LANCHOR2-3596
3567
3847
 	.fnend
3568
3848
 	.size	FtlFreeSysBLkSort, .-FtlFreeSysBLkSort
3569
3849
 	.align	2
3570
3850
 	.global	FtlFreeSysBlkQueueOut
3851
+	.syntax unified
3852
+	.arm
3853
+	.fpu softvfp
3571
3854
 	.type	FtlFreeSysBlkQueueOut, %function
3572
3855
 FtlFreeSysBlkQueueOut:
3573
3856
 	.fnstart
3574
3857
 	@ args = 0, pretend = 0, frame = 0
3575
3858
 	@ frame_needed = 0, uses_anonymous_args = 0
3576
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
3859
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
3577
3860
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
3578
-	ldr	r7, .L613
3579
-	add	r4, r7, #2512
3580
-	mov	r8, r4
3581
-.L603:
3861
+	ldr	r4, .L616
3862
+	ldr	r8, .L616+4
3863
+	mov	r7, r4
3864
+.L606:
3582
3865
 	ldrh	r1, [r4, #6]
3583
3866
 	cmp	r1, #0
3584
-	beq	.L604
3585
-	ldr	r5, .L613+4
3867
+	beq	.L607
3868
+	ldr	r5, .L616+8
3586
3869
 	sub	r1, r1, #1
3587
3870
 	ldrh	r3, [r4, #2]
3588
3871
 	strh	r1, [r4, #6]	@ movhi
3589
-	ldr	r10, [r5, #-3616]
3590
-	add	r2, r4, r3, asl #1
3872
+	ldr	r10, [r5, #-3612]
3873
+	add	r2, r4, r3, lsl #1
3591
3874
 	add	r3, r3, #1
3592
3875
 	cmp	r10, #0
3593
3876
 	ubfx	r3, r3, #0, #10
3594
3877
 	ldrh	r6, [r2, #8]
3595
3878
 	strh	r3, [r4, #2]	@ movhi
3596
-	bne	.L605
3879
+	bne	.L608
3597
3880
 	mov	r0, r6
3598
3881
 	bl	P2V_block_in_plane
3599
-	mov	r3, r6, asl #10
3600
3882
 	mov	r9, r0
3601
-	ldr	r0, [r5, #-3612]
3883
+	ldr	r0, [r5, #-3608]
3884
+	lsl	r3, r6, #10
3602
3885
 	str	r3, [r0, #4]
3603
-	ldrb	r3, [r7, #144]	@ zero_extendqisi2
3886
+	ldrb	r3, [r8, #152]	@ zero_extendqisi2
3604
3887
 	cmp	r3, #0
3605
-	beq	.L606
3606
-	mov	r1, r10
3888
+	beq	.L609
3607
3889
 	mov	r2, #1
3890
+	mov	r1, r10
3608
3891
 	bl	FlashEraseBlocks
3609
-.L606:
3610
-	mov	r1, #1
3611
-	ldr	r0, [r5, #-3612]
3612
-	mov	r2, r1
3892
+.L609:
3893
+	mov	r2, #1
3894
+	ldr	r0, [r5, #-3608]
3895
+	mov	r1, r2
3613
3896
 	bl	FlashEraseBlocks
3614
-	ldr	r1, [r5, #-3608]
3615
-	mov	r3, r9, asl #1
3616
-	ldrh	r2, [r1, r3]
3617
-	add	r2, r2, #1
3618
-	strh	r2, [r1, r3]	@ movhi
3619
-	ldr	r3, [r5, #-3604]
3897
+	ldr	r2, [r5, #-3604]
3898
+	lsl	r0, r9, #1
3899
+	ldrh	r3, [r2, r0]
3620
3900
 	add	r3, r3, #1
3621
-	str	r3, [r5, #-3604]
3622
-	b	.L605
3623
-.L604:
3624
-	ldr	r0, .L613+8
3625
-	bl	printk
3626
-.L607:
3627
-	b	.L607
3628
-.L605:
3901
+	strh	r3, [r2, r0]	@ movhi
3902
+	ldr	r3, [r5, #-3600]
3903
+	add	r3, r3, #1
3904
+	str	r3, [r5, #-3600]
3905
+.L608:
3629
3906
 	sub	r3, r6, #1
3630
3907
 	movw	r2, #65533
3631
3908
 	uxth	r3, r3
3632
3909
 	cmp	r3, r2
3633
-	bls	.L608
3910
+	bls	.L611
3911
+	ldrh	r2, [r7, #6]
3634
3912
 	mov	r1, r6
3635
-	ldrh	r2, [r8, #6]
3636
-	ldr	r0, .L613+12
3913
+	ldr	r0, .L616+12
3637
3914
 	bl	printk
3638
-	b	.L603
3639
-.L608:
3915
+	b	.L606
3916
+.L607:
3917
+	ldr	r0, .L616+16
3918
+	bl	printk
3919
+.L610:
3920
+	b	.L610
3921
+.L611:
3640
3922
 	mov	r0, r6
3641
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
3642
-.L614:
3923
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
3924
+.L617:
3643
3925
 	.align	2
3644
-.L613:
3926
+.L616:
3927
+	.word	.LANCHOR0+2516
3645
3928
 	.word	.LANCHOR0
3646
3929
 	.word	.LANCHOR2
3647
-	.word	.LC3
3648
3930
 	.word	.LC4
3931
+	.word	.LC3
3649
3932
 	.fnend
3650
3933
 	.size	FtlFreeSysBlkQueueOut, .-FtlFreeSysBlkQueueOut
3651
3934
 	.align	2
3652
3935
 	.global	test_node_in_list
3936
+	.syntax unified
3937
+	.arm
3938
+	.fpu softvfp
3653
3939
 	.type	test_node_in_list, %function
3654
3940
 test_node_in_list:
3655
3941
 	.fnstart
3656
3942
 	@ args = 0, pretend = 0, frame = 0
3657
3943
 	@ frame_needed = 0, uses_anonymous_args = 0
3658
-	ldr	r3, .L621
3944
+	ldr	r3, .L624
3659
3945
 	str	lr, [sp, #-4]!
3660
3946
 	.save {lr}
3661
3947
 	movw	lr, #65535
3662
-	ldr	ip, [r3, #-3552]
3663
3948
 	ldr	r2, [r0]
3664
-	ldr	r3, .L621+4
3665
-	rsb	r0, ip, r2
3666
-	mov	r0, r0, asr #1
3949
+	ldr	ip, [r3, #-3548]
3950
+	sub	r3, r2, ip
3951
+	asr	r0, r3, #1
3952
+	ldr	r3, .L624+4
3667
3953
 	mul	r3, r3, r0
3668
3954
 	mov	r0, #6
3669
3955
 	uxth	r3, r3
3670
-.L617:
3671
-	cmp	r1, r3
3672
-	beq	.L618
3956
+.L620:
3957
+	cmp	r3, r1
3958
+	beq	.L621
3673
3959
 	ldrh	r3, [r2]
3674
3960
 	cmp	r3, lr
3675
-	beq	.L619
3961
+	beq	.L622
3676
3962
 	mla	r2, r0, r3, ip
3677
-	b	.L617
3678
-.L618:
3963
+	b	.L620
3964
+.L621:
3679
3965
 	mov	r0, #1
3680
3966
 	ldr	pc, [sp], #4
3681
-.L619:
3967
+.L622:
3682
3968
 	mov	r0, #0
3683
3969
 	ldr	pc, [sp], #4
3684
-.L622:
3970
+.L625:
3685
3971
 	.align	2
3686
-.L621:
3972
+.L624:
3687
3973
 	.word	.LANCHOR2
3688
3974
 	.word	-1431655765
3689
3975
 	.fnend
3690
3976
 	.size	test_node_in_list, .-test_node_in_list
3691
3977
 	.align	2
3692
3978
 	.global	insert_data_list
3979
+	.syntax unified
3980
+	.arm
3981
+	.fpu softvfp
3693
3982
 	.type	insert_data_list, %function
3694
3983
 insert_data_list:
3695
3984
 	.fnstart
3696
3985
 	@ args = 0, pretend = 0, frame = 8
3697
3986
 	@ frame_needed = 0, uses_anonymous_args = 0
3698
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
3987
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
3699
3988
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
3700
3989
 	.pad #12
3701
-	movw	r3, #2328
3702
-	ldr	r5, .L640
3703
-	ldrh	r3, [r5, r3]
3990
+	movw	r3, #2332
3991
+	ldr	r4, .L642
3992
+	ldrh	r3, [r4, r3]
3704
3993
 	cmp	r3, r0
3705
-	bls	.L625
3706
-	ldr	r2, .L640+4
3994
+	bls	.L628
3995
+	ldr	r2, .L642+4
3707
3996
 	mov	lr, #6
3708
3997
 	mul	lr, lr, r0
3709
3998
 	mvn	ip, #0
3710
-	ldr	r6, [r2, #-3552]
3711
-	mov	r10, r2
3999
+	ldr	r6, [r2, #-3548]
4000
+	mov	r5, r2
3712
4001
 	add	r1, r6, lr
3713
4002
 	strh	ip, [r1, #2]	@ movhi
3714
4003
 	strh	ip, [r6, lr]	@ movhi
3715
-	ldr	r3, [r2, #-3548]
4004
+	ldr	r3, [r2, #-3544]
3716
4005
 	cmp	r3, #0
3717
-	beq	.L639
3718
-	ldr	r8, [r2, #-3544]
3719
-	mov	r4, r0, asl #1
4006
+	streq	r1, [r2, #-3544]
4007
+	beq	.L628
4008
+	ldr	r8, [r2, #-3540]
4009
+	lsl	r10, r0, #1
3720
4010
 	ldrh	r2, [r1, #4]
3721
-	ldrh	r7, [r8, r4]
4011
+	ldrh	r7, [r8, r10]
3722
4012
 	cmp	r2, #0
3723
4013
 	mulne	ip, r2, r7
3724
-	ldr	r7, [r10, #-3552]
3725
-	ldr	r2, .L640+8
3726
-	rsb	r9, r7, r3
3727
-	mov	r9, r9, asr #1
4014
+	ldr	r7, [r5, #-3548]
4015
+	sub	r2, r3, r7
4016
+	asr	r9, r2, #1
4017
+	ldr	r2, .L642+8
3728
4018
 	mul	r2, r2, r9
3729
-	movw	r9, #2328
3730
-	ldrh	r5, [r5, r9]
3731
-	ldr	r9, [r10, #-3608]
3732
-	add	r4, r9, r4
3733
-	str	r4, [sp, #4]
4019
+	movw	r9, #2332
4020
+	ldrh	r4, [r4, r9]
4021
+	ldr	r9, [r5, #-3604]
4022
+	str	r4, [sp]
3734
4023
 	uxth	r2, r2
4024
+	add	r4, r9, r10
4025
+	str	r4, [sp, #4]
3735
4026
 	mov	r4, #0
3736
-	str	r5, [sp]
3737
-.L634:
3738
-	add	r4, r4, #1
4027
+.L637:
3739
4028
 	ldr	r5, [sp]
4029
+	add	r4, r4, #1
3740
4030
 	uxth	r4, r4
3741
4031
 	cmp	r4, r5
3742
4032
 	movls	r5, #0
..
..
@@ -3744,64 +4034,60 @@
3744
4034
 	cmp	r0, r2
3745
4035
 	orreq	r5, r5, #1
3746
4036
 	cmp	r5, #0
3747
-	bne	.L625
3748
-	mov	r10, r2, asl #1
4037
+	bne	.L628
4038
+	lsl	r10, r2, #1
3749
4039
 	ldrh	r5, [r3, #4]
3750
4040
 	ldrh	fp, [r8, r10]
3751
4041
 	cmp	r5, #0
3752
4042
 	mvneq	r5, #0
3753
4043
 	mulne	r5, r5, fp
3754
-	cmp	r5, ip
3755
-	bne	.L630
4044
+	cmp	ip, r5
4045
+	bne	.L633
3756
4046
 	ldr	r5, [sp, #4]
3757
4047
 	ldrh	r10, [r9, r10]
3758
4048
 	ldrh	r5, [r5]
3759
4049
 	cmp	r10, r5
3760
-	bcc	.L632
3761
-	b	.L631
3762
-.L630:
3763
-	bhi	.L631
3764
-.L632:
4050
+	bcc	.L635
4051
+.L634:
4052
+	strh	r2, [r6, lr]	@ movhi
4053
+	ldr	ip, .L642+4
4054
+	ldrh	r2, [r3, #2]
4055
+	strh	r2, [r1, #2]	@ movhi
4056
+	ldr	r2, [ip, #-3544]
4057
+	cmp	r3, r2
4058
+	ldrhne	lr, [r3, #2]
4059
+	movne	r2, #6
4060
+	ldrne	r1, [ip, #-3548]
4061
+	strheq	r0, [r3, #2]	@ movhi
4062
+	streq	r1, [ip, #-3544]
4063
+	mulne	r2, r2, lr
4064
+	strhne	r0, [r1, r2]	@ movhi
4065
+	strhne	r0, [r3, #2]	@ movhi
4066
+	b	.L628
4067
+.L633:
4068
+	bcc	.L634
4069
+.L635:
3765
4070
 	ldrh	r5, [r3]
3766
4071
 	movw	r10, #65535
3767
4072
 	cmp	r5, r10
3768
-	streqh	r2, [r1, #2]	@ movhi
3769
-	streqh	r0, [r3]	@ movhi
3770
-	ldreq	r3, .L640+4
3771
-	streq	r1, [r3, #-3540]
3772
-	beq	.L625
3773
-.L633:
3774
-	mov	r3, #6
3775
-	mov	r2, r5
3776
-	mla	r3, r3, r5, r7
3777
-	b	.L634
3778
-.L631:
3779
-	strh	r2, [r6, lr]	@ movhi
3780
-	ldrh	r2, [r3, #2]
4073
+	bne	.L636
3781
4074
 	strh	r2, [r1, #2]	@ movhi
3782
-	ldr	r2, .L640+4
3783
-	ldr	ip, [r2, #-3548]
3784
-	cmp	r3, ip
3785
-	bne	.L635
3786
-	strh	r0, [r3, #2]	@ movhi
3787
-.L639:
3788
-	str	r1, [r2, #-3548]
3789
-	b	.L625
3790
-.L635:
3791
-	ldrh	ip, [r3, #2]
3792
-	ldr	r1, [r2, #-3552]
3793
-	mov	r2, #6
3794
-	mul	r2, r2, ip
3795
-	strh	r0, [r1, r2]	@ movhi
3796
-	strh	r0, [r3, #2]	@ movhi
3797
-.L625:
4075
+	strh	r0, [r3]	@ movhi
4076
+	ldr	r3, .L642+4
4077
+	str	r1, [r3, #-3536]
4078
+.L628:
3798
4079
 	mov	r0, #0
3799
4080
 	add	sp, sp, #12
3800
4081
 	@ sp needed
3801
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
3802
-.L641:
4082
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
4083
+.L636:
4084
+	mov	r3, #6
4085
+	mov	r2, r5
4086
+	mla	r3, r3, r5, r7
4087
+	b	.L637
4088
+.L643:
3803
4089
 	.align	2
3804
-.L640:
4090
+.L642:
3805
4091
 	.word	.LANCHOR0
3806
4092
 	.word	.LANCHOR2
3807
4093
 	.word	-1431655765
..
..
@@ -3809,180 +4095,193 @@
3809
4095
 	.size	insert_data_list, .-insert_data_list
3810
4096
 	.align	2
3811
4097
 	.global	INSERT_DATA_LIST
4098
+	.syntax unified
4099
+	.arm
4100
+	.fpu softvfp
3812
4101
 	.type	INSERT_DATA_LIST, %function
3813
4102
 INSERT_DATA_LIST:
3814
4103
 	.fnstart
3815
4104
 	@ args = 0, pretend = 0, frame = 0
3816
4105
 	@ frame_needed = 0, uses_anonymous_args = 0
3817
-	stmfd	sp!, {r3, lr}
3818
-	.save {r3, lr}
4106
+	push	{r4, lr}
4107
+	.save {r4, lr}
3819
4108
 	bl	insert_data_list
3820
-	ldr	r2, .L644
3821
-	ldrh	r3, [r2]
4109
+	ldr	r2, .L646
4110
+	ldrh	r3, [r2, #-12]
3822
4111
 	add	r3, r3, #1
3823
-	strh	r3, [r2]	@ movhi
3824
-	ldmfd	sp!, {r3, pc}
3825
-.L645:
4112
+	strh	r3, [r2, #-12]	@ movhi
4113
+	pop	{r4, pc}
4114
+.L647:
3826
4115
 	.align	2
3827
-.L644:
3828
-	.word	.LANCHOR2-3536
4116
+.L646:
4117
+	.word	.LANCHOR2-3520
3829
4118
 	.fnend
3830
4119
 	.size	INSERT_DATA_LIST, .-INSERT_DATA_LIST
3831
4120
 	.align	2
3832
4121
 	.global	insert_free_list
4122
+	.syntax unified
4123
+	.arm
4124
+	.fpu softvfp
3833
4125
 	.type	insert_free_list, %function
3834
4126
 insert_free_list:
3835
4127
 	.fnstart
3836
4128
 	@ args = 0, pretend = 0, frame = 0
3837
4129
 	@ frame_needed = 0, uses_anonymous_args = 0
3838
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
4130
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
3839
4131
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
3840
4132
 	movw	r4, #65535
3841
4133
 	cmp	r0, r4
3842
-	beq	.L647
3843
-	ldr	r2, .L655
3844
-	mov	lr, #6
3845
-	mul	r6, lr, r0
4134
+	beq	.L649
4135
+	ldr	r2, .L656
4136
+	mov	r1, #6
4137
+	mul	r5, r1, r0
3846
4138
 	mvn	r3, #0
3847
-	ldr	r7, [r2, #-3552]
3848
-	mov	r5, r2
3849
-	add	ip, r7, r6
3850
-	strh	r3, [ip, #2]	@ movhi
3851
-	strh	r3, [r7, r6]	@ movhi
3852
-	ldr	r3, [r2, #-3532]
4139
+	ldr	r6, [r2, #-3548]
4140
+	mov	ip, r2
4141
+	add	lr, r6, r5
4142
+	strh	r3, [lr, #2]	@ movhi
4143
+	strh	r3, [r6, r5]	@ movhi
4144
+	ldr	r3, [r2, #-3528]
3853
4145
 	cmp	r3, #0
3854
-	beq	.L654
3855
-	ldr	r9, [r2, #-3608]
3856
-	mov	r2, r0, asl #1
3857
-	ldr	r8, [r5, #-3552]
3858
-	rsb	r1, r8, r3
3859
-	ldrh	r10, [r9, r2]
3860
-	ldr	r2, .L655+4
3861
-	mov	r1, r1, asr #1
3862
-	mul	r1, r2, r1
3863
-	uxth	r2, r1
3864
-.L651:
3865
-	mov	r1, r2, asl #1
3866
-	ldrh	r1, [r9, r1]
3867
-	cmp	r1, r10
3868
-	bcs	.L649
4146
+	streq	lr, [r2, #-3528]
4147
+	beq	.L649
4148
+	ldr	r8, [r2, #-3604]
4149
+	lsl	r2, r0, #1
4150
+	ldr	r7, [ip, #-3548]
4151
+	ldrh	r9, [r8, r2]
4152
+	sub	r2, r3, r7
4153
+	asr	r10, r2, #1
4154
+	ldr	r2, .L656+4
4155
+	mul	r2, r2, r10
4156
+	mov	r10, r1
4157
+	uxth	r2, r2
4158
+.L653:
4159
+	lsl	r1, r2, #1
4160
+	ldrh	r1, [r8, r1]
4161
+	cmp	r1, r9
4162
+	bcs	.L651
3869
4163
 	ldrh	r1, [r3]
3870
4164
 	cmp	r1, r4
3871
-	streqh	r2, [ip, #2]	@ movhi
3872
-	streqh	r0, [r3]	@ movhi
3873
-	beq	.L647
3874
-.L650:
3875
-	mla	r3, lr, r1, r8
3876
-	mov	r2, r1
3877
-	b	.L651
3878
-.L649:
3879
-	ldrh	r1, [r3, #2]
3880
-	strh	r1, [ip, #2]	@ movhi
3881
-	strh	r2, [r7, r6]	@ movhi
3882
-	ldr	r1, [r5, #-3532]
3883
-	ldr	r2, .L655
3884
-	cmp	r3, r1
3885
4165
 	bne	.L652
3886
-	strh	r0, [r3, #2]	@ movhi
3887
-.L654:
3888
-	str	ip, [r2, #-3532]
3889
-	b	.L647
3890
-.L652:
3891
-	ldrh	ip, [r3, #2]
3892
-	ldr	r1, [r2, #-3552]
3893
-	mov	r2, #6
3894
-	mul	r2, r2, ip
3895
-	strh	r0, [r1, r2]	@ movhi
3896
-	strh	r0, [r3, #2]	@ movhi
3897
-.L647:
4166
+	strh	r2, [lr, #2]	@ movhi
4167
+	strh	r0, [r3]	@ movhi
4168
+.L649:
3898
4169
 	mov	r0, #0
3899
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
3900
-.L656:
4170
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
4171
+.L652:
4172
+	mla	r3, r10, r1, r7
4173
+	mov	r2, r1
4174
+	b	.L653
4175
+.L651:
4176
+	ldrh	r1, [r3, #2]
4177
+	strh	r1, [lr, #2]	@ movhi
4178
+	strh	r2, [r6, r5]	@ movhi
4179
+	ldr	r2, [ip, #-3528]
4180
+	cmp	r3, r2
4181
+	ldrhne	lr, [r3, #2]
4182
+	movne	r2, #6
4183
+	ldrne	r1, [ip, #-3548]
4184
+	strheq	r0, [r3, #2]	@ movhi
4185
+	streq	lr, [ip, #-3528]
4186
+	mulne	r2, r2, lr
4187
+	strhne	r0, [r1, r2]	@ movhi
4188
+	strhne	r0, [r3, #2]	@ movhi
4189
+	b	.L649
4190
+.L657:
3901
4191
 	.align	2
3902
-.L655:
4192
+.L656:
3903
4193
 	.word	.LANCHOR2
3904
4194
 	.word	-1431655765
3905
4195
 	.fnend
3906
4196
 	.size	insert_free_list, .-insert_free_list
3907
4197
 	.align	2
3908
4198
 	.global	INSERT_FREE_LIST
4199
+	.syntax unified
4200
+	.arm
4201
+	.fpu softvfp
3909
4202
 	.type	INSERT_FREE_LIST, %function
3910
4203
 INSERT_FREE_LIST:
3911
4204
 	.fnstart
3912
4205
 	@ args = 0, pretend = 0, frame = 0
3913
4206
 	@ frame_needed = 0, uses_anonymous_args = 0
3914
-	stmfd	sp!, {r3, lr}
3915
-	.save {r3, lr}
4207
+	push	{r4, lr}
4208
+	.save {r4, lr}
3916
4209
 	bl	insert_free_list
3917
-	ldr	r2, .L659
3918
-	ldrh	r3, [r2, #-8]
4210
+	ldr	r2, .L660
4211
+	ldrh	r3, [r2, #-4]
3919
4212
 	add	r3, r3, #1
3920
-	strh	r3, [r2, #-8]	@ movhi
3921
-	ldmfd	sp!, {r3, pc}
3922
-.L660:
4213
+	strh	r3, [r2, #-4]	@ movhi
4214
+	pop	{r4, pc}
4215
+.L661:
3923
4216
 	.align	2
3924
-.L659:
4217
+.L660:
3925
4218
 	.word	.LANCHOR2-3520
3926
4219
 	.fnend
3927
4220
 	.size	INSERT_FREE_LIST, .-INSERT_FREE_LIST
3928
4221
 	.align	2
3929
4222
 	.global	List_remove_node
4223
+	.syntax unified
4224
+	.arm
4225
+	.fpu softvfp
3930
4226
 	.type	List_remove_node, %function
3931
4227
 List_remove_node:
3932
4228
 	.fnstart
3933
4229
 	@ args = 0, pretend = 0, frame = 0
3934
4230
 	@ frame_needed = 0, uses_anonymous_args = 0
3935
-	stmfd	sp!, {r4, r5, lr}
4231
+	push	{r4, r5, lr}
3936
4232
 	.save {r4, r5, lr}
3937
4233
 	mov	ip, #6
3938
-	ldr	r4, .L667
3939
-	movw	r5, #65535
4234
+	ldr	r4, .L668
3940
4235
 	mul	r1, ip, r1
4236
+	movw	r5, #65535
3941
4237
 	ldr	r3, [r0]
3942
-	ldr	r2, [r4, #-3552]
4238
+	ldr	r2, [r4, #-3548]
3943
4239
 	add	lr, r2, r1
3944
4240
 	cmp	lr, r3
3945
4241
 	ldrh	r3, [r2, r1]
3946
-	bne	.L662
4242
+	bne	.L663
3947
4243
 	cmp	r3, r5
3948
4244
 	mlane	r3, ip, r3, r2
3949
4245
 	moveq	r3, #0
3950
4246
 	streq	r3, [r0]
3951
4247
 	strne	r3, [r0]
3952
4248
 	mvnne	r0, #0
3953
-	strneh	r0, [r3, #2]	@ movhi
3954
-	b	.L664
3955
-.L662:
3956
-	cmp	r3, r5
3957
-	ldrh	r0, [lr, #2]
3958
-	bne	.L665
3959
-	cmp	r0, r3
3960
-	mulne	r0, ip, r0
3961
-	mvnne	r3, #0
3962
-	strneh	r3, [r2, r0]	@ movhi
3963
-	b	.L664
4249
+	strhne	r0, [r3, #2]	@ movhi
3964
4250
 .L665:
3965
-	mla	r3, ip, r3, r2
3966
-	strh	r0, [r3, #2]	@ movhi
3967
-	ldrh	r5, [lr, #2]
3968
-	ldrh	r0, [r2, r1]
3969
-	ldr	r3, [r4, #-3552]
3970
-	mul	ip, ip, r5
3971
-	strh	r0, [r3, ip]	@ movhi
3972
-.L664:
3973
4251
 	mvn	r3, #0
3974
4252
 	mov	r0, #0
3975
4253
 	strh	r3, [r2, r1]	@ movhi
3976
4254
 	strh	r3, [lr, #2]	@ movhi
3977
-	ldmfd	sp!, {r4, r5, pc}
3978
-.L668:
4255
+	pop	{r4, r5, pc}
4256
+.L663:
4257
+	cmp	r3, r5
4258
+	ldrh	r0, [lr, #2]
4259
+	bne	.L666
4260
+	cmp	r0, r3
4261
+	mulne	r3, ip, r0
4262
+	mvnne	r0, #0
4263
+	strhne	r0, [r2, r3]	@ movhi
4264
+	b	.L665
4265
+.L666:
4266
+	mla	r3, ip, r3, r2
4267
+	strh	r0, [r3, #2]	@ movhi
4268
+	ldrh	r3, [lr, #2]
4269
+	ldrh	r5, [r2, r1]
4270
+	ldr	r0, [r4, #-3548]
4271
+	mul	r3, ip, r3
4272
+	strh	r5, [r0, r3]	@ movhi
4273
+	b	.L665
4274
+.L669:
3979
4275
 	.align	2
3980
-.L667:
4276
+.L668:
3981
4277
 	.word	.LANCHOR2
3982
4278
 	.fnend
3983
4279
 	.size	List_remove_node, .-List_remove_node
3984
4280
 	.align	2
3985
4281
 	.global	List_pop_index_node
4282
+	.syntax unified
4283
+	.arm
4284
+	.fpu softvfp
3986
4285
 	.type	List_pop_index_node, %function
3987
4286
 List_pop_index_node:
3988
4287
 	.fnstart
..
..
@@ -3990,1133 +4289,1182 @@
3990
4289
 	@ frame_needed = 0, uses_anonymous_args = 0
3991
4290
 	ldr	r3, [r0]
3992
4291
 	cmp	r3, #0
3993
-	beq	.L675
3994
-	ldr	r2, .L678
3995
-	movw	ip, #65535
3996
-	stmfd	sp!, {r4, lr}
4292
+	beq	.L676
4293
+	ldr	r2, .L681
4294
+	push	{r4, lr}
3997
4295
 	.save {r4, lr}
3998
-	mov	lr, #6
3999
-	ldr	r4, [r2, #-3552]
4000
-.L671:
4001
-	cmp	r1, #0
4002
-	bne	.L672
4003
-.L674:
4004
-	rsb	r4, r4, r3
4005
-	ldr	r3, .L678+4
4006
-	mov	r4, r4, asr #1
4007
-	mul	r4, r3, r4
4008
-	uxth	r4, r4
4009
-	mov	r1, r4
4010
-	bl	List_remove_node
4011
-	mov	r0, r4
4012
-	ldmfd	sp!, {r4, pc}
4296
+	movw	lr, #65535
4297
+	mov	r4, #6
4298
+	ldr	r2, [r2, #-3548]
4013
4299
 .L672:
4014
-	ldrh	r2, [r3]
4015
-	cmp	r2, ip
4016
-	beq	.L674
4017
-	sub	r1, r1, #1
4018
-	mla	r3, lr, r2, r4
4019
-	uxth	r1, r1
4020
-	b	.L671
4300
+	cmp	r1, #0
4301
+	bne	.L673
4021
4302
 .L675:
4303
+	ldr	r4, .L681+4
4304
+	sub	r3, r3, r2
4305
+	asr	r3, r3, #1
4306
+	mul	r4, r4, r3
4307
+	uxth	r1, r4
4308
+	bl	List_remove_node
4309
+	uxth	r0, r4
4310
+	pop	{r4, pc}
4311
+.L673:
4312
+	ldrh	ip, [r3]
4313
+	cmp	ip, lr
4314
+	beq	.L675
4315
+	sub	r1, r1, #1
4316
+	mla	r3, r4, ip, r2
4317
+	uxth	r1, r1
4318
+	b	.L672
4319
+.L676:
4022
4320
 	movw	r0, #65535
4023
4321
 	bx	lr
4024
-.L679:
4322
+.L682:
4025
4323
 	.align	2
4026
-.L678:
4324
+.L681:
4027
4325
 	.word	.LANCHOR2
4028
4326
 	.word	-1431655765
4029
4327
 	.fnend
4030
4328
 	.size	List_pop_index_node, .-List_pop_index_node
4031
4329
 	.align	2
4032
4330
 	.global	List_get_gc_head_node
4331
+	.syntax unified
4332
+	.arm
4333
+	.fpu softvfp
4033
4334
 	.type	List_get_gc_head_node, %function
4034
4335
 List_get_gc_head_node:
4035
4336
 	.fnstart
4036
4337
 	@ args = 0, pretend = 0, frame = 0
4037
4338
 	@ frame_needed = 0, uses_anonymous_args = 0
4038
4339
 	@ link register save eliminated.
4039
-	ldr	r2, .L687
4040
-	ldr	r3, [r2, #-3548]
4340
+	ldr	r2, .L689
4341
+	ldr	r3, [r2, #-3544]
4041
4342
 	cmp	r3, #0
4042
-	ldrne	r1, [r2, #-3552]
4343
+	ldrne	r1, [r2, #-3548]
4043
4344
 	movne	ip, #6
4044
4345
 	movwne	r2, #65535
4045
-	beq	.L685
4046
-.L682:
4047
-	cmp	r0, #0
4048
-	beq	.L683
4049
-	ldrh	r3, [r3]
4050
-	cmp	r3, r2
4051
-	subne	r0, r0, #1
4052
-	mlane	r3, ip, r3, r1
4053
-	uxthne	r0, r0
4054
-	bne	.L682
4055
-.L685:
4346
+	bne	.L685
4347
+.L688:
4056
4348
 	movw	r0, #65535
4057
4349
 	bx	lr
4058
-.L683:
4059
-	rsb	r3, r1, r3
4060
-	ldr	r0, .L687+4
4061
-	mov	r3, r3, asr #1
4062
-	mul	r0, r0, r3
4063
-	uxth	r0, r0
4064
-	bx	lr
4065
-.L688:
4066
-	.align	2
4067
4350
 .L687:
4351
+	sub	r0, r0, #1
4352
+	mla	r3, ip, r3, r1
4353
+	uxth	r0, r0
4354
+.L685:
4355
+	cmp	r0, #0
4356
+	beq	.L686
4357
+	ldrh	r3, [r3]
4358
+	cmp	r3, r2
4359
+	bne	.L687
4360
+	b	.L688
4361
+.L686:
4362
+	ldr	r0, .L689+4
4363
+	sub	r3, r3, r1
4364
+	asr	r3, r3, #1
4365
+	mul	r3, r0, r3
4366
+	uxth	r0, r3
4367
+	bx	lr
4368
+.L690:
4369
+	.align	2
4370
+.L689:
4068
4371
 	.word	.LANCHOR2
4069
4372
 	.word	-1431655765
4070
4373
 	.fnend
4071
4374
 	.size	List_get_gc_head_node, .-List_get_gc_head_node
4072
4375
 	.align	2
4073
4376
 	.global	List_update_data_list
4377
+	.syntax unified
4378
+	.arm
4379
+	.fpu softvfp
4074
4380
 	.type	List_update_data_list, %function
4075
4381
 List_update_data_list:
4076
4382
 	.fnstart
4077
4383
 	@ args = 0, pretend = 0, frame = 0
4078
4384
 	@ frame_needed = 0, uses_anonymous_args = 0
4079
-	stmfd	sp!, {r3, r4, r5, lr}
4080
-	.save {r3, r4, r5, lr}
4081
-	ldr	r3, .L697
4082
-	sub	r2, r3, #3520
4083
-	ldrh	r2, [r2, #-4]
4385
+	ldr	r3, .L699
4386
+	push	{r4, r5, r6, lr}
4387
+	.save {r4, r5, r6, lr}
4388
+	sub	r5, r3, #3520
4389
+	ldrh	r2, [r5]
4084
4390
 	cmp	r2, r0
4085
-	beq	.L690
4391
+	beq	.L692
4086
4392
 	sub	r2, r3, #3472
4087
-	ldrh	r2, [r2, #-4]
4393
+	ldrh	r2, [r2]
4088
4394
 	cmp	r2, r0
4089
-	beq	.L690
4395
+	beq	.L692
4090
4396
 	sub	r2, r3, #3424
4091
-	ldrh	r2, [r2, #-4]
4397
+	ldrh	r2, [r2]
4092
4398
 	cmp	r2, r0
4093
-	beq	.L690
4399
+	beq	.L692
4094
4400
 	mov	lr, #6
4095
-	ldr	r1, [r3, #-3552]
4401
+	ldr	r1, [r3, #-3548]
4096
4402
 	mul	lr, lr, r0
4097
-	ldr	r2, [r3, #-3548]
4403
+	ldr	r2, [r3, #-3544]
4098
4404
 	add	ip, r1, lr
4099
4405
 	cmp	ip, r2
4100
-	beq	.L690
4101
-	ldr	r4, [r3, #-3544]
4102
-	mov	r3, r0, asl #1
4103
-	ldrh	r2, [r4, r3]
4104
-	ldrh	r3, [ip, #4]
4105
-	ldrh	ip, [ip, #2]
4106
-	cmp	r3, #0
4107
-	mulne	r2, r3, r2
4406
+	beq	.L692
4407
+	ldr	r4, [r3, #-3540]
4408
+	lsl	r3, r0, #1
4409
+	ldrh	r2, [ip, #4]
4410
+	ldrh	r3, [r4, r3]
4411
+	cmp	r2, #0
4108
4412
 	mvneq	r2, #0
4109
-	movw	r3, #65535
4110
-	cmp	ip, r3
4111
-	bne	.L692
4112
-	ldrh	r3, [r1, lr]
4413
+	mulne	r2, r2, r3
4414
+	ldrh	r3, [ip, #2]
4415
+	movw	ip, #65535
4113
4416
 	cmp	r3, ip
4114
-	beq	.L690
4115
-.L692:
4116
-	mov	r3, #6
4117
-	mul	ip, r3, ip
4118
-	ldr	r3, .L697+4
4417
+	bne	.L694
4418
+	ldrh	ip, [r1, lr]
4419
+	cmp	ip, r3
4420
+	beq	.L692
4421
+.L694:
4422
+	mov	ip, #6
4423
+	mul	ip, ip, r3
4424
+	ldr	r3, .L699+4
4425
+	asr	lr, ip, #1
4119
4426
 	add	r1, r1, ip
4120
-	mov	lr, ip, asr #1
4121
4427
 	mul	r3, r3, lr
4122
-	mov	r3, r3, asl #1
4428
+	lsl	r3, r3, #1
4123
4429
 	ldrh	lr, [r4, r3]
4124
4430
 	ldrh	r3, [r1, #4]
4125
4431
 	cmp	r3, #0
4126
4432
 	mulne	r3, r3, lr
4127
4433
 	mvneq	r3, #0
4128
4434
 	cmp	r2, r3
4129
-	bcs	.L690
4130
-	ldr	r5, .L697+8
4435
+	bcs	.L692
4131
4436
 	mov	r4, r0
4132
-	mov	r1, r4
4133
-	sub	r0, r5, #12
4437
+	mov	r1, r0
4438
+	ldr	r0, .L699+8
4134
4439
 	bl	List_remove_node
4135
-	ldrh	r3, [r5]
4440
+	ldrh	r3, [r5, #-12]
4136
4441
 	mov	r0, r4
4137
4442
 	sub	r3, r3, #1
4138
-	strh	r3, [r5]	@ movhi
4443
+	strh	r3, [r5, #-12]	@ movhi
4139
4444
 	bl	INSERT_DATA_LIST
4140
-.L690:
4445
+.L692:
4141
4446
 	mov	r0, #0
4142
-	ldmfd	sp!, {r3, r4, r5, pc}
4143
-.L698:
4447
+	pop	{r4, r5, r6, pc}
4448
+.L700:
4144
4449
 	.align	2
4145
-.L697:
4450
+.L699:
4146
4451
 	.word	.LANCHOR2
4147
4452
 	.word	-1431655765
4148
-	.word	.LANCHOR2-3536
4453
+	.word	.LANCHOR2-3544
4149
4454
 	.fnend
4150
4455
 	.size	List_update_data_list, .-List_update_data_list
4151
4456
 	.align	2
4152
4457
 	.global	ftl_map_blk_alloc_new_blk
4458
+	.syntax unified
4459
+	.arm
4460
+	.fpu softvfp
4153
4461
 	.type	ftl_map_blk_alloc_new_blk, %function
4154
4462
 ftl_map_blk_alloc_new_blk:
4155
4463
 	.fnstart
4156
4464
 	@ args = 0, pretend = 0, frame = 0
4157
4465
 	@ frame_needed = 0, uses_anonymous_args = 0
4158
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
4159
-	.save {r3, r4, r5, r6, r7, lr}
4466
+	push	{r4, r5, r6, r7, r8, lr}
4467
+	.save {r4, r5, r6, r7, r8, lr}
4160
4468
 	mov	r3, #0
4161
4469
 	ldrh	r1, [r0, #10]
4162
4470
 	ldr	r2, [r0, #12]
4163
-.L700:
4471
+.L702:
4164
4472
 	uxth	r5, r3
4165
4473
 	cmp	r5, r1
4166
-	bcs	.L703
4474
+	bcs	.L705
4167
4475
 	mov	r7, r2
4168
4476
 	add	r3, r3, #1
4169
4477
 	ldrh	r6, [r7]
4170
4478
 	add	r2, r2, #2
4171
4479
 	cmp	r6, #0
4172
-	bne	.L700
4480
+	bne	.L702
4173
4481
 	mov	r4, r0
4174
4482
 	bl	FtlFreeSysBlkQueueOut
4175
-	movw	r2, #65533
4176
4483
 	sub	r3, r0, #1
4484
+	movw	r2, #65533
4485
+	uxth	r3, r3
4177
4486
 	mov	r1, r0
4178
4487
 	strh	r0, [r7]	@ movhi
4179
-	uxth	r3, r3
4180
4488
 	cmp	r3, r2
4181
-	bls	.L701
4182
-	ldr	r3, .L707
4183
-	ldr	r0, .L707+4
4489
+	bls	.L703
4490
+	ldr	r3, .L709
4491
+	ldr	r0, .L709+4
4184
4492
 	ldrh	r2, [r3, #6]
4185
4493
 	bl	printk
4186
-.L702:
4187
-	b	.L702
4188
-.L701:
4494
+.L704:
4495
+	b	.L704
4496
+.L703:
4189
4497
 	ldr	r3, [r4, #28]
4190
4498
 	strh	r6, [r4, #2]	@ movhi
4499
+	strh	r5, [r4]	@ movhi
4191
4500
 	add	r3, r3, #1
4192
4501
 	str	r3, [r4, #28]
4193
4502
 	ldrh	r3, [r4, #8]
4194
-	strh	r5, [r4]	@ movhi
4195
4503
 	add	r3, r3, #1
4196
4504
 	strh	r3, [r4, #8]	@ movhi
4197
-.L703:
4505
+.L705:
4198
4506
 	mov	r0, #0
4199
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
4200
-.L708:
4507
+	pop	{r4, r5, r6, r7, r8, pc}
4508
+.L710:
4201
4509
 	.align	2
4202
-.L707:
4203
-	.word	.LANCHOR0+2512
4510
+.L709:
4511
+	.word	.LANCHOR0+2516
4204
4512
 	.word	.LC5
4205
4513
 	.fnend
4206
4514
 	.size	ftl_map_blk_alloc_new_blk, .-ftl_map_blk_alloc_new_blk
4207
4515
 	.align	2
4208
4516
 	.global	select_l2p_ram_region
4517
+	.syntax unified
4518
+	.arm
4519
+	.fpu softvfp
4209
4520
 	.type	select_l2p_ram_region, %function
4210
4521
 select_l2p_ram_region:
4211
4522
 	.fnstart
4212
4523
 	@ args = 0, pretend = 0, frame = 0
4213
4524
 	@ frame_needed = 0, uses_anonymous_args = 0
4214
-	ldr	r2, .L725
4215
-	movw	r3, #2426
4216
-	stmfd	sp!, {r4, r5, r6, lr}
4525
+	ldr	r2, .L722
4526
+	movw	r3, #2430
4527
+	push	{r4, r5, r6, lr}
4217
4528
 	.save {r4, r5, r6, lr}
4218
4529
 	mov	r1, #0
4219
-	ldrh	r2, [r2, r3]
4220
4530
 	mov	ip, #12
4221
-	ldr	r3, .L725+4
4222
4531
 	movw	lr, #65535
4223
-	ldr	r3, [r3, #-3380]
4224
-.L710:
4532
+	ldrh	r2, [r2, r3]
4533
+	ldr	r3, .L722+4
4534
+	ldr	r3, [r3, #-3376]
4535
+.L712:
4225
4536
 	uxth	r0, r1
4226
4537
 	cmp	r0, r2
4227
-	bcs	.L722
4228
-	add	r1, r1, #1
4229
-	mla	r4, ip, r1, r3
4230
-	ldrh	r4, [r4, #-12]
4231
-	cmp	r4, lr
4232
-	bne	.L710
4233
-	ldmfd	sp!, {r4, r5, r6, pc}
4234
-.L722:
4538
+	bcc	.L714
4235
4539
 	mov	r0, r2
4236
4540
 	mov	r1, #0
4237
4541
 	mov	ip, #-2147483648
4238
4542
 	mov	r5, #12
4239
-.L713:
4543
+.L715:
4240
4544
 	uxth	r4, r1
4241
4545
 	cmp	r4, r2
4242
-	bcs	.L723
4546
+	bcc	.L717
4547
+	cmp	r0, r2
4548
+	popcc	{r4, r5, r6, pc}
4549
+	ldr	r1, .L722+8
4550
+	mov	r0, r2
4551
+	mvn	ip, #0
4552
+	ldrh	r5, [r1, #-12]
4553
+	mov	r1, #0
4554
+.L718:
4555
+	uxth	lr, r1
4556
+	cmp	lr, r2
4557
+	bcc	.L720
4558
+	pop	{r4, r5, r6, pc}
4559
+.L714:
4560
+	add	r1, r1, #1
4561
+	mla	r4, ip, r1, r3
4562
+	ldrh	r4, [r4, #-12]
4563
+	cmp	r4, lr
4564
+	bne	.L712
4565
+	pop	{r4, r5, r6, pc}
4566
+.L717:
4243
4567
 	mla	lr, r5, r1, r3
4244
4568
 	add	r1, r1, #1
4245
4569
 	ldr	lr, [lr, #4]
4246
-	cmp	lr, ip
4247
-	mvn	r6, lr
4248
-	mov	r6, r6, lsr #31
4249
-	movcs	r6, #0
4570
+	cmp	ip, lr
4571
+	movls	r6, #0
4572
+	movhi	r6, #1
4573
+	cmp	lr, #0
4574
+	movlt	r6, #0
4250
4575
 	cmp	r6, #0
4251
4576
 	movne	ip, lr
4252
4577
 	movne	r0, r4
4253
-	b	.L713
4254
-.L723:
4255
-	cmp	r0, r2
4256
-	ldmccfd	sp!, {r4, r5, r6, pc}
4257
-	ldr	r1, .L725+8
4258
-	mov	r0, r2
4259
-	mvn	ip, #0
4260
-	ldrh	r5, [r1]
4261
-	mov	r1, #0
4262
-.L716:
4263
-	uxth	lr, r1
4264
-	cmp	lr, r2
4265
-	bcs	.L724
4578
+	b	.L715
4579
+.L720:
4266
4580
 	ldr	r4, [r3, #4]
4267
-	cmp	r4, ip
4268
-	bcs	.L717
4581
+	cmp	ip, r4
4582
+	bls	.L719
4269
4583
 	ldrh	r6, [r3]
4270
4584
 	cmp	r6, r5
4271
4585
 	movne	ip, r4
4272
4586
 	movne	r0, lr
4273
-.L717:
4587
+.L719:
4274
4588
 	add	r1, r1, #1
4275
4589
 	add	r3, r3, #12
4276
-	b	.L716
4277
-.L724:
4278
-	ldmfd	sp!, {r4, r5, r6, pc}
4279
-.L726:
4590
+	b	.L718
4591
+.L723:
4280
4592
 	.align	2
4281
-.L725:
4593
+.L722:
4282
4594
 	.word	.LANCHOR0
4283
4595
 	.word	.LANCHOR2
4284
-	.word	.LANCHOR2-3376
4596
+	.word	.LANCHOR2-3360
4285
4597
 	.fnend
4286
4598
 	.size	select_l2p_ram_region, .-select_l2p_ram_region
4287
4599
 	.align	2
4288
4600
 	.global	FtlUpdateVaildLpn
4601
+	.syntax unified
4602
+	.arm
4603
+	.fpu softvfp
4289
4604
 	.type	FtlUpdateVaildLpn, %function
4290
4605
 FtlUpdateVaildLpn:
4291
4606
 	.fnstart
4292
4607
 	@ args = 0, pretend = 0, frame = 0
4293
4608
 	@ frame_needed = 0, uses_anonymous_args = 0
4294
-	ldr	r3, .L735
4609
+	ldr	r3, .L733
4295
4610
 	sub	r1, r3, #3360
4296
-	ldrh	r2, [r1, #-14]
4611
+	ldrh	r2, [r1, #-10]
4297
4612
 	cmp	r2, #4
4298
4613
 	cmpls	r0, #0
4299
-	addeq	r2, r2, #1
4300
-	streqh	r2, [r1, #-14]	@ movhi
4301
-	bxeq	lr
4302
-	ldr	r0, .L735+4
4614
+	bne	.L725
4615
+	add	r2, r2, #1
4616
+	strh	r2, [r1, #-10]	@ movhi
4617
+	bx	lr
4618
+.L725:
4619
+	ldr	r0, .L733+4
4303
4620
 	mov	r2, #0
4304
4621
 	str	lr, [sp, #-4]!
4305
4622
 	.save {lr}
4306
-	movw	ip, #65535
4307
-	strh	r2, [r1, #-14]	@ movhi
4308
-	movw	r1, #2328
4309
-	ldrh	r0, [r0, r1]
4310
-	str	r2, [r3, #-3372]
4311
-	ldr	r2, [r3, #-3544]
4312
-	add	r0, r2, r0, asl #1
4313
-.L729:
4314
-	cmp	r2, r0
4315
-	beq	.L734
4316
-	ldrh	r1, [r2], #2
4317
-	cmp	r1, ip
4318
-	ldrne	lr, [r3, #-3372]
4319
-	addne	r1, r1, lr
4320
-	strne	r1, [r3, #-3372]
4321
-	b	.L729
4322
-.L734:
4623
+	movw	lr, #65535
4624
+	strh	r2, [r1, #-10]	@ movhi
4625
+	movw	r1, #2332
4626
+	str	r2, [r3, #-3368]
4627
+	ldrh	r1, [r0, r1]
4628
+	ldr	r2, [r3, #-3540]
4629
+	add	r1, r2, r1, lsl #1
4630
+.L726:
4631
+	cmp	r2, r1
4632
+	bne	.L728
4323
4633
 	ldr	pc, [sp], #4
4324
-.L736:
4634
+.L728:
4635
+	ldrh	ip, [r2], #2
4636
+	cmp	ip, lr
4637
+	ldrne	r0, [r3, #-3368]
4638
+	addne	r0, r0, ip
4639
+	strne	r0, [r3, #-3368]
4640
+	b	.L726
4641
+.L734:
4325
4642
 	.align	2
4326
-.L735:
4643
+.L733:
4327
4644
 	.word	.LANCHOR2
4328
4645
 	.word	.LANCHOR0
4329
4646
 	.fnend
4330
4647
 	.size	FtlUpdateVaildLpn, .-FtlUpdateVaildLpn
4331
4648
 	.align	2
4332
4649
 	.global	ftl_set_blk_mode
4650
+	.syntax unified
4651
+	.arm
4652
+	.fpu softvfp
4333
4653
 	.type	ftl_set_blk_mode, %function
4334
4654
 ftl_set_blk_mode:
4335
4655
 	.fnstart
4336
4656
 	@ args = 0, pretend = 0, frame = 0
4337
4657
 	@ frame_needed = 0, uses_anonymous_args = 0
4338
4658
 	@ link register save eliminated.
4339
-	ldr	r2, .L741
4340
-	mov	r3, r0, lsr #5
4341
4659
 	cmp	r1, #0
4342
-	and	r0, r0, #31
4343
-	uxth	r3, r3
4660
+	mov	r3, r0
4661
+	beq	.L736
4662
+	b	ftl_set_blk_mode.part.9
4663
+.L736:
4664
+	ldr	r2, .L737
4665
+	lsr	r0, r0, #5
4666
+	and	r3, r3, #31
4344
4667
 	mov	ip, #1
4345
-	ldr	r1, [r2, #-3368]
4346
-	ldr	r2, [r1, r3, asl #2]
4347
-	orrne	r0, r2, ip, asl r0
4348
-	biceq	r0, r2, ip, asl r0
4349
-	str	r0, [r1, r3, asl #2]
4668
+	ldr	r1, [r2, #32]
4669
+	ldr	r2, [r1, r0, lsl #2]
4670
+	bic	r3, r2, ip, lsl r3
4671
+	str	r3, [r1, r0, lsl #2]
4350
4672
 	bx	lr
4351
-.L742:
4673
+.L738:
4352
4674
 	.align	2
4353
-.L741:
4354
-	.word	.LANCHOR2
4675
+.L737:
4676
+	.word	.LANCHOR0
4355
4677
 	.fnend
4356
4678
 	.size	ftl_set_blk_mode, .-ftl_set_blk_mode
4357
4679
 	.align	2
4358
4680
 	.global	ftl_get_blk_mode
4681
+	.syntax unified
4682
+	.arm
4683
+	.fpu softvfp
4359
4684
 	.type	ftl_get_blk_mode, %function
4360
4685
 ftl_get_blk_mode:
4361
4686
 	.fnstart
4362
4687
 	@ args = 0, pretend = 0, frame = 0
4363
4688
 	@ frame_needed = 0, uses_anonymous_args = 0
4364
4689
 	@ link register save eliminated.
4365
-	ldr	r3, .L744
4366
-	mov	r2, r0, lsr #5
4690
+	ldr	r3, .L740
4691
+	lsr	r2, r0, #5
4367
4692
 	and	r0, r0, #31
4368
-	ldr	r3, [r3, #-3368]
4369
-	ldr	r3, [r3, r2, asl #2]
4370
-	mov	r0, r3, lsr r0
4693
+	ldr	r3, [r3, #32]
4694
+	ldr	r3, [r3, r2, lsl #2]
4695
+	lsr	r0, r3, r0
4371
4696
 	and	r0, r0, #1
4372
4697
 	bx	lr
4373
-.L745:
4698
+.L741:
4374
4699
 	.align	2
4375
-.L744:
4376
-	.word	.LANCHOR2
4700
+.L740:
4701
+	.word	.LANCHOR0
4377
4702
 	.fnend
4378
4703
 	.size	ftl_get_blk_mode, .-ftl_get_blk_mode
4379
4704
 	.align	2
4380
4705
 	.global	ftl_sb_update_avl_pages
4706
+	.syntax unified
4707
+	.arm
4708
+	.fpu softvfp
4381
4709
 	.type	ftl_sb_update_avl_pages, %function
4382
4710
 ftl_sb_update_avl_pages:
4383
4711
 	.fnstart
4384
4712
 	@ args = 0, pretend = 0, frame = 0
4385
4713
 	@ frame_needed = 0, uses_anonymous_args = 0
4386
4714
 	mov	r3, #0
4715
+	movw	ip, #2324
4387
4716
 	strh	r3, [r0, #4]	@ movhi
4388
-	ldr	r3, .L756
4389
-	stmfd	sp!, {r4, r5, lr}
4717
+	ldr	r3, .L750
4718
+	push	{r4, r5, lr}
4390
4719
 	.save {r4, r5, lr}
4391
-	movw	r4, #65535
4392
-	ldrh	lr, [r3]
4393
-	add	r3, r2, #7
4394
-	add	r3, r0, r3, asl #1
4395
-.L747:
4396
-	cmp	r2, lr
4397
-	bcs	.L754
4398
-	ldrh	ip, [r3, #2]!
4399
-	add	r2, r2, #1
4400
-	cmp	ip, r4
4401
-	uxth	r2, r2
4402
-	ldrneh	ip, [r0, #4]
4403
-	addne	ip, ip, #1
4404
-	strneh	ip, [r0, #4]	@ movhi
4405
-	b	.L747
4406
-.L754:
4407
-	ldr	r2, .L756+4
4408
-	movw	r3, #2388
4409
-	add	ip, r0, #14
4410
4720
 	movw	r5, #65535
4411
-	ldrh	r4, [r2, r3]
4412
-	mov	r2, #0
4413
-.L750:
4414
-	uxth	r3, r2
4415
-	cmp	r3, lr
4416
-	bcs	.L755
4417
-	ldrh	r3, [ip, #2]!
4721
+	ldrh	lr, [r3, ip]
4722
+	add	ip, r0, r2, lsl #1
4723
+	add	ip, ip, #14
4724
+.L743:
4725
+	cmp	r2, lr
4726
+	bcc	.L745
4727
+	movw	r2, #2390
4728
+	add	ip, r0, #16
4729
+	ldrh	r3, [r3, r2]
4730
+	movw	r4, #65535
4731
+	sub	r3, r3, #1
4732
+	sub	r1, r3, r1
4733
+	mov	r3, #0
4734
+	uxth	r1, r1
4735
+.L746:
4736
+	uxth	r2, r3
4737
+	cmp	lr, r2
4738
+	bhi	.L748
4739
+	pop	{r4, r5, pc}
4740
+.L745:
4741
+	ldrh	r4, [ip, #2]!
4418
4742
 	add	r2, r2, #1
4419
-	cmp	r3, r5
4420
-	ldrneh	r3, [r0, #4]
4421
-	addne	r3, r4, r3
4422
-	subne	r3, r3, #1
4423
-	rsbne	r3, r1, r3
4424
-	strneh	r3, [r0, #4]	@ movhi
4425
-	b	.L750
4426
-.L755:
4427
-	ldmfd	sp!, {r4, r5, pc}
4428
-.L757:
4743
+	uxth	r2, r2
4744
+	cmp	r4, r5
4745
+	ldrhne	r4, [r0, #4]
4746
+	addne	r4, r4, #1
4747
+	strhne	r4, [r0, #4]	@ movhi
4748
+	b	.L743
4749
+.L748:
4750
+	ldrh	r2, [ip], #2
4751
+	add	r3, r3, #1
4752
+	cmp	r2, r4
4753
+	ldrhne	r2, [r0, #4]
4754
+	addne	r2, r1, r2
4755
+	strhne	r2, [r0, #4]	@ movhi
4756
+	b	.L746
4757
+.L751:
4429
4758
 	.align	2
4430
-.L756:
4431
-	.word	.LANCHOR0+2320
4759
+.L750:
4432
4760
 	.word	.LANCHOR0
4433
4761
 	.fnend
4434
4762
 	.size	ftl_sb_update_avl_pages, .-ftl_sb_update_avl_pages
4435
4763
 	.align	2
4436
4764
 	.global	make_superblock
4765
+	.syntax unified
4766
+	.arm
4767
+	.fpu softvfp
4437
4768
 	.type	make_superblock, %function
4438
4769
 make_superblock:
4439
4770
 	.fnstart
4440
4771
 	@ args = 0, pretend = 0, frame = 0
4441
4772
 	@ frame_needed = 0, uses_anonymous_args = 0
4442
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
4443
-	.save {r4, r5, r6, r7, r8, r9, r10, lr}
4444
-	add	r6, r0, #16
4445
-	ldr	r7, .L772
4773
+	push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
4774
+	.save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
4775
+	movw	r3, #2324
4776
+	ldr	r6, .L765
4446
4777
 	mov	r4, r0
4778
+	add	r7, r0, #16
4447
4779
 	mvn	r9, #0
4780
+	ldr	r10, .L765+4
4448
4781
 	mov	r5, #0
4782
+	ldrh	r8, [r6, r3]
4449
4783
 	strh	r5, [r0, #4]	@ movhi
4450
-	ldrh	r8, [r7], #28
4451
4784
 	strb	r5, [r0, #7]
4452
-.L759:
4785
+.L753:
4453
4786
 	uxth	r3, r5
4454
-	cmp	r3, r8
4455
-	bcs	.L771
4456
-	ldrb	r0, [r7, r5]	@ zero_extendqisi2
4457
-	add	r6, r6, #2
4458
-	ldrh	r1, [r4]
4459
-	add	r5, r5, #1
4460
-	bl	V2P_block
4461
-	strh	r9, [r6, #-2]	@ movhi
4462
-	mov	r10, r0
4463
-	bl	FtlBbmIsBadBlock
4464
-	cmp	r0, #0
4465
-	streqh	r10, [r6, #-2]	@ movhi
4466
-	ldreqb	r3, [r4, #7]	@ zero_extendqisi2
4467
-	addeq	r3, r3, #1
4468
-	streqb	r3, [r4, #7]
4469
-	b	.L759
4470
-.L771:
4471
-	ldr	r3, .L772+4
4472
-	movw	r2, #2388
4473
-	ldrb	r1, [r4, #7]	@ zero_extendqisi2
4474
-	ldrh	r2, [r3, r2]
4475
-	smulbb	r2, r1, r2
4476
-	strh	r2, [r4, #4]	@ movhi
4477
-	mov	r2, #0
4478
-	strb	r2, [r4, #9]
4479
-	ldr	r2, [r3, #2244]
4480
-	cmp	r2, #0
4481
-	beq	.L762
4482
-	ldr	r1, .L772+8
4483
-	ldrh	r2, [r4]
4484
-	ldr	r1, [r1, #-3608]
4485
-	mov	r2, r2, asl #1
4486
-	ldrh	r2, [r1, r2]
4487
-	cmp	r2, #79
4488
-	movls	r2, #1
4489
-	strlsb	r2, [r4, #9]
4490
-.L762:
4491
-	ldrb	r3, [r3]	@ zero_extendqisi2
4787
+	cmp	r8, r3
4788
+	bhi	.L755
4789
+	movw	r2, #2390
4790
+	ldrb	r3, [r4, #7]	@ zero_extendqisi2
4791
+	ldrh	r2, [r6, r2]
4792
+	smulbb	r3, r3, r2
4793
+	strh	r3, [r4, #4]	@ movhi
4794
+	mov	r3, #0
4795
+	strb	r3, [r4, #9]
4796
+	ldr	r3, [r6, #2248]
4797
+	cmp	r3, #0
4798
+	beq	.L756
4799
+	ldrh	r3, [r4]
4800
+	ldr	r2, .L765+8
4801
+	ldr	r2, [r2, #-3604]
4802
+	lsl	r3, r3, #1
4803
+	ldrh	r3, [r2, r3]
4804
+	cmp	r3, #79
4805
+	movls	r3, #1
4806
+	strbls	r3, [r4, #9]
4807
+.L756:
4808
+	ldrb	r3, [r6, #36]	@ zero_extendqisi2
4492
4809
 	mov	r0, #0
4493
4810
 	cmp	r3, #0
4494
4811
 	movne	r3, #1
4495
-	strneb	r3, [r4, #9]
4496
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
4497
-.L773:
4812
+	strbne	r3, [r4, #9]
4813
+	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
4814
+.L755:
4815
+	ldrb	r0, [r10, r5]	@ zero_extendqisi2
4816
+	add	r7, r7, #2
4817
+	ldrh	r1, [r4]
4818
+	add	r5, r5, #1
4819
+	bl	V2P_block
4820
+	strh	r9, [r7, #-2]	@ movhi
4821
+	mov	fp, r0
4822
+	bl	FtlBbmIsBadBlock
4823
+	cmp	r0, #0
4824
+	strheq	fp, [r7, #-2]	@ movhi
4825
+	ldrbeq	r3, [r4, #7]	@ zero_extendqisi2
4826
+	addeq	r3, r3, #1
4827
+	strbeq	r3, [r4, #7]
4828
+	b	.L753
4829
+.L766:
4498
4830
 	.align	2
4499
-.L772:
4500
-	.word	.LANCHOR0+2320
4831
+.L765:
4501
4832
 	.word	.LANCHOR0
4833
+	.word	.LANCHOR0+2350
4502
4834
 	.word	.LANCHOR2
4503
4835
 	.fnend
4504
4836
 	.size	make_superblock, .-make_superblock
4505
4837
 	.align	2
4506
4838
 	.global	update_multiplier_value
4839
+	.syntax unified
4840
+	.arm
4841
+	.fpu softvfp
4507
4842
 	.type	update_multiplier_value, %function
4508
4843
 update_multiplier_value:
4509
4844
 	.fnstart
4510
4845
 	@ args = 0, pretend = 0, frame = 0
4511
4846
 	@ frame_needed = 0, uses_anonymous_args = 0
4512
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
4513
-	.save {r3, r4, r5, r6, r7, r8, r9, lr}
4847
+	ldr	r3, .L774
4848
+	movw	r2, #2324
4849
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
4850
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
4514
4851
 	mov	r5, #0
4515
-	ldr	r3, .L784
4852
+	ldr	r9, .L774+4
4516
4853
 	mov	r6, r0
4517
-	ldr	r9, .L784+4
4518
4854
 	mov	r4, r5
4519
-	add	r2, r3, #2320
4520
-	ldrh	r7, [r2]
4521
-	movw	r2, #2388
4855
+	ldrh	r7, [r3, r2]
4856
+	movw	r2, #2390
4522
4857
 	ldrh	r8, [r3, r2]
4523
-.L775:
4858
+.L768:
4524
4859
 	uxth	r3, r5
4525
-	cmp	r3, r7
4526
-	bcs	.L783
4527
-	ldrb	r0, [r9, r5]	@ zero_extendqisi2
4528
-	mov	r1, r6
4529
-	bl	V2P_block
4530
-	add	r5, r5, #1
4531
-	bl	FtlBbmIsBadBlock
4532
-	cmp	r0, #0
4533
-	addeq	r4, r4, r8
4534
-	uxtheq	r4, r4
4535
-	b	.L775
4536
-.L783:
4860
+	cmp	r7, r3
4861
+	bhi	.L770
4537
4862
 	cmp	r4, #0
4538
-	beq	.L778
4863
+	moveq	r0, r4
4864
+	beq	.L771
4539
4865
 	mov	r1, r4
4540
4866
 	mov	r0, #32768
4541
4867
 	bl	__aeabi_idiv
4542
-	uxth	r4, r0
4543
-.L778:
4544
-	ldr	r3, .L784+8
4868
+.L771:
4869
+	ldr	r3, .L774+8
4545
4870
 	mov	r2, #6
4546
-	mov	r0, #0
4547
-	ldr	r3, [r3, #-3552]
4871
+	ldr	r3, [r3, #-3548]
4548
4872
 	mla	r6, r2, r6, r3
4549
-	strh	r4, [r6, #4]	@ movhi
4550
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
4551
-.L785:
4873
+	strh	r0, [r6, #4]	@ movhi
4874
+	mov	r0, #0
4875
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
4876
+.L770:
4877
+	mov	r1, r6
4878
+	ldrb	r0, [r9, r5]	@ zero_extendqisi2
4879
+	bl	V2P_block
4880
+	bl	FtlBbmIsBadBlock
4881
+	cmp	r0, #0
4882
+	add	r5, r5, #1
4883
+	addeq	r4, r4, r8
4884
+	uxtheq	r4, r4
4885
+	b	.L768
4886
+.L775:
4552
4887
 	.align	2
4553
-.L784:
4888
+.L774:
4554
4889
 	.word	.LANCHOR0
4555
-	.word	.LANCHOR0+2348
4890
+	.word	.LANCHOR0+2350
4556
4891
 	.word	.LANCHOR2
4557
4892
 	.fnend
4558
4893
 	.size	update_multiplier_value, .-update_multiplier_value
4559
4894
 	.align	2
4560
4895
 	.global	GetFreeBlockMinEraseCount
4896
+	.syntax unified
4897
+	.arm
4898
+	.fpu softvfp
4561
4899
 	.type	GetFreeBlockMinEraseCount, %function
4562
4900
 GetFreeBlockMinEraseCount:
4563
4901
 	.fnstart
4564
4902
 	@ args = 0, pretend = 0, frame = 0
4565
4903
 	@ frame_needed = 0, uses_anonymous_args = 0
4566
4904
 	@ link register save eliminated.
4567
-	ldr	r2, .L789
4568
-	ldr	r0, [r2, #-3532]
4905
+	ldr	r2, .L779
4906
+	ldr	r0, [r2, #-3528]
4569
4907
 	cmp	r0, #0
4570
4908
 	bxeq	lr
4571
-	ldr	r3, [r2, #-3552]
4572
-	rsb	r0, r3, r0
4573
-	ldr	r3, .L789+4
4574
-	mov	r0, r0, asr #1
4909
+	ldr	r3, [r2, #-3548]
4910
+	sub	r0, r0, r3
4911
+	ldr	r3, .L779+4
4912
+	asr	r0, r0, #1
4575
4913
 	mul	r0, r3, r0
4576
-	ldr	r3, [r2, #-3608]
4914
+	ldr	r3, [r2, #-3604]
4577
4915
 	uxth	r0, r0
4578
-	mov	r0, r0, asl #1
4916
+	lsl	r0, r0, #1
4579
4917
 	ldrh	r0, [r3, r0]
4580
4918
 	bx	lr
4581
-.L790:
4919
+.L780:
4582
4920
 	.align	2
4583
-.L789:
4921
+.L779:
4584
4922
 	.word	.LANCHOR2
4585
4923
 	.word	-1431655765
4586
4924
 	.fnend
4587
4925
 	.size	GetFreeBlockMinEraseCount, .-GetFreeBlockMinEraseCount
4588
4926
 	.align	2
4589
4927
 	.global	GetFreeBlockMaxEraseCount
4928
+	.syntax unified
4929
+	.arm
4930
+	.fpu softvfp
4590
4931
 	.type	GetFreeBlockMaxEraseCount, %function
4591
4932
 GetFreeBlockMaxEraseCount:
4592
4933
 	.fnstart
4593
4934
 	@ args = 0, pretend = 0, frame = 0
4594
4935
 	@ frame_needed = 0, uses_anonymous_args = 0
4595
-	ldr	r1, .L801
4596
-	ldr	r3, [r1, #-3532]
4936
+	ldr	r1, .L793
4937
+	ldr	r3, [r1, #-3528]
4597
4938
 	cmp	r3, #0
4598
-	beq	.L797
4939
+	beq	.L787
4599
4940
 	sub	r2, r1, #3520
4600
-	stmfd	sp!, {r4, r5, lr}
4941
+	push	{r4, r5, lr}
4601
4942
 	.save {r4, r5, lr}
4943
+	ldrh	r2, [r2, #-4]
4602
4944
 	mov	r4, #6
4603
-	ldrh	r2, [r2, #-8]
4604
4945
 	movw	r5, #65535
4605
-	ldr	ip, [r1, #-3552]
4606
-	rsb	r2, r2, r2, asl #3
4607
-	rsb	r3, ip, r3
4608
-	mov	r2, r2, asr #3
4609
-	mov	r3, r3, asr #1
4946
+	ldr	ip, [r1, #-3548]
4947
+	rsb	r2, r2, r2, lsl #3
4948
+	sub	r3, r3, ip
4949
+	asr	r2, r2, #3
4950
+	asr	r3, r3, #1
4610
4951
 	cmp	r0, r2
4611
4952
 	uxthgt	r0, r2
4612
-	ldr	r2, .L801+4
4953
+	ldr	r2, .L793+4
4613
4954
 	mul	r3, r2, r3
4614
4955
 	mov	r2, #0
4615
4956
 	uxth	r3, r3
4616
-.L794:
4957
+.L784:
4617
4958
 	uxth	lr, r2
4618
-	cmp	lr, r0
4619
-	bcs	.L796
4959
+	cmp	r0, lr
4960
+	bls	.L786
4620
4961
 	mul	lr, r4, r3
4621
4962
 	add	r2, r2, #1
4622
4963
 	ldrh	lr, [ip, lr]
4623
4964
 	cmp	lr, r5
4624
-	bne	.L798
4625
-.L796:
4626
-	ldr	r2, [r1, #-3608]
4627
-	mov	r3, r3, asl #1
4965
+	bne	.L788
4966
+.L786:
4967
+	ldr	r2, [r1, #-3604]
4968
+	lsl	r3, r3, #1
4628
4969
 	ldrh	r0, [r2, r3]
4629
-	ldmfd	sp!, {r4, r5, pc}
4630
-.L798:
4970
+	pop	{r4, r5, pc}
4971
+.L788:
4631
4972
 	mov	r3, lr
4632
-	b	.L794
4633
-.L797:
4973
+	b	.L784
4974
+.L787:
4634
4975
 	mov	r0, r3
4635
4976
 	bx	lr
4636
-.L802:
4977
+.L794:
4637
4978
 	.align	2
4638
-.L801:
4979
+.L793:
4639
4980
 	.word	.LANCHOR2
4640
4981
 	.word	-1431655765
4641
4982
 	.fnend
4642
4983
 	.size	GetFreeBlockMaxEraseCount, .-GetFreeBlockMaxEraseCount
4643
4984
 	.align	2
4644
4985
 	.global	FtlPrintInfo2buf
4986
+	.syntax unified
4987
+	.arm
4988
+	.fpu softvfp
4645
4989
 	.type	FtlPrintInfo2buf, %function
4646
4990
 FtlPrintInfo2buf:
4647
4991
 	.fnstart
4648
4992
 	@ args = 0, pretend = 0, frame = 16
4649
4993
 	@ frame_needed = 0, uses_anonymous_args = 0
4650
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
4651
-	.save {r4, r5, r6, r7, r8, r9, r10, lr}
4652
-	mov	r7, r0
4653
-	ldr	r8, .L814
4654
-	add	r4, r7, #12
4655
-	ldr	r1, .L814+4
4656
-	.pad #32
4657
-	sub	sp, sp, #32
4994
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
4995
+	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
4996
+	mov	r8, r0
4997
+	ldr	r9, .L808
4998
+	add	r5, r8, #12
4999
+	.pad #36
5000
+	sub	sp, sp, #36
5001
+	ldr	r1, .L808+4
4658
5002
 	bl	strcpy
4659
-	mov	r0, r4
4660
-	ldr	r1, .L814+8
4661
-	ldr	r2, [r8, #116]
5003
+	ldr	r2, [r9, #124]
5004
+	mov	r0, r5
5005
+	ldr	r1, .L808+8
4662
5006
 	bl	sprintf
4663
-	ldr	r1, .L814+12
4664
-	ldr	r2, [r8, #2404]
4665
-	add	r4, r4, r0
4666
-	mov	r0, r4
5007
+	add	r5, r5, r0
5008
+	ldr	r2, [r9, #2408]
5009
+	mov	r0, r5
5010
+	ldr	r1, .L808+12
4667
5011
 	bl	sprintf
4668
-	ldr	r3, .L814+16
4669
-	ldr	r3, [r3, #504]
5012
+	ldr	r3, .L808+16
5013
+	add	r5, r5, r0
5014
+	ldr	r3, [r3, #500]
4670
5015
 	cmp	r3, #1
4671
-	add	r4, r4, r0
4672
-	bne	.L809
4673
-	add	r0, sp, #16
4674
-	add	r1, sp, #20
4675
-	add	r2, sp, #24
5016
+	subne	r0, r5, r8
5017
+	bne	.L795
4676
5018
 	add	r3, sp, #28
5019
+	add	r2, sp, #24
5020
+	add	r1, sp, #20
5021
+	add	r0, sp, #16
4677
5022
 	bl	NandcGetTimeCfg
4678
-	mov	r0, r4
4679
-	ldr	r1, .L814+20
4680
-	ldr	r6, .L814+24
4681
-	sub	r10, r6, #3520
4682
-	ldr	r3, [sp, #24]
4683
-	ldr	r2, [sp, #16]
4684
-	str	r3, [sp]
4685
5023
 	ldr	r3, [sp, #28]
5024
+	mov	r0, r5
5025
+	ldr	r2, [sp, #16]
5026
+	ldr	r1, .L808+20
4686
5027
 	str	r3, [sp, #4]
5028
+	ldr	r3, [sp, #24]
5029
+	ldr	r7, .L808+24
5030
+	str	r3, [sp]
4687
5031
 	ldr	r3, [sp, #20]
5032
+	sub	r10, r7, #3520
4688
5033
 	bl	sprintf
4689
-	ldr	r1, .L814+28
4690
-	add	r4, r4, r0
4691
-	add	r5, r4, #10
4692
-	mov	r0, r4
4693
-	sub	r4, r6, #3600
5034
+	add	r6, r5, r0
5035
+	ldr	r1, .L808+28
5036
+	mov	r0, r6
5037
+	add	r6, r6, #10
4694
5038
 	bl	strcpy
4695
-	mov	r0, r5
4696
-	ldr	r1, .L814+32
4697
-	ldr	r2, [r8, #2448]
5039
+	ldr	r2, [r9, #2452]
5040
+	mov	r0, r6
5041
+	ldr	r1, .L808+32
5042
+	sub	r4, r7, #3584
4698
5043
 	bl	sprintf
4699
-	ldr	r1, .L814+36
4700
-	ldr	r2, [r6, #-3372]
4701
-	add	r5, r5, r0
4702
-	mov	r0, r5
5044
+	add	r6, r6, r0
5045
+	ldr	r2, [r7, #-3368]
5046
+	ldr	r1, .L808+36
5047
+	mov	r0, r6
4703
5048
 	bl	sprintf
4704
-	ldr	r1, .L814+40
4705
-	ldr	r2, [r6, #-3364]
4706
-	add	r5, r5, r0
4707
-	mov	r0, r5
5049
+	add	r6, r6, r0
5050
+	ldr	r2, [r7, #-3364]
5051
+	ldr	r1, .L808+40
5052
+	mov	r0, r6
4708
5053
 	bl	sprintf
4709
-	ldr	r1, .L814+44
4710
-	ldr	r2, [r6, #-3360]
4711
-	add	r5, r5, r0
4712
-	mov	r0, r5
5054
+	add	r6, r6, r0
5055
+	ldr	r2, [r7, #-3360]
5056
+	ldr	r1, .L808+44
5057
+	mov	r0, r6
4713
5058
 	bl	sprintf
4714
-	ldr	r1, .L814+48
4715
-	ldr	r2, [r6, #-3356]
4716
-	add	r5, r5, r0
4717
-	mov	r0, r5
5059
+	add	r6, r6, r0
5060
+	ldr	r2, [r7, #-3356]
5061
+	ldr	r1, .L808+48
5062
+	mov	r0, r6
4718
5063
 	bl	sprintf
4719
-	ldr	r1, .L814+52
4720
-	ldr	r2, [r6, #-3352]
4721
-	add	r5, r5, r0
4722
-	mov	r0, r5
5064
+	add	r6, r6, r0
5065
+	ldr	r2, [r7, #-3352]
5066
+	ldr	r1, .L808+52
5067
+	mov	r0, r6
4723
5068
 	bl	sprintf
4724
-	ldr	r1, .L814+56
4725
-	ldr	r2, [r6, #-3348]
4726
-	add	r5, r5, r0
4727
-	mov	r0, r5
5069
+	add	r6, r6, r0
5070
+	ldr	r2, [r7, #-3348]
5071
+	ldr	r1, .L808+56
5072
+	mov	r0, r6
4728
5073
 	bl	sprintf
4729
-	ldr	r1, .L814+60
4730
-	ldr	r2, [r6, #-3344]
4731
-	add	r5, r5, r0
4732
-	mov	r0, r5
5074
+	add	r6, r6, r0
5075
+	ldr	r2, [r7, #-3344]
5076
+	ldr	r1, .L808+60
5077
+	mov	r0, r6
4733
5078
 	bl	sprintf
4734
-	ldr	r2, [r6, #-3340]
4735
-	ldr	r1, .L814+64
4736
-	mov	r2, r2, lsr #11
4737
-	add	r5, r5, r0
4738
-	mov	r0, r5
5079
+	ldr	r2, [r7, #-3340]
5080
+	add	r6, r6, r0
5081
+	ldr	r1, .L808+64
5082
+	mov	r0, r6
5083
+	sub	r5, r7, #3280
5084
+	lsr	r2, r2, #11
4739
5085
 	bl	sprintf
4740
-	ldr	r2, [r6, #-3336]
4741
-	ldr	r1, .L814+68
4742
-	mov	r2, r2, lsr #11
4743
-	add	r5, r5, r0
4744
-	mov	r0, r5
5086
+	ldr	r2, [r7, #-3336]
5087
+	add	r6, r6, r0
5088
+	ldr	r1, .L808+68
5089
+	mov	r0, r6
5090
+	lsr	r2, r2, #11
4745
5091
 	bl	sprintf
4746
-	ldr	r1, .L814+72
4747
-	ldr	r2, [r6, #-3332]
4748
-	add	r5, r5, r0
4749
-	mov	r0, r5
5092
+	add	r6, r6, r0
5093
+	ldr	r2, [r7, #-3332]
5094
+	ldr	r1, .L808+72
5095
+	mov	r0, r6
4750
5096
 	bl	sprintf
4751
-	ldr	r1, .L814+76
4752
-	ldr	r2, [r6, #-3328]
4753
-	add	r5, r5, r0
4754
-	mov	r0, r5
5097
+	add	r6, r6, r0
5098
+	ldr	r2, [r7, #-3328]
5099
+	ldr	r1, .L808+76
5100
+	mov	r0, r6
4755
5101
 	bl	sprintf
4756
-	add	r5, r5, r0
5102
+	add	r6, r6, r0
4757
5103
 	bl	FtlBbtCalcTotleCnt
4758
-	ldr	r2, .L814+80
4759
-	ldr	r1, .L814+84
4760
-	ldrh	r2, [r2, #6]
5104
+	ldr	r2, .L808+80
4761
5105
 	mov	r3, r0
4762
-	mov	r0, r5
5106
+	ldr	r1, .L808+84
5107
+	mov	r0, r6
5108
+	ldrh	r2, [r2, #6]
4763
5109
 	bl	sprintf
4764
-	ldr	r1, .L814+88
4765
-	ldrh	r2, [r10, #-8]
4766
-	add	r5, r5, r0
4767
-	mov	r0, r5
4768
-	bl	sprintf
4769
-	ldr	r1, .L814+92
4770
-	ldr	r2, [r6, #-3324]
4771
-	add	r5, r5, r0
4772
-	mov	r0, r5
4773
-	bl	sprintf
4774
-	ldr	r1, .L814+96
4775
-	ldr	r2, [r6, #-3320]
4776
-	add	r5, r5, r0
4777
-	mov	r0, r5
4778
-	bl	sprintf
4779
-	ldr	r1, .L814+100
4780
-	ldr	r2, [r6, #-3316]
4781
-	add	r5, r5, r0
4782
-	mov	r0, r5
4783
-	bl	sprintf
4784
-	ldr	r1, .L814+104
4785
-	ldr	r2, [r6, #-3604]
4786
-	add	r5, r5, r0
4787
-	mov	r0, r5
4788
-	bl	sprintf
4789
-	ldr	r1, .L814+108
4790
-	ldr	r2, [r6, #-3312]
4791
-	add	r5, r5, r0
4792
-	mov	r0, r5
4793
-	bl	sprintf
4794
-	ldr	r1, .L814+112
4795
-	ldr	r2, [r6, #-3308]
4796
-	add	r5, r5, r0
4797
-	mov	r0, r5
4798
-	bl	sprintf
4799
-	ldrh	r2, [r4, #30]
4800
-	ldr	r1, .L814+116
4801
-	add	r5, r5, r0
4802
-	mov	r0, r5
4803
-	bl	sprintf
4804
-	ldrh	r2, [r4, #28]
4805
-	ldr	r1, .L814+120
4806
-	sub	r4, r6, #3296
4807
-	add	r5, r5, r0
4808
-	mov	r0, r5
4809
-	bl	sprintf
4810
-	ldr	r1, .L814+124
4811
-	ldr	r2, [r8, #2428]
4812
-	add	r5, r5, r0
4813
-	mov	r0, r5
4814
-	bl	sprintf
4815
-	ldr	r1, .L814+128
4816
-	ldr	r2, [r8, #2420]
4817
-	add	r5, r5, r0
4818
-	mov	r0, r5
4819
-	bl	sprintf
4820
-	ldr	r1, .L814+132
4821
-	ldr	r2, [r8, #2316]
4822
-	add	r5, r5, r0
4823
-	mov	r0, r5
4824
-	bl	sprintf
4825
-	add	r3, r8, #2512
4826
-	ldr	r1, .L814+136
4827
-	ldrh	r2, [r3, #6]
4828
-	add	r5, r5, r0
4829
-	mov	r0, r5
4830
-	bl	sprintf
4831
-	movw	r3, #2328
4832
-	ldrh	r2, [r8, r3]
4833
-	ldr	r1, .L814+140
4834
-	add	r5, r5, r0
4835
-	mov	r0, r5
4836
-	bl	sprintf
4837
-	ldrh	r2, [r4, #-8]
4838
-	ldr	r1, .L814+144
4839
-	add	r5, r5, r0
4840
-	mov	r0, r5
4841
-	bl	sprintf
4842
-	ldr	r1, .L814+148
4843
-	ldr	r2, [r8, #2332]
4844
-	add	r5, r5, r0
4845
-	mov	r0, r5
4846
-	bl	sprintf
4847
-	ldrh	r2, [r4, #-4]
4848
-	ldr	r1, .L814+152
4849
-	add	r5, r5, r0
4850
-	mov	r0, r5
4851
-	bl	sprintf
4852
-	movw	r3, #2452
4853
-	ldrh	r2, [r8, r3]
4854
-	ldr	r1, .L814+156
4855
-	add	r5, r5, r0
4856
-	mov	r0, r5
4857
-	bl	sprintf
4858
-	ldrh	r2, [r4, #-226]
4859
-	ldr	r1, .L814+160
4860
-	add	r5, r5, r0
4861
-	mov	r0, r5
4862
-	bl	sprintf
4863
-	ldr	r1, .L814+164
4864
-	ldrb	r2, [r6, #-3518]	@ zero_extendqisi2
4865
-	add	r5, r5, r0
4866
-	mov	r0, r5
4867
-	bl	sprintf
4868
-	ldr	r1, .L814+168
5110
+	add	r6, r6, r0
4869
5111
 	ldrh	r2, [r10, #-4]
4870
-	add	r5, r5, r0
4871
-	mov	r0, r5
5112
+	ldr	r1, .L808+88
5113
+	mov	r0, r6
4872
5114
 	bl	sprintf
4873
-	ldr	r1, .L814+172
4874
-	ldrb	r2, [r6, #-3516]	@ zero_extendqisi2
4875
-	add	r5, r5, r0
4876
-	mov	r0, r5
5115
+	add	r6, r6, r0
5116
+	ldr	r2, [r7, #-3324]
5117
+	ldr	r1, .L808+92
5118
+	mov	r0, r6
4877
5119
 	bl	sprintf
4878
-	ldrh	r2, [r4, #-224]
4879
-	ldr	r1, .L814+176
4880
-	sub	r4, r6, #3472
4881
-	sub	r9, r4, #4
4882
-	add	r5, r5, r0
4883
-	mov	r0, r5
5120
+	add	r6, r6, r0
5121
+	ldr	r2, [r7, #-3320]
5122
+	ldr	r1, .L808+96
5123
+	mov	r0, r6
4884
5124
 	bl	sprintf
4885
-	ldrh	r3, [r10, #-4]
4886
-	ldr	r2, [r6, #-3544]
4887
-	ldr	r1, .L814+180
4888
-	mov	r3, r3, asl #1
4889
-	ldrh	r2, [r2, r3]
4890
-	add	r5, r5, r0
4891
-	mov	r0, r5
5125
+	add	r6, r6, r0
5126
+	ldr	r2, [r7, #-3316]
5127
+	ldr	r1, .L808+100
5128
+	mov	r0, r6
4892
5129
 	bl	sprintf
4893
-	ldrh	r2, [r4, #-2]
4894
-	ldr	r1, .L814+184
4895
-	add	r5, r5, r0
4896
-	mov	r0, r5
5130
+	add	r6, r6, r0
5131
+	ldr	r2, [r7, #-3600]
5132
+	ldr	r1, .L808+104
5133
+	mov	r0, r6
4897
5134
 	bl	sprintf
4898
-	ldr	r1, .L814+188
4899
-	ldrb	r2, [r6, #-3470]	@ zero_extendqisi2
4900
-	add	r5, r5, r0
4901
-	mov	r0, r5
5135
+	add	r6, r6, r0
5136
+	ldr	r2, [r7, #-3312]
5137
+	ldr	r1, .L808+108
5138
+	mov	r0, r6
4902
5139
 	bl	sprintf
5140
+	add	r6, r6, r0
5141
+	ldr	r2, [r7, #-3308]
5142
+	ldr	r1, .L808+112
5143
+	mov	r0, r6
5144
+	bl	sprintf
5145
+	add	r6, r6, r0
5146
+	ldrh	r2, [r4, #18]
5147
+	ldr	r1, .L808+116
5148
+	mov	r0, r6
5149
+	bl	sprintf
5150
+	add	r6, r6, r0
5151
+	ldrh	r2, [r4, #16]
5152
+	ldr	r1, .L808+120
5153
+	mov	r0, r6
5154
+	bl	sprintf
5155
+	add	r6, r6, r0
5156
+	ldr	r2, [r9, #2432]
5157
+	ldr	r1, .L808+124
5158
+	mov	r0, r6
5159
+	bl	sprintf
5160
+	add	r6, r6, r0
5161
+	ldr	r2, [r9, #2424]
5162
+	ldr	r1, .L808+128
5163
+	mov	r0, r6
5164
+	bl	sprintf
5165
+	add	r6, r6, r0
5166
+	ldr	r2, [r9, #2320]
5167
+	ldr	r1, .L808+132
5168
+	mov	r0, r6
5169
+	bl	sprintf
5170
+	ldr	r3, .L808+136
5171
+	add	r6, r6, r0
5172
+	ldr	r1, .L808+140
5173
+	mov	r0, r6
5174
+	sub	r4, r7, #3296
5175
+	ldrh	r2, [r3, #6]
5176
+	bl	sprintf
5177
+	movw	r3, #2332
5178
+	add	r6, r6, r0
5179
+	ldrh	r2, [r9, r3]
5180
+	mov	r0, r6
5181
+	ldr	r1, .L808+144
5182
+	bl	sprintf
5183
+	add	r6, r6, r0
5184
+	ldrh	r2, [r4, #-8]
5185
+	ldr	r1, .L808+148
5186
+	mov	r0, r6
5187
+	bl	sprintf
5188
+	add	r6, r6, r0
5189
+	ldr	r2, [r9, #2336]
5190
+	ldr	r1, .L808+152
5191
+	mov	r0, r6
5192
+	bl	sprintf
5193
+	add	r6, r6, r0
4903
5194
 	ldrh	r2, [r4, #-4]
4904
-	ldr	r1, .L814+192
4905
-	add	r5, r5, r0
4906
-	mov	r0, r5
5195
+	ldr	r1, .L808+156
5196
+	mov	r0, r6
4907
5197
 	bl	sprintf
4908
-	ldr	r1, .L814+196
4909
-	ldrb	r2, [r6, #-3468]	@ zero_extendqisi2
4910
-	add	r5, r5, r0
4911
-	mov	r0, r5
5198
+	movw	r3, #2456
5199
+	add	r6, r6, r0
5200
+	ldrh	r2, [r9, r3]
5201
+	mov	r0, r6
5202
+	ldr	r1, .L808+160
5203
+	sub	r4, r7, #3472
4912
5204
 	bl	sprintf
4913
-	ldrh	r2, [r9, #4]
4914
-	ldr	r1, .L814+200
4915
-	sub	r9, r6, #3424
4916
-	add	r5, r5, r0
4917
-	mov	r0, r5
5205
+	add	r6, r6, r0
5206
+	ldrh	r2, [r10, #2]
5207
+	ldr	r1, .L808+164
5208
+	mov	r0, r6
4918
5209
 	bl	sprintf
4919
-	ldrh	r3, [r4, #-4]
4920
-	ldr	r2, [r6, #-3544]
4921
-	ldr	r1, .L814+204
4922
-	mov	r3, r3, asl #1
5210
+	add	r6, r6, r0
5211
+	ldrb	r2, [r7, #-3514]	@ zero_extendqisi2
5212
+	ldr	r1, .L808+168
5213
+	mov	r0, r6
5214
+	bl	sprintf
5215
+	add	r6, r6, r0
5216
+	ldrh	r2, [r10]
5217
+	ldr	r1, .L808+172
5218
+	mov	r0, r6
5219
+	bl	sprintf
5220
+	add	r6, r6, r0
5221
+	ldrb	r2, [r7, #-3512]	@ zero_extendqisi2
5222
+	ldr	r1, .L808+176
5223
+	mov	r0, r6
5224
+	bl	sprintf
5225
+	add	r6, r6, r0
5226
+	ldrh	r2, [r10, #4]
5227
+	ldr	r1, .L808+180
5228
+	mov	r0, r6
5229
+	bl	sprintf
5230
+	ldrh	r3, [r10]
5231
+	add	r6, r6, r0
5232
+	ldr	r2, [r7, #-3540]
5233
+	mov	r0, r6
5234
+	ldr	r1, .L808+184
5235
+	lsl	r3, r3, #1
4923
5236
 	ldrh	r2, [r2, r3]
4924
-	add	r5, r5, r0
4925
-	mov	r0, r5
4926
5237
 	bl	sprintf
4927
-	ldrh	r2, [r4, #46]
4928
-	ldr	r1, .L814+208
4929
-	add	r5, r5, r0
4930
-	mov	r0, r5
5238
+	add	r6, r6, r0
5239
+	ldrh	r2, [r4, #2]
5240
+	ldr	r1, .L808+188
5241
+	mov	r0, r6
4931
5242
 	bl	sprintf
4932
-	ldr	r1, .L814+212
4933
-	ldrb	r2, [r6, #-3422]	@ zero_extendqisi2
4934
-	add	r5, r5, r0
4935
-	mov	r0, r5
5243
+	add	r6, r6, r0
5244
+	ldrb	r2, [r7, #-3466]	@ zero_extendqisi2
5245
+	ldr	r1, .L808+192
5246
+	mov	r0, r6
4936
5247
 	bl	sprintf
4937
-	ldrh	r2, [r9, #-4]
4938
-	ldr	r1, .L814+216
4939
-	sub	r9, r6, #3280
4940
-	add	r5, r5, r0
4941
-	mov	r0, r5
5248
+	add	r6, r6, r0
5249
+	ldrh	r2, [r4]
5250
+	ldr	r1, .L808+196
5251
+	mov	r0, r6
4942
5252
 	bl	sprintf
4943
-	ldr	r1, .L814+220
4944
-	ldrb	r2, [r6, #-3420]	@ zero_extendqisi2
4945
-	add	r5, r5, r0
4946
-	mov	r0, r5
5253
+	add	r6, r6, r0
5254
+	ldrb	r2, [r7, #-3464]	@ zero_extendqisi2
5255
+	ldr	r1, .L808+200
5256
+	mov	r0, r6
4947
5257
 	bl	sprintf
4948
-	ldrh	r2, [r4, #48]
4949
-	ldr	r1, .L814+224
4950
-	add	r5, r5, r0
4951
-	mov	r0, r5
5258
+	add	r6, r6, r0
5259
+	ldrh	r2, [r4, #4]
5260
+	ldr	r1, .L808+204
5261
+	mov	r0, r6
4952
5262
 	bl	sprintf
4953
-	ldrh	r2, [r4, #190]
4954
-	ldr	r1, .L814+228
4955
-	add	r5, r5, r0
4956
-	mov	r0, r5
5263
+	ldrh	r3, [r4]
5264
+	add	r6, r6, r0
5265
+	ldr	r2, [r7, #-3540]
5266
+	mov	r0, r6
5267
+	ldr	r1, .L808+208
5268
+	sub	r4, r7, #3424
5269
+	lsl	r3, r3, #1
5270
+	ldrh	r2, [r2, r3]
4957
5271
 	bl	sprintf
4958
-	ldr	r1, .L814+232
4959
-	ldrb	r2, [r6, #-3278]	@ zero_extendqisi2
4960
-	add	r5, r5, r0
4961
-	mov	r0, r5
5272
+	add	r6, r6, r0
5273
+	ldrh	r2, [r4, #2]
5274
+	ldr	r1, .L808+212
5275
+	mov	r0, r6
4962
5276
 	bl	sprintf
4963
-	ldr	r1, .L814+236
4964
-	ldrh	r2, [r9, #-4]
4965
-	add	r5, r5, r0
4966
-	mov	r0, r5
5277
+	add	r6, r6, r0
5278
+	ldrb	r2, [r7, #-3418]	@ zero_extendqisi2
5279
+	ldr	r1, .L808+216
5280
+	mov	r0, r6
4967
5281
 	bl	sprintf
4968
-	ldr	r1, .L814+240
4969
-	ldrb	r2, [r6, #-3276]	@ zero_extendqisi2
4970
-	add	r5, r5, r0
4971
-	mov	r0, r5
5282
+	add	r6, r6, r0
5283
+	ldrh	r2, [r4]
5284
+	ldr	r1, .L808+220
5285
+	mov	r0, r6
4972
5286
 	bl	sprintf
4973
-	ldrh	r2, [r4, #192]
4974
-	ldr	r1, .L814+244
4975
-	add	r5, r5, r0
4976
-	mov	r0, r5
5287
+	add	r6, r6, r0
5288
+	ldrb	r2, [r7, #-3416]	@ zero_extendqisi2
5289
+	ldr	r1, .L808+224
5290
+	mov	r0, r6
4977
5291
 	bl	sprintf
4978
-	ldr	r1, [r6, #-3148]
4979
-	ldr	r3, [r8, #2244]
4980
-	ldr	r2, [r6, #-3236]
4981
-	orr	r2, r3, r2, asl #8
4982
-	ldr	r3, [r6, #-3152]
4983
-	str	r1, [sp]
4984
-	add	r5, r5, r0
4985
-	ldr	r1, [r6, #-3156]
4986
-	mov	r0, r5
4987
-	str	r1, [sp, #4]
4988
-	ldr	r1, .L814+248
5292
+	add	r6, r6, r0
5293
+	ldrh	r2, [r4, #4]
5294
+	ldr	r1, .L808+228
5295
+	mov	r0, r6
4989
5296
 	bl	sprintf
4990
-	ldr	r1, .L814+252
4991
-	ldr	r2, [r6, #-3160]
4992
-	add	r4, r5, r0
4993
-	sub	r5, r6, #2704
5297
+	add	r6, r6, r0
5298
+	ldrh	r2, [r5, #-2]
5299
+	ldr	r1, .L808+232
5300
+	mov	r0, r6
5301
+	bl	sprintf
5302
+	add	r6, r6, r0
5303
+	ldrb	r2, [r7, #-3278]	@ zero_extendqisi2
5304
+	ldr	r1, .L808+236
5305
+	mov	r0, r6
5306
+	bl	sprintf
5307
+	add	r6, r6, r0
5308
+	ldrh	r2, [r5, #-4]
5309
+	ldr	r1, .L808+240
5310
+	mov	r0, r6
5311
+	bl	sprintf
5312
+	add	r6, r6, r0
5313
+	ldrb	r2, [r7, #-3276]	@ zero_extendqisi2
5314
+	ldr	r1, .L808+244
5315
+	mov	r0, r6
5316
+	bl	sprintf
5317
+	sub	r4, r5, #4
5318
+	add	r6, r6, r0
5319
+	ldrh	r2, [r4, #4]
5320
+	mov	r0, r6
5321
+	ldr	r1, .L808+248
5322
+	bl	sprintf
5323
+	ldr	r3, [r7, #-3160]
5324
+	add	r6, r6, r0
5325
+	ldr	r2, [r9, #2248]
5326
+	mov	r0, r6
5327
+	ldr	r1, [r7, #-2724]
5328
+	str	r3, [sp, #4]
5329
+	ldr	r3, [r7, #-3152]
5330
+	orr	r2, r2, r1, lsl #8
5331
+	ldr	r1, .L808+252
5332
+	str	r3, [sp]
5333
+	ldr	r3, [r7, #-3156]
5334
+	bl	sprintf
5335
+	add	r4, r6, r0
5336
+	ldr	r2, [r7, #-3164]
5337
+	ldr	r1, .L808+256
4994
5338
 	mov	r0, r4
4995
5339
 	bl	sprintf
4996
-	ldr	r1, .L814+256
4997
-	ldr	r2, [r6, #-3136]
4998
5340
 	add	r4, r4, r0
5341
+	ldr	r2, [r7, #-3140]
5342
+	ldr	r1, .L808+260
4999
5343
 	mov	r0, r4
5000
5344
 	bl	sprintf
5001
-	sub	r3, r6, #2720
5002
-	ldr	r1, .L814+260
5345
+	sub	r3, r7, #2720
5346
+	add	r4, r4, r0
5003
5347
 	ldrh	r2, [r3]
5348
+	mov	r0, r4
5349
+	ldr	r1, .L808+264
5350
+	sub	r6, r7, #2704
5351
+	bl	sprintf
5004
5352
 	add	r4, r4, r0
5353
+	ldrh	r2, [r6, #-14]
5354
+	ldr	r1, .L808+268
5005
5355
 	mov	r0, r4
5006
5356
 	bl	sprintf
5007
-	ldr	r1, .L814+264
5008
-	ldrh	r2, [r5, #-14]
5009
5357
 	add	r4, r4, r0
5358
+	ldr	r2, [r7, #-2716]
5359
+	ldr	r1, .L808+272
5010
5360
 	mov	r0, r4
5011
5361
 	bl	sprintf
5012
-	ldr	r1, .L814+268
5013
-	ldr	r2, [r6, #-2716]
5014
5362
 	add	r4, r4, r0
5015
-	mov	r0, r4
5016
-	bl	sprintf
5017
-	ldr	r1, .L814+272
5018
-	ldrh	r2, [r5, #-8]
5019
-	add	r4, r4, r0
5363
+	ldrh	r2, [r6, #-8]
5364
+	ldr	r1, .L808+276
5020
5365
 	mov	r0, r4
5021
5366
 	bl	sprintf
5022
5367
 	add	r4, r4, r0
5023
5368
 	bl	GetFreeBlockMinEraseCount
5024
-	ldr	r1, .L814+276
5369
+	ldr	r1, .L808+280
5025
5370
 	mov	r2, r0
5026
5371
 	mov	r0, r4
5027
5372
 	bl	sprintf
5028
5373
 	add	r4, r4, r0
5029
-	ldrh	r0, [r10, #-8]
5374
+	ldrh	r0, [r10, #-4]
5030
5375
 	bl	GetFreeBlockMaxEraseCount
5031
-	ldr	r1, .L814+280
5376
+	ldr	r1, .L808+284
5032
5377
 	mov	r2, r0
5033
5378
 	mov	r0, r4
5034
5379
 	bl	sprintf
5035
-	ldrh	r3, [r9, #-4]
5380
+	ldrh	r3, [r5, #-4]
5036
5381
 	movw	r2, #65535
5037
-	cmp	r3, r2
5038
5382
 	add	r4, r4, r0
5039
-	beq	.L806
5040
-	ldr	r2, [r6, #-3544]
5041
-	mov	r3, r3, asl #1
5383
+	cmp	r3, r2
5384
+	beq	.L798
5385
+	ldr	r2, [r7, #-3540]
5386
+	lsl	r3, r3, #1
5042
5387
 	mov	r0, r4
5043
-	ldr	r1, .L814+284
5388
+	ldr	r1, .L808+288
5044
5389
 	ldrh	r2, [r2, r3]
5045
5390
 	bl	sprintf
5046
5391
 	add	r4, r4, r0
5047
-.L806:
5392
+.L798:
5048
5393
 	mov	r0, #0
5049
-	mov	r5, #0
5394
+	ldr	r9, .L808+292
5050
5395
 	bl	List_get_gc_head_node
5051
-	movw	r10, #65535
5052
-	mov	r9, #6
5053
5396
 	uxth	r3, r0
5054
-.L808:
5055
-	cmp	r3, r10
5056
-	beq	.L807
5057
-	ldr	r2, [r6, #-3544]
5058
-	mov	r1, r3, asl #1
5059
-	mul	r8, r9, r3
5397
+	mov	r5, #0
5398
+	movw	fp, #65535
5399
+	mov	r10, #6
5400
+.L800:
5401
+	cmp	r3, fp
5402
+	beq	.L799
5403
+	ldr	r2, [r7, #-3604]
5404
+	lsl	r1, r3, #1
5405
+	mul	r6, r10, r3
5060
5406
 	mov	r0, r4
5061
5407
 	ldrh	r2, [r2, r1]
5062
-	str	r2, [sp]
5063
-	ldr	r2, [r6, #-3552]
5064
-	add	r2, r2, r8
5408
+	str	r2, [sp, #8]
5409
+	ldr	r2, [r7, #-3548]
5410
+	add	r2, r2, r6
5065
5411
 	ldrh	r2, [r2, #4]
5066
5412
 	str	r2, [sp, #4]
5067
-	ldr	r2, [r6, #-3608]
5413
+	ldr	r2, [r7, #-3540]
5068
5414
 	ldrh	r2, [r2, r1]
5069
-	ldr	r1, .L814+288
5070
-	str	r2, [sp, #8]
5415
+	mov	r1, r9
5416
+	str	r2, [sp]
5071
5417
 	mov	r2, r5
5072
5418
 	bl	sprintf
5073
5419
 	add	r5, r5, #1
5074
-	ldr	r3, [r6, #-3552]
5420
+	ldr	r3, [r7, #-3548]
5075
5421
 	cmp	r5, #16
5076
-	ldrh	r3, [r3, r8]
5077
5422
 	add	r4, r4, r0
5078
-	bne	.L808
5079
-.L807:
5080
-	ldr	r2, [r6, #-3552]
5423
+	ldrh	r3, [r3, r6]
5424
+	bne	.L800
5425
+.L799:
5426
+	ldr	r2, [r7, #-3548]
5081
5427
 	mov	r5, #0
5082
-	ldr	r3, [r6, #-3532]
5083
-	movw	r10, #65535
5084
-	mov	r9, #6
5085
-	rsb	r3, r2, r3
5086
-	ldr	r2, .L814+292
5087
-	mov	r3, r3, asr #1
5428
+	ldr	r3, [r7, #-3528]
5429
+	movw	r9, #65535
5430
+	ldr	fp, .L808+296
5431
+	mov	r10, #6
5432
+	sub	r3, r3, r2
5433
+	ldr	r2, .L808+300
5434
+	asr	r3, r3, #1
5088
5435
 	mul	r3, r2, r3
5089
5436
 	uxth	r3, r3
5090
-.L810:
5091
-	cmp	r3, r10
5092
-	beq	.L809
5093
-	mul	r8, r9, r3
5094
-	ldr	r2, [r6, #-3552]
5095
-	ldr	r1, [r6, #-3608]
5437
+.L802:
5438
+	cmp	r3, r9
5439
+	beq	.L801
5440
+	ldr	r1, [r7, #-3604]
5441
+	lsl	r2, r3, #1
5442
+	mul	r6, r10, r3
5096
5443
 	mov	r0, r4
5097
-	add	r2, r2, r8
5444
+	ldrh	r2, [r1, r2]
5445
+	mov	r1, fp
5446
+	str	r2, [sp, #4]
5447
+	ldr	r2, [r7, #-3548]
5448
+	add	r2, r2, r6
5098
5449
 	ldrh	r2, [r2, #4]
5099
5450
 	str	r2, [sp]
5100
-	mov	r2, r3, asl #1
5101
-	ldrh	r2, [r1, r2]
5102
-	ldr	r1, .L814+296
5103
-	str	r2, [sp, #4]
5104
5451
 	mov	r2, r5
5105
-	bl	sprintf
5106
5452
 	add	r5, r5, #1
5107
-	ldr	r3, [r6, #-3552]
5453
+	bl	sprintf
5108
5454
 	cmp	r5, #4
5109
-	ldrh	r3, [r3, r8]
5110
5455
 	add	r4, r4, r0
5111
-	bne	.L810
5112
-.L809:
5113
-	rsb	r0, r7, r4
5114
-	add	sp, sp, #32
5456
+	ldrne	r3, [r7, #-3548]
5457
+	ldrhne	r3, [r3, r6]
5458
+	bne	.L802
5459
+.L801:
5460
+	sub	r0, r4, r8
5461
+.L795:
5462
+	add	sp, sp, #36
5115
5463
 	@ sp needed
5116
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
5117
-.L815:
5464
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
5465
+.L809:
5118
5466
 	.align	2
5119
-.L814:
5467
+.L808:
5120
5468
 	.word	.LANCHOR0
5121
5469
 	.word	.LC6
5122
5470
 	.word	.LC7
..
..
@@ -5137,7 +5485,7 @@
5137
5485
 	.word	.LC20
5138
5486
 	.word	.LC21
5139
5487
 	.word	.LC22
5140
-	.word	.LANCHOR0+2452
5488
+	.word	.LANCHOR0+2456
5141
5489
 	.word	.LC23
5142
5490
 	.word	.LC24
5143
5491
 	.word	.LC25
..
..
@@ -5151,6 +5499,7 @@
5151
5499
 	.word	.LC33
5152
5500
 	.word	.LC34
5153
5501
 	.word	.LC35
5502
+	.word	.LANCHOR0+2516
5154
5503
 	.word	.LC36
5155
5504
 	.word	.LC37
5156
5505
 	.word	.LC38
..
..
@@ -5190,237 +5539,243 @@
5190
5539
 	.word	.LC72
5191
5540
 	.word	.LC73
5192
5541
 	.word	.LC74
5193
-	.word	-1431655765
5194
5542
 	.word	.LC75
5543
+	.word	-1431655765
5195
5544
 	.fnend
5196
5545
 	.size	FtlPrintInfo2buf, .-FtlPrintInfo2buf
5197
5546
 	.align	2
5198
5547
 	.global	ftl_proc_ftl_read
5548
+	.syntax unified
5549
+	.arm
5550
+	.fpu softvfp
5199
5551
 	.type	ftl_proc_ftl_read, %function
5200
5552
 ftl_proc_ftl_read:
5201
5553
 	.fnstart
5202
5554
 	@ args = 0, pretend = 0, frame = 0
5203
5555
 	@ frame_needed = 0, uses_anonymous_args = 0
5204
-	stmfd	sp!, {r3, r4, r5, lr}
5205
-	.save {r3, r4, r5, lr}
5556
+	push	{r4, r5, r6, lr}
5557
+	.save {r4, r5, r6, lr}
5206
5558
 	mov	r5, r0
5207
-	ldr	r1, .L818
5208
-	ldr	r2, .L818+4
5559
+	ldr	r2, .L812
5560
+	ldr	r1, .L812+4
5209
5561
 	bl	sprintf
5210
5562
 	add	r4, r5, r0
5211
5563
 	mov	r0, r4
5212
5564
 	bl	FtlPrintInfo2buf
5213
5565
 	add	r0, r4, r0
5214
-	rsb	r0, r5, r0
5215
-	ldmfd	sp!, {r3, r4, r5, pc}
5216
-.L819:
5566
+	sub	r0, r0, r5
5567
+	pop	{r4, r5, r6, pc}
5568
+.L813:
5217
5569
 	.align	2
5218
-.L818:
5570
+.L812:
5219
5571
 	.word	.LC76
5220
5572
 	.word	.LC77
5221
5573
 	.fnend
5222
5574
 	.size	ftl_proc_ftl_read, .-ftl_proc_ftl_read
5223
5575
 	.align	2
5224
5576
 	.global	GetSwlReplaceBlock
5577
+	.syntax unified
5578
+	.arm
5579
+	.fpu softvfp
5225
5580
 	.type	GetSwlReplaceBlock, %function
5226
5581
 GetSwlReplaceBlock:
5227
5582
 	.fnstart
5228
5583
 	@ args = 0, pretend = 0, frame = 8
5229
5584
 	@ frame_needed = 0, uses_anonymous_args = 0
5230
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5585
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
5231
5586
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5232
5587
 	.pad #28
5233
5588
 	sub	sp, sp, #28
5234
-	ldr	r4, .L850
5589
+	ldr	r4, .L842
5235
5590
 	ldr	r2, [r4, #-3316]
5236
5591
 	ldr	r3, [r4, #-3308]
5237
5592
 	cmp	r2, r3
5238
-	bcs	.L821
5239
-	ldr	r2, .L850+4
5240
-	movw	r1, #2328
5241
-	ldr	r0, [r4, #-3608]
5593
+	bcs	.L815
5594
+	ldr	r0, .L842+4
5595
+	movw	r2, #2332
5242
5596
 	mov	r3, #0
5243
5597
 	str	r3, [r4, #-3324]
5244
-	ldrh	r1, [r2, r1]
5245
-	sub	r0, r0, #2
5246
-	mov	r5, r2
5247
-.L822:
5598
+	ldrh	r1, [r0, r2]
5599
+	mov	r6, r0
5600
+	ldr	r2, [r4, #-3604]
5601
+	sub	r2, r2, #2
5602
+.L816:
5248
5603
 	cmp	r3, r1
5249
-	bcs	.L849
5250
-	ldrh	r2, [r0, #2]!
5251
-	add	r3, r3, #1
5252
-	ldr	ip, [r4, #-3324]
5253
-	add	r2, r2, ip
5254
-	str	r2, [r4, #-3324]
5255
-	b	.L822
5256
-.L849:
5257
-	ldr	r6, [r4, #-3324]
5258
-	mov	r0, r6
5604
+	bcc	.L817
5605
+	ldr	r5, [r4, #-3324]
5606
+	mov	r0, r5
5259
5607
 	bl	__aeabi_uidiv
5260
-	movw	r3, #2380
5261
-	ldrh	r1, [r5, r3]
5262
5608
 	str	r0, [r4, #-3316]
5609
+	movw	r3, #2382
5263
5610
 	ldr	r0, [r4, #-3320]
5264
-	rsb	r0, r0, r6
5611
+	ldrh	r1, [r6, r3]
5612
+	sub	r0, r5, r0
5265
5613
 	bl	__aeabi_uidiv
5266
5614
 	str	r0, [r4, #-3324]
5267
-	b	.L824
5268
-.L821:
5269
-	ldr	r3, [r4, #-3312]
5270
-	cmp	r2, r3
5271
-	bls	.L824
5272
-	ldr	ip, .L850+8
5273
-	add	r3, r3, #1
5274
-	str	r3, [r4, #-3312]
5275
-	mov	r3, #0
5276
-.L826:
5277
-	ldrh	r2, [ip]
5278
-	cmp	r3, r2
5279
-	bcs	.L824
5280
-	ldr	r0, [r4, #-3608]
5281
-	mov	r1, r3, asl #1
5282
-	add	r3, r3, #1
5283
-	ldrh	r2, [r0, r1]
5284
-	add	r2, r2, #1
5285
-	strh	r2, [r0, r1]	@ movhi
5286
-	b	.L826
5287
-.L824:
5288
-	ldr	r6, [r4, #-3308]
5615
+.L818:
5616
+	ldr	r5, [r4, #-3308]
5289
5617
 	ldr	r8, [r4, #-3316]
5290
-	add	r3, r6, #256
5618
+	add	r3, r5, #256
5291
5619
 	cmp	r3, r8
5292
-	bls	.L829
5293
-	ldr	r2, .L850
5294
-	add	r3, r6, #768
5295
-	ldr	r2, [r2, #-3312]
5620
+	bls	.L823
5621
+	ldr	r2, [r4, #-3312]
5622
+	add	r3, r5, #768
5296
5623
 	cmp	r3, r2
5297
-	bls	.L829
5298
-	ldr	r3, .L850+4
5299
-	cmp	r6, #40
5300
-	ldr	r2, [r3, #2244]
5624
+	bls	.L823
5625
+	ldr	r3, .L842+4
5626
+	cmp	r5, #40
5627
+	ldr	r2, [r3, #2248]
5301
5628
 	movls	r3, #0
5302
5629
 	movhi	r3, #1
5303
5630
 	cmp	r2, #0
5304
5631
 	orreq	r3, r3, #1
5305
5632
 	cmp	r3, #0
5306
-	beq	.L829
5307
-.L831:
5308
-	movw	r0, #65535
5309
-	b	.L830
5310
-.L829:
5311
-	ldr	r5, .L850
5312
-	sub	r3, r5, #3520
5313
-	ldrh	r0, [r3, #-8]
5314
-	add	r0, r0, r0, asl #1
5315
-	ubfx	r0, r0, #2, #16
5316
-	bl	GetFreeBlockMaxEraseCount
5317
-	add	r1, r6, #64
5318
-	cmp	r0, r1
5319
-	mov	r9, r0
5320
-	movcs	r1, #0
5321
-	movcc	r1, #1
5322
-	cmp	r6, #40
5323
-	movls	r1, #0
5324
-	cmp	r1, #0
5325
-	bne	.L831
5326
-	ldr	r3, [r5, #-3548]
5327
-	cmp	r3, #0
5328
-	beq	.L831
5329
-	ldr	r0, .L850+4
5330
-	movw	r2, #2328
5331
-	ldr	ip, .L850+12
5332
-	movw	r7, #65535
5333
-	ldr	r10, [r5, #-3608]
5334
-	mov	lr, #6
5335
-	ldrh	r2, [r0, r2]
5336
-	ldr	r0, [r5, #-3552]
5337
-	mov	r5, r7
5338
-	str	r2, [sp, #20]
5339
-.L832:
5340
-	ldrh	r2, [r3]
5341
-	movw	fp, #65535
5342
-	cmp	r2, fp
5343
-	beq	.L834
5344
-	add	r1, r1, #1
5345
-	ldr	fp, [sp, #20]
5346
-	uxth	r1, r1
5347
-	cmp	r1, fp
5348
-	bhi	.L831
5349
-	ldrh	fp, [r3, #4]
5350
-	cmp	fp, #0
5351
-	beq	.L833
5352
-	rsb	r3, r0, r3
5353
-	mov	r3, r3, asr #1
5354
-	mul	r3, ip, r3
5355
-	uxth	r3, r3
5356
-	mov	fp, r3, asl #1
5357
-	ldrh	fp, [r10, fp]
5358
-	cmp	fp, r6
5359
-	bls	.L838
5360
-	cmp	fp, r7
5361
-	movcc	r7, fp
5362
-	movcc	r5, r3
5363
-.L833:
5364
-	mla	r3, lr, r2, r0
5365
-	b	.L832
5366
-.L838:
5367
-	mov	r5, r3
5368
-.L834:
5369
-	movw	r3, #65535
5370
-	cmp	r5, r3
5371
-	beq	.L831
5372
-	mov	r3, r5, asl #1
5373
-	ldrh	fp, [r10, r3]
5374
-	cmp	fp, r6
5375
-	bls	.L836
5376
-	str	r3, [sp, #20]
5377
-	bl	GetFreeBlockMinEraseCount
5378
-	ldr	r3, [sp, #20]
5379
-	cmp	r0, r6
5380
-	strhi	r7, [r4, #-3308]
5381
-.L836:
5382
-	cmp	fp, r8
5383
-	bcs	.L831
5384
-	add	r2, fp, #128
5385
-	cmp	r9, r2
5386
-	ble	.L831
5387
-	add	r2, fp, #256
5388
-	cmp	r2, r8
5389
-	bcc	.L837
5390
-	ldr	r2, [r4, #-3312]
5391
-	add	fp, fp, #768
5392
-	cmp	fp, r2
5393
-	bcs	.L831
5394
-.L837:
5395
-	ldr	r2, [r4, #-3544]
5396
-	mov	r1, r5
5397
-	ldr	r0, .L850+16
5398
-	ldrh	r2, [r2, r3]
5399
-	str	r2, [sp]
5400
-	mov	r2, r8
5401
-	ldrh	r3, [r10, r3]
5402
-	stmib	sp, {r3, r9}
5403
-	ldr	r3, [r4, #-3312]
5404
-	bl	printk
5405
-	mov	r0, r5
5406
-	mov	r3, #1
5407
-	str	r3, [r4, #-2708]
5408
-.L830:
5633
+	beq	.L823
5634
+.L825:
5635
+	movw	r6, #65535
5636
+.L824:
5637
+	mov	r0, r6
5409
5638
 	add	sp, sp, #28
5410
5639
 	@ sp needed
5411
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
5412
-.L851:
5640
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
5641
+.L817:
5642
+	ldrh	r0, [r2, #2]!
5643
+	add	r3, r3, #1
5644
+	ldr	ip, [r4, #-3324]
5645
+	add	r0, r0, ip
5646
+	str	r0, [r4, #-3324]
5647
+	b	.L816
5648
+.L815:
5649
+	ldr	r3, [r4, #-3312]
5650
+	cmp	r2, r3
5651
+	bls	.L818
5652
+	ldr	ip, .L842+8
5653
+	add	r3, r3, #1
5654
+	str	r3, [r4, #-3312]
5655
+	mov	r3, #0
5656
+.L820:
5657
+	ldrh	r2, [ip]
5658
+	cmp	r3, r2
5659
+	bcs	.L818
5660
+	ldr	r0, [r4, #-3604]
5661
+	lsl	r1, r3, #1
5662
+	add	r3, r3, #1
5663
+	ldrh	r2, [r0, r1]
5664
+	add	r2, r2, #1
5665
+	strh	r2, [r0, r1]	@ movhi
5666
+	b	.L820
5667
+.L823:
5668
+	ldr	r3, .L842+12
5669
+	ldrh	r0, [r3, #-4]
5670
+	add	r0, r0, r0, lsl #1
5671
+	ubfx	r0, r0, #2, #16
5672
+	bl	GetFreeBlockMaxEraseCount
5673
+	add	r1, r5, #64
5674
+	mov	r10, r0
5675
+	cmp	r0, r1
5676
+	movcs	r1, #0
5677
+	movcc	r1, #1
5678
+	cmp	r5, #40
5679
+	movls	r1, #0
5680
+	cmp	r1, #0
5681
+	bne	.L825
5682
+	ldr	r3, [r4, #-3544]
5683
+	cmp	r3, #0
5684
+	beq	.L825
5685
+	ldr	r0, .L842+4
5686
+	movw	r2, #2332
5687
+	ldr	ip, [r4, #-3548]
5688
+	movw	r7, #65535
5689
+	ldr	r9, [r4, #-3604]
5690
+	mov	fp, #6
5691
+	ldrh	r2, [r0, r2]
5692
+	ldr	lr, .L842+16
5693
+	str	r2, [sp, #20]
5694
+	mov	r2, r7
5695
+.L826:
5696
+	ldrh	r0, [r3]
5697
+	movw	r6, #65535
5698
+	cmp	r0, r6
5699
+	bne	.L829
5700
+	mov	r6, r2
5701
+.L828:
5702
+	movw	r3, #65535
5703
+	cmp	r6, r3
5704
+	beq	.L825
5705
+	lsl	fp, r6, #1
5706
+	ldrh	r1, [r9, fp]
5707
+	cmp	r5, r1
5708
+	bcs	.L830
5709
+	bl	GetFreeBlockMinEraseCount
5710
+	cmp	r5, r0
5711
+	strcc	r7, [r4, #-3308]
5712
+.L830:
5713
+	cmp	r8, r1
5714
+	bls	.L825
5715
+	add	r3, r1, #128
5716
+	cmp	r10, r3
5717
+	ble	.L825
5718
+	add	r3, r1, #256
5719
+	cmp	r8, r3
5720
+	bhi	.L831
5721
+	ldr	r3, [r4, #-3312]
5722
+	add	r1, r1, #768
5723
+	cmp	r1, r3
5724
+	bcs	.L825
5725
+.L831:
5726
+	str	r10, [sp, #8]
5727
+	mov	r2, r8
5728
+	ldrh	r3, [r9, fp]
5729
+	mov	r1, r6
5730
+	ldr	r0, .L842+20
5731
+	str	r3, [sp, #4]
5732
+	ldr	r3, [r4, #-3540]
5733
+	ldrh	r3, [r3, fp]
5734
+	str	r3, [sp]
5735
+	ldr	r3, [r4, #-3312]
5736
+	bl	printk
5737
+	mov	r3, #1
5738
+	str	r3, [r4, #-2708]
5739
+	b	.L824
5740
+.L829:
5741
+	add	r1, r1, #1
5742
+	ldr	r6, [sp, #20]
5743
+	uxth	r1, r1
5744
+	cmp	r1, r6
5745
+	bhi	.L825
5746
+	ldrh	r6, [r3, #4]
5747
+	cmp	r6, #0
5748
+	beq	.L827
5749
+	sub	r3, r3, ip
5750
+	asr	r3, r3, #1
5751
+	mul	r3, lr, r3
5752
+	uxth	r6, r3
5753
+	lsl	r3, r6, #1
5754
+	ldrh	r3, [r9, r3]
5755
+	cmp	r5, r3
5756
+	bcs	.L828
5757
+	cmp	r7, r3
5758
+	movhi	r7, r3
5759
+	movhi	r2, r6
5760
+.L827:
5761
+	mla	r3, fp, r0, ip
5762
+	b	.L826
5763
+.L843:
5413
5764
 	.align	2
5414
-.L850:
5765
+.L842:
5415
5766
 	.word	.LANCHOR2
5416
5767
 	.word	.LANCHOR0
5417
-	.word	.LANCHOR0+2328
5768
+	.word	.LANCHOR0+2332
5769
+	.word	.LANCHOR2-3520
5418
5770
 	.word	-1431655765
5419
5771
 	.word	.LC78
5420
5772
 	.fnend
5421
5773
 	.size	GetSwlReplaceBlock, .-GetSwlReplaceBlock
5422
5774
 	.align	2
5423
5775
 	.global	free_data_superblock
5776
+	.syntax unified
5777
+	.arm
5778
+	.fpu softvfp
5424
5779
 	.type	free_data_superblock, %function
5425
5780
 free_data_superblock:
5426
5781
 	.fnstart
..
..
@@ -5428,467 +5783,494 @@
5428
5783
 	@ frame_needed = 0, uses_anonymous_args = 0
5429
5784
 	movw	r2, #65535
5430
5785
 	cmp	r0, r2
5431
-	stmfd	sp!, {r3, lr}
5432
-	.save {r3, lr}
5433
-	beq	.L853
5434
-	ldr	r2, .L855
5435
-	mov	r3, r0, asl #1
5786
+	beq	.L847
5787
+	ldr	r2, .L850
5788
+	lsl	r3, r0, #1
5789
+	push	{r4, lr}
5790
+	.save {r4, lr}
5436
5791
 	mov	r1, #0
5437
-	ldr	r2, [r2, #-3544]
5792
+	ldr	r2, [r2, #-3540]
5438
5793
 	strh	r1, [r2, r3]	@ movhi
5439
5794
 	bl	INSERT_FREE_LIST
5440
-.L853:
5441
5795
 	mov	r0, #0
5442
-	ldmfd	sp!, {r3, pc}
5443
-.L856:
5796
+	pop	{r4, pc}
5797
+.L847:
5798
+	mov	r0, #0
5799
+	bx	lr
5800
+.L851:
5444
5801
 	.align	2
5445
-.L855:
5802
+.L850:
5446
5803
 	.word	.LANCHOR2
5447
5804
 	.fnend
5448
5805
 	.size	free_data_superblock, .-free_data_superblock
5449
5806
 	.align	2
5450
5807
 	.global	FtlGcBufInit
5808
+	.syntax unified
5809
+	.arm
5810
+	.fpu softvfp
5451
5811
 	.type	FtlGcBufInit, %function
5452
5812
 FtlGcBufInit:
5453
5813
 	.fnstart
5454
5814
 	@ args = 0, pretend = 0, frame = 0
5455
5815
 	@ frame_needed = 0, uses_anonymous_args = 0
5456
-	ldr	ip, .L865
5816
+	ldr	ip, .L858
5457
5817
 	mov	r3, #0
5458
-	ldr	r1, .L865+4
5459
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
5818
+	ldr	r2, .L858+4
5819
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
5460
5820
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
5461
-	add	r7, ip, #78
5462
-	mov	r5, #12
5463
-	mov	r6, #1
5464
-	mov	r8, #36
5465
-	str	r3, [r1, #-2704]
5466
-.L858:
5467
-	ldrh	r2, [ip]
5468
-	add	r4, r3, #1
5469
-	uxth	r3, r3
5470
-	cmp	r3, r2
5471
-	bcs	.L863
5472
-	mul	r0, r5, r3
5473
-	ldr	lr, [r1, #-2700]
5474
-	add	r2, lr, r0
5475
-	str	r6, [r2, #8]
5476
-	ldrh	r2, [r7]
5477
-	mul	r2, r2, r3
5478
-	add	r9, r2, #3
5479
-	cmp	r2, #0
5480
-	movlt	r2, r9
5481
-	ldr	r9, [r1, #-2696]
5482
-	bic	r2, r2, #3
5483
-	add	r2, r9, r2
5484
-	str	r2, [lr, r0]
5485
-	ldr	r2, .L865+8
5486
-	ldr	r9, [r1, #-2700]
5487
-	ldrh	r2, [r2]
5488
-	add	lr, r9, r0
5489
-	mul	r2, r2, r3
5490
-	add	r10, r2, #3
5491
-	cmp	r2, #0
5492
-	movlt	r2, r10
5493
-	ldr	r10, [r1, #-2692]
5494
-	bic	r2, r2, #3
5495
-	add	r2, r10, r2
5496
-	str	r2, [lr, #4]
5497
-	ldr	r2, [r1, #-2688]
5498
-	mla	r3, r8, r3, r2
5499
-	ldr	r2, [r9, r0]
5500
-	str	r2, [r3, #8]
5501
-	ldr	r2, [lr, #4]
5502
-	str	r2, [r3, #12]
5503
-	mov	r3, r4
5504
-	b	.L858
5505
-.L863:
5506
-	ldr	r0, .L865+4
5821
+	mov	r4, #12
5822
+	mov	r5, #1
5823
+	add	r6, ip, #76
5824
+	mov	r7, #36
5825
+	str	r3, [r2, #-2704]
5826
+.L853:
5827
+	ldrh	r1, [ip]
5828
+	uxth	r0, r3
5829
+	add	lr, r3, #1
5830
+	cmp	r0, r1
5831
+	bcc	.L854
5832
+	ldr	r4, .L858+8
5507
5833
 	mov	ip, #12
5508
-	ldr	r4, .L865+12
5509
5834
 	mov	lr, #0
5510
-.L860:
5511
-	ldr	r3, [r1, #-2684]
5512
-	cmp	r2, r3
5513
-	bcs	.L864
5514
-	mul	r5, ip, r2
5515
-	ldr	r7, [r0, #-2700]
5516
-	add	r3, r7, r5
5835
+.L855:
5836
+	ldr	r3, [r2, #-2684]
5837
+	cmp	r1, r3
5838
+	bcc	.L856
5839
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
5840
+.L854:
5841
+	uxth	r3, r3
5842
+	ldr	r8, [r2, #-2700]
5843
+	mul	r0, r4, r3
5844
+	add	r1, r8, r0
5845
+	str	r5, [r1, #8]
5846
+	ldrh	r1, [r6]
5847
+	mul	r1, r3, r1
5848
+	add	r9, r1, #3
5849
+	cmp	r1, #0
5850
+	movlt	r1, r9
5851
+	ldr	r9, [r2, #-2696]
5852
+	bic	r1, r1, #3
5853
+	add	r1, r9, r1
5854
+	str	r1, [r8, r0]
5855
+	ldr	r1, .L858+12
5856
+	ldr	r9, [r2, #-2700]
5857
+	ldrh	r1, [r1]
5858
+	add	r8, r9, r0
5859
+	mul	r1, r3, r1
5860
+	add	r10, r1, #3
5861
+	cmp	r1, #0
5862
+	movlt	r1, r10
5863
+	ldr	r10, [r2, #-2692]
5864
+	bic	r1, r1, #3
5865
+	add	r1, r10, r1
5866
+	str	r1, [r8, #4]
5867
+	ldr	r1, [r2, #-2688]
5868
+	mla	r3, r7, r3, r1
5869
+	ldr	r1, [r9, r0]
5870
+	str	r1, [r3, #8]
5871
+	ldr	r1, [r8, #4]
5872
+	str	r1, [r3, #12]
5873
+	mov	r3, lr
5874
+	b	.L853
5875
+.L856:
5876
+	mul	r5, ip, r1
5877
+	ldr	r6, [r2, #-2700]
5878
+	add	r3, r6, r5
5517
5879
 	str	lr, [r3, #8]
5518
5880
 	ldrh	r3, [r4]
5519
-	mul	r3, r3, r2
5520
-	add	r6, r3, #3
5881
+	mul	r3, r1, r3
5882
+	add	r0, r3, #3
5521
5883
 	cmp	r3, #0
5522
-	movlt	r3, r6
5523
-	ldr	r6, [r0, #-2696]
5884
+	movlt	r3, r0
5885
+	ldr	r0, [r2, #-2696]
5524
5886
 	bic	r3, r3, #3
5525
-	add	r3, r6, r3
5526
-	str	r3, [r7, r5]
5527
-	ldr	r3, .L865+8
5528
-	ldr	r6, [r0, #-2700]
5887
+	add	r3, r0, r3
5888
+	str	r3, [r6, r5]
5889
+	ldr	r3, .L858+12
5890
+	ldr	r0, [r2, #-2700]
5529
5891
 	ldrh	r3, [r3]
5530
-	add	r5, r6, r5
5531
-	mul	r3, r3, r2
5532
-	add	r2, r2, #1
5533
-	uxth	r2, r2
5534
-	add	r6, r3, #3
5892
+	add	r0, r0, r5
5893
+	mul	r3, r1, r3
5894
+	add	r1, r1, #1
5895
+	uxth	r1, r1
5896
+	add	r5, r3, #3
5535
5897
 	cmp	r3, #0
5536
-	movlt	r3, r6
5537
-	ldr	r6, [r0, #-2692]
5898
+	movlt	r3, r5
5899
+	ldr	r5, [r2, #-2692]
5538
5900
 	bic	r3, r3, #3
5539
-	add	r3, r6, r3
5540
-	str	r3, [r5, #4]
5541
-	b	.L860
5542
-.L864:
5543
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
5544
-.L866:
5901
+	add	r3, r5, r3
5902
+	str	r3, [r0, #4]
5903
+	b	.L855
5904
+.L859:
5545
5905
 	.align	2
5546
-.L865:
5547
-	.word	.LANCHOR0+2320
5906
+.L858:
5907
+	.word	.LANCHOR0+2324
5548
5908
 	.word	.LANCHOR2
5549
5909
 	.word	.LANCHOR0+2400
5550
-	.word	.LANCHOR0+2398
5910
+	.word	.LANCHOR0+2402
5551
5911
 	.fnend
5552
5912
 	.size	FtlGcBufInit, .-FtlGcBufInit
5553
5913
 	.align	2
5554
5914
 	.global	FtlGcBufFree
5915
+	.syntax unified
5916
+	.arm
5917
+	.fpu softvfp
5555
5918
 	.type	FtlGcBufFree, %function
5556
5919
 FtlGcBufFree:
5557
5920
 	.fnstart
5558
5921
 	@ args = 0, pretend = 0, frame = 0
5559
5922
 	@ frame_needed = 0, uses_anonymous_args = 0
5560
-	ldr	r3, .L875
5561
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
5923
+	ldr	r3, .L868
5924
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
5562
5925
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
5563
5926
 	mov	lr, #0
5564
-	ldr	r6, [r3, #-2684]
5565
5927
 	mov	r5, #36
5928
+	mov	r7, #12
5929
+	mov	r8, lr
5930
+	ldr	r6, [r3, #-2684]
5566
5931
 	ldr	r4, [r3, #-2700]
5567
-	mov	r7, lr
5568
-	mov	r8, #12
5569
-.L868:
5570
-	uxth	ip, lr
5571
-	cmp	ip, r1
5572
-	ldmcsfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
5573
-	mla	ip, r5, ip, r0
5932
+.L861:
5933
+	uxth	r3, lr
5934
+	cmp	r1, r3
5935
+	popls	{r4, r5, r6, r7, r8, r9, r10, pc}
5936
+	mla	ip, r5, r3, r0
5574
5937
 	mov	r2, #0
5575
-.L869:
5938
+.L862:
5576
5939
 	uxth	r3, r2
5577
-	cmp	r3, r6
5578
-	bcs	.L870
5579
-	mul	r3, r8, r3
5940
+	cmp	r6, r3
5941
+	bls	.L863
5942
+	mul	r3, r7, r3
5580
5943
 	add	r2, r2, #1
5581
-	add	r9, r4, r3
5582
5944
 	ldr	r10, [r4, r3]
5945
+	add	r9, r4, r3
5583
5946
 	ldr	r3, [ip, #8]
5584
5947
 	cmp	r10, r3
5585
-	bne	.L869
5586
-	str	r7, [r9, #8]
5587
-.L870:
5948
+	bne	.L862
5949
+	str	r8, [r9, #8]
5950
+.L863:
5588
5951
 	add	lr, lr, #1
5589
-	b	.L868
5590
-.L876:
5952
+	b	.L861
5953
+.L869:
5591
5954
 	.align	2
5592
-.L875:
5955
+.L868:
5593
5956
 	.word	.LANCHOR2
5594
5957
 	.fnend
5595
5958
 	.size	FtlGcBufFree, .-FtlGcBufFree
5596
5959
 	.align	2
5597
5960
 	.global	FtlGcBufAlloc
5961
+	.syntax unified
5962
+	.arm
5963
+	.fpu softvfp
5598
5964
 	.type	FtlGcBufAlloc, %function
5599
5965
 FtlGcBufAlloc:
5600
5966
 	.fnstart
5601
5967
 	@ args = 0, pretend = 0, frame = 0
5602
5968
 	@ frame_needed = 0, uses_anonymous_args = 0
5603
-	ldr	r3, .L886
5969
+	ldr	r3, .L878
5604
5970
 	mov	ip, #0
5605
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, lr}
5971
+	push	{r4, r5, r6, r7, r8, r9, lr}
5606
5972
 	.save {r4, r5, r6, r7, r8, r9, lr}
5607
5973
 	mov	r6, #12
5608
-	ldr	r4, [r3, #-2684]
5609
5974
 	mov	r7, #1
5610
-	ldr	r5, [r3, #-2700]
5611
5975
 	mov	r8, #36
5612
-.L878:
5976
+	ldr	r4, [r3, #-2684]
5977
+	ldr	r5, [r3, #-2700]
5978
+.L871:
5613
5979
 	uxth	r2, ip
5614
-	cmp	r2, r1
5615
-	bcs	.L885
5980
+	cmp	r1, r2
5981
+	bhi	.L875
5982
+	pop	{r4, r5, r6, r7, r8, r9, pc}
5983
+.L875:
5616
5984
 	mov	lr, #0
5617
-.L879:
5985
+.L872:
5618
5986
 	uxth	r3, lr
5619
-	cmp	r3, r4
5620
-	bcs	.L880
5987
+	cmp	r4, r3
5988
+	bls	.L873
5621
5989
 	mla	r3, r6, r3, r5
5622
5990
 	add	lr, lr, #1
5623
5991
 	ldr	r9, [r3, #8]
5624
5992
 	cmp	r9, #0
5625
-	bne	.L879
5993
+	bne	.L872
5626
5994
 	mla	r2, r8, r2, r0
5627
5995
 	ldr	lr, [r3]
5628
5996
 	str	r7, [r3, #8]
5629
5997
 	str	lr, [r2, #8]
5630
5998
 	ldr	r3, [r3, #4]
5631
5999
 	str	r3, [r2, #12]
5632
-.L880:
6000
+.L873:
5633
6001
 	add	ip, ip, #1
5634
-	b	.L878
5635
-.L885:
5636
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, pc}
5637
-.L887:
6002
+	b	.L871
6003
+.L879:
5638
6004
 	.align	2
5639
-.L886:
6005
+.L878:
5640
6006
 	.word	.LANCHOR2
5641
6007
 	.fnend
5642
6008
 	.size	FtlGcBufAlloc, .-FtlGcBufAlloc
5643
6009
 	.align	2
5644
6010
 	.global	IsBlkInGcList
6011
+	.syntax unified
6012
+	.arm
6013
+	.fpu softvfp
5645
6014
 	.type	IsBlkInGcList, %function
5646
6015
 IsBlkInGcList:
5647
6016
 	.fnstart
5648
6017
 	@ args = 0, pretend = 0, frame = 0
5649
6018
 	@ frame_needed = 0, uses_anonymous_args = 0
5650
6019
 	@ link register save eliminated.
5651
-	ldr	r2, .L894
6020
+	ldr	r2, .L885
6021
+	ldr	r3, [r2, #-2680]
5652
6022
 	sub	r2, r2, #2672
5653
-	ldr	r3, [r2, #-8]
5654
6023
 	ldrh	r2, [r2, #-4]
5655
-	add	r2, r3, r2, asl #1
5656
-.L889:
6024
+	add	r2, r3, r2, lsl #1
6025
+.L881:
5657
6026
 	cmp	r3, r2
5658
-	beq	.L893
5659
-	ldrh	r1, [r3], #2
5660
-	cmp	r1, r0
5661
-	bne	.L889
5662
-	mov	r0, #1
5663
-	bx	lr
5664
-.L893:
6027
+	bne	.L883
5665
6028
 	mov	r0, #0
5666
6029
 	bx	lr
5667
-.L895:
6030
+.L883:
6031
+	ldrh	r1, [r3], #2
6032
+	cmp	r1, r0
6033
+	bne	.L881
6034
+	mov	r0, #1
6035
+	bx	lr
6036
+.L886:
5668
6037
 	.align	2
5669
-.L894:
6038
+.L885:
5670
6039
 	.word	.LANCHOR2
5671
6040
 	.fnend
5672
6041
 	.size	IsBlkInGcList, .-IsBlkInGcList
5673
6042
 	.align	2
5674
6043
 	.global	FtlGcUpdatePage
6044
+	.syntax unified
6045
+	.arm
6046
+	.fpu softvfp
5675
6047
 	.type	FtlGcUpdatePage, %function
5676
6048
 FtlGcUpdatePage:
5677
6049
 	.fnstart
5678
6050
 	@ args = 0, pretend = 0, frame = 0
5679
6051
 	@ frame_needed = 0, uses_anonymous_args = 0
5680
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
5681
-	.save {r3, r4, r5, r6, r7, r8, r9, lr}
6052
+	push	{r4, r5, r6, r7, r8, lr}
6053
+	.save {r4, r5, r6, r7, r8, lr}
5682
6054
 	mov	r4, r0
5683
6055
 	ubfx	r0, r0, #10, #16
5684
6056
 	mov	r5, r1
5685
6057
 	mov	r6, r2
5686
6058
 	bl	P2V_block_in_plane
5687
-	ldr	r2, .L904
5688
-	mov	lr, #0
5689
-	sub	r3, r2, #2672
5690
-	ldr	r8, [r2, #-2680]
5691
-	ldrh	r1, [r3, #-4]
5692
-	sub	r7, r8, #2
5693
-.L897:
5694
-	uxth	ip, lr
5695
-	cmp	ip, r1
5696
-	bcs	.L901
5697
-	ldrh	r9, [r7, #2]!
5698
-	add	lr, lr, #1
5699
-	cmp	r9, r0
5700
-	bne	.L897
5701
-.L901:
5702
-	cmp	ip, r1
5703
-	moveq	ip, ip, asl #1
5704
-	streqh	r0, [r8, ip]	@ movhi
5705
-	ldreqh	ip, [r3, #-4]
5706
-	addeq	ip, ip, #1
5707
-	streqh	ip, [r3, #-4]	@ movhi
5708
-.L899:
5709
-	ldr	r3, .L904+4
5710
-	mov	ip, #12
6059
+	ldr	r2, .L892
6060
+	mov	r3, #0
6061
+	sub	ip, r2, #2672
6062
+	ldr	lr, [r2, #-2680]
6063
+	ldrh	r7, [ip, #-4]
6064
+	sub	r1, lr, #2
6065
+.L888:
6066
+	uxth	r8, r3
6067
+	cmp	r8, r7
6068
+	bcc	.L890
6069
+	moveq	r3, r8
6070
+	lsleq	r3, r3, #1
6071
+	strheq	r0, [lr, r3]	@ movhi
6072
+	ldrheq	r3, [ip, #-4]
6073
+	addeq	r3, r3, #1
6074
+	strheq	r3, [ip, #-4]	@ movhi
6075
+	b	.L889
6076
+.L890:
6077
+	ldrh	r8, [r1, #2]!
6078
+	add	r3, r3, #1
6079
+	cmp	r8, r0
6080
+	bne	.L888
6081
+.L889:
6082
+	ldr	r0, .L892+4
6083
+	mov	r3, #12
5711
6084
 	ldr	r2, [r2, #-2672]
5712
-	ldrh	r1, [r3, #-12]
5713
-	mul	ip, ip, r1
5714
-	add	r1, r2, ip
6085
+	ldrh	r1, [r0, #-12]
6086
+	mul	r3, r3, r1
6087
+	add	r1, r2, r3
5715
6088
 	stmib	r1, {r5, r6}
5716
-	str	r4, [r2, ip]
5717
-	ldrh	r2, [r3, #-12]
5718
-	add	r2, r2, #1
5719
-	strh	r2, [r3, #-12]	@ movhi
5720
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
5721
-.L905:
6089
+	str	r4, [r2, r3]
6090
+	ldrh	r3, [r0, #-12]
6091
+	add	r3, r3, #1
6092
+	strh	r3, [r0, #-12]	@ movhi
6093
+	pop	{r4, r5, r6, r7, r8, pc}
6094
+.L893:
5722
6095
 	.align	2
5723
-.L904:
6096
+.L892:
5724
6097
 	.word	.LANCHOR2
5725
6098
 	.word	.LANCHOR2-2656
5726
6099
 	.fnend
5727
6100
 	.size	FtlGcUpdatePage, .-FtlGcUpdatePage
5728
6101
 	.align	2
5729
6102
 	.global	FtlGcRefreshOpenBlock
6103
+	.syntax unified
6104
+	.arm
6105
+	.fpu softvfp
5730
6106
 	.type	FtlGcRefreshOpenBlock, %function
5731
6107
 FtlGcRefreshOpenBlock:
5732
6108
 	.fnstart
5733
6109
 	@ args = 0, pretend = 0, frame = 0
5734
6110
 	@ frame_needed = 0, uses_anonymous_args = 0
5735
-	stmfd	sp!, {r3, r4, r5, lr}
5736
-	.save {r3, r4, r5, lr}
5737
-	mov	r5, r0
5738
-	ldr	r4, .L914
6111
+	push	{r4, r5, r6, lr}
6112
+	.save {r4, r5, r6, lr}
6113
+	ldr	r4, .L902
5739
6114
 	ldrh	r3, [r4, #-10]
5740
6115
 	cmp	r3, r0
5741
-	beq	.L908
6116
+	beq	.L896
5742
6117
 	ldrh	r3, [r4, #-8]
5743
6118
 	cmp	r3, r0
5744
-	beq	.L908
6119
+	beq	.L896
5745
6120
 	ldrh	r3, [r4, #-6]
5746
6121
 	cmp	r3, r0
5747
-	beq	.L908
6122
+	beq	.L896
5748
6123
 	ldrh	r3, [r4, #-4]
5749
6124
 	cmp	r3, r0
5750
-	beq	.L908
5751
-	ldr	r0, .L914+4
5752
-	mov	r1, r5
6125
+	beq	.L896
6126
+	mov	r5, r0
6127
+	mov	r1, r0
6128
+	ldr	r0, .L902+4
5753
6129
 	bl	printk
5754
6130
 	ldrh	r2, [r4, #-10]
5755
6131
 	movw	r3, #65535
5756
6132
 	cmp	r2, r3
5757
-	streqh	r5, [r4, #-10]	@ movhi
5758
-	beq	.L908
6133
+	strheq	r5, [r4, #-10]	@ movhi
6134
+	beq	.L896
5759
6135
 	ldrh	r2, [r4, #-8]
5760
6136
 	cmp	r2, r3
5761
-	streqh	r5, [r4, #-8]	@ movhi
5762
-	beq	.L908
6137
+	strheq	r5, [r4, #-8]	@ movhi
6138
+	beq	.L896
5763
6139
 	ldrh	r2, [r4, #-6]
5764
6140
 	cmp	r2, r3
5765
-	streqh	r5, [r4, #-6]	@ movhi
5766
-	beq	.L908
6141
+	strheq	r5, [r4, #-6]	@ movhi
6142
+	beq	.L896
5767
6143
 	ldrh	r2, [r4, #-4]
5768
6144
 	cmp	r2, r3
5769
-	streqh	r5, [r4, #-4]	@ movhi
5770
-.L908:
6145
+	strheq	r5, [r4, #-4]	@ movhi
6146
+.L896:
5771
6147
 	mov	r0, #0
5772
-	ldmfd	sp!, {r3, r4, r5, pc}
5773
-.L915:
6148
+	pop	{r4, r5, r6, pc}
6149
+.L903:
5774
6150
 	.align	2
5775
-.L914:
6151
+.L902:
5776
6152
 	.word	.LANCHOR2-2656
5777
6153
 	.word	.LC79
5778
6154
 	.fnend
5779
6155
 	.size	FtlGcRefreshOpenBlock, .-FtlGcRefreshOpenBlock
5780
6156
 	.align	2
5781
6157
 	.global	FtlGcRefreshBlock
6158
+	.syntax unified
6159
+	.arm
6160
+	.fpu softvfp
5782
6161
 	.type	FtlGcRefreshBlock, %function
5783
6162
 FtlGcRefreshBlock:
5784
6163
 	.fnstart
5785
6164
 	@ args = 0, pretend = 0, frame = 0
5786
6165
 	@ frame_needed = 0, uses_anonymous_args = 0
5787
-	stmfd	sp!, {r3, r4, r5, lr}
5788
-	.save {r3, r4, r5, lr}
5789
-	mov	r5, r0
5790
-	ldr	r4, .L927
6166
+	push	{r4, r5, r6, lr}
6167
+	.save {r4, r5, r6, lr}
6168
+	ldr	r4, .L915
5791
6169
 	ldrh	r3, [r4, #-10]
5792
6170
 	cmp	r3, r0
5793
-	beq	.L924
6171
+	beq	.L912
5794
6172
 	ldrh	r3, [r4, #-8]
5795
6173
 	cmp	r3, r0
5796
-	beq	.L924
6174
+	beq	.L912
5797
6175
 	ldrh	r3, [r4, #-6]
5798
6176
 	cmp	r3, r0
5799
-	beq	.L924
6177
+	beq	.L912
5800
6178
 	ldrh	r3, [r4, #-4]
5801
6179
 	cmp	r3, r0
5802
-	beq	.L924
5803
-	ldr	r0, .L927+4
5804
-	mov	r1, r5
6180
+	beq	.L912
6181
+	mov	r5, r0
6182
+	mov	r1, r0
6183
+	ldr	r0, .L915+4
5805
6184
 	bl	printk
5806
6185
 	ldrh	r2, [r4, #-10]
5807
6186
 	movw	r3, #65535
5808
6187
 	cmp	r2, r3
5809
-	streqh	r5, [r4, #-10]	@ movhi
5810
-	beq	.L924
6188
+	strheq	r5, [r4, #-10]	@ movhi
6189
+	beq	.L912
5811
6190
 	ldrh	r2, [r4, #-8]
5812
6191
 	cmp	r2, r3
5813
-	streqh	r5, [r4, #-8]	@ movhi
5814
-	beq	.L924
6192
+	strheq	r5, [r4, #-8]	@ movhi
6193
+	beq	.L912
5815
6194
 	ldrh	r2, [r4, #-6]
5816
6195
 	cmp	r2, r3
5817
-	streqh	r5, [r4, #-6]	@ movhi
5818
-	beq	.L924
6196
+	strheq	r5, [r4, #-6]	@ movhi
6197
+	beq	.L912
5819
6198
 	ldrh	r2, [r4, #-4]
5820
6199
 	cmp	r2, r3
5821
-	bne	.L925
6200
+	bne	.L913
5822
6201
 	strh	r5, [r4, #-4]	@ movhi
5823
-.L924:
6202
+.L912:
5824
6203
 	mov	r0, #0
5825
-	ldmfd	sp!, {r3, r4, r5, pc}
5826
-.L925:
6204
+	pop	{r4, r5, r6, pc}
6205
+.L913:
5827
6206
 	mvn	r0, #0
5828
-	ldmfd	sp!, {r3, r4, r5, pc}
5829
-.L928:
6207
+	pop	{r4, r5, r6, pc}
6208
+.L916:
5830
6209
 	.align	2
5831
-.L927:
6210
+.L915:
5832
6211
 	.word	.LANCHOR2-2656
5833
6212
 	.word	.LC79
5834
6213
 	.fnend
5835
6214
 	.size	FtlGcRefreshBlock, .-FtlGcRefreshBlock
5836
6215
 	.align	2
5837
6216
 	.global	FtlGcMarkBadPhyBlk
6217
+	.syntax unified
6218
+	.arm
6219
+	.fpu softvfp
5838
6220
 	.type	FtlGcMarkBadPhyBlk, %function
5839
6221
 FtlGcMarkBadPhyBlk:
5840
6222
 	.fnstart
5841
6223
 	@ args = 0, pretend = 0, frame = 0
5842
6224
 	@ frame_needed = 0, uses_anonymous_args = 0
5843
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
5844
-	.save {r3, r4, r5, r6, r7, lr}
6225
+	push	{r4, r5, r6, r7, r8, lr}
6226
+	.save {r4, r5, r6, r7, r8, lr}
5845
6227
 	mov	r5, r0
6228
+	ldr	r6, .L926
5846
6229
 	bl	P2V_block_in_plane
5847
-	ldr	r6, .L939
5848
-	mov	r2, r5
5849
6230
 	sub	r7, r6, #2656
5850
-	ldrh	r1, [r7, #-2]
5851
6231
 	mov	r4, r0
5852
-	ldr	r0, .L939+4
6232
+	mov	r2, r5
6233
+	ldrh	r1, [r7, #-2]
6234
+	ldr	r0, .L926+4
5853
6235
 	bl	printk
5854
6236
 	mov	r0, r4
5855
6237
 	bl	FtlGcRefreshBlock
5856
-	ldr	r3, .L939+8
5857
-	ldr	r3, [r3, #2244]
6238
+	ldr	r3, .L926+8
6239
+	ldr	r3, [r3, #2248]
5858
6240
 	cmp	r3, #0
5859
6241
 	mov	r3, r7
5860
-	beq	.L930
5861
-	ldr	r1, [r6, #-3608]
5862
-	mov	r4, r4, asl #1
6242
+	beq	.L918
6243
+	ldr	r1, [r6, #-3604]
6244
+	lsl	r4, r4, #1
5863
6245
 	ldrh	r2, [r1, r4]
5864
6246
 	cmp	r2, #39
5865
6247
 	subhi	r2, r2, #40
5866
-	strhih	r2, [r1, r4]	@ movhi
5867
-.L930:
6248
+	strhhi	r2, [r1, r4]	@ movhi
6249
+.L918:
5868
6250
 	ldrh	r2, [r3, #-2]
5869
6251
 	mov	r1, #0
5870
-.L931:
6252
+.L919:
5871
6253
 	uxth	r0, r1
5872
-	cmp	r0, r2
5873
-	bcs	.L938
5874
-	add	r1, r1, #1
5875
-	add	r0, r3, r1, asl #1
5876
-	ldrh	r0, [r0, #-2]
5877
-	cmp	r0, r5
5878
-	bne	.L931
5879
-	b	.L932
5880
-.L938:
6254
+	cmp	r2, r0
6255
+	bhi	.L921
5881
6256
 	cmp	r2, #15
5882
6257
 	addls	r1, r2, #1
5883
-	movls	r2, r2, asl #1
5884
-	strlsh	r1, [r3, #-2]	@ movhi
5885
-	strlsh	r5, [r3, r2]	@ movhi
5886
-.L932:
6258
+	lslls	r2, r2, #1
6259
+	strhls	r1, [r3, #-2]	@ movhi
6260
+	strhls	r5, [r3, r2]	@ movhi
6261
+	b	.L920
6262
+.L921:
6263
+	add	r1, r1, #1
6264
+	add	r0, r3, r1, lsl #1
6265
+	ldrh	r0, [r0, #-2]
6266
+	cmp	r0, r5
6267
+	bne	.L919
6268
+.L920:
5887
6269
 	mov	r0, #0
5888
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
5889
-.L940:
6270
+	pop	{r4, r5, r6, r7, r8, pc}
6271
+.L927:
5890
6272
 	.align	2
5891
-.L939:
6273
+.L926:
5892
6274
 	.word	.LANCHOR2
5893
6275
 	.word	.LC80
5894
6276
 	.word	.LANCHOR0
..
..
@@ -5896,28 +6278,31 @@
5896
6278
 	.size	FtlGcMarkBadPhyBlk, .-FtlGcMarkBadPhyBlk
5897
6279
 	.align	2
5898
6280
 	.global	FtlGcReFreshBadBlk
6281
+	.syntax unified
6282
+	.arm
6283
+	.fpu softvfp
5899
6284
 	.type	FtlGcReFreshBadBlk, %function
5900
6285
 FtlGcReFreshBadBlk:
5901
6286
 	.fnstart
5902
6287
 	@ args = 0, pretend = 0, frame = 0
5903
6288
 	@ frame_needed = 0, uses_anonymous_args = 0
5904
-	ldr	r3, .L949
6289
+	ldr	r3, .L938
5905
6290
 	ldrh	r2, [r3, #-2]
5906
6291
 	cmp	r2, #0
5907
-	beq	.L948
6292
+	beq	.L935
5908
6293
 	ldrh	r0, [r3, #-10]
5909
6294
 	movw	r1, #65535
5910
6295
 	cmp	r0, r1
5911
-	bne	.L948
5912
-	stmfd	sp!, {r4, lr}
6296
+	bne	.L935
6297
+	push	{r4, lr}
5913
6298
 	.save {r4, lr}
5914
6299
 	add	r4, r3, #48
5915
6300
 	ldrh	r1, [r4, #-14]
5916
6301
 	cmp	r1, r2
5917
6302
 	movcs	r2, #0
5918
-	strcsh	r2, [r4, #-14]	@ movhi
6303
+	strhcs	r2, [r4, #-14]	@ movhi
5919
6304
 	ldrh	r2, [r4, #-14]
5920
-	mov	r2, r2, asl #1
6305
+	lsl	r2, r2, #1
5921
6306
 	ldrh	r0, [r3, r2]
5922
6307
 	bl	P2V_block_in_plane
5923
6308
 	bl	FtlGcRefreshBlock
..
..
@@ -5925,18 +6310,21 @@
5925
6310
 	mov	r0, #0
5926
6311
 	add	r3, r3, #1
5927
6312
 	strh	r3, [r4, #-14]	@ movhi
5928
-	ldmfd	sp!, {r4, pc}
5929
-.L948:
6313
+	pop	{r4, pc}
6314
+.L935:
5930
6315
 	mov	r0, #0
5931
6316
 	bx	lr
5932
-.L950:
6317
+.L939:
5933
6318
 	.align	2
5934
-.L949:
6319
+.L938:
5935
6320
 	.word	.LANCHOR2-2656
5936
6321
 	.fnend
5937
6322
 	.size	FtlGcReFreshBadBlk, .-FtlGcReFreshBadBlk
5938
6323
 	.align	2
5939
6324
 	.global	ftl_memset
6325
+	.syntax unified
6326
+	.arm
6327
+	.fpu softvfp
5940
6328
 	.type	ftl_memset, %function
5941
6329
 ftl_memset:
5942
6330
 	.fnstart
..
..
@@ -5948,459 +6336,470 @@
5948
6336
 	.size	ftl_memset, .-ftl_memset
5949
6337
 	.align	2
5950
6338
 	.global	BuildFlashLsbPageTable
6339
+	.syntax unified
6340
+	.arm
6341
+	.fpu softvfp
5951
6342
 	.type	BuildFlashLsbPageTable, %function
5952
6343
 BuildFlashLsbPageTable:
5953
6344
 	.fnstart
5954
6345
 	@ args = 0, pretend = 0, frame = 0
5955
6346
 	@ frame_needed = 0, uses_anonymous_args = 0
5956
6347
 	cmp	r0, #0
5957
-	stmfd	sp!, {r4, lr}
5958
-	.save {r4, lr}
6348
+	push	{r4, r5, r6, lr}
6349
+	.save {r4, r5, r6, lr}
5959
6350
 	mov	r4, r1
5960
-	bne	.L953
5961
-	ldr	r3, .L996
5962
-.L954:
5963
-	mov	r2, r0, asl #1
6351
+	bne	.L942
6352
+	ldr	r3, .L998
6353
+.L943:
6354
+	lsl	r2, r0, #1
5964
6355
 	strh	r0, [r2, r3]	@ movhi
5965
6356
 	add	r0, r0, #1
5966
6357
 	cmp	r0, #512
5967
-	bne	.L954
5968
-.L958:
6358
+	bne	.L943
6359
+.L949:
6360
+	ldr	r5, .L998+4
5969
6361
 	mov	r1, #255
5970
-	ldr	r0, .L996+4
5971
6362
 	mov	r2, #2048
5972
6363
 	uxth	r4, r4
6364
+	sub	r0, r5, #12
6365
+	sub	r5, r5, #12
5973
6366
 	bl	ftl_memset
6367
+	ldr	r1, .L998
5974
6368
 	mov	r3, #0
5975
-	ldr	r1, .L996
5976
-	ldr	r0, .L996+4
5977
-	b	.L955
5978
-.L953:
6369
+.L944:
6370
+	uxth	r2, r3
6371
+	cmp	r4, r2
6372
+	bhi	.L977
6373
+	pop	{r4, r5, r6, pc}
6374
+.L942:
5979
6375
 	cmp	r0, #1
5980
-	bne	.L956
5981
-	ldr	ip, .L996
6376
+	bne	.L945
6377
+	ldr	r1, .L998
5982
6378
 	mov	r3, #0
5983
-.L957:
6379
+.L948:
6380
+	cmp	r3, #3
5984
6381
 	uxth	r2, r3
5985
-	mov	lr, r3, asl #1
5986
-	cmp	r2, #3
5987
-	movls	r0, #0
5988
-	movhi	r0, #1
5989
-	bics	r1, r0, r3
6382
+	bls	.L946
6383
+	tst	r2, #1
6384
+	movne	r0, #3
6385
+	moveq	r0, #2
6386
+	rsb	r2, r0, r2, lsl #1
6387
+	uxth	r2, r2
6388
+.L946:
6389
+	lsl	r0, r3, #1
5990
6390
 	add	r3, r3, #1
5991
-	movne	r1, #2
5992
-	moveq	r1, #3
5993
-	cmp	r0, #0
5994
-	rsb	r1, r1, r2, asl #1
5995
-	movne	r2, r1
5996
-	cmp	r3, #512
5997
-	strh	r2, [lr, ip]	@ movhi
5998
-	bne	.L957
5999
-	b	.L958
6000
-.L956:
6001
-	cmp	r0, #2
6002
-	bne	.L959
6003
-	ldr	r1, .L996
6004
-	mov	r3, #0
6005
-.L960:
6006
-	uxth	r2, r3
6007
-	mov	r0, r3, asl #1
6008
-	cmp	r2, #1
6009
-	add	r3, r3, #1
6010
-	mov	ip, r2, asl #1
6011
-	subhi	r2, ip, #1
6012
6391
 	cmp	r3, #512
6013
6392
 	strh	r2, [r0, r1]	@ movhi
6014
-	bne	.L960
6015
-	b	.L958
6016
-.L959:
6393
+	bne	.L948
6394
+	b	.L949
6395
+.L945:
6396
+	cmp	r0, #2
6397
+	bne	.L950
6398
+	ldr	r1, .L998
6399
+	mov	r2, #0
6400
+.L952:
6401
+	uxth	r3, r2
6402
+	cmp	r2, #1
6403
+	lsl	r0, r2, #1
6404
+	add	r2, r2, #1
6405
+	lslhi	r3, r3, #1
6406
+	subhi	r3, r3, #1
6407
+	uxthhi	r3, r3
6408
+	cmp	r2, #512
6409
+	strh	r3, [r0, r1]	@ movhi
6410
+	bne	.L952
6411
+	b	.L949
6412
+.L950:
6017
6413
 	cmp	r0, #3
6018
-	bne	.L961
6019
-	ldr	ip, .L996
6414
+	bne	.L953
6415
+	ldr	r1, .L998
6020
6416
 	mov	r3, #0
6021
-.L962:
6417
+.L956:
6418
+	cmp	r3, #5
6022
6419
 	uxth	r2, r3
6023
-	mov	lr, r3, asl #1
6024
-	cmp	r2, #5
6025
-	movls	r0, #0
6026
-	movhi	r0, #1
6027
-	bics	r1, r0, r3
6420
+	bls	.L954
6421
+	tst	r2, #1
6422
+	movne	r0, #5
6423
+	moveq	r0, #4
6424
+	rsb	r2, r0, r2, lsl #1
6425
+	uxth	r2, r2
6426
+.L954:
6427
+	lsl	r0, r3, #1
6028
6428
 	add	r3, r3, #1
6029
-	movne	r1, #4
6030
-	moveq	r1, #5
6031
-	cmp	r0, #0
6032
-	rsb	r1, r1, r2, asl #1
6033
-	movne	r2, r1
6034
6429
 	cmp	r3, #512
6035
-	strh	r2, [lr, ip]	@ movhi
6036
-	bne	.L962
6037
-	b	.L958
6038
-.L961:
6430
+	strh	r2, [r0, r1]	@ movhi
6431
+	bne	.L956
6432
+	b	.L949
6433
+.L953:
6039
6434
 	cmp	r0, #4
6040
6435
 	mov	r3, #0
6041
-	bne	.L963
6042
-	ldr	r2, .L996+8
6043
-	strh	r3, [r2, #148]	@ movhi
6436
+	bne	.L957
6437
+	ldr	r2, .L998+8
6438
+	strh	r3, [r2, #156]	@ movhi
6044
6439
 	mov	r3, #1
6045
-	strh	r0, [r2, #156]	@ movhi
6046
-	strh	r3, [r2, #150]	@ movhi
6047
-	mov	r3, #2
6048
-	strh	r3, [r2, #152]	@ movhi
6049
-	mov	r3, #3
6050
-	strh	r3, [r2, #154]	@ movhi
6051
-	mov	r3, #5
6052
6440
 	strh	r3, [r2, #158]	@ movhi
6053
-	mov	r3, #7
6441
+	mov	r3, #2
6054
6442
 	strh	r3, [r2, #160]	@ movhi
6443
+	mov	r3, #3
6444
+	strh	r3, [r2, #162]	@ movhi
6445
+	mov	r3, #5
6446
+	strh	r3, [r2, #166]	@ movhi
6447
+	mov	r3, #7
6448
+	strh	r3, [r2, #168]	@ movhi
6055
6449
 	mov	r3, #8
6056
-	strh	r3, [r2, #162]!	@ movhi
6057
-.L964:
6450
+	strh	r0, [r2, #164]	@ movhi
6451
+	strh	r3, [r2, #170]!	@ movhi
6452
+.L959:
6058
6453
 	tst	r3, #1
6059
6454
 	movne	r1, #7
6060
6455
 	moveq	r1, #6
6061
-	rsb	r1, r1, r3, asl #1
6456
+	rsb	r1, r1, r3, lsl #1
6062
6457
 	add	r3, r3, #1
6063
-	strh	r1, [r2, #2]!	@ movhi
6064
6458
 	uxth	r3, r3
6459
+	strh	r1, [r2, #2]!	@ movhi
6065
6460
 	cmp	r3, #512
6066
-	bne	.L964
6067
-	b	.L958
6068
-.L963:
6461
+	bne	.L959
6462
+	b	.L949
6463
+.L957:
6069
6464
 	cmp	r0, #5
6070
-	bne	.L965
6071
-	ldr	r2, .L996
6072
-.L966:
6073
-	mov	r1, r3, asl #1
6074
-	strh	r3, [r1, r2]	@ movhi
6465
+	bne	.L960
6466
+	ldr	r2, .L998+8
6467
+	add	r1, r2, #156
6468
+.L961:
6469
+	lsl	r0, r3, #1
6470
+	strh	r3, [r0, r1]	@ movhi
6075
6471
 	add	r3, r3, #1
6076
6472
 	cmp	r3, #16
6077
-	bne	.L966
6078
-	ldr	r2, .L996+12
6079
-.L967:
6473
+	bne	.L961
6474
+	add	r2, r2, #186
6475
+.L962:
6080
6476
 	strh	r3, [r2, #2]!	@ movhi
6081
6477
 	add	r3, r3, #2
6082
6478
 	uxth	r3, r3
6083
6479
 	cmp	r3, #1008
6084
-	bne	.L967
6085
-	b	.L958
6086
-.L965:
6480
+	bne	.L962
6481
+	b	.L949
6482
+.L960:
6087
6483
 	cmp	r0, #6
6088
-	bne	.L968
6089
-	ldr	r1, .L996+16
6090
-.L969:
6091
-	cmp	r3, #5
6092
-	add	r2, r3, r3, asl #1
6093
-	movls	r0, #0
6094
-	movhi	r0, #1
6095
-	bics	ip, r0, r3
6096
-	movne	ip, #10
6097
-	moveq	ip, #12
6098
-	cmp	r0, #0
6099
-	subne	r2, r2, ip
6100
-	moveq	r2, r3
6101
-	add	r3, r3, #1
6102
-	strh	r2, [r1, #2]!	@ movhi
6484
+	bne	.L963
6485
+	ldr	r0, .L998
6486
+	mov	r1, r3
6487
+.L966:
6488
+	cmp	r1, #5
6489
+	uxth	r2, r1
6490
+	bls	.L964
6491
+	tst	r2, #1
6492
+	movne	r2, #12
6493
+	moveq	r2, #10
6494
+	sub	r2, r3, r2
6495
+	uxth	r2, r2
6496
+.L964:
6497
+	lsl	ip, r1, #1
6498
+	add	r1, r1, #1
6499
+	cmp	r1, #512
6500
+	add	r3, r3, #3
6501
+	strh	r2, [ip, r0]	@ movhi
6103
6502
 	uxth	r3, r3
6104
-	cmp	r3, #512
6105
-	bne	.L969
6106
-	b	.L958
6107
-.L968:
6503
+	bne	.L966
6504
+	b	.L949
6505
+.L963:
6108
6506
 	cmp	r0, #9
6109
-	bne	.L970
6110
-	ldr	r2, .L996+8
6507
+	bne	.L967
6508
+	ldr	r2, .L998+8
6111
6509
 	movw	r1, #1021
6112
-	strh	r3, [r2, #148]	@ movhi
6510
+	strh	r3, [r2, #156]	@ movhi
6113
6511
 	mov	r3, #1
6114
-	strh	r3, [r2, #150]	@ movhi
6115
-	mov	r3, #2
6116
-	strh	r3, [r2, #152]!	@ movhi
6117
-	mov	r3, #3
6512
+	strh	r3, [r2, #158]	@ movhi
6513
+	mov	r3, r2
6514
+	mov	r2, #2
6515
+	strh	r2, [r3, #160]!	@ movhi
6516
+	mov	r2, #3
6517
+.L968:
6518
+	strh	r2, [r3, #2]!	@ movhi
6519
+	add	r2, r2, #2
6520
+	uxth	r2, r2
6521
+	cmp	r2, r1
6522
+	bne	.L968
6523
+	b	.L949
6524
+.L967:
6525
+	cmp	r0, #10
6526
+	bne	.L969
6527
+	ldr	r2, .L998+8
6528
+	add	r1, r2, #156
6529
+.L970:
6530
+	lsl	r0, r3, #1
6531
+	strh	r3, [r0, r1]	@ movhi
6532
+	add	r3, r3, #1
6533
+	cmp	r3, #63
6534
+	bne	.L970
6535
+	add	r2, r2, #280
6536
+	movw	r1, #961
6118
6537
 .L971:
6119
6538
 	strh	r3, [r2, #2]!	@ movhi
6120
6539
 	add	r3, r3, #2
6121
6540
 	uxth	r3, r3
6122
6541
 	cmp	r3, r1
6123
6542
 	bne	.L971
6124
-	b	.L958
6125
-.L970:
6126
-	cmp	r0, #10
6127
-	bne	.L972
6128
-	ldr	r2, .L996
6129
-.L973:
6130
-	mov	r1, r3, asl #1
6131
-	strh	r3, [r1, r2]	@ movhi
6132
-	add	r3, r3, #1
6133
-	cmp	r3, #63
6134
-	bne	.L973
6135
-	ldr	r2, .L996+20
6136
-	movw	r1, #961
6137
-.L974:
6138
-	strh	r3, [r2, #2]!	@ movhi
6139
-	add	r3, r3, #2
6140
-	uxth	r3, r3
6141
-	cmp	r3, r1
6142
-	bne	.L974
6143
-	b	.L958
6144
-.L972:
6543
+	b	.L949
6544
+.L969:
6145
6545
 	cmp	r0, #11
6146
-	bne	.L975
6147
-	ldr	r2, .L996
6546
+	bne	.L972
6547
+	ldr	r2, .L998+8
6148
6548
 	mov	r3, #0
6149
-.L976:
6150
-	mov	r1, r3, asl #1
6151
-	strh	r3, [r1, r2]	@ movhi
6549
+	add	r1, r2, #156
6550
+.L973:
6551
+	lsl	r0, r3, #1
6552
+	strh	r3, [r0, r1]	@ movhi
6152
6553
 	add	r3, r3, #1
6153
6554
 	cmp	r3, #8
6154
-	bne	.L976
6155
-	ldr	r1, .L996+24
6156
-.L977:
6157
-	tst	r3, #1
6158
-	movne	r2, #7
6159
-	moveq	r2, #6
6160
-	rsb	r2, r2, r3, asl #1
6161
-	add	r3, r3, #1
6162
-	strh	r2, [r1, #2]!	@ movhi
6163
-	uxth	r3, r3
6164
-	cmp	r3, #512
6165
-	bne	.L977
6166
-	b	.L958
6555
+	bne	.L973
6556
+	add	r2, r2, #170
6167
6557
 .L975:
6558
+	tst	r3, #1
6559
+	movne	r1, #7
6560
+	moveq	r1, #6
6561
+	rsb	r1, r1, r3, lsl #1
6562
+	add	r3, r3, #1
6563
+	uxth	r3, r3
6564
+	strh	r1, [r2, #2]!	@ movhi
6565
+	cmp	r3, #512
6566
+	bne	.L975
6567
+	b	.L949
6568
+.L972:
6168
6569
 	cmp	r0, #12
6169
-	bne	.L958
6170
-	ldr	r3, .L996+8
6570
+	bne	.L949
6571
+	ldr	r3, .L998+8
6171
6572
 	mov	r2, #0
6172
-	strh	r2, [r3, #148]	@ movhi
6573
+	strh	r2, [r3, #156]	@ movhi
6173
6574
 	mov	r2, #1
6174
-	strh	r2, [r3, #150]	@ movhi
6575
+	strh	r2, [r3, #158]	@ movhi
6175
6576
 	mov	r2, #2
6176
-	strh	r2, [r3, #152]	@ movhi
6577
+	strh	r2, [r3, #160]	@ movhi
6177
6578
 	mov	r2, #3
6178
-	strh	r2, [r3, #154]!	@ movhi
6579
+	strh	r2, [r3, #162]!	@ movhi
6179
6580
 	mov	r2, #4
6180
-.L978:
6581
+.L976:
6181
6582
 	sub	r1, r2, #1
6182
6583
 	add	r1, r1, r2, lsr #1
6183
6584
 	add	r2, r2, #1
6184
-	strh	r1, [r3, #2]!	@ movhi
6185
6585
 	uxth	r2, r2
6586
+	strh	r1, [r3, #2]!	@ movhi
6186
6587
 	cmp	r2, #512
6187
-	bne	.L978
6188
-	b	.L958
6189
-.L955:
6190
-	uxth	r2, r3
6191
-	cmp	r2, r4
6192
-	bcs	.L995
6193
-	mov	r2, r3, asl #1
6588
+	bne	.L976
6589
+	b	.L949
6590
+.L977:
6591
+	lsl	r2, r3, #1
6194
6592
 	add	r3, r3, #1
6195
6593
 	ldrh	r2, [r2, r1]
6196
-	mov	ip, r2, asl #1
6197
-	strh	r2, [r0, ip]	@ movhi
6198
-	b	.L955
6199
-.L995:
6200
-	ldmfd	sp!, {r4, pc}
6201
-.L997:
6594
+	lsl	r0, r2, #1
6595
+	strh	r2, [r5, r0]	@ movhi
6596
+	b	.L944
6597
+.L999:
6202
6598
 	.align	2
6203
-.L996:
6204
-	.word	.LANCHOR0+148
6205
-	.word	.LANCHOR2-2620
6599
+.L998:
6600
+	.word	.LANCHOR0+156
6601
+	.word	.LANCHOR2-2608
6206
6602
 	.word	.LANCHOR0
6207
-	.word	.LANCHOR0+178
6208
-	.word	.LANCHOR0+146
6209
-	.word	.LANCHOR0+272
6210
-	.word	.LANCHOR0+162
6211
6603
 	.fnend
6212
6604
 	.size	BuildFlashLsbPageTable, .-BuildFlashLsbPageTable
6213
6605
 	.align	2
6214
6606
 	.global	FlashDieInfoInit
6607
+	.syntax unified
6608
+	.arm
6609
+	.fpu softvfp
6215
6610
 	.type	FlashDieInfoInit, %function
6216
6611
 FlashDieInfoInit:
6217
6612
 	.fnstart
6218
6613
 	@ args = 0, pretend = 0, frame = 0
6219
6614
 	@ frame_needed = 0, uses_anonymous_args = 0
6220
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
6221
-	.save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
6615
+	ldr	r3, .L1015
6616
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
6617
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
6222
6618
 	mov	r6, #0
6223
-	ldr	r3, .L1013
6224
-	ldr	r5, .L1013+4
6225
-	ldr	r9, .L1013+8
6619
+	ldr	r4, .L1015+4
6620
+	ldr	r10, .L1015+8
6226
6621
 	ldrh	r0, [r3, #10]
6227
-	strb	r6, [r5, #2230]
6228
-	mov	r7, r5
6229
-	strb	r6, [r9, #-572]
6622
+	strb	r6, [r4, #2234]
6623
+	strb	r6, [r10, #-572]
6230
6624
 	bl	FlashBlockAlignInit
6231
-	mov	r1, r6
6232
6625
 	mov	r2, #8
6233
-	ldr	r0, .L1013+12
6234
-	bl	ftl_memset
6235
6626
 	mov	r1, r6
6627
+	ldr	r0, .L1015+12
6628
+	bl	ftl_memset
6236
6629
 	mov	r2, #32
6237
-	ldr	r0, .L1013+16
6238
-	bl	ftl_memset
6239
-	ldr	r0, .L1013+20
6240
6630
 	mov	r1, r6
6241
-	mov	r2, #128
6631
+	ldr	r0, .L1015+16
6242
6632
 	bl	ftl_memset
6243
-	ldr	r4, [r5, #44]
6244
-	ldr	fp, .L1013+24
6245
-	add	r8, r4, #1
6246
-.L1000:
6247
-	mov	r0, r8
6248
-	add	r1, fp, r6, asl #3
6249
-	ldrb	r2, [r4]	@ zero_extendqisi2
6250
-	bl	FlashMemCmp8
6251
-	ldr	r10, .L1013+24
6252
-	cmp	r0, #0
6253
-	bne	.L999
6254
-	ldrb	r3, [r7, #2230]	@ zero_extendqisi2
6255
-	add	r2, r7, r3, asl #2
6256
-	str	r0, [r2, #1172]
6257
-	add	r2, r3, #1
6258
-	add	r3, r7, r3
6259
-	strb	r2, [r7, #2230]
6260
-	strb	r6, [r3, #2232]
6261
-.L999:
6262
-	add	r6, r6, #1
6263
-	cmp	r6, #4
6264
-	bne	.L1000
6265
-	ldrb	r3, [r5, #2230]	@ zero_extendqisi2
6266
-	ldr	r7, .L1013+4
6267
-	strb	r3, [r9, #-572]
6268
-	ldrb	r3, [r4, #8]	@ zero_extendqisi2
6269
-	cmp	r3, #2
6270
-	beq	.L1001
6271
-.L1005:
6272
-	ldrb	r3, [r4, #13]	@ zero_extendqisi2
6273
-	ldrb	r2, [r5, #2230]	@ zero_extendqisi2
6274
-	smulbb	r2, r2, r3
6275
-	ldrh	r3, [r4, #14]
6276
-	smulbb	r3, r2, r3
6277
-	ldr	r2, .L1013+28
6278
-	strh	r3, [r2, #-2]	@ movhi
6279
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
6280
-.L1001:
6281
-	ldr	r9, [r7, #4]
6282
-	mov	r6, #0
6283
-.L1004:
6284
-	mov	r0, r8
6285
-	add	r1, r10, r6, asl #3
6286
-	ldrb	r2, [r4]	@ zero_extendqisi2
6287
-	bl	FlashMemCmp8
6288
-	cmp	r0, #0
6289
-	bne	.L1002
6290
-	ldrb	r1, [r4, #13]	@ zero_extendqisi2
6291
-	ldrh	r3, [r4, #14]
6292
-	ldrb	r2, [r7, #2230]	@ zero_extendqisi2
6293
-	mul	r1, r9, r1
6294
-	and	r3, r3, #65280
6295
-	add	r0, r7, r2, asl #2
6296
-	mul	r3, r3, r1
6297
-	str	r3, [r0, #1172]
6298
-	ldrb	r1, [r4, #23]	@ zero_extendqisi2
6299
-	cmp	r1, #0
6300
-	movne	r3, r3, asl #1
6301
-	strne	r3, [r0, #1172]
6302
-	add	r3, r2, #1
6303
-	add	r2, r5, r2
6304
-	strb	r3, [r5, #2230]
6305
-	strb	r6, [r2, #2232]
6633
+	mov	r2, #128
6634
+	mov	r1, r6
6635
+	ldr	r0, .L1015+20
6636
+	bl	ftl_memset
6637
+	ldr	r9, .L1015+24
6638
+	ldr	r5, [r4, #48]
6639
+	mov	r8, r9
6640
+	add	r7, r5, #1
6306
6641
 .L1002:
6642
+	ldrb	r2, [r5]	@ zero_extendqisi2
6643
+	add	r1, r9, r6, lsl #3
6644
+	mov	r0, r7
6645
+	bl	FlashMemCmp8
6646
+	cmp	r0, #0
6647
+	bne	.L1001
6648
+	ldrb	r3, [r4, #2234]	@ zero_extendqisi2
6649
+	add	r2, r4, r3, lsl #2
6650
+	str	r0, [r2, #1180]
6651
+	add	r2, r3, #1
6652
+	add	r3, r4, r3
6653
+	strb	r2, [r4, #2234]
6654
+	strb	r6, [r3, #2236]
6655
+.L1001:
6307
6656
 	add	r6, r6, #1
6308
6657
 	cmp	r6, #4
6658
+	bne	.L1002
6659
+	ldrb	r3, [r4, #2234]	@ zero_extendqisi2
6660
+	strb	r3, [r10, #-572]
6661
+	ldrb	r3, [r5, #8]	@ zero_extendqisi2
6662
+	cmp	r3, #2
6663
+	beq	.L1003
6664
+.L1007:
6665
+	ldrh	r2, [r5, #14]
6666
+	ldrb	r3, [r4, #2234]	@ zero_extendqisi2
6667
+	smulbb	r3, r3, r2
6668
+	ldrb	r2, [r5, #13]	@ zero_extendqisi2
6669
+	smulbb	r3, r3, r2
6670
+	ldr	r2, .L1015+28
6671
+	strh	r3, [r2, #-2]	@ movhi
6672
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
6673
+.L1003:
6674
+	ldr	r9, [r4, #40]
6675
+	mov	r6, #0
6676
+.L1006:
6677
+	ldrb	r2, [r5]	@ zero_extendqisi2
6678
+	add	r1, r8, r6, lsl #3
6679
+	mov	r0, r7
6680
+	bl	FlashMemCmp8
6681
+	cmp	r0, #0
6309
6682
 	bne	.L1004
6310
-	b	.L1005
6311
-.L1014:
6683
+	ldrh	r3, [r5, #14]
6684
+	ldrb	r2, [r4, #2234]	@ zero_extendqisi2
6685
+	and	r1, r3, #65280
6686
+	ldrb	r3, [r5, #13]	@ zero_extendqisi2
6687
+	mul	r3, r9, r3
6688
+	mul	r3, r3, r1
6689
+	add	r1, r4, r2, lsl #2
6690
+	str	r3, [r1, #1180]
6691
+	ldrb	r0, [r5, #23]	@ zero_extendqisi2
6692
+	cmp	r0, #0
6693
+	lslne	r3, r3, #1
6694
+	strne	r3, [r1, #1180]
6695
+	add	r3, r2, #1
6696
+	add	r2, r4, r2
6697
+	strb	r3, [r4, #2234]
6698
+	strb	r6, [r2, #2236]
6699
+.L1004:
6700
+	add	r6, r6, #1
6701
+	cmp	r6, #4
6702
+	bne	.L1006
6703
+	b	.L1007
6704
+.L1016:
6312
6705
 	.align	2
6313
-.L1013:
6314
-	.word	.LANCHOR1+472
6706
+.L1015:
6707
+	.word	.LANCHOR1+468
6315
6708
 	.word	.LANCHOR0
6316
6709
 	.word	.LANCHOR2
6317
-	.word	.LANCHOR0+2232
6318
-	.word	.LANCHOR0+1172
6319
-	.word	.LANCHOR0+2100
6320
-	.word	.LANCHOR0+2068
6710
+	.word	.LANCHOR0+2236
6711
+	.word	.LANCHOR0+1180
6712
+	.word	.LANCHOR0+2104
6713
+	.word	.LANCHOR0+2072
6321
6714
 	.word	.LANCHOR2-568
6322
6715
 	.fnend
6323
6716
 	.size	FlashDieInfoInit, .-FlashDieInfoInit
6324
6717
 	.align	2
6325
6718
 	.global	ftl_read_flash_info
6719
+	.syntax unified
6720
+	.arm
6721
+	.fpu softvfp
6326
6722
 	.type	ftl_read_flash_info, %function
6327
6723
 ftl_read_flash_info:
6328
6724
 	.fnstart
6329
6725
 	@ args = 0, pretend = 0, frame = 0
6330
6726
 	@ frame_needed = 0, uses_anonymous_args = 0
6331
-	stmfd	sp!, {r4, lr}
6727
+	push	{r4, lr}
6332
6728
 	.save {r4, lr}
6333
-	mov	r1, #0
6334
6729
 	mov	r2, #11
6730
+	mov	r1, #0
6335
6731
 	mov	r4, r0
6336
6732
 	bl	ftl_memset
6337
-	ldr	r2, .L1020
6338
-	ldr	r0, .L1020+4
6733
+	ldr	r2, .L1021
6339
6734
 	mov	ip, #1
6340
-	ldr	r3, [r2, #44]
6341
-	ldrb	r1, [r3, #9]	@ zero_extendqisi2
6342
-	ldr	r3, [r2, #4]
6343
-	smulbb	r3, r1, r3
6735
+	ldr	r0, .L1021+4
6736
+	ldr	r3, [r2, #48]
6737
+	ldr	r1, [r2, #40]
6738
+	ldrb	r3, [r3, #9]	@ zero_extendqisi2
6739
+	smulbb	r3, r3, r1
6344
6740
 	strh	r3, [r4, #4]	@ unaligned
6345
-	ldrb	r3, [r2, #2312]	@ zero_extendqisi2
6741
+	ldrb	r3, [r2, #2316]	@ zero_extendqisi2
6346
6742
 	strb	r3, [r4, #7]
6347
-	ldr	r3, [r2, #2428]
6743
+	ldr	r3, [r2, #2432]
6348
6744
 	str	r3, [r4]	@ unaligned
6349
-	ldr	r3, [r2, #44]
6745
+	ldr	r3, [r2, #48]
6350
6746
 	ldrb	r1, [r3, #9]	@ zero_extendqisi2
6351
6747
 	strb	r1, [r4, #6]
6352
6748
 	mov	r1, #32
6353
6749
 	strb	r1, [r4, #8]
6354
-	ldrb	r1, [r2, #2230]	@ zero_extendqisi2
6750
+	ldrb	r1, [r2, #2234]	@ zero_extendqisi2
6355
6751
 	ldrb	r3, [r3, #7]	@ zero_extendqisi2
6356
6752
 	strb	r3, [r4, #9]
6357
6753
 	mov	r3, #0
6358
6754
 	strb	r3, [r4, #10]
6359
-.L1016:
6755
+.L1018:
6360
6756
 	uxtb	r2, r3
6361
-	cmp	r2, r1
6362
-	bcs	.L1019
6757
+	cmp	r1, r2
6758
+	bhi	.L1019
6759
+	pop	{r4, pc}
6760
+.L1019:
6363
6761
 	ldrb	lr, [r3, r0]	@ zero_extendqisi2
6364
6762
 	add	r3, r3, #1
6365
6763
 	ldrb	r2, [r4, #10]	@ zero_extendqisi2
6366
-	orr	r2, r2, ip, asl lr
6764
+	orr	r2, r2, ip, lsl lr
6367
6765
 	strb	r2, [r4, #10]
6368
-	b	.L1016
6369
-.L1019:
6370
-	ldmfd	sp!, {r4, pc}
6371
-.L1021:
6766
+	b	.L1018
6767
+.L1022:
6372
6768
 	.align	2
6373
-.L1020:
6769
+.L1021:
6374
6770
 	.word	.LANCHOR0
6375
-	.word	.LANCHOR0+2232
6771
+	.word	.LANCHOR0+2236
6376
6772
 	.fnend
6377
6773
 	.size	ftl_read_flash_info, .-ftl_read_flash_info
6378
6774
 	.align	2
6379
6775
 	.global	FtlMemInit
6776
+	.syntax unified
6777
+	.arm
6778
+	.fpu softvfp
6380
6779
 	.type	FtlMemInit, %function
6381
6780
 FtlMemInit:
6382
6781
 	.fnstart
6383
6782
 	@ args = 0, pretend = 0, frame = 0
6384
6783
 	@ frame_needed = 0, uses_anonymous_args = 0
6385
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
6386
-	.save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
6784
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
6785
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
6387
6786
 	mov	r6, #0
6388
-	ldr	r4, .L1127
6787
+	ldr	r4, .L1126
6389
6788
 	mvn	r2, #0
6390
-	ldr	r5, .L1127+4
6391
6789
 	mov	r1, #32
6392
-	sub	r3, r4, #568
6393
6790
 	mov	r0, #1024
6791
+	ldr	r5, .L1126+4
6792
+	mov	r8, #12
6793
+	sub	r3, r4, #568
6394
6794
 	str	r6, [r4, #-564]
6395
-	add	r7, r5, #2320
6396
6795
 	strh	r6, [r3]	@ movhi
6397
6796
 	movw	r3, #65535
6398
6797
 	str	r3, [r4, #-556]
6399
6798
 	sub	r3, r4, #2656
6400
-	str	r6, [r4, #-3236]
6401
-	mov	r8, #36
6402
6799
 	strh	r2, [r3, #-10]	@ movhi
6800
+	movw	r9, #2324
6403
6801
 	strh	r2, [r3, #-8]	@ movhi
6802
+	mov	r7, #36
6404
6803
 	strh	r2, [r3, #-6]	@ movhi
6405
6804
 	strh	r2, [r3, #-4]	@ movhi
6406
6805
 	sub	r2, r4, #2720
..
..
@@ -6409,12 +6808,11 @@
6409
6808
 	strh	r1, [r2]	@ movhi
6410
6809
 	sub	r2, r4, #2704
6411
6810
 	strh	r6, [r3]	@ movhi
6412
-	sub	r3, r4, #2608
6413
-	strh	r6, [r2, #-8]	@ movhi
6414
6811
 	mov	r1, #128
6415
-	strh	r6, [r3, #-14]	@ movhi
6416
-	movw	r3, #2394
6812
+	sub	r3, r4, #2608
6417
6813
 	strh	r1, [r2, #-14]	@ movhi
6814
+	strh	r6, [r2, #-8]	@ movhi
6815
+	str	r6, [r4, #-2724]
6418
6816
 	str	r6, [r4, #-3332]
6419
6817
 	str	r6, [r4, #-3328]
6420
6818
 	str	r6, [r4, #-3344]
..
..
@@ -6425,7 +6823,7 @@
6425
6823
 	str	r6, [r4, #-3364]
6426
6824
 	str	r6, [r4, #-3324]
6427
6825
 	str	r6, [r4, #-3320]
6428
-	str	r6, [r4, #-3604]
6826
+	str	r6, [r4, #-3600]
6429
6827
 	str	r6, [r4, #-3312]
6430
6828
 	str	r6, [r4, #-3308]
6431
6829
 	str	r6, [r4, #-560]
..
..
@@ -6433,27 +6831,29 @@
6433
6831
 	str	r6, [r4, #-552]
6434
6832
 	str	r6, [r4, #-2716]
6435
6833
 	str	r6, [r4, #-548]
6834
+	strh	r6, [r3, #-14]	@ movhi
6835
+	movw	r3, #2396
6436
6836
 	ldrh	r1, [r5, r3]
6437
6837
 	bl	__aeabi_idiv
6438
-	ldrh	r10, [r7]
6439
-	str	r6, [r5, #2440]
6440
-	movw	r6, #2392
6441
-	mov	r9, r10, asl #2
6442
-	cmp	r0, r9
6838
+	movw	r3, #2324
6839
+	str	r6, [r5, #2444]
6840
+	ldrh	r3, [r5, r3]
6841
+	movw	r6, #2394
6443
6842
 	str	r0, [r4, #-540]
6843
+	lsl	r3, r3, #2
6844
+	cmp	r0, r3
6444
6845
 	ldrh	r0, [r5, r6]
6445
-	strhi	r9, [r4, #-540]
6446
-	mov	r9, #12
6447
-	mov	r0, r0, asl #1
6846
+	strhi	r3, [r4, #-540]
6847
+	lsl	r0, r0, #1
6448
6848
 	bl	ftl_malloc
6449
6849
 	str	r0, [r4, #-2680]
6450
6850
 	ldrh	r0, [r5, r6]
6451
-	mul	r0, r9, r0
6851
+	mul	r0, r8, r0
6452
6852
 	bl	ftl_malloc
6453
-	ldrh	r6, [r7]
6454
-	mul	r6, r8, r6
6455
-	mov	r10, r6, asl #3
6853
+	ldrh	r6, [r5, r9]
6456
6854
 	str	r0, [r4, #-2672]
6855
+	mul	r6, r7, r6
6856
+	lsl	r10, r6, #3
6457
6857
 	mov	r0, r10
6458
6858
 	bl	ftl_malloc
6459
6859
 	str	r0, [r4, #-536]
..
..
@@ -6462,421 +6862,437 @@
6462
6862
 	str	r0, [r4, #-532]
6463
6863
 	mov	r0, r10
6464
6864
 	bl	ftl_malloc
6465
-	movw	r10, #2398
6466
6865
 	str	r0, [r4, #-528]
6467
6866
 	mov	r0, r6
6468
6867
 	bl	ftl_malloc
6469
-	str	r0, [r4, #-3612]
6868
+	str	r0, [r4, #-3608]
6470
6869
 	mov	r0, r6
6471
6870
 	bl	ftl_malloc
6472
6871
 	str	r0, [r4, #-2688]
6872
+	movw	r10, #2402
6473
6873
 	ldr	r0, [r4, #-540]
6474
-	mul	r0, r8, r0
6874
+	ldr	r6, .L1126+8
6875
+	mul	r0, r7, r0
6475
6876
 	bl	ftl_malloc
6476
-	ldrh	r6, [r5, r10]
6477
-	ldrh	r3, [r7]
6478
-	movw	r8, #2330
6479
-	mov	r3, r3, asl #1
6877
+	ldrh	r3, [r5, r9]
6878
+	ldrh	r7, [r6]
6879
+	str	r0, [r5, #2448]
6880
+	lsl	r3, r3, #1
6881
+	mov	r0, r7
6480
6882
 	add	r3, r3, #1
6481
6883
 	str	r3, [r4, #-2684]
6482
-	str	r0, [r5, #2444]
6483
-	mov	r0, r6
6484
6884
 	bl	ftl_malloc
6485
6885
 	str	r0, [r4, #-524]
6486
-	mov	r0, r6
6886
+	mov	r0, r7
6487
6887
 	bl	ftl_malloc
6488
6888
 	str	r0, [r4, #-520]
6489
-	mov	r0, r6
6889
+	mov	r0, r7
6490
6890
 	bl	ftl_malloc
6491
6891
 	str	r0, [r4, #-516]
6492
6892
 	ldr	r0, [r4, #-2684]
6493
-	mul	r0, r0, r6
6893
+	mul	r0, r0, r7
6494
6894
 	bl	ftl_malloc
6495
6895
 	str	r0, [r4, #-2696]
6496
6896
 	ldr	r0, [r4, #-540]
6497
-	mul	r0, r0, r6
6897
+	mul	r0, r0, r7
6498
6898
 	bl	ftl_malloc
6499
6899
 	str	r0, [r4, #-512]
6500
-	mov	r0, r6
6900
+	mov	r0, r7
6501
6901
 	bl	ftl_malloc
6502
6902
 	str	r0, [r4, #-508]
6503
-	mov	r0, r6
6903
+	mov	r0, r7
6504
6904
 	bl	ftl_malloc
6505
-	ldr	r6, .L1127+8
6506
6905
 	str	r0, [r4, #-504]
6507
6906
 	ldr	r0, [r4, #-2684]
6508
-	mul	r0, r9, r0
6907
+	mul	r0, r8, r0
6509
6908
 	bl	ftl_malloc
6510
-	ldrh	r3, [r6]
6511
-	ldrh	r7, [r7]
6512
-	mul	r7, r7, r3
6909
+	ldrh	r3, [r5, r10]
6910
+	ldrh	r7, [r5, r9]
6911
+	movw	r9, #2334
6513
6912
 	str	r0, [r4, #-2700]
6913
+	mul	r7, r7, r3
6514
6914
 	mov	r0, r7
6515
6915
 	bl	ftl_malloc
6516
6916
 	str	r0, [r4, #-500]
6517
-	mov	r0, r7, asl #3
6917
+	lsl	r0, r7, #3
6918
+	ldr	r7, .L1126+12
6518
6919
 	bl	ftl_malloc
6519
-	ldrh	r3, [r6]
6520
-	ldr	r7, .L1127+12
6920
+	ldrh	r3, [r5, r10]
6521
6921
 	str	r0, [r4, #-496]
6522
6922
 	ldr	r0, [r4, #-2684]
6523
6923
 	mul	r0, r0, r3
6524
6924
 	bl	ftl_malloc
6525
-	ldrh	r3, [r6], #80
6925
+	ldrh	r3, [r5, r10]
6526
6926
 	str	r0, [r4, #-2692]
6527
6927
 	ldr	r0, [r4, #-540]
6528
6928
 	mul	r0, r0, r3
6529
6929
 	bl	ftl_malloc
6530
6930
 	str	r0, [r4, #-492]
6531
-	ldrh	r0, [r5, r8]
6532
-	mov	r0, r0, asl #1
6931
+	ldrh	r0, [r5, r9]
6932
+	lsl	r0, r0, #1
6533
6933
 	uxth	r0, r0
6534
6934
 	strh	r0, [r7]	@ movhi
6535
6935
 	bl	ftl_malloc
6536
6936
 	str	r0, [r4, #-484]
6537
6937
 	ldrh	r0, [r7]
6938
+	ldr	r3, .L1126+16
6538
6939
 	add	r0, r0, #544
6539
6940
 	add	r0, r0, #3
6540
-	mov	r0, r0, lsr #9
6941
+	lsr	r0, r0, #9
6541
6942
 	strh	r0, [r7]	@ movhi
6542
-	mov	r0, r0, asl #9
6943
+	and	r0, r3, r0, lsl #9
6543
6944
 	bl	ftl_malloc
6544
-	ldrh	fp, [r5, r8]
6545
-	mov	fp, fp, asl #1
6945
+	ldrh	r10, [r5, r9]
6546
6946
 	str	r0, [r4, #-480]
6547
6947
 	add	r0, r0, #32
6548
-	str	r0, [r4, #-3608]
6549
-	mov	r0, fp
6948
+	str	r0, [r4, #-3604]
6949
+	lsl	r10, r10, #1
6950
+	mov	r0, r10
6550
6951
 	bl	ftl_malloc
6551
6952
 	str	r0, [r4, #-476]
6552
-	mov	r0, fp
6953
+	mov	r0, r10
6553
6954
 	bl	ftl_malloc
6554
-	ldr	fp, [r5, #2416]
6555
-	mov	fp, fp, asl #1
6556
-	str	r0, [r4, #-3544]
6557
-	mov	r0, fp
6955
+	ldr	r10, [r5, #2420]
6956
+	str	r0, [r4, #-3540]
6957
+	lsl	r10, r10, #1
6958
+	mov	r0, r10
6558
6959
 	bl	ftl_malloc
6559
6960
 	str	r0, [r4, #-472]
6560
-	mov	r0, fp
6961
+	mov	r0, r10
6561
6962
 	bl	ftl_malloc
6562
-	movw	fp, #2408
6563
6963
 	str	r0, [r4, #-468]
6564
-	ldrh	r0, [r5, r8]
6565
-	mov	r0, r0, lsr #3
6964
+	movw	r10, #2412
6965
+	ldrh	r0, [r5, r9]
6966
+	lsr	r0, r0, #3
6566
6967
 	add	r0, r0, #4
6567
6968
 	bl	ftl_malloc
6568
-	str	r0, [r4, #-3368]
6569
-	ldrh	r0, [r5, fp]
6570
-	mov	r0, r0, asl #1
6969
+	str	r0, [r5, #32]
6970
+	ldrh	r0, [r5, r10]
6971
+	lsl	r0, r0, #1
6571
6972
 	bl	ftl_malloc
6572
-	str	r0, [r5, #2436]
6573
-	ldrh	r0, [r5, fp]
6574
-	mov	r0, r0, asl #1
6973
+	str	r0, [r5, #2440]
6974
+	ldrh	r0, [r5, r10]
6975
+	lsl	r0, r0, #1
6575
6976
 	bl	ftl_malloc
6576
6977
 	str	r0, [r4, #-464]
6577
-	ldrh	r0, [r5, fp]
6578
-	movw	fp, #2410
6579
-	mov	r0, r0, asl #2
6978
+	ldrh	r0, [r5, r10]
6979
+	movw	r10, #2414
6980
+	lsl	r0, r0, #2
6580
6981
 	bl	ftl_malloc
6581
6982
 	str	r0, [r4, #-460]
6582
-	ldrh	r0, [r5, fp]
6583
-	mov	r0, r0, asl #2
6983
+	ldrh	r0, [r5, r10]
6984
+	lsl	r0, r0, #2
6584
6985
 	bl	ftl_malloc
6585
-	ldrh	r2, [r5, fp]
6986
+	ldrh	r2, [r5, r10]
6586
6987
 	mov	r1, #0
6587
-	mov	r2, r2, asl #2
6588
6988
 	str	r0, [r4, #-456]
6989
+	lsl	r2, r2, #2
6589
6990
 	bl	ftl_memset
6590
-	movw	r3, #2424
6591
-	ldrh	fp, [r5, r3]
6592
-	mov	fp, fp, asl #2
6593
-	mov	r0, fp
6991
+	movw	r3, #2428
6992
+	ldrh	r10, [r5, r3]
6993
+	lsl	r10, r10, #2
6994
+	mov	r0, r10
6594
6995
 	bl	ftl_malloc
6595
6996
 	str	r0, [r4, #-452]
6596
-	mov	r0, fp
6997
+	mov	r0, r10
6597
6998
 	bl	ftl_malloc
6598
-	movw	fp, #2426
6599
6999
 	str	r0, [r4, #-448]
6600
-	ldr	r0, [r5, #2416]
6601
-	mov	r0, r0, asl #2
7000
+	movw	r10, #2430
7001
+	ldr	r0, [r5, #2420]
7002
+	lsl	r0, r0, #2
6602
7003
 	bl	ftl_malloc
6603
7004
 	str	r0, [r4, #-444]
6604
-	ldrh	r0, [r5, fp]
6605
-	mul	r0, r9, r0
6606
-	bl	ftl_malloc
6607
-	ldrh	r3, [r5, fp]
6608
-	str	r0, [r4, #-3380]
6609
7005
 	ldrh	r0, [r5, r10]
7006
+	mul	r0, r8, r0
7007
+	mov	r8, r6
7008
+	add	r6, r6, #56
7009
+	bl	ftl_malloc
7010
+	ldrh	r3, [r5, r10]
7011
+	str	r0, [r4, #-3376]
7012
+	ldrh	r0, [r8], #84
6610
7013
 	mul	r0, r0, r3
6611
7014
 	bl	ftl_malloc
6612
-	ldrh	r3, [r5, r8]
6613
-	movw	r8, #2342
7015
+	ldrh	r3, [r5, r9]
7016
+	movw	r9, #2346
6614
7017
 	str	r0, [r4, #-440]
6615
7018
 	mov	r0, #6
6616
7019
 	mul	r0, r0, r3
6617
7020
 	bl	ftl_malloc
6618
-	movw	r3, #2386
6619
-	ldrh	r3, [r5, r3]
6620
-	add	r3, r3, #31
6621
-	mov	r3, r3, asr #5
6622
-	strh	r3, [r7, #52]!	@ movhi
6623
-	str	r0, [r4, #-3552]
6624
-	ldrh	r0, [r5, r8]
7021
+	movw	r3, #2388
7022
+	str	r0, [r4, #-3548]
7023
+	ldrh	r0, [r5, r3]
7024
+	ldrh	r3, [r5, r9]
7025
+	add	r0, r0, #31
7026
+	asr	r0, r0, #5
7027
+	strh	r0, [r7, #52]!	@ movhi
6625
7028
 	mul	r0, r0, r3
6626
-	mov	r0, r0, asl #2
7029
+	lsl	r0, r0, #2
6627
7030
 	bl	ftl_malloc
6628
7031
 	ldrh	r2, [r7]
6629
-	ldrh	ip, [r5, r8]
6630
7032
 	mov	r3, #1
6631
-	mov	r2, r2, asl #2
7033
+	ldrh	ip, [r5, r9]
7034
+	str	r0, [r5, #2484]
7035
+	lsl	r2, r2, #2
6632
7036
 	mov	r1, r2
6633
-	str	r0, [r5, #2480]
6634
-.L1024:
7037
+.L1025:
6635
7038
 	cmp	r3, ip
6636
-	bcs	.L1125
6637
-	ldr	r0, [r5, #2480]
7039
+	bcc	.L1026
7040
+	add	r6, r6, r3, lsl #2
7041
+	ldr	r3, .L1126+20
7042
+	mov	r2, #0
7043
+	add	r6, r6, #24
7044
+.L1027:
7045
+	cmp	r3, r6
7046
+	bne	.L1028
7047
+	ldr	r3, [r4, #-472]
7048
+	cmp	r3, #0
7049
+	bne	.L1029
7050
+.L1031:
7051
+	ldr	r1, .L1126+24
7052
+	ldr	r0, .L1126+28
7053
+	bl	printk
7054
+	mvn	r0, #0
7055
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
7056
+.L1026:
7057
+	ldr	r0, [r5, #2484]
6638
7058
 	add	r3, r3, #1
6639
7059
 	add	r0, r0, r1
6640
7060
 	add	r1, r1, r2
6641
-	str	r0, [r6, #4]!
6642
-	b	.L1024
6643
-.L1125:
6644
-	ldr	r2, .L1127+16
6645
-	mov	r1, #0
6646
-.L1026:
6647
-	cmp	r3, #8
6648
-	addne	r0, r2, r3, asl #2
6649
-	addne	r3, r3, #1
6650
-	strne	r1, [r0, #28]
6651
-	bne	.L1026
6652
-.L1126:
6653
-	ldr	r2, [r4, #-472]
6654
-	ldr	r3, .L1127
6655
-	cmp	r2, #0
6656
-	bne	.L1028
6657
-.L1030:
6658
-	ldr	r1, .L1127+20
6659
-	ldr	r0, .L1127+24
6660
-	bl	printk
6661
-	mvn	r0, #0
6662
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
7061
+	str	r0, [r8, #4]!
7062
+	b	.L1025
6663
7063
 .L1028:
6664
-	ldr	r2, [r3, #-468]
6665
-	cmp	r2, #0
6666
-	beq	.L1030
6667
-	ldr	r2, [r3, #-452]
6668
-	cmp	r2, #0
6669
-	beq	.L1030
6670
-	ldr	r2, [r3, #-444]
6671
-	cmp	r2, #0
6672
-	beq	.L1030
6673
-	ldr	r2, [r3, #-3380]
6674
-	cmp	r2, #0
6675
-	beq	.L1030
6676
-	ldr	r2, [r3, #-440]
6677
-	cmp	r2, #0
6678
-	beq	.L1030
6679
-	ldr	r2, [r3, #-3552]
6680
-	cmp	r2, #0
6681
-	beq	.L1030
6682
-	ldr	r2, [r5, #2480]
6683
-	cmp	r2, #0
6684
-	beq	.L1030
6685
-	ldr	r3, [r3, #-3544]
7064
+	str	r2, [r6, #4]!
7065
+	b	.L1027
7066
+.L1029:
7067
+	ldr	r3, [r4, #-468]
6686
7068
 	cmp	r3, #0
6687
-	beq	.L1030
6688
-	ldr	r2, [r4, #-2680]
6689
-	ldr	r3, .L1127
6690
-	cmp	r2, #0
6691
-	beq	.L1030
6692
-	ldr	r2, [r3, #-2672]
6693
-	cmp	r2, #0
6694
-	beq	.L1030
6695
-	ldr	r2, [r3, #-536]
6696
-	cmp	r2, #0
6697
-	beq	.L1030
6698
-	ldr	r2, [r3, #-528]
6699
-	cmp	r2, #0
6700
-	beq	.L1030
6701
-	ldr	r2, [r3, #-3612]
6702
-	cmp	r2, #0
6703
-	beq	.L1030
6704
-	ldr	r2, [r3, #-2688]
6705
-	cmp	r2, #0
6706
-	beq	.L1030
6707
-	ldr	r2, [r3, #-532]
6708
-	cmp	r2, #0
6709
-	beq	.L1030
6710
-	ldr	r2, [r3, #-524]
6711
-	cmp	r2, #0
6712
-	beq	.L1030
6713
-	ldr	r2, [r3, #-520]
6714
-	cmp	r2, #0
6715
-	beq	.L1030
6716
-	ldr	r3, [r3, #-516]
7069
+	beq	.L1031
7070
+	ldr	r3, [r4, #-452]
6717
7071
 	cmp	r3, #0
6718
-	beq	.L1030
6719
-	ldr	r2, [r4, #-2696]
6720
-	ldr	r3, .L1127
6721
-	cmp	r2, #0
6722
-	beq	.L1030
6723
-	ldr	r2, [r3, #-508]
6724
-	cmp	r2, #0
6725
-	beq	.L1030
6726
-	ldr	r2, [r3, #-504]
6727
-	cmp	r2, #0
6728
-	beq	.L1030
6729
-	ldr	r2, [r3, #-2700]
6730
-	cmp	r2, #0
6731
-	beq	.L1030
6732
-	ldr	r2, [r3, #-500]
6733
-	cmp	r2, #0
6734
-	beq	.L1030
6735
-	ldr	r2, [r3, #-496]
6736
-	cmp	r2, #0
6737
-	beq	.L1030
6738
-	ldr	r2, [r3, #-2692]
6739
-	cmp	r2, #0
6740
-	beq	.L1030
6741
-	ldr	r2, [r3, #-3608]
6742
-	cmp	r2, #0
6743
-	beq	.L1030
6744
-	ldr	r3, [r3, #-484]
7072
+	beq	.L1031
7073
+	ldr	r3, [r4, #-444]
6745
7074
 	cmp	r3, #0
6746
-	beq	.L1030
6747
-	ldr	r3, .L1127+4
6748
-	ldr	r3, [r3, #2436]
7075
+	beq	.L1031
7076
+	ldr	r3, [r4, #-3376]
6749
7077
 	cmp	r3, #0
6750
-	beq	.L1030
6751
-	ldr	r3, .L1127
7078
+	beq	.L1031
7079
+	ldr	r3, [r4, #-440]
7080
+	cmp	r3, #0
7081
+	beq	.L1031
7082
+	ldr	r3, [r4, #-3548]
7083
+	cmp	r3, #0
7084
+	beq	.L1031
7085
+	ldr	r3, [r5, #2484]
7086
+	cmp	r3, #0
7087
+	beq	.L1031
7088
+	ldr	r3, [r4, #-3540]
7089
+	cmp	r3, #0
7090
+	beq	.L1031
7091
+	ldr	r3, [r4, #-2680]
7092
+	cmp	r3, #0
7093
+	beq	.L1031
7094
+	ldr	r3, [r4, #-2672]
7095
+	cmp	r3, #0
7096
+	beq	.L1031
7097
+	ldr	r3, [r4, #-536]
7098
+	cmp	r3, #0
7099
+	beq	.L1031
7100
+	ldr	r3, [r4, #-528]
7101
+	cmp	r3, #0
7102
+	beq	.L1031
7103
+	ldr	r3, [r4, #-3608]
7104
+	cmp	r3, #0
7105
+	beq	.L1031
7106
+	ldr	r3, [r4, #-2688]
7107
+	cmp	r3, #0
7108
+	beq	.L1031
7109
+	ldr	r3, [r4, #-532]
7110
+	cmp	r3, #0
7111
+	beq	.L1031
7112
+	ldr	r3, [r4, #-524]
7113
+	cmp	r3, #0
7114
+	beq	.L1031
7115
+	ldr	r3, [r4, #-520]
7116
+	cmp	r3, #0
7117
+	beq	.L1031
7118
+	ldr	r3, [r4, #-516]
7119
+	cmp	r3, #0
7120
+	beq	.L1031
7121
+	ldr	r3, [r4, #-2696]
7122
+	cmp	r3, #0
7123
+	beq	.L1031
7124
+	ldr	r3, [r4, #-508]
7125
+	cmp	r3, #0
7126
+	beq	.L1031
7127
+	ldr	r3, [r4, #-504]
7128
+	cmp	r3, #0
7129
+	beq	.L1031
7130
+	ldr	r3, [r4, #-2700]
7131
+	cmp	r3, #0
7132
+	beq	.L1031
7133
+	ldr	r3, [r4, #-500]
7134
+	cmp	r3, #0
7135
+	beq	.L1031
7136
+	ldr	r3, [r4, #-496]
7137
+	cmp	r3, #0
7138
+	beq	.L1031
7139
+	ldr	r3, [r4, #-2692]
7140
+	cmp	r3, #0
7141
+	beq	.L1031
7142
+	ldr	r3, [r4, #-3604]
7143
+	cmp	r3, #0
7144
+	beq	.L1031
7145
+	ldr	r3, [r4, #-484]
7146
+	cmp	r3, #0
7147
+	beq	.L1031
7148
+	ldr	r3, .L1126+4
7149
+	ldr	r3, [r3, #2440]
7150
+	cmp	r3, #0
7151
+	beq	.L1031
7152
+	ldr	r3, .L1126
6752
7153
 	ldr	r2, [r3, #-464]
6753
7154
 	cmp	r2, #0
6754
-	beq	.L1030
7155
+	beq	.L1031
6755
7156
 	ldr	r2, [r3, #-460]
6756
7157
 	cmp	r2, #0
6757
-	beq	.L1030
7158
+	beq	.L1031
6758
7159
 	ldr	r3, [r3, #-456]
6759
7160
 	cmp	r3, #0
6760
-	beq	.L1030
7161
+	beq	.L1031
6761
7162
 	mov	r0, #0
6762
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
6763
-.L1128:
6764
-	.align	2
7163
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
6765
7164
 .L1127:
7165
+	.align	2
7166
+.L1126:
6766
7167
 	.word	.LANCHOR2
6767
7168
 	.word	.LANCHOR0
6768
7169
 	.word	.LANCHOR0+2400
6769
7170
 	.word	.LANCHOR2-488
6770
-	.word	.LANCHOR0+2452
7171
+	.word	33553920
7172
+	.word	.LANCHOR0+2512
6771
7173
 	.word	.LANCHOR3
6772
7174
 	.word	.LC81
6773
7175
 	.fnend
6774
7176
 	.size	FtlMemInit, .-FtlMemInit
6775
7177
 	.align	2
6776
7178
 	.global	FtlBbt2Bitmap
7179
+	.syntax unified
7180
+	.arm
7181
+	.fpu softvfp
6777
7182
 	.type	FtlBbt2Bitmap, %function
6778
7183
 FtlBbt2Bitmap:
6779
7184
 	.fnstart
6780
7185
 	@ args = 0, pretend = 0, frame = 0
6781
7186
 	@ frame_needed = 0, uses_anonymous_args = 0
6782
-	ldr	r3, .L1135
6783
-	stmfd	sp!, {r4, r5, r6, lr}
7187
+	ldr	r3, .L1134
7188
+	push	{r4, r5, r6, lr}
6784
7189
 	.save {r4, r5, r6, lr}
6785
-	mov	r4, r0
6786
-	ldrh	r2, [r3]
6787
-	mov	r0, r1
6788
7190
 	mov	r5, r1
7191
+	mov	r4, r0
6789
7192
 	mov	r1, #0
7193
+	mov	r0, r5
6790
7194
 	movw	r6, #65535
6791
-	mov	r2, r2, asl #2
7195
+	ldrh	r2, [r3]
7196
+	lsl	r2, r2, #2
6792
7197
 	bl	ftl_memset
6793
-	add	r3, r4, #1020
6794
-	ldr	ip, .L1135+4
6795
-	add	r3, r3, #2
6796
-	sub	r1, r4, #2
7198
+	ldr	ip, .L1134+4
7199
+	add	r0, r4, #1020
7200
+	sub	r2, r4, #2
7201
+	add	r0, r0, #2
6797
7202
 	mov	r4, #1
6798
-.L1131:
6799
-	ldrh	r2, [r1, #2]!
6800
-	cmp	r2, r6
6801
-	ldmeqfd	sp!, {r4, r5, r6, pc}
6802
-	mov	lr, r2, lsr #5
6803
-	and	r2, r2, #31
6804
-	cmp	r1, r3
6805
-	ldr	r0, [r5, lr, asl #2]
6806
-	orr	r2, r0, r4, asl r2
6807
-	str	r2, [r5, lr, asl #2]
6808
-	ldrh	r2, [ip, #6]
6809
-	add	r2, r2, #1
6810
-	strh	r2, [ip, #6]	@ movhi
6811
-	bne	.L1131
6812
-	ldmfd	sp!, {r4, r5, r6, pc}
6813
-.L1136:
6814
-	.align	2
7203
+.L1130:
7204
+	ldrh	r3, [r2, #2]!
7205
+	cmp	r3, r6
7206
+	popeq	{r4, r5, r6, pc}
7207
+	lsr	lr, r3, #5
7208
+	and	r3, r3, #31
7209
+	cmp	r2, r0
7210
+	ldr	r1, [r5, lr, lsl #2]
7211
+	orr	r3, r1, r4, lsl r3
7212
+	str	r3, [r5, lr, lsl #2]
7213
+	ldrh	r3, [ip, #6]
7214
+	add	r3, r3, #1
7215
+	strh	r3, [ip, #6]	@ movhi
7216
+	bne	.L1130
7217
+	pop	{r4, r5, r6, pc}
6815
7218
 .L1135:
7219
+	.align	2
7220
+.L1134:
6816
7221
 	.word	.LANCHOR2-436
6817
-	.word	.LANCHOR0+2452
7222
+	.word	.LANCHOR0+2456
6818
7223
 	.fnend
6819
7224
 	.size	FtlBbt2Bitmap, .-FtlBbt2Bitmap
6820
7225
 	.align	2
6821
7226
 	.global	FtlBbtMemInit
7227
+	.syntax unified
7228
+	.arm
7229
+	.fpu softvfp
6822
7230
 	.type	FtlBbtMemInit, %function
6823
7231
 FtlBbtMemInit:
6824
7232
 	.fnstart
6825
7233
 	@ args = 0, pretend = 0, frame = 0
6826
7234
 	@ frame_needed = 0, uses_anonymous_args = 0
6827
7235
 	@ link register save eliminated.
6828
-	ldr	r0, .L1138
6829
-	movw	r3, #2452
7236
+	ldr	r2, .L1137
7237
+	movw	r3, #2456
6830
7238
 	mvn	r1, #0
6831
-	add	r2, r0, r3
6832
-	strh	r1, [r0, r3]	@ movhi
7239
+	add	r0, r2, r3
7240
+	strh	r1, [r2, r3]	@ movhi
6833
7241
 	mov	r3, #0
6834
-	add	r0, r0, #2464
6835
-	strh	r3, [r2, #6]	@ movhi
6836
-	mov	r1, #255
6837
7242
 	mov	r2, #16
7243
+	strh	r3, [r0, #6]	@ movhi
7244
+	mov	r1, #255
7245
+	add	r0, r0, #12
6838
7246
 	b	ftl_memset
6839
-.L1139:
6840
-	.align	2
6841
7247
 .L1138:
7248
+	.align	2
7249
+.L1137:
6842
7250
 	.word	.LANCHOR0
6843
7251
 	.fnend
6844
7252
 	.size	FtlBbtMemInit, .-FtlBbtMemInit
6845
7253
 	.align	2
6846
7254
 	.global	FtlFreeSysBlkQueueInit
7255
+	.syntax unified
7256
+	.arm
7257
+	.fpu softvfp
6847
7258
 	.type	FtlFreeSysBlkQueueInit, %function
6848
7259
 FtlFreeSysBlkQueueInit:
6849
7260
 	.fnstart
6850
7261
 	@ args = 0, pretend = 0, frame = 0
6851
7262
 	@ frame_needed = 0, uses_anonymous_args = 0
6852
-	ldr	r3, .L1142
6853
-	mov	r2, #2048
6854
-	stmfd	sp!, {r4, lr}
7263
+	ldr	r1, .L1141
7264
+	movw	r2, #2516
7265
+	push	{r4, lr}
6855
7266
 	.save {r4, lr}
6856
7267
 	mov	r4, #0
7268
+	add	r3, r1, r2
7269
+	strh	r0, [r1, r2]	@ movhi
7270
+	mov	r2, #2048
6857
7271
 	mov	r1, r4
7272
+	add	r0, r3, #8
6858
7273
 	strh	r4, [r3, #2]	@ movhi
6859
7274
 	strh	r4, [r3, #4]	@ movhi
6860
7275
 	strh	r4, [r3, #6]	@ movhi
6861
-	strh	r0, [r3], #8	@ movhi
6862
-	mov	r0, r3
6863
7276
 	bl	ftl_memset
6864
7277
 	mov	r0, r4
6865
-	ldmfd	sp!, {r4, pc}
6866
-.L1143:
6867
-	.align	2
7278
+	pop	{r4, pc}
6868
7279
 .L1142:
6869
-	.word	.LANCHOR0+2512
7280
+	.align	2
7281
+.L1141:
7282
+	.word	.LANCHOR0
6870
7283
 	.fnend
6871
7284
 	.size	FtlFreeSysBlkQueueInit, .-FtlFreeSysBlkQueueInit
6872
7285
 	.align	2
6873
7286
 	.global	ftl_free_no_use_map_blk
7287
+	.syntax unified
7288
+	.arm
7289
+	.fpu softvfp
6874
7290
 	.type	ftl_free_no_use_map_blk, %function
6875
7291
 ftl_free_no_use_map_blk:
6876
7292
 	.fnstart
6877
7293
 	@ args = 0, pretend = 0, frame = 0
6878
7294
 	@ frame_needed = 0, uses_anonymous_args = 0
6879
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
7295
+	push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
6880
7296
 	.save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
6881
7297
 	mov	r1, #0
6882
7298
 	ldrh	r2, [r0, #10]
..
..
@@ -6884,165 +7300,148 @@
6884
7300
 	ldr	r5, [r0, #20]
6885
7301
 	ldr	r7, [r0, #12]
6886
7302
 	ldr	r6, [r0, #24]
6887
-	mov	r2, r2, asl #1
7303
+	lsl	r2, r2, #1
6888
7304
 	mov	r0, r5
6889
7305
 	bl	ftl_memset
6890
7306
 	mov	r2, #0
6891
-.L1145:
7307
+.L1144:
6892
7308
 	ldrh	r1, [r4, #6]
6893
7309
 	uxth	r3, r2
6894
7310
 	cmp	r1, r3
6895
-	bls	.L1165
6896
-	ldr	r0, [r6, r3, asl #2]
7311
+	bhi	.L1148
7312
+	ldr	r2, .L1164
7313
+	movw	r3, #2392
7314
+	mov	r6, #0
7315
+	mov	r8, r6
7316
+	mov	r10, r6
7317
+	ldrh	r2, [r2, r3]
7318
+	ldrh	r3, [r4]
7319
+	lsl	r3, r3, #1
7320
+	strh	r2, [r5, r3]	@ movhi
7321
+	ldrh	r9, [r5]
7322
+.L1149:
7323
+	ldrh	r3, [r4, #10]
7324
+	uxth	r1, r6
7325
+	cmp	r3, r1
7326
+	bhi	.L1153
7327
+	mov	r0, r8
7328
+	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
7329
+.L1148:
7330
+	uxth	r3, r2
6897
7331
 	mov	r1, #0
7332
+	ldr	r0, [r6, r3, lsl #2]
6898
7333
 	ubfx	r0, r0, #10, #16
6899
-.L1146:
7334
+.L1145:
6900
7335
 	ldrh	ip, [r4, #10]
6901
7336
 	uxth	r3, r1
6902
7337
 	cmp	ip, r3
6903
-	bls	.L1166
6904
-	mov	r3, r3, asl #1
7338
+	addls	r2, r2, #1
7339
+	bls	.L1144
7340
+.L1147:
7341
+	uxth	r3, r1
6905
7342
 	add	r1, r1, #1
7343
+	lsl	r3, r3, #1
6906
7344
 	ldrh	ip, [r7, r3]
6907
-	rsb	lr, ip, r0
6908
-	cmp	ip, #0
6909
-	clz	lr, lr
6910
-	mov	lr, lr, lsr #5
6911
-	moveq	lr, #0
7345
+	adds	lr, ip, #0
7346
+	movne	lr, #1
7347
+	cmp	r0, ip
7348
+	movne	lr, #0
6912
7349
 	cmp	lr, #0
6913
-	ldrneh	ip, [r5, r3]
7350
+	ldrhne	ip, [r5, r3]
6914
7351
 	addne	ip, ip, #1
6915
-	strneh	ip, [r5, r3]	@ movhi
6916
-	b	.L1146
6917
-.L1166:
6918
-	add	r2, r2, #1
7352
+	strhne	ip, [r5, r3]	@ movhi
6919
7353
 	b	.L1145
6920
-.L1165:
6921
-	ldr	r2, .L1168
6922
-	movw	r3, #2390
6923
-	mov	r8, #0
6924
-	mov	r1, r8
6925
-	mov	fp, r8
6926
-	ldrh	r2, [r2, r3]
6927
-	ldrh	r3, [r4]
6928
-	mov	r3, r3, asl #1
6929
-	strh	r2, [r5, r3]	@ movhi
6930
-	ldrh	r9, [r5]
6931
-.L1150:
6932
-	ldrh	r3, [r4, #10]
6933
-	uxth	r6, r8
6934
-	cmp	r3, r6
6935
-	bls	.L1167
6936
-	mov	r2, r6, asl #1
6937
-	ldrh	r3, [r5, r2]
6938
-	cmp	r9, r3
6939
-	bls	.L1151
6940
-	ldrh	r0, [r7, r2]
6941
-	add	r10, r7, r2
7354
+.L1153:
7355
+	uxth	r3, r6
7356
+	lsl	r3, r3, #1
7357
+	ldrh	r2, [r5, r3]
7358
+	cmp	r9, r2
7359
+	bls	.L1150
7360
+	ldrh	r0, [r7, r3]
7361
+	add	fp, r7, r3
6942
7362
 	cmp	r0, #0
6943
-	bne	.L1152
6944
-	b	.L1153
6945
-.L1151:
6946
-	cmp	r3, #0
6947
-	bne	.L1153
6948
-	ldrh	r0, [r7, r2]
6949
-	add	r10, r7, r2
6950
-	cmp	r0, #0
6951
-	movne	r6, r1
6952
-	beq	.L1153
6953
-	b	.L1155
7363
+	bne	.L1151
6954
7364
 .L1152:
6955
-	cmp	r3, #0
6956
-	movne	r1, r6
6957
-	movne	r9, r3
6958
-	bne	.L1153
6959
-	mov	r9, r3
6960
-.L1155:
7365
+	add	r6, r6, #1
7366
+	b	.L1149
7367
+.L1150:
7368
+	cmp	r2, #0
7369
+	bne	.L1152
7370
+	ldrh	r0, [r7, r3]
7371
+	add	fp, r7, r3
7372
+	cmp	r0, #0
7373
+	beq	.L1152
7374
+.L1154:
6961
7375
 	mov	r1, #1
6962
7376
 	bl	FtlFreeSysBlkQueueIn
6963
-	strh	fp, [r10]	@ movhi
7377
+	strh	r10, [fp]	@ movhi
6964
7378
 	ldrh	r3, [r4, #8]
6965
-	mov	r1, r6
6966
7379
 	sub	r3, r3, #1
6967
7380
 	strh	r3, [r4, #8]	@ movhi
6968
-.L1153:
6969
-	add	r8, r8, #1
6970
-	b	.L1150
6971
-.L1167:
6972
-	mov	r0, r1
6973
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
6974
-.L1169:
7381
+	b	.L1152
7382
+.L1151:
7383
+	subs	r9, r2, #0
7384
+	mov	r8, r1
7385
+	beq	.L1154
7386
+	b	.L1152
7387
+.L1165:
6975
7388
 	.align	2
6976
-.L1168:
7389
+.L1164:
6977
7390
 	.word	.LANCHOR0
6978
7391
 	.fnend
6979
7392
 	.size	ftl_free_no_use_map_blk, .-ftl_free_no_use_map_blk
6980
7393
 	.align	2
6981
7394
 	.global	FtlL2PDataInit
7395
+	.syntax unified
7396
+	.arm
7397
+	.fpu softvfp
6982
7398
 	.type	FtlL2PDataInit, %function
6983
7399
 FtlL2PDataInit:
6984
7400
 	.fnstart
6985
7401
 	@ args = 0, pretend = 0, frame = 0
6986
7402
 	@ frame_needed = 0, uses_anonymous_args = 0
6987
-	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
6988
-	.save {r4, r5, r6, r7, r8, lr}
7403
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
7404
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
6989
7405
 	mov	r1, #0
6990
-	ldr	r5, .L1175
6991
-	mvn	r6, #0
6992
-	ldr	r4, .L1175+4
6993
-	ldr	r2, [r5, #2416]
6994
-	ldr	r0, [r4, #-468]
6995
-	mov	r2, r2, asl #1
7406
+	ldr	r4, .L1170
7407
+	mvn	r7, #0
7408
+	ldr	r5, .L1170+4
7409
+	ldr	r2, [r4, #2420]
7410
+	add	r6, r4, #2400
7411
+	ldr	r0, [r5, #-468]
7412
+	lsl	r2, r2, #1
6996
7413
 	bl	ftl_memset
6997
-	movw	r3, #2398
6998
-	movw	r2, #2426
6999
-	ldrh	r3, [r5, r3]
7000
-	ldrh	r2, [r5, r2]
7414
+	movw	r2, #2430
7415
+	ldrh	r3, [r6]
7416
+	ldrh	r2, [r4, r2]
7001
7417
 	mov	r1, #255
7002
-	ldr	r0, [r4, #-440]
7418
+	ldr	r0, [r5, #-440]
7003
7419
 	mul	r2, r2, r3
7004
7420
 	bl	ftl_memset
7005
-	ldr	ip, .L1175+8
7006
-	mov	r1, #0
7007
-	mov	r3, r4
7008
-	sub	r7, ip, #28
7009
-	mov	r4, #12
7010
-	mov	r5, r1
7011
-.L1171:
7012
-	ldrh	r2, [ip]
7013
-	add	lr, r1, #1
7014
-	uxth	r1, r1
7015
-	ldr	r0, .L1175
7016
-	cmp	r2, r1
7017
-	bls	.L1174
7018
-	mul	r0, r4, r1
7019
-	ldr	r2, [r3, #-3380]
7020
-	add	r8, r2, r0
7021
-	str	r5, [r8, #4]
7022
-	strh	r6, [r2, r0]	@ movhi
7023
-	ldr	r2, [r3, #-3380]
7024
-	add	r0, r2, r0
7025
-	ldrh	r2, [r7]
7026
-	mul	r2, r1, r2
7027
-	ldr	r1, [r3, #-440]
7028
-	bic	r2, r2, #3
7029
-	add	r2, r1, r2
7030
-	mov	r1, lr
7031
-	str	r2, [r0, #8]
7032
-	b	.L1171
7033
-.L1174:
7034
-	ldr	r2, .L1175+12
7421
+	mov	r2, #0
7422
+	mov	r3, r5
7423
+	mov	r1, r6
7424
+	add	ip, r6, #30
7425
+	mov	r5, #12
7426
+	mov	r6, r2
7427
+.L1167:
7428
+	ldrh	r8, [ip]
7429
+	uxth	r0, r2
7430
+	add	lr, r2, #1
7431
+	cmp	r8, r0
7432
+	bhi	.L1168
7433
+	ldr	r2, .L1170+8
7035
7434
 	mvn	r1, #0
7036
7435
 	strh	r1, [r2, #2]	@ movhi
7037
7436
 	strh	r1, [r2]	@ movhi
7038
-	ldr	r1, [r0, #2416]
7437
+	ldr	r1, [r4, #2420]
7039
7438
 	strh	r1, [r2, #10]	@ movhi
7040
-	ldr	r1, .L1175+16
7439
+	ldr	r1, .L1170+12
7041
7440
 	strh	r1, [r2, #4]	@ movhi
7042
7441
 	ldrh	r1, [r2, #44]
7043
7442
 	strh	r1, [r2, #8]	@ movhi
7044
-	movw	r1, #2424
7045
-	ldrh	r1, [r0, r1]
7443
+	movw	r1, #2428
7444
+	ldrh	r1, [r4, r1]
7046
7445
 	strh	r1, [r2, #6]	@ movhi
7047
7446
 	ldr	r2, [r3, #-472]
7048
7447
 	str	r2, [r3, #-420]
..
..
@@ -7052,236 +7451,249 @@
7052
7451
 	str	r2, [r3, #-412]
7053
7452
 	ldr	r2, [r3, #-452]
7054
7453
 	str	r2, [r3, #-408]
7055
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
7056
-.L1176:
7454
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
7455
+.L1168:
7456
+	uxth	r2, r2
7457
+	ldr	r8, [r3, #-3376]
7458
+	mul	r0, r5, r2
7459
+	add	r9, r8, r0
7460
+	str	r6, [r9, #4]
7461
+	strh	r7, [r8, r0]	@ movhi
7462
+	ldr	r8, [r3, #-3376]
7463
+	add	r0, r8, r0
7464
+	ldrh	r8, [r1]
7465
+	mul	r2, r2, r8
7466
+	ldr	r8, [r3, #-440]
7467
+	bic	r2, r2, #3
7468
+	add	r2, r8, r2
7469
+	str	r2, [r0, #8]
7470
+	mov	r2, lr
7471
+	b	.L1167
7472
+.L1171:
7057
7473
 	.align	2
7058
-.L1175:
7474
+.L1170:
7059
7475
 	.word	.LANCHOR0
7060
7476
 	.word	.LANCHOR2
7061
-	.word	.LANCHOR0+2426
7062
7477
 	.word	.LANCHOR2-432
7063
7478
 	.word	-3902
7064
7479
 	.fnend
7065
7480
 	.size	FtlL2PDataInit, .-FtlL2PDataInit
7066
7481
 	.align	2
7067
7482
 	.global	FtlVariablesInit
7483
+	.syntax unified
7484
+	.arm
7485
+	.fpu softvfp
7068
7486
 	.type	FtlVariablesInit, %function
7069
7487
 FtlVariablesInit:
7070
7488
 	.fnstart
7071
7489
 	@ args = 0, pretend = 0, frame = 0
7072
7490
 	@ frame_needed = 0, uses_anonymous_args = 0
7073
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
7074
-	.save {r3, r4, r5, r6, r7, lr}
7491
+	push	{r4, r5, r6, r7, r8, lr}
7492
+	.save {r4, r5, r6, r7, r8, lr}
7075
7493
 	mvn	r3, #0
7076
-	ldr	r5, .L1179
7494
+	ldr	r5, .L1174
7077
7495
 	mov	r4, #0
7078
-	ldr	r6, .L1179+4
7079
7496
 	mov	r1, r4
7497
+	movw	r7, #2334
7498
+	ldr	r6, .L1174+4
7080
7499
 	sub	r2, r5, #380
7081
-	movw	r7, #2330
7082
7500
 	str	r3, [r5, #-368]
7083
7501
 	strh	r3, [r2]	@ movhi
7084
-	movw	r3, #2434
7502
+	movw	r3, #2438
7085
7503
 	strh	r4, [r6, r3]	@ movhi
7086
-	movw	r3, #2408
7504
+	movw	r3, #2412
7087
7505
 	ldrh	r2, [r6, r3]
7088
-	ldr	r0, [r6, #2436]
7506
+	ldr	r0, [r6, #2440]
7089
7507
 	str	r4, [r5, #-384]
7090
-	mov	r2, r2, asl #1
7091
7508
 	str	r4, [r5, #-376]
7509
+	lsl	r2, r2, #1
7092
7510
 	str	r4, [r5, #-372]
7093
-	str	r4, [r6, #2244]
7511
+	str	r4, [r6, #2248]
7094
7512
 	bl	ftl_memset
7095
7513
 	ldrh	r2, [r6, r7]
7096
7514
 	mov	r1, r4
7097
-	ldr	r0, [r5, #-3608]
7098
-	mov	r2, r2, asl #1
7515
+	ldr	r0, [r5, #-3604]
7516
+	lsl	r2, r2, #1
7099
7517
 	bl	ftl_memset
7100
7518
 	ldrh	r2, [r6, r7]
7101
7519
 	mov	r1, r4
7102
7520
 	ldr	r0, [r5, #-484]
7103
-	mov	r2, r2, asl #1
7521
+	lsl	r2, r2, #1
7104
7522
 	bl	ftl_memset
7523
+	sub	r0, r5, #3584
7105
7524
 	mov	r1, r4
7106
-	sub	r0, r5, #3600
7107
7525
 	mov	r2, #48
7526
+	sub	r0, r0, #12
7108
7527
 	bl	ftl_memset
7109
-	mov	r1, r4
7110
-	mov	r2, #512
7111
7528
 	sub	r0, r5, #3232
7529
+	mov	r2, #512
7530
+	mov	r1, r4
7531
+	sub	r0, r0, #4
7112
7532
 	bl	ftl_memset
7113
7533
 	bl	FtlGcBufInit
7114
7534
 	bl	FtlL2PDataInit
7115
7535
 	mov	r0, r4
7116
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
7117
-.L1180:
7536
+	pop	{r4, r5, r6, r7, r8, pc}
7537
+.L1175:
7118
7538
 	.align	2
7119
-.L1179:
7539
+.L1174:
7120
7540
 	.word	.LANCHOR2
7121
7541
 	.word	.LANCHOR0
7122
7542
 	.fnend
7123
7543
 	.size	FtlVariablesInit, .-FtlVariablesInit
7124
7544
 	.align	2
7125
7545
 	.global	SupperBlkListInit
7546
+	.syntax unified
7547
+	.arm
7548
+	.fpu softvfp
7126
7549
 	.type	SupperBlkListInit, %function
7127
7550
 SupperBlkListInit:
7128
7551
 	.fnstart
7129
-	@ args = 0, pretend = 0, frame = 24
7552
+	@ args = 0, pretend = 0, frame = 16
7130
7553
 	@ frame_needed = 0, uses_anonymous_args = 0
7131
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7554
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
7132
7555
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7133
-	movw	r3, #2330
7134
-	ldr	r10, .L1193
7556
+	movw	r3, #2334
7557
+	ldr	r6, .L1187
7558
+	mov	r4, #0
7135
7559
 	mov	r2, #6
7136
-	ldr	r6, .L1193+4
7560
+	.pad #20
7561
+	sub	sp, sp, #20
7562
+	ldr	r5, .L1187+4
7137
7563
 	mov	r1, #0
7138
-	.pad #28
7139
-	sub	sp, sp, #28
7140
-	mov	r7, #0
7141
-	ldrh	r3, [r10, r3]
7142
-	mov	r4, r7
7143
-	ldr	r0, [r6, #-3552]
7144
-	mov	r8, r7
7145
-	mov	r9, r7
7146
-	mov	r5, r6
7564
+	ldrh	r3, [r6, r3]
7565
+	mov	r9, r4
7566
+	mov	r10, r4
7567
+	ldr	r0, [r5, #-3548]
7568
+	sub	r7, r5, #3520
7147
7569
 	mul	r2, r2, r3
7148
7570
 	bl	ftl_memset
7149
-	sub	r3, r6, #3520
7150
-	sub	r1, r6, #3536
7151
-	mov	fp, r6
7152
-	strh	r7, [r3, #-8]	@ movhi
7153
-	sub	r3, r6, #568
7154
-	str	r7, [r6, #-3532]
7155
-	str	r7, [r6, #-3548]
7156
-	str	r7, [r6, #-3540]
7157
-	strh	r7, [r1]	@ movhi
7158
-	strh	r7, [r3]	@ movhi
7159
-	str	r10, [sp, #8]
7160
-	str	r1, [sp, #12]
7161
-.L1182:
7162
-	ldr	r3, .L1193+8
7163
-	uxth	r7, r4
7164
-	sxth	r10, r7
7165
-	ldrh	r2, [r3]
7166
-	cmp	r10, r2
7167
-	bge	.L1189
7168
-	sub	r3, r3, #8
7169
-	ldr	r2, .L1193+12
7170
-	mov	ip, r7
7571
+	sub	r3, r5, #568
7572
+	str	r4, [r5, #-3528]
7573
+	str	r4, [r5, #-3544]
7574
+	str	r4, [r5, #-3536]
7575
+	strh	r4, [r7, #-12]	@ movhi
7576
+	strh	r4, [r7, #-4]	@ movhi
7577
+	strh	r4, [r3]	@ movhi
7578
+	str	r6, [sp]
7579
+.L1177:
7580
+	ldr	r3, .L1187+8
7581
+	sxth	r8, r4
7171
7582
 	ldrh	r3, [r3]
7172
-	str	r3, [sp]
7173
-	ldrh	r3, [r2]
7174
-	mov	r2, #0
7175
-	mov	r6, r2
7176
-	str	r3, [sp, #4]
7177
-.L1190:
7583
+	cmp	r8, r3
7584
+	bge	.L1184
7585
+	ldr	r3, .L1187+12
7586
+	uxth	r1, r4
7587
+	mov	fp, #0
7588
+	mov	r6, fp
7589
+	str	r1, [sp, #4]
7590
+	ldrh	r2, [r3]
7591
+	add	r3, r3, #66
7592
+	ldrh	r3, [r3]
7593
+	b	.L1185
7594
+.L1179:
7595
+	str	r3, [sp, #12]
7596
+	add	fp, fp, #1
7178
7597
 	ldr	r3, [sp]
7179
-	sxth	r1, r2
7180
-	cmp	r1, r3
7181
-	bge	.L1192
7182
-	ldr	r3, [sp, #8]
7183
-	str	r2, [sp, #20]
7184
-	add	r1, r3, r1
7185
-	str	ip, [sp, #16]
7186
-	ldrb	r0, [r1, #2348]	@ zero_extendqisi2
7187
-	mov	r1, ip
7598
+	str	r2, [sp, #8]
7599
+	add	r0, r3, r1
7600
+	ldr	r1, [sp, #4]
7601
+	ldrb	r0, [r0, #2350]	@ zero_extendqisi2
7188
7602
 	bl	V2P_block
7189
7603
 	bl	FtlBbmIsBadBlock
7604
+	ldr	r3, [sp, #12]
7190
7605
 	cmp	r0, #0
7191
-	ldr	r2, [sp, #20]
7192
-	ldr	ip, [sp, #16]
7193
-	ldreq	r3, [sp, #4]
7194
-	add	r2, r2, #1
7606
+	ldr	r2, [sp, #8]
7195
7607
 	addeq	r6, r3, r6
7196
-	uxtheq	r6, r6
7197
-	b	.L1190
7198
-.L1192:
7608
+	sxtheq	r6, r6
7609
+.L1185:
7610
+	sxth	r1, fp
7611
+	cmp	r1, r2
7612
+	blt	.L1179
7199
7613
 	cmp	r6, #0
7200
-	beq	.L1185
7201
-	sxth	r1, r6
7614
+	lsl	fp, r8, #1
7615
+	ldreq	r3, [r5, #-3540]
7616
+	mvneq	r2, #0
7617
+	strheq	r2, [r3, fp]	@ movhi
7618
+	beq	.L1181
7619
+	mov	r1, r6
7202
7620
 	mov	r0, #32768
7203
7621
 	bl	__aeabi_idiv
7204
-	uxth	r6, r0
7205
-	b	.L1186
7206
-.L1185:
7207
-	sxth	r7, r7
7208
-	ldr	r2, [r5, #-3544]
7209
-	mvn	r1, #0
7210
-	mov	r7, r7, asl #1
7211
-	strh	r1, [r2, r7]	@ movhi
7212
-.L1186:
7213
-	mov	r1, r10, asl #1
7214
-	ldr	r2, [r5, #-3552]
7215
-	add	r0, r1, r10
7216
-	add	r2, r2, r0, asl #1
7217
-	strh	r6, [r2, #4]	@ movhi
7218
-	ldr	r2, .L1193+16
7219
-	ldrh	r0, [r2]
7220
-	cmp	r10, r0
7221
-	beq	.L1187
7222
-	ldrh	r0, [r2, #48]
7223
-	cmp	r10, r0
7224
-	beq	.L1187
7225
-	ldrh	r2, [r2, #96]
7226
-	cmp	r10, r2
7227
-	beq	.L1187
7228
-	ldr	r3, [fp, #-3544]
7622
+	sxth	r6, r0
7623
+.L1181:
7624
+	ldr	r2, [r5, #-3548]
7625
+	add	r3, fp, r8
7626
+	add	r3, r2, r3, lsl #1
7627
+	strh	r6, [r3, #4]	@ movhi
7628
+	ldrh	r3, [r7]
7629
+	cmp	r8, r3
7630
+	beq	.L1182
7631
+	ldr	r3, .L1187+16
7632
+	ldrh	r3, [r3]
7633
+	cmp	r8, r3
7634
+	beq	.L1182
7635
+	ldr	r3, .L1187+20
7636
+	ldrh	r3, [r3]
7637
+	cmp	r8, r3
7638
+	beq	.L1182
7639
+	ldr	r3, [r5, #-3540]
7229
7640
 	uxth	r0, r4
7230
-	ldrh	r3, [r3, r1]
7641
+	ldrh	r3, [r3, fp]
7231
7642
 	cmp	r3, #0
7232
-	bne	.L1188
7233
-	add	r8, r8, #1
7234
-	uxth	r8, r8
7235
-	bl	INSERT_FREE_LIST
7236
-	b	.L1187
7237
-.L1188:
7643
+	bne	.L1183
7238
7644
 	add	r9, r9, #1
7239
7645
 	uxth	r9, r9
7240
-	bl	INSERT_DATA_LIST
7241
-.L1187:
7646
+	bl	INSERT_FREE_LIST
7647
+.L1182:
7242
7648
 	add	r4, r4, #1
7649
+	b	.L1177
7650
+.L1183:
7651
+	add	r10, r10, #1
7652
+	uxth	r10, r10
7653
+	bl	INSERT_DATA_LIST
7243
7654
 	b	.L1182
7244
-.L1189:
7245
-	ldr	r3, [sp, #12]
7655
+.L1184:
7246
7656
 	mov	r0, #0
7247
-	strh	r9, [r3]	@ movhi
7248
-	ldr	r3, .L1193+20
7249
-	strh	r8, [r3, #-8]	@ movhi
7250
-	add	sp, sp, #28
7657
+	strh	r10, [r7, #-12]	@ movhi
7658
+	strh	r9, [r7, #-4]	@ movhi
7659
+	add	sp, sp, #20
7251
7660
 	@ sp needed
7252
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
7253
-.L1194:
7661
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
7662
+.L1188:
7254
7663
 	.align	2
7255
-.L1193:
7664
+.L1187:
7256
7665
 	.word	.LANCHOR0
7257
7666
 	.word	.LANCHOR2
7258
-	.word	.LANCHOR0+2328
7259
-	.word	.LANCHOR0+2388
7260
-	.word	.LANCHOR2-3524
7261
-	.word	.LANCHOR2-3520
7667
+	.word	.LANCHOR0+2332
7668
+	.word	.LANCHOR0+2324
7669
+	.word	.LANCHOR2-3472
7670
+	.word	.LANCHOR2-3424
7262
7671
 	.fnend
7263
7672
 	.size	SupperBlkListInit, .-SupperBlkListInit
7264
7673
 	.align	2
7265
7674
 	.global	FtlGcPageVarInit
7675
+	.syntax unified
7676
+	.arm
7677
+	.fpu softvfp
7266
7678
 	.type	FtlGcPageVarInit, %function
7267
7679
 FtlGcPageVarInit:
7268
7680
 	.fnstart
7269
7681
 	@ args = 0, pretend = 0, frame = 0
7270
7682
 	@ frame_needed = 0, uses_anonymous_args = 0
7271
-	stmfd	sp!, {r4, r5, r6, lr}
7683
+	push	{r4, r5, r6, lr}
7272
7684
 	.save {r4, r5, r6, lr}
7273
7685
 	mov	r3, #0
7274
-	ldr	r4, .L1197
7275
-	movw	r5, #2392
7276
-	ldr	r6, .L1197+4
7686
+	ldr	r4, .L1191
7687
+	movw	r5, #2394
7277
7688
 	mov	r1, #255
7689
+	ldr	r6, .L1191+4
7278
7690
 	sub	r2, r4, #2672
7279
7691
 	ldr	r0, [r4, #-2680]
7280
7692
 	strh	r3, [r2, #-4]	@ movhi
7281
7693
 	sub	r2, r4, #2656
7282
7694
 	strh	r3, [r2, #-12]	@ movhi
7283
7695
 	ldrh	r2, [r6, r5]
7284
-	mov	r2, r2, asl #1
7696
+	lsl	r2, r2, #1
7285
7697
 	bl	ftl_memset
7286
7698
 	ldrh	r3, [r6, r5]
7287
7699
 	mov	r2, #12
..
..
@@ -7289,17 +7701,20 @@
7289
7701
 	mov	r1, #255
7290
7702
 	mul	r2, r2, r3
7291
7703
 	bl	ftl_memset
7292
-	ldmfd	sp!, {r4, r5, r6, lr}
7704
+	pop	{r4, r5, r6, lr}
7293
7705
 	b	FtlGcBufInit
7294
-.L1198:
7706
+.L1192:
7295
7707
 	.align	2
7296
-.L1197:
7708
+.L1191:
7297
7709
 	.word	.LANCHOR2
7298
7710
 	.word	.LANCHOR0
7299
7711
 	.fnend
7300
7712
 	.size	FtlGcPageVarInit, .-FtlGcPageVarInit
7301
7713
 	.align	2
7302
7714
 	.global	ftl_memcpy
7715
+	.syntax unified
7716
+	.arm
7717
+	.fpu softvfp
7303
7718
 	.type	ftl_memcpy, %function
7304
7719
 ftl_memcpy:
7305
7720
 	.fnstart
..
..
@@ -7311,158 +7726,155 @@
7311
7726
 	.size	ftl_memcpy, .-ftl_memcpy
7312
7727
 	.align	2
7313
7728
 	.global	FlashReadIdbData
7729
+	.syntax unified
7730
+	.arm
7731
+	.fpu softvfp
7314
7732
 	.type	FlashReadIdbData, %function
7315
7733
 FlashReadIdbData:
7316
7734
 	.fnstart
7317
7735
 	@ args = 0, pretend = 0, frame = 0
7318
7736
 	@ frame_needed = 0, uses_anonymous_args = 0
7319
-	stmfd	sp!, {r3, lr}
7320
-	.save {r3, lr}
7737
+	push	{r4, lr}
7738
+	.save {r4, lr}
7321
7739
 	mov	r2, #2048
7322
-	ldr	r1, .L1202
7740
+	ldr	r1, .L1196
7323
7741
 	bl	ftl_memcpy
7324
7742
 	mov	r0, #0
7325
-	ldmfd	sp!, {r3, pc}
7326
-.L1203:
7743
+	pop	{r4, pc}
7744
+.L1197:
7327
7745
 	.align	2
7328
-.L1202:
7746
+.L1196:
7329
7747
 	.word	.LANCHOR2-364
7330
7748
 	.fnend
7331
7749
 	.size	FlashReadIdbData, .-FlashReadIdbData
7332
7750
 	.align	2
7333
7751
 	.global	FlashLoadPhyInfoInRam
7752
+	.syntax unified
7753
+	.arm
7754
+	.fpu softvfp
7334
7755
 	.type	FlashLoadPhyInfoInRam, %function
7335
7756
 FlashLoadPhyInfoInRam:
7336
7757
 	.fnstart
7337
7758
 	@ args = 0, pretend = 0, frame = 0
7338
7759
 	@ frame_needed = 0, uses_anonymous_args = 0
7339
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
7340
-	.save {r3, r4, r5, r6, r7, r8, r9, lr}
7760
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
7761
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
7341
7762
 	mov	r4, #0
7342
-	ldr	r8, .L1217
7343
-.L1208:
7344
-	mov	r7, r4, asl #5
7345
-	ldr	r1, .L1217+4
7346
-	add	r0, r7, #1
7347
-	ldrb	r2, [r8, r4, asl #5]	@ zero_extendqisi2
7348
-	add	r0, r8, r0
7349
-	ldr	r6, .L1217+8
7763
+	ldr	r5, .L1207
7764
+	ldr	r9, .L1207+4
7765
+	add	r6, r5, #504
7766
+.L1201:
7767
+	lsl	r8, r4, #5
7768
+	ldrb	r2, [r6, r4, lsl #5]	@ zero_extendqisi2
7769
+	mov	r1, r9
7770
+	add	r0, r8, #1
7771
+	add	r0, r6, r0
7350
7772
 	bl	FlashMemCmp8
7351
-	add	r9, r6, #508
7352
-	subs	r5, r0, #0
7353
-	bne	.L1205
7354
-	adds	r9, r9, r7
7355
-	beq	.L1211
7356
-	add	r4, r6, r7
7357
-	mov	r3, r5
7358
-	ldr	r1, .L1217+12
7359
-	ldrb	r2, [r4, #530]	@ zero_extendqisi2
7360
-	b	.L1210
7361
-.L1205:
7362
-	add	r4, r4, #1
7363
-	cmp	r4, #86
7364
-	bne	.L1208
7365
-	b	.L1211
7366
-.L1216:
7773
+	subs	r7, r0, #0
7774
+	bne	.L1199
7775
+	add	r5, r5, r8
7776
+	ldr	r2, .L1207+8
7777
+	ldrb	r0, [r5, #526]	@ zero_extendqisi2
7778
+	add	r6, r6, r8
7779
+	mov	r3, r7
7780
+	mov	r1, r2
7781
+.L1200:
7782
+	ldrb	ip, [r2, r3, lsl #5]	@ zero_extendqisi2
7783
+	cmp	ip, r0
7784
+	beq	.L1203
7367
7785
 	add	r3, r3, #1
7368
7786
 	cmp	r3, #4
7369
-	beq	.L1209
7370
-.L1210:
7371
-	ldrb	r0, [r1, r3, asl #5]	@ zero_extendqisi2
7372
-	cmp	r0, r2
7373
-	bne	.L1216
7374
-.L1209:
7375
-	ldr	r4, .L1217+16
7787
+	bne	.L1200
7788
+.L1203:
7789
+	ldr	r4, .L1207+12
7790
+	add	r1, r1, r3, lsl #5
7376
7791
 	mov	r2, #32
7377
-	ldr	r1, .L1217+12
7378
-	ldr	r0, .L1217+20
7379
-	add	r1, r1, r3, asl #5
7792
+	ldr	r0, .L1207+16
7380
7793
 	bl	ftl_memcpy
7381
-	mov	r0, r4
7382
-	mov	r1, r9
7383
7794
 	mov	r2, #32
7795
+	mov	r1, r6
7796
+	mov	r0, r4
7384
7797
 	bl	ftl_memcpy
7385
7798
 	ldrh	r0, [r4, #10]
7386
7799
 	bl	FlashBlockAlignInit
7387
-	b	.L1206
7388
-.L1211:
7389
-	mvn	r5, #0
7390
-.L1206:
7391
-	mov	r0, r5
7392
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
7393
-.L1218:
7800
+	b	.L1198
7801
+.L1199:
7802
+	add	r4, r4, #1
7803
+	cmp	r4, #86
7804
+	bne	.L1201
7805
+	mvn	r7, #0
7806
+.L1198:
7807
+	mov	r0, r7
7808
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
7809
+.L1208:
7394
7810
 	.align	2
7395
-.L1217:
7396
-	.word	.LANCHOR1+508
7397
-	.word	.LANCHOR0+2068
7811
+.L1207:
7398
7812
 	.word	.LANCHOR1
7399
-	.word	.LANCHOR1+3260
7400
-	.word	.LANCHOR1+472
7401
-	.word	.LANCHOR0+48
7813
+	.word	.LANCHOR0+2072
7814
+	.word	.LANCHOR1+3256
7815
+	.word	.LANCHOR1+468
7816
+	.word	.LANCHOR0+52
7402
7817
 	.fnend
7403
7818
 	.size	FlashLoadPhyInfoInRam, .-FlashLoadPhyInfoInRam
7404
7819
 	.align	2
7405
7820
 	.global	NandcCopy1KB
7821
+	.syntax unified
7822
+	.arm
7823
+	.fpu softvfp
7406
7824
 	.type	NandcCopy1KB, %function
7407
7825
 NandcCopy1KB:
7408
7826
 	.fnstart
7409
7827
 	@ args = 4, pretend = 0, frame = 0
7410
7828
 	@ frame_needed = 0, uses_anonymous_args = 0
7411
7829
 	cmp	r1, #1
7412
-	stmfd	sp!, {r4, r5, r6, lr}
7830
+	push	{r4, r5, r6, lr}
7413
7831
 	.save {r4, r5, r6, lr}
7414
7832
 	mov	r4, r2
7415
7833
 	add	r2, r0, #4096
7416
-	ldr	r5, [sp, #16]
7417
7834
 	add	r6, r0, #512
7418
-	add	r2, r2, r4, asl #9
7419
-	bne	.L1220
7835
+	add	r0, r2, r4, lsl #9
7836
+	ldr	r5, [sp, #16]
7837
+	bne	.L1210
7420
7838
 	cmp	r3, #0
7421
-	beq	.L1221
7422
-	mov	r0, r2
7839
+	beq	.L1211
7840
+	mov	r2, #1024
7423
7841
 	mov	r1, r3
7424
-	mov	r2, #1024
7425
7842
 	bl	ftl_memcpy
7426
-.L1221:
7843
+.L1211:
7427
7844
 	cmp	r5, #0
7428
-	ldmeqfd	sp!, {r4, r5, r6, pc}
7429
-	ldrb	r3, [r5, #2]	@ zero_extendqisi2
7430
-	mov	r4, r4, lsr #1
7431
-	ldrb	r2, [r5, #1]	@ zero_extendqisi2
7432
-	add	r4, r4, r4, asl #1
7433
-	mov	r3, r3, asl #16
7434
-	orr	r2, r3, r2, asl #8
7435
-	ldrb	r3, [r5]	@ zero_extendqisi2
7436
-	orr	r3, r2, r3
7437
-	ldrb	r2, [r5, #3]	@ zero_extendqisi2
7438
-	orr	r3, r3, r2, asl #24
7439
-	str	r3, [r6, r4, asl #4]
7440
-	ldmfd	sp!, {r4, r5, r6, pc}
7441
-.L1220:
7845
+	lsrne	r4, r4, #1
7846
+	ldrne	r3, [r5]	@ unaligned
7847
+	addne	r4, r4, r4, lsl #1
7848
+	strne	r3, [r6, r4, lsl #4]
7849
+	pop	{r4, r5, r6, pc}
7850
+.L1210:
7442
7851
 	cmp	r3, #0
7443
-	beq	.L1224
7444
-	mov	r1, r2
7445
-	mov	r0, r3
7852
+	beq	.L1214
7853
+	mov	r1, r0
7446
7854
 	mov	r2, #1024
7855
+	mov	r0, r3
7447
7856
 	bl	ftl_memcpy
7448
-.L1224:
7857
+.L1214:
7449
7858
 	cmp	r5, #0
7450
-	ldmeqfd	sp!, {r4, r5, r6, pc}
7451
-	mov	r4, r4, lsr #1
7452
-	add	r4, r4, r4, asl #1
7453
-	ldr	r3, [r6, r4, asl #4]
7454
-	mov	r2, r3, lsr #8
7859
+	popeq	{r4, r5, r6, pc}
7860
+	lsr	r4, r4, #1
7861
+	add	r4, r4, r4, lsl #1
7862
+	ldr	r3, [r6, r4, lsl #4]
7455
7863
 	strb	r3, [r5]
7864
+	lsr	r2, r3, #8
7456
7865
 	strb	r2, [r5, #1]
7457
-	mov	r2, r3, lsr #16
7458
-	mov	r3, r3, lsr #24
7866
+	lsr	r2, r3, #16
7867
+	lsr	r3, r3, #24
7459
7868
 	strb	r2, [r5, #2]
7460
7869
 	strb	r3, [r5, #3]
7461
-	ldmfd	sp!, {r4, r5, r6, pc}
7870
+	pop	{r4, r5, r6, pc}
7462
7871
 	.fnend
7463
7872
 	.size	NandcCopy1KB, .-NandcCopy1KB
7464
7873
 	.align	2
7465
7874
 	.global	ftl_memcpy32
7875
+	.syntax unified
7876
+	.arm
7877
+	.fpu softvfp
7466
7878
 	.type	ftl_memcpy32, %function
7467
7879
 ftl_memcpy32:
7468
7880
 	.fnstart
..
..
@@ -7470,18 +7882,22 @@
7470
7882
 	@ frame_needed = 0, uses_anonymous_args = 0
7471
7883
 	@ link register save eliminated.
7472
7884
 	mov	r3, #0
7473
-.L1237:
7885
+.L1227:
7474
7886
 	cmp	r3, r2
7475
-	ldrne	ip, [r1, r3, asl #2]
7476
-	strne	ip, [r0, r3, asl #2]
7477
-	addne	r3, r3, #1
7478
-	bne	.L1237
7479
-.L1239:
7887
+	bne	.L1228
7480
7888
 	bx	lr
7889
+.L1228:
7890
+	ldr	ip, [r1, r3, lsl #2]
7891
+	str	ip, [r0, r3, lsl #2]
7892
+	add	r3, r3, #1
7893
+	b	.L1227
7481
7894
 	.fnend
7482
7895
 	.size	ftl_memcpy32, .-ftl_memcpy32
7483
7896
 	.align	2
7484
7897
 	.global	ftl_memcmp
7898
+	.syntax unified
7899
+	.arm
7900
+	.fpu softvfp
7485
7901
 	.type	ftl_memcmp, %function
7486
7902
 ftl_memcmp:
7487
7903
 	.fnstart
..
..
@@ -7493,52 +7909,60 @@
7493
7909
 	.size	ftl_memcmp, .-ftl_memcmp
7494
7910
 	.align	2
7495
7911
 	.global	timer_get_time
7912
+	.syntax unified
7913
+	.arm
7914
+	.fpu softvfp
7496
7915
 	.type	timer_get_time, %function
7497
7916
 timer_get_time:
7498
7917
 	.fnstart
7499
7918
 	@ args = 0, pretend = 0, frame = 0
7500
7919
 	@ frame_needed = 0, uses_anonymous_args = 0
7501
7920
 	@ link register save eliminated.
7502
-	ldr	r3, .L1242
7921
+	ldr	r3, .L1231
7503
7922
 	ldr	r0, [r3]
7504
7923
 	b	jiffies_to_msecs
7505
-.L1243:
7924
+.L1232:
7506
7925
 	.align	2
7507
-.L1242:
7926
+.L1231:
7508
7927
 	.word	jiffies
7509
7928
 	.fnend
7510
7929
 	.size	timer_get_time, .-timer_get_time
7511
7930
 	.align	2
7512
7931
 	.global	FlashSramLoadStore
7932
+	.syntax unified
7933
+	.arm
7934
+	.fpu softvfp
7513
7935
 	.type	FlashSramLoadStore, %function
7514
7936
 FlashSramLoadStore:
7515
7937
 	.fnstart
7516
7938
 	@ args = 0, pretend = 0, frame = 0
7517
7939
 	@ frame_needed = 0, uses_anonymous_args = 0
7518
-	ldr	ip, .L1248
7940
+	ldr	ip, .L1238
7519
7941
 	cmp	r2, #0
7520
7942
 	moveq	r2, r3
7521
7943
 	ldr	ip, [ip, #1684]
7522
7944
 	add	ip, ip, #4096
7523
-	add	r1, ip, r1
7524
-	beq	.L1247
7525
-	str	lr, [sp, #-4]!
7945
+	add	ip, ip, r1
7946
+	moveq	r1, ip
7947
+	strne	lr, [sp, #-4]!
7526
7948
 	.save {lr}
7527
-	mov	lr, r0
7528
-	mov	r0, r1
7529
-	mov	r1, lr
7530
-	ldr	lr, [sp], #4
7531
-	mov	r2, r3
7532
-.L1247:
7949
+	movne	r1, r0
7950
+	ldrne	lr, [sp], #4
7951
+	movne	r2, r3
7952
+	movne	r0, ip
7953
+.L1237:
7533
7954
 	b	ftl_memcpy
7534
-.L1249:
7955
+.L1239:
7535
7956
 	.align	2
7536
-.L1248:
7957
+.L1238:
7537
7958
 	.word	.LANCHOR2
7538
7959
 	.fnend
7539
7960
 	.size	FlashSramLoadStore, .-FlashSramLoadStore
7540
7961
 	.align	2
7541
7962
 	.global	FlashCs123Init
7963
+	.syntax unified
7964
+	.arm
7965
+	.fpu softvfp
7542
7966
 	.type	FlashCs123Init, %function
7543
7967
 FlashCs123Init:
7544
7968
 	.fnstart
..
..
@@ -7549,7 +7973,51 @@
7549
7973
 	.fnend
7550
7974
 	.size	FlashCs123Init, .-FlashCs123Init
7551
7975
 	.align	2
7976
+	.global	ftl_dma32_malloc
7977
+	.syntax unified
7978
+	.arm
7979
+	.fpu softvfp
7980
+	.type	ftl_dma32_malloc, %function
7981
+ftl_dma32_malloc:
7982
+	.fnstart
7983
+	@ args = 0, pretend = 0, frame = 0
7984
+	@ frame_needed = 0, uses_anonymous_args = 0
7985
+	cmp	r0, #8192
7986
+	ble	.L1242
7987
+	b	ftl_malloc
7988
+.L1242:
7989
+	push	{r4, r5, r6, lr}
7990
+	.save {r4, r5, r6, lr}
7991
+	add	r4, r0, #63
7992
+	ldr	r5, .L1246
7993
+	bic	r4, r4, #63
7994
+	ldr	r3, [r5, #1688]
7995
+	cmp	r4, r3
7996
+	ble	.L1243
7997
+	mov	r0, #16384
7998
+	bl	ftl_malloc
7999
+	mov	r3, #16384
8000
+	str	r0, [r5, #1692]
8001
+	str	r3, [r5, #1688]
8002
+.L1243:
8003
+	ldr	r3, [r5, #1688]
8004
+	ldr	r0, [r5, #1692]
8005
+	sub	r3, r3, r4
8006
+	add	r4, r0, r4
8007
+	str	r3, [r5, #1688]
8008
+	str	r4, [r5, #1692]
8009
+	pop	{r4, r5, r6, pc}
8010
+.L1247:
8011
+	.align	2
8012
+.L1246:
8013
+	.word	.LANCHOR2
8014
+	.fnend
8015
+	.size	ftl_dma32_malloc, .-ftl_dma32_malloc
8016
+	.align	2
7552
8017
 	.global	rk_nand_suspend
8018
+	.syntax unified
8019
+	.arm
8020
+	.fpu softvfp
7553
8021
 	.type	rk_nand_suspend, %function
7554
8022
 rk_nand_suspend:
7555
8023
 	.fnstart
..
..
@@ -7561,6 +8029,9 @@
7561
8029
 	.size	rk_nand_suspend, .-rk_nand_suspend
7562
8030
 	.align	2
7563
8031
 	.global	rk_nand_resume
8032
+	.syntax unified
8033
+	.arm
8034
+	.fpu softvfp
7564
8035
 	.type	rk_nand_resume, %function
7565
8036
 rk_nand_resume:
7566
8037
 	.fnstart
..
..
@@ -7572,23 +8043,29 @@
7572
8043
 	.size	rk_nand_resume, .-rk_nand_resume
7573
8044
 	.align	2
7574
8045
 	.global	rk_ftl_get_capacity
8046
+	.syntax unified
8047
+	.arm
8048
+	.fpu softvfp
7575
8049
 	.type	rk_ftl_get_capacity, %function
7576
8050
 rk_ftl_get_capacity:
7577
8051
 	.fnstart
7578
8052
 	@ args = 0, pretend = 0, frame = 0
7579
8053
 	@ frame_needed = 0, uses_anonymous_args = 0
7580
8054
 	@ link register save eliminated.
7581
-	ldr	r3, .L1254
7582
-	ldr	r0, [r3, #2428]
8055
+	ldr	r3, .L1251
8056
+	ldr	r0, [r3, #2432]
7583
8057
 	bx	lr
7584
-.L1255:
8058
+.L1252:
7585
8059
 	.align	2
7586
-.L1254:
8060
+.L1251:
7587
8061
 	.word	.LANCHOR0
7588
8062
 	.fnend
7589
8063
 	.size	rk_ftl_get_capacity, .-rk_ftl_get_capacity
7590
8064
 	.align	2
7591
8065
 	.global	rk_nandc_get_irq_status
8066
+	.syntax unified
8067
+	.arm
8068
+	.fpu softvfp
7592
8069
 	.type	rk_nandc_get_irq_status, %function
7593
8070
 rk_nandc_get_irq_status:
7594
8071
 	.fnstart
..
..
@@ -7601,6 +8078,9 @@
7601
8078
 	.size	rk_nandc_get_irq_status, .-rk_nandc_get_irq_status
7602
8079
 	.align	2
7603
8080
 	.global	rknand_proc_ftlread
8081
+	.syntax unified
8082
+	.arm
8083
+	.fpu softvfp
7604
8084
 	.type	rknand_proc_ftlread, %function
7605
8085
 rknand_proc_ftlread:
7606
8086
 	.fnstart
..
..
@@ -7612,6 +8092,9 @@
7612
8092
 	.size	rknand_proc_ftlread, .-rknand_proc_ftlread
7613
8093
 	.align	2
7614
8094
 	.global	ReadFlashInfo
8095
+	.syntax unified
8096
+	.arm
8097
+	.fpu softvfp
7615
8098
 	.type	ReadFlashInfo, %function
7616
8099
 ReadFlashInfo:
7617
8100
 	.fnstart
..
..
@@ -7623,266 +8106,275 @@
7623
8106
 	.size	ReadFlashInfo, .-ReadFlashInfo
7624
8107
 	.align	2
7625
8108
 	.global	rknand_print_hex
8109
+	.syntax unified
8110
+	.arm
8111
+	.fpu softvfp
7626
8112
 	.type	rknand_print_hex, %function
7627
8113
 rknand_print_hex:
7628
8114
 	.fnstart
7629
8115
 	@ args = 0, pretend = 0, frame = 0
7630
8116
 	@ frame_needed = 0, uses_anonymous_args = 0
7631
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
7632
-	.save {r3, r4, r5, r6, r7, r8, r9, lr}
8117
+	push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
8118
+	.save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
7633
8119
 	mov	r5, #0
7634
-	mov	r9, r0
8120
+	ldr	r7, .L1266
8121
+	mov	r10, r0
7635
8122
 	mov	r6, r1
7636
-	mov	r7, r2
7637
-	mov	r8, r3
8123
+	mov	r8, r2
8124
+	ldr	fp, .L1266+4
8125
+	mov	r9, r3
7638
8126
 	mov	r4, r5
7639
-.L1260:
7640
-	cmp	r4, r8
7641
-	beq	.L1269
8127
+.L1257:
8128
+	cmp	r4, r9
8129
+	bne	.L1263
8130
+	ldr	r1, .L1266+4
8131
+	ldr	r0, .L1266+8
8132
+	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
8133
+	b	printk
8134
+.L1263:
7642
8135
 	cmp	r5, #0
7643
-	bne	.L1261
7644
-	ldr	r0, .L1270
7645
-	mov	r1, r9
7646
-	mov	r2, r6
8136
+	bne	.L1258
7647
8137
 	mov	r3, r4
8138
+	mov	r2, r6
8139
+	mov	r1, r10
8140
+	ldr	r0, .L1266+12
7648
8141
 	bl	printk
7649
-.L1261:
7650
-	cmp	r7, #4
7651
-	ldreq	r0, .L1270+4
7652
-	ldreq	r1, [r6, r4, asl #2]
7653
-	beq	.L1268
7654
-	cmp	r7, #2
7655
-	moveq	r3, r4, asl #1
7656
-	ldreq	r0, .L1270+4
7657
-	ldreqsh	r1, [r6, r3]
7658
-	ldrne	r0, .L1270+4
7659
-	ldrneb	r1, [r6, r4]	@ zero_extendqisi2
7660
-.L1268:
8142
+.L1258:
8143
+	cmp	r8, #4
8144
+	ldreq	r1, [r6, r4, lsl #2]
8145
+	beq	.L1265
8146
+	cmp	r8, #2
8147
+	lsleq	r3, r4, #1
8148
+	ldrbne	r1, [r6, r4]	@ zero_extendqisi2
8149
+	ldrsheq	r1, [r6, r3]
8150
+.L1265:
8151
+	mov	r0, r7
7661
8152
 	add	r5, r5, #1
7662
8153
 	bl	printk
7663
8154
 	cmp	r5, #15
7664
-	bls	.L1265
7665
-	ldr	r0, .L1270+8
8155
+	bls	.L1262
7666
8156
 	mov	r5, #0
7667
-	ldr	r1, .L1270+12
8157
+	mov	r1, fp
8158
+	ldr	r0, .L1266+8
7668
8159
 	bl	printk
7669
-.L1265:
8160
+.L1262:
7670
8161
 	add	r4, r4, #1
7671
-	b	.L1260
7672
-.L1269:
7673
-	ldr	r0, .L1270+8
7674
-	ldr	r1, .L1270+12
7675
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
7676
-	b	printk
7677
-.L1271:
8162
+	b	.L1257
8163
+.L1267:
7678
8164
 	.align	2
7679
-.L1270:
7680
-	.word	.LC82
8165
+.L1266:
7681
8166
 	.word	.LC83
7682
-	.word	.LC76
7683
8167
 	.word	.LC84
8168
+	.word	.LC77
8169
+	.word	.LC82
7684
8170
 	.fnend
7685
8171
 	.size	rknand_print_hex, .-rknand_print_hex
7686
8172
 	.align	2
7687
8173
 	.global	HynixGetReadRetryDefault
8174
+	.syntax unified
8175
+	.arm
8176
+	.fpu softvfp
7688
8177
 	.type	HynixGetReadRetryDefault, %function
7689
8178
 HynixGetReadRetryDefault:
7690
8179
 	.fnstart
7691
-	@ args = 0, pretend = 0, frame = 40
8180
+	@ args = 0, pretend = 0, frame = 56
7692
8181
 	@ frame_needed = 0, uses_anonymous_args = 0
7693
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
8182
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
7694
8183
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7695
-	cmp	r0, #2
7696
-	ldr	r7, .L1381
7697
8184
 	mvn	r3, #83
8185
+	ldr	r7, .L1384
8186
+	cmp	r0, #2
7698
8187
 	mvn	r1, #82
7699
8188
 	mvn	r2, #81
7700
-	.pad #44
7701
-	sub	sp, sp, #44
8189
+	.pad #60
8190
+	sub	sp, sp, #60
7702
8191
 	mov	r4, r0
7703
-	strb	r3, [r7, #1214]
7704
-	mvn	r3, #80
7705
-	strb	r0, [r7, #1210]
7706
-	strb	r1, [r7, #1215]
7707
-	strb	r2, [r7, #1216]
7708
-	strb	r3, [r7, #1217]
7709
-	bne	.L1273
7710
-	mvn	r3, #88
7711
-	strb	r3, [r7, #1214]
7712
-	ldr	r3, .L1381+4
7713
-	mvn	r2, #8
7714
-	mov	r5, #7
7715
-	strb	r2, [r3, #3405]
7716
-	b	.L1334
7717
-.L1273:
7718
-	cmp	r0, #3
7719
-	bne	.L1275
7720
-	mvn	r3, #79
7721
-	strb	r3, [r7, #1214]
7722
-	mvn	r3, #78
7723
-	strb	r3, [r7, #1215]
7724
-	mvn	r3, #77
7725
-	strb	r3, [r7, #1216]
7726
-	mvn	r3, #76
7727
-	strb	r3, [r7, #1217]
7728
-	mvn	r3, #75
7729
-	strb	r3, [r7, #1218]
7730
-	mvn	r3, #74
7731
-	strb	r3, [r7, #1219]
7732
-	mvn	r3, #73
7733
8192
 	strb	r3, [r7, #1220]
7734
-	mvn	r3, #72
7735
-	b	.L1375
7736
-.L1275:
7737
-	cmp	r0, #4
7738
-	bne	.L1276
7739
-	mvn	r0, #51
7740
-	strb	r1, [r7, #1219]
7741
-	strb	r0, [r7, #1214]
7742
-	mvn	r0, #64
7743
-	strb	r2, [r7, #1220]
7744
-	strb	r0, [r7, #1215]
7745
-	mvn	r0, #85
8193
+	mvn	r3, #80
7746
8194
 	strb	r0, [r7, #1216]
7747
-	mvn	r0, #84
7748
-	strb	r0, [r7, #1217]
7749
-	mvn	r0, #50
7750
-	strb	r0, [r7, #1218]
7751
-.L1375:
7752
-	mov	r5, #8
8195
+	strb	r1, [r7, #1221]
8196
+	strb	r2, [r7, #1222]
8197
+	strb	r3, [r7, #1223]
8198
+	bne	.L1269
8199
+	mvn	r3, #88
8200
+	mov	r5, #7
8201
+	strb	r3, [r7, #1220]
8202
+	mvn	r2, #8
8203
+	ldr	r3, .L1384+4
8204
+	strb	r2, [r3, #3401]
8205
+.L1334:
8206
+	mov	r6, #4
8207
+	b	.L1270
8208
+.L1269:
8209
+	cmp	r0, #3
8210
+	bne	.L1271
8211
+	mvn	r3, #79
8212
+	strb	r3, [r7, #1220]
8213
+	mvn	r3, #78
7753
8214
 	strb	r3, [r7, #1221]
8215
+	mvn	r3, #77
8216
+	strb	r3, [r7, #1222]
8217
+	mvn	r3, #76
8218
+	strb	r3, [r7, #1223]
8219
+	mvn	r3, #75
8220
+	strb	r3, [r7, #1224]
8221
+	mvn	r3, #74
8222
+	strb	r3, [r7, #1225]
8223
+	mvn	r3, #73
8224
+	strb	r3, [r7, #1226]
8225
+	mvn	r3, #72
8226
+.L1379:
8227
+	mov	r5, #8
8228
+	strb	r3, [r7, #1227]
7754
8229
 	mov	r6, r5
7755
-	b	.L1274
7756
-.L1276:
8230
+.L1270:
8231
+	sub	r3, r4, #1
8232
+	cmp	r3, #1
8233
+	bhi	.L1276
8234
+	ldr	fp, .L1384+8
8235
+	mov	r10, #0
8236
+	ldr	r2, .L1384+12
8237
+.L1277:
8238
+	ldrb	r1, [r7, #2234]	@ zero_extendqisi2
8239
+	uxtb	r3, r10
8240
+	cmp	r1, r3
8241
+	bhi	.L1283
8242
+.L1284:
8243
+	ldr	r3, .L1384
8244
+	strb	r6, [r3, #1217]
8245
+	strb	r5, [r3, #1218]
8246
+	add	sp, sp, #60
8247
+	@ sp needed
8248
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
8249
+.L1271:
8250
+	cmp	r0, #4
8251
+	bne	.L1272
8252
+	mvn	r0, #51
8253
+	strb	r1, [r7, #1225]
8254
+	strb	r0, [r7, #1220]
8255
+	mvn	r0, #64
8256
+	strb	r0, [r7, #1221]
8257
+	mvn	r0, #85
8258
+	strb	r0, [r7, #1222]
8259
+	mvn	r0, #84
8260
+	strb	r0, [r7, #1223]
8261
+	mvn	r0, #50
8262
+	strb	r0, [r7, #1224]
8263
+	strb	r2, [r7, #1226]
8264
+	b	.L1379
8265
+.L1272:
7757
8266
 	cmp	r0, #5
7758
-	bne	.L1277
8267
+	bne	.L1273
7759
8268
 	mov	r3, #56
7760
8269
 	mov	r5, #8
7761
-	strb	r3, [r7, #1214]
8270
+	strb	r3, [r7, #1220]
7762
8271
 	mov	r3, #57
7763
-	strb	r3, [r7, #1215]
8272
+	strb	r3, [r7, #1221]
7764
8273
 	mov	r3, #58
7765
-	strb	r3, [r7, #1216]
8274
+	strb	r3, [r7, #1222]
7766
8275
 	mov	r3, #59
7767
-	strb	r3, [r7, #1217]
8276
+	strb	r3, [r7, #1223]
7768
8277
 	b	.L1334
7769
-.L1277:
8278
+.L1273:
7770
8279
 	cmp	r0, #6
7771
-	bne	.L1278
8280
+	bne	.L1274
7772
8281
 	mov	r3, #14
7773
8282
 	mov	r5, #12
7774
-	strb	r3, [r7, #1214]
8283
+	strb	r3, [r7, #1220]
7775
8284
 	mov	r3, #15
7776
-	strb	r3, [r7, #1215]
8285
+	strb	r3, [r7, #1221]
7777
8286
 	mov	r3, #16
7778
-	strb	r3, [r7, #1216]
8287
+	strb	r3, [r7, #1222]
7779
8288
 	mov	r3, #17
7780
-	strb	r3, [r7, #1217]
8289
+	strb	r3, [r7, #1223]
7781
8290
 	b	.L1334
7782
-.L1278:
8291
+.L1274:
7783
8292
 	cmp	r0, #7
7784
-	bne	.L1279
8293
+	bne	.L1275
7785
8294
 	mvn	r3, #79
7786
8295
 	mov	r5, #12
7787
-	strb	r3, [r7, #1214]
7788
-	mov	r6, #10
7789
-	mvn	r3, #78
7790
-	strb	r3, [r7, #1215]
7791
-	mvn	r3, #77
7792
-	strb	r3, [r7, #1216]
7793
-	mvn	r3, #76
7794
-	strb	r3, [r7, #1217]
7795
-	mvn	r3, #75
7796
-	strb	r3, [r7, #1218]
7797
-	mvn	r3, #74
7798
-	strb	r3, [r7, #1219]
7799
-	mvn	r3, #73
7800
8296
 	strb	r3, [r7, #1220]
7801
-	mvn	r3, #72
8297
+	mvn	r3, #78
7802
8298
 	strb	r3, [r7, #1221]
7803
-	mvn	r3, #43
8299
+	mvn	r3, #77
7804
8300
 	strb	r3, [r7, #1222]
7805
-	mvn	r3, #42
8301
+	mvn	r3, #76
7806
8302
 	strb	r3, [r7, #1223]
7807
-	b	.L1274
7808
-.L1279:
8303
+	mvn	r3, #75
8304
+	strb	r3, [r7, #1224]
8305
+	mvn	r3, #74
8306
+	strb	r3, [r7, #1225]
8307
+	mvn	r3, #73
8308
+	strb	r3, [r7, #1226]
8309
+	mvn	r3, #72
8310
+	strb	r3, [r7, #1227]
8311
+	mvn	r3, #43
8312
+	strb	r3, [r7, #1228]
8313
+	mvn	r3, #42
8314
+	strb	r3, [r7, #1229]
8315
+	mov	r6, #10
8316
+	b	.L1270
8317
+.L1275:
7809
8318
 	cmp	r0, #8
7810
8319
 	mov	r5, #7
7811
8320
 	bne	.L1334
7812
8321
 	mov	r3, #6
7813
-	strb	r5, [r7, #1215]
7814
-	strb	r3, [r7, #1214]
7815
-	mov	r5, #50
8322
+	strb	r5, [r7, #1221]
8323
+	strb	r3, [r7, #1220]
7816
8324
 	mov	r3, #9
7817
-	strb	r0, [r7, #1216]
7818
-	strb	r3, [r7, #1217]
7819
-	mov	r6, #5
8325
+	strb	r3, [r7, #1223]
7820
8326
 	mov	r3, #10
7821
-	strb	r3, [r7, #1218]
7822
-	b	.L1274
7823
-.L1334:
7824
-	mov	r6, #4
7825
-.L1274:
7826
-	sub	r3, r4, #1
7827
-	cmp	r3, #1
7828
-	bhi	.L1371
7829
-	ldr	r10, .L1381+8
7830
-	mov	r9, #0
7831
-.L1280:
7832
-	ldrb	r1, [r7, #2230]	@ zero_extendqisi2
7833
-	uxtb	r2, r9
7834
-	ldr	r3, .L1381
7835
-	cmp	r1, r2
7836
-	bls	.L1287
7837
-	add	r2, r3, r2
7838
-	ldr	r4, .L1381+12
7839
-	ldr	r1, .L1381+16
7840
-	mov	ip, #55
7841
-	ldrb	r2, [r2, #2232]	@ zero_extendqisi2
7842
-	add	r3, r3, r2, asl #3
7843
-	add	r4, r4, r2, asl #6
7844
-	add	r4, r4, #20
7845
-	ldrb	r8, [r3, #16]	@ zero_extendqisi2
7846
-	ldr	r0, [r3, #12]
7847
-	mov	fp, r4
7848
-	mov	r2, r4
7849
-	add	r8, r0, r8, asl #8
7850
-.L1282:
7851
-	str	ip, [r8, #2056]
7852
-	mov	r0, #80
7853
-	ldrb	r3, [r1, #1]!	@ zero_extendqisi2
7854
-	str	r2, [sp, #12]
7855
-	str	ip, [sp, #8]
7856
-	str	r3, [r8, #2052]
7857
-	str	r1, [sp, #4]
7858
-	str	r1, [sp, #16]
7859
-	bl	NandcDelayns
7860
-	ldr	r3, [r8, #2048]
7861
-	ldr	r2, [sp, #12]
7862
-	ldmib	sp, {r1, ip}
7863
-	strb	r3, [r2], #1
7864
-	rsb	r3, r4, r2
7865
-	uxtb	r3, r3
7866
-	cmp	r3, r6
7867
-	bcc	.L1282
7868
-	mov	r2, #0
8327
+	strb	r0, [r7, #1222]
8328
+	mov	r5, #50
8329
+	strb	r3, [r7, #1224]
8330
+	mov	r6, #5
8331
+	b	.L1270
7869
8332
 .L1283:
7870
-	add	r0, r10, r2
8333
+	add	r3, r7, r3
8334
+	mov	r8, #0
8335
+	ldrb	r3, [r3, #2236]	@ zero_extendqisi2
8336
+	mov	r1, #55
8337
+	ldr	r9, [r7, r3, lsl #3]
8338
+	add	r4, fp, r3, lsl #6
8339
+	add	r3, r7, r3, lsl #3
8340
+	ldrb	r3, [r3, #4]	@ zero_extendqisi2
8341
+	add	r4, r4, #20
8342
+	add	r9, r9, r3, lsl #8
8343
+.L1278:
8344
+	add	r3, fp, r8
8345
+	str	r1, [r9, #2056]
8346
+	ldrb	r3, [r3, #4]	@ zero_extendqisi2
8347
+	mov	r0, #80
8348
+	str	r2, [sp, #4]
8349
+	str	r1, [sp]
8350
+	str	r3, [r9, #2052]
8351
+	bl	ndelay
8352
+	ldr	r3, [r9, #2048]
8353
+	ldm	sp, {r1, r2}
8354
+	strb	r3, [r4, r8]
8355
+	add	r8, r8, #1
8356
+	uxtb	r3, r8
8357
+	cmp	r6, r3
8358
+	bhi	.L1278
8359
+	mov	r0, r4
8360
+	mov	r1, #0
8361
+.L1281:
7871
8362
 	mov	r3, #1
7872
-.L1284:
7873
-	ldrb	r1, [r0, r3, asl #2]	@ zero_extendqisi2
7874
-	ldrb	ip, [fp]	@ zero_extendqisi2
7875
-	add	r1, r1, ip
7876
-	strb	r1, [fp, r3, asl #3]
8363
+	add	lr, r2, r1
8364
+.L1280:
8365
+	ldrb	ip, [lr, r3, lsl #2]	@ zero_extendqisi2
8366
+	ldrb	r8, [r0]	@ zero_extendqisi2
8367
+	add	ip, ip, r8
8368
+	strb	ip, [r0, r3, lsl #3]
7877
8369
 	add	r3, r3, #1
7878
8370
 	cmp	r3, #7
7879
-	bne	.L1284
7880
-	add	r2, r2, #1
7881
-	add	fp, fp, #1
7882
-	cmp	r2, #4
7883
-	bne	.L1283
8371
+	bne	.L1280
8372
+	add	r1, r1, #1
8373
+	add	r0, r0, #1
8374
+	cmp	r1, #4
8375
+	bne	.L1281
7884
8376
 	mov	r3, #0
7885
-	add	r9, r9, #1
8377
+	add	r10, r10, #1
7886
8378
 	strb	r3, [r4, #16]
7887
8379
 	strb	r3, [r4, #24]
7888
8380
 	strb	r3, [r4, #32]
..
..
@@ -7890,102 +8382,71 @@
7890
8382
 	strb	r3, [r4, #48]
7891
8383
 	strb	r3, [r4, #41]
7892
8384
 	strb	r3, [r4, #49]
7893
-	b	.L1280
7894
-.L1371:
8385
+	b	.L1277
8386
+.L1276:
7895
8387
 	sub	r3, r4, #3
7896
8388
 	cmp	r3, #5
7897
-	bhi	.L1287
7898
-	smulbb	r2, r6, r5
7899
-	mov	r3, r2, asl #4
7900
-	mov	r2, r2, asr #1
7901
-	str	r3, [sp, #36]
7902
-	mov	r3, r2, asl #1
7903
-	str	r3, [sp, #8]
8389
+	bhi	.L1284
8390
+	smulbb	r3, r6, r5
8391
+	ldr	r8, .L1384
8392
+	asr	r2, r3, #1
8393
+	lsl	r3, r3, #4
8394
+	str	r3, [sp, #48]
8395
+	lsl	r3, r2, #2
8396
+	str	r2, [sp, #4]
8397
+	str	r3, [sp, #40]
8398
+	lsl	r3, r2, #1
8399
+	str	r3, [sp, #28]
7904
8400
 	mov	r3, #0
7905
-.L1379:
7906
-	str	r3, [sp, #16]
7907
-	ldrb	r3, [sp, #16]	@ zero_extendqisi2
7908
-	str	r3, [sp, #12]
7909
-	ldr	r3, .L1381
7910
-	ldr	r2, [sp, #12]
7911
-	ldrb	r3, [r3, #2230]	@ zero_extendqisi2
8401
+	str	r3, [sp, #24]
8402
+	add	r3, r8, #1216
8403
+	add	r3, r3, #28
8404
+	str	r3, [sp, #52]
8405
+.L1285:
8406
+	ldrb	r3, [sp, #24]	@ zero_extendqisi2
8407
+	str	r3, [sp, #8]
8408
+	ldr	r2, [sp, #8]
8409
+	ldrb	r3, [r8, #2234]	@ zero_extendqisi2
7912
8410
 	cmp	r3, r2
7913
-	bhi	.L1332
7914
-.L1287:
7915
-	ldr	r3, .L1381
7916
-	strb	r6, [r3, #1211]
7917
-	strb	r5, [r3, #1212]
7918
-	add	sp, sp, #44
7919
-	@ sp needed
7920
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
7921
-.L1332:
7922
-	ldr	r2, [sp, #12]
7923
-	ldr	r3, .L1381
7924
-	add	r3, r3, r2
7925
-	ldrb	r10, [r3, #2232]	@ zero_extendqisi2
7926
-	ldr	r3, .L1381
7927
-	add	r3, r3, r10, asl #3
7928
-	mov	r0, r10
7929
-	ldrb	fp, [r3, #16]	@ zero_extendqisi2
7930
-	ldr	r8, [r3, #12]
8411
+	bls	.L1284
8412
+	ldr	r3, [sp, #8]
8413
+	add	r3, r8, r3
8414
+	ldrb	r9, [r3, #2236]	@ zero_extendqisi2
8415
+	ldr	fp, [r8, r9, lsl #3]
8416
+	mov	r0, r9
8417
+	add	r3, r8, r9, lsl #3
8418
+	ldrb	r10, [r3, #4]	@ zero_extendqisi2
7931
8419
 	mov	r3, #255
7932
-	mov	r9, fp, asl #8
7933
-	add	r7, r8, r9
8420
+	add	r7, fp, r10, lsl #8
7934
8421
 	str	r3, [r7, #2056]
7935
8422
 	bl	NandcWaitFlashReady
7936
8423
 	cmp	r4, #7
7937
-	ldreq	r3, .L1381+12
7938
-	moveq	r7, #160
7939
-	mlaeq	r7, r7, r10, r3
7940
-	addeq	r3, r7, #28
7941
-	beq	.L1376
7942
-.L1289:
7943
-	cmp	r4, #8
7944
-	beq	.L1291
7945
-	ldr	r3, .L1381+12
7946
-	add	r7, r3, r10, asl #6
7947
-	add	r3, r7, #20
7948
-.L1376:
8424
+	bne	.L1286
8425
+	ldr	r3, .L1384+8
8426
+	mov	r0, #160
8427
+	mla	r0, r0, r9, r3
8428
+	add	r3, r0, #28
8429
+.L1380:
7949
8430
 	str	r3, [sp, #20]
7950
8431
 	cmp	r4, #4
7951
-	add	r3, r8, fp, asl #8
8432
+	add	r3, fp, r10, lsl #8
7952
8433
 	mov	r2, #54
7953
8434
 	str	r2, [r3, #2056]
7954
-	bne	.L1292
7955
-	add	r9, r8, r9
7956
-	mov	r3, #255
7957
-	str	r3, [r9, #2052]
7958
-	mov	r3, #64
7959
-	str	r3, [r9, #2048]
7960
-	mov	r3, #204
7961
-	b	.L1377
7962
-.L1292:
7963
-	sub	r2, r4, #5
7964
-	cmp	r2, #1
7965
-	bhi	.L1294
7966
-	ldr	r2, .L1381
7967
-	ldrb	r2, [r2, #1214]	@ zero_extendqisi2
8435
+	bne	.L1289
8436
+	mov	r2, #255
7968
8437
 	str	r2, [r3, #2052]
7969
-	mov	r2, #82
8438
+	mov	r2, #64
7970
8439
 	str	r2, [r3, #2048]
7971
-	b	.L1293
7972
-.L1294:
7973
-	cmp	r4, #7
7974
-	bne	.L1293
7975
-	add	r9, r8, r9
7976
-	mov	r3, #174
7977
-	str	r3, [r9, #2052]
7978
-	mov	r3, #0
7979
-	str	r3, [r9, #2048]
7980
-	mov	r3, #176
7981
-.L1377:
7982
-	str	r3, [r9, #2052]
7983
-	mov	r3, #77
7984
-	str	r3, [r9, #2048]
7985
-.L1293:
7986
-	add	r3, r8, fp, asl #8
7987
-	cmp	r4, #6
8440
+	mov	r2, #204
8441
+.L1381:
8442
+	str	r2, [r3, #2052]
8443
+	mov	r2, #77
8444
+.L1382:
8445
+	str	r2, [r3, #2048]
8446
+.L1290:
8447
+	add	r3, fp, r10, lsl #8
7988
8448
 	mov	r2, #22
8449
+	cmp	r4, #6
7989
8450
 	str	r2, [r3, #2056]
7990
8451
 	mov	r2, #23
7991
8452
 	str	r2, [r3, #2056]
..
..
@@ -8004,174 +8465,153 @@
8004
8465
 	mov	r2, #0
8005
8466
 	str	r2, [r3, #2052]
8006
8467
 .L1333:
8007
-	add	r3, r8, fp, asl #8
8468
+	add	r3, fp, r10, lsl #8
8008
8469
 	mov	r2, #48
8009
-	mov	r0, r10
8470
+	mov	r0, r9
8010
8471
 	str	r2, [r3, #2056]
8011
8472
 	bl	NandcWaitFlashReady
8012
8473
 	sub	r3, r4, #5
8013
-	cmp	r3, #1
8014
-	movhi	r3, #0
8015
-	movls	r3, #1
8016
-	str	r3, [sp, #24]
8017
-	sub	r3, r4, #8
8018
-	clz	r3, r3
8019
-	mov	r3, r3, lsr #5
8020
-	str	r3, [sp, #4]
8021
-	ldr	r2, [sp, #4]
8022
-	ldr	r3, [sp, #24]
8023
-	orrs	r3, r3, r2
8024
-	movne	ip, #16
8025
-	bne	.L1297
8474
+	cmp	r4, #8
8475
+	cmpne	r3, #1
8476
+	str	r3, [sp, #44]
8477
+	movls	r2, #16
8478
+	bls	.L1294
8026
8479
 	cmp	r4, #7
8027
-	movne	ip, #2
8028
-	moveq	ip, #32
8029
-.L1297:
8030
-	ldr	r3, .L1381+20
8031
-	add	r0, r8, fp, asl #8
8032
-	ldr	r3, [r3, #1688]
8033
-	mov	r1, r3
8034
-.L1298:
8035
-	ldr	r2, [r0, #2048]
8036
-	strb	r2, [r1], #1
8037
-	rsb	r2, r3, r1
8038
-	uxtb	r2, r2
8039
-	cmp	r2, ip
8040
-	bcc	.L1298
8041
-	ldr	r2, [sp, #4]
8042
-	cmp	r2, #0
8043
-	beq	.L1299
8480
+	moveq	r2, #32
8481
+	movne	r2, #2
8482
+.L1294:
8483
+	ldr	r3, .L1384+16
8484
+	sub	r2, r2, #1
8485
+	add	ip, fp, r10, lsl #8
8486
+	ldr	r3, [r3, #1696]
8487
+	str	ip, [sp]
8488
+	sub	r1, r3, #1
8489
+	uxtab	r2, r3, r2
8490
+	mov	r0, r1
8491
+.L1295:
8492
+	ldr	ip, [sp]
8493
+	ldr	ip, [ip, #2048]
8494
+	strb	ip, [r0, #1]!
8495
+	cmp	r2, r0
8496
+	bne	.L1295
8497
+	cmp	r4, #8
8498
+	bne	.L1296
8044
8499
 	mov	r2, #0
8045
-.L1301:
8046
-	ldrb	ip, [r3, r2, asl #2]	@ zero_extendqisi2
8500
+.L1298:
8501
+	ldrb	r0, [r3, r2, lsl #2]	@ zero_extendqisi2
8047
8502
 	uxtb	r1, r2
8048
-	cmp	ip, #50
8049
-	beq	.L1300
8050
-	add	ip, r3, r2, asl #2
8051
-	ldrb	ip, [ip, #1]	@ zero_extendqisi2
8052
-	cmp	ip, #5
8053
-	beq	.L1300
8503
+	cmp	r0, #50
8504
+	beq	.L1297
8505
+	add	r0, r3, r2, lsl #2
8506
+	ldrb	r0, [r0, #1]	@ zero_extendqisi2
8507
+	cmp	r0, #5
8508
+	beq	.L1297
8054
8509
 	add	r2, r2, #1
8055
8510
 	cmp	r2, #8
8056
-	bne	.L1301
8057
-	b	.L1302
8058
-.L1300:
8059
-	cmp	r1, #6
8060
-	bls	.L1303
8061
-.L1302:
8062
-	ldr	r0, .L1381+24
8063
-	mov	r1, #0
8064
-	bl	printk
8065
-.L1304:
8066
-	b	.L1304
8511
+	bne	.L1298
8067
8512
 .L1299:
8513
+	mov	r1, #0
8514
+	ldr	r0, .L1384+20
8515
+	bl	printk
8516
+.L1301:
8517
+	b	.L1301
8518
+.L1286:
8519
+	cmp	r4, #8
8520
+	beq	.L1288
8521
+	ldr	r3, .L1384+8
8522
+	add	r0, r3, r9, lsl #6
8523
+	add	r3, r0, #20
8524
+	b	.L1380
8525
+.L1289:
8526
+	sub	r2, r4, #5
8527
+	cmp	r2, #1
8528
+	ldrbls	r2, [r8, #1220]	@ zero_extendqisi2
8529
+	strls	r2, [r3, #2052]
8530
+	movls	r2, #82
8531
+	bls	.L1382
8068
8532
 	cmp	r4, #7
8069
-	bne	.L1305
8070
-	ldr	r2, [sp, #4]
8071
-.L1307:
8072
-	ldrb	ip, [r3, r2, asl #2]	@ zero_extendqisi2
8073
-	uxtb	r1, r2
8074
-	cmp	ip, #12
8075
-	beq	.L1306
8076
-	add	ip, r3, r2, asl #2
8077
-	ldrb	ip, [ip, #1]	@ zero_extendqisi2
8078
-	cmp	ip, #10
8079
-	beq	.L1306
8080
-	add	r2, r2, #1
8081
-	cmp	r2, #8
8082
-	bne	.L1307
8083
-	b	.L1308
8084
-.L1306:
8085
-	cmp	r1, #7
8086
-	bne	.L1303
8087
-.L1308:
8088
-	ldr	r0, .L1381+24
8089
-	mov	r1, #0
8090
-	bl	printk
8091
-.L1309:
8092
-	b	.L1309
8093
-.L1305:
8094
-	cmp	r4, #6
8095
-	bne	.L1303
8096
-	sub	r2, r3, #1
8097
-	add	r3, r3, #7
8098
-.L1310:
8099
-	ldrb	r1, [r2, #1]!	@ zero_extendqisi2
8100
-	cmp	r1, #12
8101
-	beq	.L1303
8102
-	ldrb	r1, [r2, #8]	@ zero_extendqisi2
8103
-	cmp	r1, #4
8104
-	beq	.L1303
8105
-	cmp	r2, r3
8106
-	bne	.L1310
8107
-	ldr	r0, .L1381+24
8108
-	mov	r1, #0
8109
-	bl	printk
8110
-.L1312:
8111
-	b	.L1312
8112
-.L1303:
8113
-	ldr	r1, .L1381+20
8114
-	ldr	ip, [sp, #36]
8115
-	ldr	r2, [r1, #1688]
8116
-	add	ip, r2, ip
8533
+	bne	.L1290
8534
+	mov	r2, #174
8535
+	str	r2, [r3, #2052]
8536
+	mov	r2, #0
8537
+	str	r2, [r3, #2048]
8538
+	mov	r2, #176
8539
+	b	.L1381
8540
+.L1297:
8541
+	cmp	r1, #6
8542
+	bhi	.L1299
8543
+.L1300:
8544
+	ldr	r1, .L1384+16
8545
+	ldr	r2, [r1, #1696]
8117
8546
 	mov	r3, r2
8547
+.L1310:
8548
+	ldr	ip, [sp, #48]
8549
+	sub	r0, r3, r2
8550
+	cmp	r0, ip
8551
+	blt	.L1311
8552
+	ldr	r3, [sp, #28]
8553
+	ldr	r1, [r1, #1696]
8554
+	add	r0, r1, r3
8555
+	mov	r3, #8
8118
8556
 .L1313:
8119
-	cmp	r3, ip
8120
-	ldrne	lr, [r0, #2048]
8121
-	strneb	lr, [r3], #1
8557
+	mov	lr, r0
8558
+	mov	ip, #0
8559
+.L1312:
8560
+	ldrh	r7, [lr]
8561
+	add	ip, ip, #1
8562
+	mvn	r7, r7
8563
+	strh	r7, [lr], #2	@ movhi
8564
+	ldr	r7, [sp, #4]
8565
+	cmp	r7, ip
8566
+	bgt	.L1312
8567
+	ldr	ip, [sp, #40]
8568
+	subs	r3, r3, #1
8569
+	add	r0, r0, ip
8122
8570
 	bne	.L1313
8123
-.L1380:
8124
-	ldr	r3, [r1, #1688]
8125
-	mov	r0, #8
8126
-	ldr	r1, [sp, #8]
8127
-	add	r1, r3, r1
8128
-	str	r1, [sp, #28]
8129
-.L1316:
8130
-	ldr	ip, [sp, #8]
8131
-	add	lr, r1, ip
8132
-.L1315:
8133
-	ldrh	ip, [r1]
8134
-	mvn	ip, ip
8135
-	strh	ip, [r1], #2	@ movhi
8136
-	cmp	r1, lr
8137
-	bne	.L1315
8138
-	ldr	ip, [sp, #8]
8139
-	subs	r0, r0, #1
8140
-	add	r1, r1, ip
8141
-	bne	.L1316
8142
-.L1317:
8571
+	str	r1, [sp, #12]
8572
+	str	r3, [sp, #16]
8573
+.L1319:
8143
8574
 	mov	ip, #0
8144
8575
 	mov	r0, ip
8145
-.L1320:
8146
-	mov	r1, #1
8147
-	mov	lr, #0
8148
-	mov	r1, r1, asl r0
8149
-	mov	r7, #16
8150
-	str	r7, [sp, #32]
8151
-	mov	r7, lr
8152
8576
 .L1318:
8153
-	ldrh	r9, [r3, lr]
8154
-	and	r9, r9, r1
8155
-	cmp	r9, r1
8577
+	mov	lr, #1
8578
+	mov	r7, #16
8579
+	lsl	lr, lr, r0
8580
+	str	r7, [sp, #36]
8581
+	mov	r7, #0
8582
+	str	lr, [sp, #32]
8583
+	ldr	lr, [sp, #12]
8584
+.L1316:
8585
+	ldrh	r3, [lr]
8586
+	mov	r1, r3
8587
+	ldr	r3, [sp, #32]
8588
+	bics	r3, r3, r1
8589
+	ldr	r3, [sp, #28]
8156
8590
 	addeq	r7, r7, #1
8157
-	ldr	r9, [sp, #8]
8158
-	add	lr, lr, r9
8159
-	ldr	r9, [sp, #32]
8160
-	subs	r9, r9, #1
8161
-	str	r9, [sp, #32]
8162
-	bne	.L1318
8591
+	add	lr, lr, r3
8592
+	ldr	r3, [sp, #36]
8593
+	subs	r3, r3, #1
8594
+	str	r3, [sp, #36]
8595
+	bne	.L1316
8163
8596
 	cmp	r7, #8
8164
8597
 	add	r0, r0, #1
8165
-	orrhi	ip, ip, r1
8598
+	ldrhi	r3, [sp, #32]
8599
+	orrhi	ip, ip, r3
8166
8600
 	uxthhi	ip, ip
8167
8601
 	cmp	r0, #16
8168
-	bne	.L1320
8169
-	ldr	r1, [sp, #28]
8602
+	bne	.L1318
8603
+	ldr	r3, [sp, #12]
8170
8604
 	strh	ip, [r3], #2	@ movhi
8605
+	str	r3, [sp, #12]
8606
+	ldr	r3, [sp, #16]
8607
+	add	r3, r3, #1
8608
+	str	r3, [sp, #16]
8609
+	ldr	r1, [sp, #16]
8610
+	ldr	r3, [sp, #4]
8171
8611
 	cmp	r3, r1
8172
-	bne	.L1317
8173
-	ldr	r3, .L1381+20
8174
-	ldr	r1, [r3, #1688]
8612
+	bgt	.L1319
8613
+	ldr	r3, .L1384+16
8614
+	ldr	r1, [r3, #1696]
8175
8615
 	mov	r3, #0
8176
8616
 	sub	r0, r1, #4
8177
8617
 	add	ip, r1, #28
..
..
@@ -8179,91 +8619,141 @@
8179
8619
 	ldr	lr, [r0, #4]!
8180
8620
 	cmp	lr, #0
8181
8621
 	addeq	r3, r3, #1
8182
-	cmp	r0, ip
8622
+	cmp	ip, r0
8183
8623
 	bne	.L1322
8184
8624
 	cmp	r3, #7
8185
8625
 	ble	.L1323
8186
-	ldr	r0, .L1381+28
8187
-	mov	r2, #1
8626
+	ldr	r0, .L1384+24
8188
8627
 	mov	r3, #1024
8628
+	mov	r2, #1
8189
8629
 	bl	rknand_print_hex
8190
-	ldr	r0, .L1381+24
8191
8630
 	mov	r1, #0
8631
+	ldr	r0, .L1384+20
8192
8632
 	bl	printk
8193
8633
 .L1324:
8194
8634
 	b	.L1324
8635
+.L1296:
8636
+	cmp	r4, #7
8637
+	bne	.L1302
8638
+	mov	r2, #0
8639
+.L1304:
8640
+	ldrb	r0, [r3, r2, lsl #2]	@ zero_extendqisi2
8641
+	uxtb	r1, r2
8642
+	cmp	r0, #12
8643
+	beq	.L1303
8644
+	add	r0, r3, r2, lsl #2
8645
+	ldrb	r0, [r0, #1]	@ zero_extendqisi2
8646
+	cmp	r0, #10
8647
+	beq	.L1303
8648
+	add	r2, r2, #1
8649
+	cmp	r2, #8
8650
+	bne	.L1304
8651
+.L1305:
8652
+	mov	r1, #0
8653
+	ldr	r0, .L1384+20
8654
+	bl	printk
8655
+.L1306:
8656
+	b	.L1306
8657
+.L1303:
8658
+	cmp	r1, #6
8659
+	bls	.L1300
8660
+	b	.L1305
8661
+.L1302:
8662
+	cmp	r4, #6
8663
+	bne	.L1300
8664
+	add	r3, r3, #7
8665
+.L1307:
8666
+	ldrb	r2, [r1, #1]!	@ zero_extendqisi2
8667
+	cmp	r2, #12
8668
+	beq	.L1300
8669
+	ldrb	r2, [r1, #8]	@ zero_extendqisi2
8670
+	cmp	r2, #4
8671
+	beq	.L1300
8672
+	cmp	r3, r1
8673
+	bne	.L1307
8674
+	mov	r1, #0
8675
+	ldr	r0, .L1384+20
8676
+	bl	printk
8677
+.L1309:
8678
+	b	.L1309
8679
+.L1311:
8680
+	ldr	r0, [sp]
8681
+	ldr	r0, [r0, #2048]
8682
+	strb	r0, [r3], #1
8683
+	b	.L1310
8195
8684
 .L1323:
8196
8685
 	cmp	r4, #6
8197
-	moveq	r0, #4
8686
+	moveq	ip, #4
8198
8687
 	beq	.L1325
8199
8688
 	cmp	r4, #7
8200
-	moveq	r0, #10
8689
+	moveq	ip, #10
8201
8690
 	beq	.L1325
8202
-	ldr	r3, [sp, #4]
8203
-	cmp	r3, #0
8204
-	moveq	r0, #8
8205
-	movne	r0, #5
8691
+	cmp	r4, #8
8692
+	moveq	ip, #5
8693
+	movne	ip, #8
8206
8694
 .L1325:
8207
-	sub	r9, r6, #1
8208
-	ldr	r1, [sp, #20]
8209
-	mov	ip, #0
8210
-	uxtb	r9, r9
8211
-	add	r9, r9, #1
8695
+	sub	r3, r6, #1
8696
+	ldr	r0, [sp, #20]
8697
+	uxtb	r3, r3
8698
+	mov	lr, #0
8699
+	add	r3, r3, #1
8700
+	str	r3, [sp, #12]
8212
8701
 .L1326:
8213
-	mov	r7, r1
8214
-	mov	r3, r2
8702
+	mov	r3, r0
8703
+	mov	r1, r2
8215
8704
 .L1327:
8216
-	ldrb	lr, [r3], #1	@ zero_extendqisi2
8217
-	strb	lr, [r7], #1
8218
-	rsb	lr, r2, r3
8219
-	uxtb	lr, lr
8220
-	cmp	lr, r6
8221
-	bcc	.L1327
8222
-	add	ip, ip, #1
8223
-	add	r2, r2, r9
8224
-	cmp	ip, r5
8225
-	add	r1, r1, r0
8226
-	blt	.L1326
8227
-	add	r7, r8, fp, asl #8
8705
+	ldrb	r7, [r1], #1	@ zero_extendqisi2
8706
+	strb	r7, [r3], #1
8707
+	sub	r7, r1, r2
8708
+	uxtb	r7, r7
8709
+	cmp	r6, r7
8710
+	bhi	.L1327
8711
+	ldr	r3, [sp, #12]
8712
+	add	lr, lr, #1
8713
+	cmp	r5, lr
8714
+	add	r0, r0, ip
8715
+	add	r2, r2, r3
8716
+	bgt	.L1326
8717
+	add	r10, fp, r10, lsl #8
8228
8718
 	mov	r3, #255
8229
-	mov	r0, r10
8230
-	str	r3, [r7, #2056]
8719
+	mov	r0, r9
8720
+	str	r3, [r10, #2056]
8721
+	bl	NandcWaitFlashReady
8722
+	ldr	r3, [sp, #44]
8723
+	cmp	r3, #1
8724
+	bhi	.L1329
8725
+	mov	r3, #54
8726
+	ldr	r2, [sp]
8727
+	str	r3, [r10, #2056]
8728
+	mvn	r1, #0
8729
+	ldrb	r3, [r8, #1220]	@ zero_extendqisi2
8730
+	ldr	r0, [sp, #8]
8731
+	str	r3, [r2, #2052]
8732
+	mov	r3, #0
8733
+	str	r3, [r2, #2048]
8734
+	mov	r3, #22
8735
+	str	r3, [r10, #2056]
8736
+	bl	FlashReadCmd
8737
+.L1330:
8738
+	mov	r0, r9
8231
8739
 	bl	NandcWaitFlashReady
8232
8740
 	ldr	r3, [sp, #24]
8233
-	cmp	r3, #0
8234
-	beq	.L1329
8235
-	mov	r3, #54
8236
-	str	r3, [r7, #2056]
8237
-	ldr	r3, .L1381
8238
-	mvn	r1, #0
8239
-	ldr	r0, [sp, #12]
8240
-	ldrb	r3, [r3, #1214]	@ zero_extendqisi2
8241
-	str	r3, [r7, #2052]
8242
-	mov	r3, #0
8243
-	str	r3, [r7, #2048]
8244
-	mov	r3, #22
8245
-	str	r3, [r7, #2056]
8246
-	bl	FlashReadCmd
8247
-	b	.L1330
8248
-.L1329:
8249
-	ldr	r3, [sp, #4]
8250
-	cmp	r3, #0
8251
-	movne	r3, #190
8252
-	moveq	r3, #56
8253
-	str	r3, [r7, #2056]
8254
-.L1330:
8255
-	mov	r0, r10
8256
-	bl	NandcWaitFlashReady
8257
-	ldr	r3, [sp, #16]
8258
8741
 	add	r3, r3, #1
8259
-	b	.L1379
8260
-.L1291:
8742
+	str	r3, [sp, #24]
8743
+	b	.L1285
8744
+.L1329:
8745
+	cmp	r4, #8
8746
+	moveq	r3, #190
8747
+	movne	r3, #56
8748
+	str	r3, [r10, #2056]
8749
+	b	.L1330
8750
+.L1288:
8261
8751
 	mov	r3, #120
8262
8752
 	mov	r2, #23
8263
8753
 	str	r3, [r7, #2056]
8264
-	mov	r1, #25
8265
8754
 	mov	r3, #0
8266
8755
 	str	r3, [r7, #2052]
8756
+	mov	r1, #25
8267
8757
 	str	r3, [r7, #2052]
8268
8758
 	str	r3, [r7, #2052]
8269
8759
 	str	r2, [r7, #2056]
..
..
@@ -8279,25 +8769,26 @@
8279
8769
 	str	r1, [r7, #2052]
8280
8770
 	str	r2, [r7, #2052]
8281
8771
 	str	r3, [r7, #2052]
8282
-	ldr	r3, .L1381+32
8772
+	ldr	r3, [sp, #52]
8283
8773
 	str	r3, [sp, #20]
8284
8774
 	b	.L1333
8285
-.L1382:
8775
+.L1385:
8286
8776
 	.align	2
8287
-.L1381:
8777
+.L1384:
8288
8778
 	.word	.LANCHOR0
8289
8779
 	.word	.LANCHOR1
8290
-	.word	.LANCHOR1+3388
8291
-	.word	.LANCHOR0+1210
8292
-	.word	.LANCHOR0+1213
8780
+	.word	.LANCHOR0+1216
8781
+	.word	.LANCHOR1+3384
8293
8782
 	.word	.LANCHOR2
8294
8783
 	.word	.LC85
8295
8784
 	.word	.LC86
8296
-	.word	.LANCHOR0+1238
8297
8785
 	.fnend
8298
8786
 	.size	HynixGetReadRetryDefault, .-HynixGetReadRetryDefault
8299
8787
 	.align	2
8300
8788
 	.global	FlashGetReadRetryDefault
8789
+	.syntax unified
8790
+	.arm
8791
+	.fpu softvfp
8301
8792
 	.type	FlashGetReadRetryDefault, %function
8302
8793
 FlashGetReadRetryDefault:
8303
8794
 	.fnstart
..
..
@@ -8308,226 +8799,227 @@
8308
8799
 	bxeq	lr
8309
8800
 	sub	r2, r3, #1
8310
8801
 	cmp	r2, #7
8311
-	bhi	.L1385
8802
+	bhi	.L1388
8312
8803
 	b	HynixGetReadRetryDefault
8313
-.L1385:
8804
+.L1388:
8314
8805
 	cmp	r3, #49
8315
-	bne	.L1386
8316
-	ldr	r2, .L1397
8317
-	ldr	r0, .L1397+4
8318
-	ldr	r1, .L1397+8
8319
-	strb	r3, [r2, #1210]
8806
+	bne	.L1389
8807
+	ldr	r2, .L1400
8808
+	ldr	r1, .L1400+4
8809
+	strb	r3, [r2, #1216]
8320
8810
 	mov	r3, #4
8321
-	strb	r3, [r2, #1211]
8811
+	strb	r3, [r2, #1217]
8322
8812
 	mov	r3, #15
8323
-	strb	r3, [r2, #1212]
8813
+	strb	r3, [r2, #1218]
8324
8814
 	mov	r2, #64
8325
-	b	.L1395
8326
-.L1386:
8815
+.L1398:
8816
+	ldr	r0, .L1400+8
8817
+	b	ftl_memcpy
8818
+.L1389:
8327
8819
 	sub	r2, r3, #65
8328
8820
 	cmp	r3, #33
8329
8821
 	cmpne	r2, #1
8330
-	ldrls	r2, .L1397
8331
-	strlsb	r3, [r2, #1210]
8332
-	movls	r3, #4
8333
-	bls	.L1396
8334
-.L1387:
8335
-	cmp	r3, #34
8336
-	cmpne	r3, #67
8337
-	bne	.L1388
8338
-	ldr	r2, .L1397
8339
-	strb	r3, [r2, #1210]
8340
-	mov	r3, #5
8341
-.L1396:
8342
-	strb	r3, [r2, #1211]
8822
+	bhi	.L1390
8823
+	ldr	r2, .L1400
8824
+	strb	r3, [r2, #1216]
8825
+	mov	r3, #4
8826
+.L1399:
8827
+	strb	r3, [r2, #1217]
8343
8828
 	mov	r3, #7
8344
-	ldr	r0, .L1397+4
8345
-	strb	r3, [r2, #1212]
8829
+	strb	r3, [r2, #1218]
8346
8830
 	mov	r2, #45
8347
-	ldr	r1, .L1397+12
8348
-	b	.L1395
8349
-.L1388:
8350
-	cmp	r3, #35
8351
-	cmpne	r3, #68
8831
+	ldr	r1, .L1400+12
8832
+	b	.L1398
8833
+.L1390:
8834
+	cmp	r3, #67
8835
+	cmpne	r3, #34
8836
+	ldreq	r2, .L1400
8837
+	strbeq	r3, [r2, #1216]
8838
+	moveq	r3, #5
8839
+	beq	.L1399
8840
+.L1391:
8841
+	cmp	r3, #68
8842
+	cmpne	r3, #35
8352
8843
 	bxne	lr
8353
-	ldr	r2, .L1397
8354
-	ldr	r0, .L1397+4
8355
-	ldr	r1, .L1397+16
8356
-	strb	r3, [r2, #1210]
8844
+	ldr	r2, .L1400
8845
+	ldr	r1, .L1400+16
8846
+	strb	r3, [r2, #1216]
8357
8847
 	mov	r3, #5
8358
-	strb	r3, [r2, #1211]
8848
+	strb	r3, [r2, #1217]
8359
8849
 	mov	r3, #17
8360
-	strb	r3, [r2, #1212]
8850
+	strb	r3, [r2, #1218]
8361
8851
 	mov	r2, #95
8362
-.L1395:
8363
-	b	ftl_memcpy
8364
-.L1398:
8852
+	b	.L1398
8853
+.L1401:
8365
8854
 	.align	2
8366
-.L1397:
8855
+.L1400:
8367
8856
 	.word	.LANCHOR0
8368
-	.word	.LANCHOR0+1214
8369
-	.word	.LANCHOR1+408
8857
+	.word	.LANCHOR1+404
8858
+	.word	.LANCHOR0+1220
8370
8859
 	.word	.LANCHOR1+256
8371
-	.word	.LANCHOR1+304
8860
+	.word	.LANCHOR1+301
8372
8861
 	.fnend
8373
8862
 	.size	FlashGetReadRetryDefault, .-FlashGetReadRetryDefault
8374
8863
 	.align	2
8375
8864
 	.global	NandcXferComp
8865
+	.syntax unified
8866
+	.arm
8867
+	.fpu softvfp
8376
8868
 	.type	NandcXferComp, %function
8377
8869
 NandcXferComp:
8378
8870
 	.fnstart
8379
8871
 	@ args = 0, pretend = 0, frame = 8
8380
8872
 	@ frame_needed = 0, uses_anonymous_args = 0
8381
-	stmfd	sp!, {r0, r1, r4, r5, r6, lr}
8382
-	.save {r4, r5, r6, lr}
8873
+	push	{r0, r1, r4, r5, r6, r7, r8, lr}
8874
+	.save {r4, r5, r6, r7, r8, lr}
8383
8875
 	.pad #8
8384
-	ldr	r5, .L1439
8385
-	add	r0, r5, r0, asl #3
8386
-	ldr	r3, [r5, #2260]
8387
-	ldr	r4, [r0, #12]
8876
+	ldr	r5, .L1442
8877
+	ldr	r3, [r5, #2264]
8878
+	ldr	r4, [r5, r0, lsl #3]
8388
8879
 	cmp	r3, #3
8389
-	bls	.L1430
8880
+	bls	.L1433
8390
8881
 	ldr	r3, [r4, #16]
8391
8882
 	tst	r3, #4
8392
-	beq	.L1430
8883
+	beq	.L1433
8393
8884
 	ldr	r6, [r4, #16]
8394
8885
 	ldr	r3, [r4, #8]
8395
8886
 	ubfx	r6, r6, #1, #1
8396
8887
 	cmp	r6, #0
8397
8888
 	str	r3, [sp]
8398
-	movne	r6, #0
8399
-	beq	.L1412
8400
-.L1402:
8889
+	beq	.L1404
8890
+	ldr	r7, .L1442+4
8891
+	mov	r6, #0
8892
+	ldr	r8, .L1442+8
8893
+.L1405:
8401
8894
 	ldr	r2, [r4, #28]
8402
8895
 	ldr	r3, [sp]
8403
8896
 	ubfx	r2, r2, #16, #5
8404
8897
 	ubfx	r3, r3, #22, #6
8405
8898
 	cmp	r2, r3
8406
-	bge	.L1410
8407
-	ldr	r3, [r5, #2260]
8899
+	bge	.L1413
8900
+	ldr	r3, [r5, #2264]
8408
8901
 	cmp	r3, #5
8409
-	bhi	.L1403
8410
-.L1406:
8902
+	bhi	.L1406
8903
+.L1409:
8411
8904
 	add	r6, r6, #1
8412
-	bic	r3, r6, #-16777216
8413
-	cmp	r3, #0
8414
-	bne	.L1405
8905
+	bics	r3, r6, #-16777216
8906
+	bne	.L1408
8415
8907
 	ldr	r2, [r4, #28]
8416
8908
 	mov	r1, r6
8417
8909
 	ldr	r3, [sp]
8910
+	mov	r0, r7
8418
8911
 	ubfx	r2, r2, #16, #5
8419
-	ldr	r0, .L1439+4
8420
8912
 	ubfx	r3, r3, #22, #6
8421
8913
 	bl	printk
8422
-	ldr	r0, .L1439+8
8423
-	mov	r1, r4
8424
-	mov	r2, #4
8425
8914
 	mov	r3, #512
8915
+	mov	r2, #4
8916
+	mov	r1, r4
8917
+	mov	r0, r8
8426
8918
 	bl	rknand_print_hex
8919
+.L1408:
8920
+	mov	r1, #5
8921
+	mov	r0, #1
8922
+	bl	usleep_range
8427
8923
 	b	.L1405
8428
-.L1403:
8924
+.L1406:
8429
8925
 	ldr	r3, [r4]
8430
8926
 	str	r3, [sp, #4]
8431
8927
 	ldr	r3, [sp, #4]
8432
8928
 	tst	r3, #8192
8433
-	beq	.L1406
8929
+	beq	.L1409
8434
8930
 	ldr	r3, [sp, #4]
8435
8931
 	tst	r3, #131072
8436
-	beq	.L1406
8437
-.L1410:
8438
-	ldr	r3, [r5, #2296]
8439
-	ldr	r4, .L1439
8932
+	beq	.L1409
8933
+.L1413:
8934
+	ldr	r3, [r5, #2300]
8440
8935
 	cmp	r3, #0
8441
-	beq	.L1411
8936
+	beq	.L1414
8442
8937
 	ldr	r1, [sp]
8443
8938
 	mov	r2, #0
8444
-	ldr	r0, [r4, #2288]
8939
+	ldr	r0, [r5, #2292]
8445
8940
 	ubfx	r1, r1, #22, #5
8446
-	mov	r1, r1, asl #10
8941
+	lsl	r1, r1, #10
8447
8942
 	bl	rknand_dma_unmap_single
8448
-	ldr	r0, [r4, #2292]
8449
-	mov	r2, #0
8450
8943
 	ldr	r1, [sp]
8944
+	mov	r2, #0
8945
+	ldr	r0, [r5, #2296]
8451
8946
 	ubfx	r1, r1, #22, #5
8452
-	mov	r1, r1, asl #7
8947
+	lsl	r1, r1, #7
8453
8948
 	bl	rknand_dma_unmap_single
8454
-	b	.L1411
8455
-.L1405:
8456
-	mov	r0, #1
8457
-	mov	r1, #5
8458
-	bl	usleep_range
8459
-	b	.L1402
8460
8949
 .L1414:
8950
+	mov	r3, #0
8951
+	str	r3, [r5, #2300]
8952
+.L1402:
8953
+	add	sp, sp, #8
8954
+	@ sp needed
8955
+	pop	{r4, r5, r6, r7, r8, pc}
8956
+.L1404:
8957
+	ldr	r7, .L1442+12
8958
+	ldr	r8, .L1442+8
8959
+.L1415:
8960
+	ldr	r3, [sp]
8961
+	tst	r3, #1048576
8962
+	beq	.L1417
8963
+	ldr	r3, [r5, #2308]
8964
+	cmp	r3, #0
8965
+	beq	.L1418
8966
+	mov	r0, r4
8967
+	bl	NandcSendDumpDataStart
8968
+.L1418:
8969
+	ldr	r3, [r5, #2300]
8970
+	cmp	r3, #0
8971
+	beq	.L1419
8972
+	ldr	r1, [sp]
8973
+	mov	r2, #1
8974
+	ldr	r0, [r5, #2292]
8975
+	ubfx	r1, r1, #22, #5
8976
+	lsl	r1, r1, #10
8977
+	bl	rknand_dma_unmap_single
8978
+	ldr	r1, [sp]
8979
+	mov	r2, #1
8980
+	ldr	r0, [r5, #2296]
8981
+	ubfx	r1, r1, #22, #5
8982
+	lsl	r1, r1, #7
8983
+	bl	rknand_dma_unmap_single
8984
+.L1419:
8985
+	ldr	r3, [r5, #2308]
8986
+	cmp	r3, #0
8987
+	beq	.L1414
8988
+	mov	r0, r4
8989
+	bl	NandcSendDumpDataDone
8990
+	b	.L1414
8991
+.L1417:
8461
8992
 	ldr	r3, [r4, #8]
8462
8993
 	add	r6, r6, #1
8463
8994
 	str	r3, [sp]
8464
-	bic	r3, r6, #-16777216
8465
-	cmp	r3, #0
8466
-	bne	.L1413
8995
+	bics	r3, r6, #-16777216
8996
+	bne	.L1416
8467
8997
 	ldr	r2, [sp]
8468
8998
 	mov	r1, r6
8469
8999
 	ldr	r3, [r4, #28]
8470
-	ldr	r0, .L1439+12
9000
+	mov	r0, r7
8471
9001
 	ubfx	r3, r3, #16, #5
8472
9002
 	bl	printk
8473
-	ldr	r0, .L1439+8
8474
-	mov	r1, r4
8475
-	mov	r2, #4
8476
9003
 	mov	r3, #512
9004
+	mov	r2, #4
9005
+	mov	r1, r4
9006
+	mov	r0, r8
8477
9007
 	bl	rknand_print_hex
8478
-.L1413:
8479
-	mov	r0, #1
8480
-	mov	r1, #5
8481
-	bl	usleep_range
8482
-.L1412:
8483
-	ldr	r3, [sp]
8484
-	tst	r3, #1048576
8485
-	beq	.L1414
8486
-	ldr	r3, [r5, #2304]
8487
-	cmp	r3, #0
8488
-	beq	.L1415
8489
-	mov	r0, r4
8490
-	bl	NandcSendDumpDataStart
8491
-.L1415:
8492
-	ldr	r3, [r5, #2296]
8493
-	ldr	r6, .L1439
8494
-	cmp	r3, #0
8495
-	beq	.L1416
8496
-	ldr	r1, [sp]
8497
-	mov	r2, #1
8498
-	ldr	r0, [r6, #2288]
8499
-	ubfx	r1, r1, #22, #5
8500
-	mov	r1, r1, asl #10
8501
-	bl	rknand_dma_unmap_single
8502
-	ldr	r0, [r6, #2292]
8503
-	mov	r2, #1
8504
-	ldr	r1, [sp]
8505
-	ubfx	r1, r1, #22, #5
8506
-	mov	r1, r1, asl #7
8507
-	bl	rknand_dma_unmap_single
8508
9008
 .L1416:
8509
-	ldr	r3, [r5, #2304]
8510
-	cmp	r3, #0
8511
-	beq	.L1411
8512
-	mov	r0, r4
8513
-	bl	NandcSendDumpDataDone
8514
-.L1411:
8515
-	mov	r3, #0
8516
-	str	r3, [r5, #2296]
8517
-	b	.L1399
8518
-.L1430:
9009
+	mov	r1, #5
9010
+	mov	r0, #1
9011
+	bl	usleep_range
9012
+	b	.L1415
9013
+.L1433:
8519
9014
 	ldr	r3, [r4, #8]
8520
9015
 	str	r3, [sp]
8521
9016
 	ldr	r3, [sp]
8522
9017
 	tst	r3, #1048576
8523
-	beq	.L1430
8524
-.L1399:
8525
-	add	sp, sp, #8
8526
-	@ sp needed
8527
-	ldmfd	sp!, {r4, r5, r6, pc}
8528
-.L1440:
9018
+	beq	.L1433
9019
+	b	.L1402
9020
+.L1443:
8529
9021
 	.align	2
8530
-.L1439:
9022
+.L1442:
8531
9023
 	.word	.LANCHOR0
8532
9024
 	.word	.LC87
8533
9025
 	.word	.LC88
..
..
@@ -8536,306 +9028,306 @@
8536
9028
 	.size	NandcXferComp, .-NandcXferComp
8537
9029
 	.align	2
8538
9030
 	.global	NandcXferData
9031
+	.syntax unified
9032
+	.arm
9033
+	.fpu softvfp
8539
9034
 	.type	NandcXferData, %function
8540
9035
 NandcXferData:
8541
9036
 	.fnstart
8542
9037
 	@ args = 4, pretend = 0, frame = 80
8543
9038
 	@ frame_needed = 0, uses_anonymous_args = 0
8544
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9039
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
8545
9040
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
8546
-	mov	r10, r3
8547
-	ldr	r6, .L1489
8548
-	tst	r10, #63
9041
+	tst	r3, #63
9042
+	ldr	r9, .L1484
8549
9043
 	.pad #92
8550
9044
 	sub	sp, sp, #92
8551
-	mov	r9, r0
8552
-	add	r3, r6, r0, asl #3
9045
+	mov	r7, r0
8553
9046
 	mov	r5, r1
8554
-	mov	r7, r2
8555
-	ldr	r8, [r3, #12]
8556
-	bne	.L1442
8557
-	ldr	r3, [sp, #128]
8558
-	cmp	r3, #0
8559
-	bne	.L1443
8560
-	add	r0, sp, #24
8561
-	mov	r1, #255
8562
-	mov	r2, #64
8563
-	bl	ftl_memset
8564
-	add	r3, sp, #24
8565
-	str	r3, [sp, #128]
8566
-.L1443:
8567
-	ldr	r3, [sp, #128]
8568
-	mov	r0, r9
8569
-	mov	r1, r5
8570
-	mov	r2, r7
8571
-	str	r10, [sp]
8572
-	str	r3, [sp, #4]
8573
-	mov	r3, #0
8574
-	bl	NandcXferStart
8575
-	mov	r0, r9
8576
-	mov	r1, r5
8577
-	bl	NandcXferComp
8578
-	cmp	r5, #0
8579
-	movne	fp, #0
8580
-	bne	.L1444
8581
-	ldr	r3, [r6, #2308]
8582
-	mov	r0, r7, lsr #1
8583
-	mov	r2, r5
8584
-	mov	r1, r5
8585
-	cmp	r3, #25
8586
-	ldr	r3, [sp, #128]
8587
-	movcc	lr, #64
8588
-	movcs	lr, #128
8589
-.L1446:
8590
-	cmp	r1, r0
8591
-	add	r3, r3, #4
8592
-	add	ip, r2, lr
8593
-	bcs	.L1487
8594
-	ldr	r4, [r6, #2276]
8595
-	mov	r2, r2, lsr #2
8596
-	add	r1, r1, #1
8597
-	ldr	r2, [r4, r2, asl #2]
8598
-	mov	r4, r2, lsr #8
8599
-	strb	r2, [r3, #-4]
8600
-	strb	r4, [r3, #-3]
8601
-	mov	r4, r2, lsr #16
8602
-	mov	r2, r2, lsr #24
8603
-	strb	r4, [r3, #-2]
8604
-	strb	r2, [r3, #-1]
8605
-	mov	r2, ip
8606
-	b	.L1446
8607
-.L1487:
8608
-	ldr	r0, [r6, #2308]
8609
-	mov	r2, #0
8610
-	ldr	r1, [r6, #2260]
8611
-	mov	r7, r7, lsr #2
8612
-	mov	fp, r2
8613
-.L1448:
8614
-	cmp	r2, r7
8615
-	bcs	.L1444
8616
-	cmp	r0, #0
8617
-	beq	.L1444
8618
-	add	r3, r2, #8
8619
-	ldr	r3, [r8, r3, asl #2]
8620
-	str	r3, [sp, #20]
8621
-	ldr	r3, [sp, #20]
8622
-	tst	r3, #4
8623
-	bne	.L1472
8624
-	ldr	r4, [sp, #20]
8625
-	ubfx	r4, r4, #15, #1
9047
+	str	r2, [sp, #8]
9048
+	mov	r8, r3
9049
+	ldr	r4, [sp, #128]
9050
+	ldr	r6, [r9, r0, lsl #3]
9051
+	bne	.L1445
8626
9052
 	cmp	r4, #0
8627
-	bne	.L1472
8628
-	cmp	r1, #5
8629
-	bls	.L1450
8630
-	ldr	ip, [sp, #20]
8631
-	ldr	r4, [sp, #20]
8632
-	ldr	r3, [sp, #20]
8633
-	ubfx	ip, ip, #3, #5
8634
-	ldr	lr, [sp, #20]
8635
-	ubfx	r4, r4, #27, #1
8636
-	ubfx	r3, r3, #16, #5
8637
-	ubfx	lr, lr, #29, #1
8638
-	orr	ip, ip, r4, asl #5
8639
-	orr	r3, r3, lr, asl #5
8640
-	cmp	ip, r3
8641
-	ldr	r3, [sp, #20]
8642
-	ldrhi	r4, [sp, #20]
8643
-	ubfxhi	r3, r3, #3, #5
8644
-	ldrls	r4, [sp, #20]
8645
-	ubfxls	r3, r3, #16, #5
8646
-	ubfxhi	r4, r4, #27, #1
8647
-	ubfxls	r4, r4, #29, #1
8648
-	b	.L1486
8649
-.L1450:
8650
-	cmp	r1, #3
8651
-	bls	.L1452
8652
-	ldr	ip, [sp, #20]
8653
-	ldr	r4, [sp, #20]
8654
-	ldr	r3, [sp, #20]
8655
-	ubfx	ip, ip, #3, #5
8656
-	ldr	lr, [sp, #20]
8657
-	ubfx	r4, r4, #28, #1
8658
-	ubfx	r3, r3, #16, #5
8659
-	ubfx	lr, lr, #30, #1
8660
-	orr	ip, ip, r4, asl #5
8661
-	orr	r3, r3, lr, asl #5
8662
-	cmp	ip, r3
8663
-	ldr	r3, [sp, #20]
8664
-	ldrhi	r4, [sp, #20]
8665
-	ubfxhi	r3, r3, #3, #5
8666
-	ldrls	r4, [sp, #20]
8667
-	ubfxls	r3, r3, #16, #5
8668
-	ubfxhi	r4, r4, #28, #1
8669
-	ubfxls	r4, r4, #30, #1
8670
-.L1486:
8671
-	orr	r4, r3, r4, asl #5
8672
-.L1452:
8673
-	cmp	fp, r4
8674
-	movcc	fp, r4
8675
-	b	.L1449
8676
-.L1472:
8677
-	mvn	fp, #0
8678
-.L1449:
8679
-	add	r2, r2, #1
8680
-	b	.L1448
8681
-.L1444:
9053
+	bne	.L1446
9054
+	mov	r2, #64
9055
+	mov	r1, #255
9056
+	add	r0, sp, #24
9057
+	bl	ftl_memset
9058
+	add	r4, sp, #24
9059
+.L1446:
8682
9060
 	mov	r3, #0
8683
-	str	r3, [r8, #16]
8684
-	b	.L1455
8685
-.L1442:
8686
-	cmp	r1, #1
8687
-	mov	r4, #0
8688
-	bne	.L1484
8689
-	mov	fp, r4
8690
-.L1456:
8691
-	cmp	r4, r7
8692
-	bcs	.L1488
8693
-	ldr	r2, [sp, #128]
8694
-	cmp	r10, #0
8695
-	addne	r3, r10, r4, asl #9
8696
-	ldr	r1, [sp, #128]
8697
-	moveq	r3, r10
8698
-	cmp	r2, #0
8699
-	and	ip, r4, #3
8700
-	mov	r0, r8
8701
-	movne	r2, #2
8702
-	moveq	r2, #0
8703
-	mla	r2, r4, r2, r1
8704
-	mov	r1, #1
8705
-	str	ip, [sp, #8]
8706
-	add	r4, r4, #2
8707
-	str	r2, [sp]
8708
-	mov	r2, ip
8709
-	bl	NandcCopy1KB
8710
-	mov	r0, r9
8711
-	mov	r1, #1
8712
-	mov	r2, #2
8713
-	ldr	ip, [sp, #8]
8714
-	str	fp, [sp]
8715
-	str	fp, [sp, #4]
8716
-	mov	r3, ip
8717
-	bl	NandcXferStart
8718
-	mov	r0, r9
8719
-	mov	r1, #1
8720
-	bl	NandcXferComp
8721
-	b	.L1456
8722
-.L1488:
8723
-	mov	fp, #0
8724
-	b	.L1455
8725
-.L1484:
8726
-	str	r4, [sp]
8727
-	mov	r1, r4
8728
-	str	r4, [sp, #4]
8729
-	mov	r2, #2
8730
-	mov	r3, r4
8731
-	mov	fp, r4
8732
-	bl	NandcXferStart
8733
-	str	r10, [sp, #8]
8734
-.L1461:
8735
-	cmp	r4, r7
8736
-	bcs	.L1455
8737
-	mov	r0, r9
9061
+	ldr	r2, [sp, #8]
8738
9062
 	mov	r1, r5
8739
-	bl	NandcXferComp
8740
-	ldr	r3, [r8, #32]
8741
-	add	ip, r4, #2
8742
-	cmp	ip, r7
8743
-	str	r3, [sp, #20]
8744
-	bcs	.L1462
8745
-	mov	r3, #0
8746
-	mov	r0, r9
8747
-	str	r3, [sp]
8748
-	mov	r1, r3
8749
-	str	r3, [sp, #4]
8750
-	mov	r2, #2
8751
-	and	r3, ip, #3
8752
-	str	ip, [sp, #12]
9063
+	mov	r0, r7
9064
+	str	r4, [sp, #4]
9065
+	str	r8, [sp]
8753
9066
 	bl	NandcXferStart
8754
-	ldr	ip, [sp, #12]
8755
-.L1462:
8756
-	ldr	r3, [sp, #20]
8757
-	tst	r3, #4
8758
-	mvnne	fp, #0
8759
-	bne	.L1463
8760
-	ldr	r2, [sp, #20]
8761
-	ldr	r3, [sp, #20]
8762
-	ubfx	r2, r2, #3, #5
8763
-	ubfx	r3, r3, #27, #1
8764
-	orr	r3, r2, r3, asl #5
8765
-	cmp	fp, r3
8766
-	movcc	fp, r3
8767
-.L1463:
8768
-	ldr	r1, [sp, #128]
8769
-	cmp	r10, #0
8770
-	ldr	r3, [sp, #8]
8771
-	sub	r2, ip, #2
8772
-	moveq	r3, #0
8773
-	ldr	r0, [sp, #128]
8774
-	cmp	r1, #0
8775
-	and	r2, r2, #3
8776
-	str	ip, [sp, #12]
8777
-	movne	r1, #2
8778
-	moveq	r1, #0
8779
-	mla	r4, r4, r1, r0
8780
-	mov	r0, r8
8781
-	mov	r1, #0
8782
-	str	r4, [sp]
8783
-	bl	NandcCopy1KB
8784
-	ldr	ip, [sp, #12]
8785
-	ldr	r3, [sp, #8]
8786
-	mov	r4, ip
8787
-	add	r3, r3, #1024
8788
-	str	r3, [sp, #8]
8789
-	b	.L1461
8790
-.L1455:
8791
-	ldr	r3, [r6, #2260]
8792
-	clz	r5, r5
8793
-	cmp	r3, #5
8794
-	mov	r5, r5, lsr #5
8795
-	movls	r5, #0
9067
+	mov	r1, r5
9068
+	mov	r0, r7
9069
+	bl	NandcXferComp
8796
9070
 	cmp	r5, #0
8797
-	beq	.L1467
8798
-	ldr	r3, [r8]
9071
+	movne	r9, #0
9072
+	bne	.L1447
9073
+	ldr	r3, [r9, #2312]
9074
+	mov	r2, r5
9075
+	cmp	r3, #25
9076
+	ldr	r3, [sp, #8]
9077
+	movcc	ip, #64
9078
+	movcs	ip, #128
9079
+	lsr	r1, r3, #1
9080
+	mov	r3, r5
9081
+.L1449:
9082
+	cmp	r2, r1
9083
+	add	r4, r4, #4
9084
+	add	r0, ip, r3
9085
+	bcc	.L1450
9086
+	ldr	r3, [sp, #8]
9087
+	mov	r2, #0
9088
+	ldr	r1, [r9, #2312]
9089
+	ldr	ip, [r9, #2264]
9090
+	mov	r9, r2
9091
+	lsr	r0, r3, #2
9092
+.L1451:
9093
+	cmp	r2, r0
9094
+	bcs	.L1447
9095
+	cmp	r1, #0
9096
+	bne	.L1457
9097
+.L1447:
9098
+	mov	r3, #0
9099
+	str	r3, [r6, #16]
9100
+.L1458:
9101
+	ldr	r3, .L1484
9102
+	ldr	r3, [r3, #2264]
9103
+	cmp	r3, #5
9104
+	movls	r3, #0
9105
+	movhi	r3, #1
9106
+	cmp	r5, #0
9107
+	movne	r3, #0
9108
+	cmp	r3, #0
9109
+	beq	.L1444
9110
+	ldr	r3, [r6]
8799
9111
 	and	r2, r3, #139264
8800
9112
 	cmp	r2, #139264
9113
+	mvneq	r9, #0
8801
9114
 	orreq	r3, r3, #131072
8802
-	streq	r3, [r8]
8803
-	mvneq	fp, #0
8804
-.L1467:
8805
-	mov	r0, fp
9115
+	streq	r3, [r6]
9116
+.L1444:
9117
+	mov	r0, r9
8806
9118
 	add	sp, sp, #92
8807
9119
 	@ sp needed
8808
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
8809
-.L1490:
9120
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
9121
+.L1450:
9122
+	ldr	lr, [r9, #2280]
9123
+	bic	r3, r3, #3
9124
+	add	r2, r2, #1
9125
+	ldr	r3, [lr, r3]
9126
+	strb	r3, [r4, #-4]
9127
+	lsr	lr, r3, #8
9128
+	strb	lr, [r4, #-3]
9129
+	lsr	lr, r3, #16
9130
+	lsr	r3, r3, #24
9131
+	strb	lr, [r4, #-2]
9132
+	strb	r3, [r4, #-1]
9133
+	mov	r3, r0
9134
+	b	.L1449
9135
+.L1457:
9136
+	add	r3, r2, #8
9137
+	ldr	r3, [r6, r3, lsl #2]
9138
+	str	r3, [sp, #20]
9139
+	ldr	r3, [sp, #20]
9140
+	tst	r3, #4
9141
+	bne	.L1473
9142
+	ldr	r3, [sp, #20]
9143
+	ubfx	r3, r3, #15, #1
9144
+	cmp	r3, #0
9145
+	bne	.L1473
9146
+	cmp	ip, #5
9147
+	bls	.L1453
9148
+	ldr	lr, [sp, #20]
9149
+	ldr	r7, [sp, #20]
9150
+	ldr	r3, [sp, #20]
9151
+	ldr	r4, [sp, #20]
9152
+	ubfx	lr, lr, #3, #5
9153
+	ubfx	r7, r7, #27, #1
9154
+	ubfx	r3, r3, #16, #5
9155
+	orr	lr, lr, r7, lsl #5
9156
+	ubfx	r4, r4, #29, #1
9157
+	orr	r3, r3, r4, lsl #5
9158
+	cmp	lr, r3
9159
+	ldr	r3, [sp, #20]
9160
+	ldrhi	lr, [sp, #20]
9161
+	ldrls	lr, [sp, #20]
9162
+	ubfxhi	r3, r3, #3, #5
9163
+	ubfxls	r3, r3, #16, #5
9164
+	ubfxhi	lr, lr, #27, #1
9165
+	ubfxls	lr, lr, #29, #1
9166
+.L1483:
9167
+	orr	r3, r3, lr, lsl #5
9168
+.L1455:
9169
+	cmp	r9, r3
9170
+	movcc	r9, r3
9171
+.L1452:
9172
+	add	r2, r2, #1
9173
+	b	.L1451
9174
+.L1453:
9175
+	cmp	ip, #3
9176
+	bls	.L1455
9177
+	ldr	lr, [sp, #20]
9178
+	ldr	r7, [sp, #20]
9179
+	ldr	r3, [sp, #20]
9180
+	ldr	r4, [sp, #20]
9181
+	ubfx	lr, lr, #3, #5
9182
+	ubfx	r7, r7, #28, #1
9183
+	ubfx	r3, r3, #16, #5
9184
+	orr	lr, lr, r7, lsl #5
9185
+	ubfx	r4, r4, #30, #1
9186
+	orr	r3, r3, r4, lsl #5
9187
+	cmp	lr, r3
9188
+	ldr	r3, [sp, #20]
9189
+	ldrhi	lr, [sp, #20]
9190
+	ldrls	lr, [sp, #20]
9191
+	ubfxhi	r3, r3, #3, #5
9192
+	ubfxls	r3, r3, #16, #5
9193
+	ubfxhi	lr, lr, #28, #1
9194
+	ubfxls	lr, lr, #30, #1
9195
+	b	.L1483
9196
+.L1473:
9197
+	mvn	r9, #0
9198
+	b	.L1452
9199
+.L1445:
9200
+	cmp	r1, #1
9201
+	bne	.L1459
9202
+	mov	r9, #0
9203
+	cmp	r4, #0
9204
+	mov	r10, r9
9205
+	movne	r3, #4
9206
+	moveq	r3, #0
9207
+	str	r3, [sp, #12]
9208
+.L1460:
9209
+	ldr	r3, [sp, #8]
9210
+	cmp	r9, r3
9211
+	movcs	r9, #0
9212
+	bcs	.L1458
9213
+.L1462:
9214
+	cmp	r8, #0
9215
+	and	fp, r9, #3
9216
+	addne	r3, r8, r9, lsl #9
9217
+	moveq	r3, r8
9218
+	str	r4, [sp]
9219
+	mov	r2, fp
9220
+	mov	r1, #1
9221
+	mov	r0, r6
9222
+	bl	NandcCopy1KB
9223
+	mov	r3, fp
9224
+	mov	r2, #2
9225
+	mov	r1, #1
9226
+	mov	r0, r7
9227
+	str	r10, [sp, #4]
9228
+	add	r9, r9, #2
9229
+	str	r10, [sp]
9230
+	bl	NandcXferStart
9231
+	mov	r1, #1
9232
+	mov	r0, r7
9233
+	bl	NandcXferComp
9234
+	ldr	r3, [sp, #12]
9235
+	add	r4, r4, r3
9236
+	b	.L1460
9237
+.L1459:
9238
+	mov	r10, #0
9239
+	mov	r2, #2
9240
+	mov	r3, r10
9241
+	str	r10, [sp, #4]
9242
+	str	r10, [sp]
9243
+	mov	r1, r10
9244
+	bl	NandcXferStart
9245
+	mov	fp, r8
9246
+	cmp	r4, r10
9247
+	mov	r9, r10
9248
+	movne	r3, #4
9249
+	moveq	r3, r10
9250
+	str	r3, [sp, #12]
9251
+.L1463:
9252
+	ldr	r3, [sp, #8]
9253
+	cmp	r10, r3
9254
+	bcs	.L1458
9255
+	mov	r1, r5
9256
+	mov	r0, r7
9257
+	bl	NandcXferComp
9258
+	ldr	r3, [r6, #32]
9259
+	add	r10, r10, #2
9260
+	str	r3, [sp, #20]
9261
+	ldr	r3, [sp, #8]
9262
+	cmp	r3, r10
9263
+	bls	.L1464
9264
+	mov	r3, #0
9265
+	mov	r2, #2
9266
+	str	r3, [sp, #4]
9267
+	mov	r1, #0
9268
+	str	r3, [sp]
9269
+	mov	r0, r7
9270
+	and	r3, r10, #3
9271
+	bl	NandcXferStart
9272
+.L1464:
9273
+	ldr	r3, [sp, #20]
9274
+	tst	r3, #4
9275
+	mvnne	r9, #0
9276
+	bne	.L1465
9277
+	ldr	r3, [sp, #20]
9278
+	ldr	r2, [sp, #20]
9279
+	ubfx	r3, r3, #3, #5
9280
+	ubfx	r2, r2, #27, #1
9281
+	orr	r3, r3, r2, lsl #5
9282
+	cmp	r9, r3
9283
+	movcc	r9, r3
9284
+.L1465:
9285
+	cmp	r8, #0
9286
+	sub	r2, r10, #2
9287
+	movne	r3, fp
9288
+	str	r4, [sp]
9289
+	moveq	r3, #0
9290
+	and	r2, r2, #3
9291
+	mov	r1, #0
9292
+	mov	r0, r6
9293
+	bl	NandcCopy1KB
9294
+	ldr	r3, [sp, #12]
9295
+	add	fp, fp, #1024
9296
+	add	r4, r4, r3
9297
+	b	.L1463
9298
+.L1485:
8810
9299
 	.align	2
8811
-.L1489:
9300
+.L1484:
8812
9301
 	.word	.LANCHOR0
8813
9302
 	.fnend
8814
9303
 	.size	NandcXferData, .-NandcXferData
8815
9304
 	.align	2
8816
9305
 	.global	FlashReadRawPage
9306
+	.syntax unified
9307
+	.arm
9308
+	.fpu softvfp
8817
9309
 	.type	FlashReadRawPage, %function
8818
9310
 FlashReadRawPage:
8819
9311
 	.fnstart
8820
9312
 	@ args = 0, pretend = 0, frame = 0
8821
9313
 	@ frame_needed = 0, uses_anonymous_args = 0
8822
-	stmfd	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
9314
+	push	{r0, r1, r4, r5, r6, r7, r8, lr}
8823
9315
 	.save {r4, r5, r6, r7, r8, lr}
8824
9316
 	.pad #8
8825
9317
 	mov	r8, r3
8826
-	ldr	r3, .L1494
9318
+	ldr	r3, .L1489
8827
9319
 	subs	r4, r0, #0
8828
9320
 	mov	r6, r1
8829
9321
 	mov	r7, r2
8830
-	ldrb	r5, [r3, #481]	@ zero_extendqisi2
8831
-	bne	.L1492
8832
-	ldr	r2, .L1494+4
8833
-	ldrb	r3, [r2, #1]	@ zero_extendqisi2
8834
-	ldr	r2, [r2, #4]
8835
-	mul	r2, r2, r3
8836
-	cmp	r1, r2
8837
-	movcc	r5, #4
8838
-.L1492:
9322
+	ldrb	r5, [r3, #477]	@ zero_extendqisi2
9323
+	bne	.L1487
9324
+	ldr	r1, .L1489+4
9325
+	ldrb	r3, [r1, #37]	@ zero_extendqisi2
9326
+	ldr	r0, [r1, #40]
9327
+	mul	r0, r0, r3
9328
+	cmp	r0, r6
9329
+	movhi	r5, #4
9330
+.L1487:
8839
9331
 	mov	r0, r4
8840
9332
 	bl	NandcWaitFlashReady
8841
9333
 	mov	r0, r4
..
..
@@ -8845,181 +9337,177 @@
8845
9337
 	bl	FlashReadCmd
8846
9338
 	mov	r0, r4
8847
9339
 	bl	NandcWaitFlashReady
8848
-	mov	r2, r5
8849
-	mov	r1, #0
8850
9340
 	mov	r3, r7
8851
-	mov	r0, r4
9341
+	mov	r2, r5
8852
9342
 	str	r8, [sp]
9343
+	mov	r1, #0
9344
+	mov	r0, r4
8853
9345
 	bl	NandcXferData
8854
-	mov	r5, r0
9346
+	mov	r1, r0
8855
9347
 	mov	r0, r4
8856
9348
 	bl	NandcFlashDeCs
8857
-	mov	r0, r5
9349
+	mov	r0, r1
8858
9350
 	add	sp, sp, #8
8859
9351
 	@ sp needed
8860
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
8861
-.L1495:
9352
+	pop	{r4, r5, r6, r7, r8, pc}
9353
+.L1490:
8862
9354
 	.align	2
8863
-.L1494:
9355
+.L1489:
8864
9356
 	.word	.LANCHOR1
8865
9357
 	.word	.LANCHOR0
8866
9358
 	.fnend
8867
9359
 	.size	FlashReadRawPage, .-FlashReadRawPage
8868
9360
 	.align	2
8869
9361
 	.global	FlashDdrTunningRead
9362
+	.syntax unified
9363
+	.arm
9364
+	.fpu softvfp
8870
9365
 	.type	FlashDdrTunningRead, %function
8871
9366
 FlashDdrTunningRead:
8872
9367
 	.fnstart
8873
9368
 	@ args = 4, pretend = 0, frame = 16
8874
9369
 	@ frame_needed = 0, uses_anonymous_args = 0
8875
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9370
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
8876
9371
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
8877
9372
 	mov	r7, r3
8878
-	ldr	r4, .L1523
9373
+	ldr	r4, .L1517
8879
9374
 	.pad #20
8880
9375
 	sub	sp, sp, #20
8881
-	mov	r10, r0
8882
9376
 	mov	fp, r2
8883
-	str	r1, [sp]
8884
-	ldr	r3, [r4, #80]
9377
+	stm	sp, {r0, r1}
9378
+	ldr	r3, [r4, #88]
8885
9379
 	ldr	r3, [r3, #304]
8886
-	str	r3, [sp, #8]
8887
-	ldr	r3, [r4, #2260]
9380
+	str	r3, [sp, #12]
9381
+	ldr	r3, [r4, #2264]
8888
9382
 	cmp	r3, #8
8889
9383
 	ldr	r3, [sp, #56]
8890
-	movcc	r9, #6
8891
-	movcs	r9, #12
9384
+	movcc	r10, #6
9385
+	movcs	r10, #12
8892
9386
 	cmp	r3, #0
8893
-	moveq	r6, #1024
8894
-	beq	.L1498
9387
+	moveq	r5, #1024
9388
+	beq	.L1493
8895
9389
 	mov	r0, #1
8896
9390
 	bl	FlashSetInterfaceMode
8897
9391
 	mov	r0, #1
8898
9392
 	bl	NandcSetMode
8899
-	mov	r0, r10
9393
+	ldr	r0, [sp]
8900
9394
 	bl	FlashReset
8901
-	mov	r2, fp
8902
9395
 	mov	r3, r7
8903
-	mov	r0, r10
8904
-	ldr	r1, [sp]
9396
+	mov	r2, fp
9397
+	ldm	sp, {r0, r1}
8905
9398
 	bl	FlashReadRawPage
8906
-	mov	r6, r0
8907
-	ldrb	r0, [r4, #2229]	@ zero_extendqisi2
9399
+	mov	r5, r0
9400
+	ldrb	r0, [r4, #2233]	@ zero_extendqisi2
8908
9401
 	bl	FlashSetInterfaceMode
8909
-	ldrb	r0, [r4, #2229]	@ zero_extendqisi2
9402
+	ldrb	r0, [r4, #2233]	@ zero_extendqisi2
8910
9403
 	bl	NandcSetMode
8911
-	cmn	r6, #1
8912
-	bne	.L1499
8913
-.L1508:
8914
-	mvn	r6, #0
8915
-	b	.L1500
8916
-.L1499:
8917
-	mov	r2, r6
8918
-	ldr	r0, .L1523+4
8919
-	ldr	r1, [sp]
9404
+	cmn	r5, #1
9405
+	bne	.L1494
9406
+.L1503:
9407
+	mvn	r5, #0
9408
+.L1491:
9409
+	mov	r0, r5
9410
+	add	sp, sp, #20
9411
+	@ sp needed
9412
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
9413
+.L1494:
9414
+	mov	r2, r5
9415
+	ldr	r1, [sp, #4]
9416
+	ldr	r0, .L1517+4
8920
9417
 	bl	printk
8921
-	cmp	r6, #9
8922
-	addls	r4, r4, r10, asl #3
8923
-	ldrls	r3, [r4, #12]
8924
-	ldr	r4, .L1523+8
9418
+	cmp	r5, #9
9419
+	ldrls	r3, [sp]
9420
+	ldrls	r3, [r4, r3, lsl #3]
8925
9421
 	ldrls	r2, [r3, #3840]
8926
9422
 	ldrls	r2, [r3]
8927
9423
 	orrls	r2, r2, #131072
8928
9424
 	strls	r2, [r3]
8929
-	ldr	r3, [r4, #1692]
9425
+	ldr	r2, .L1517+8
9426
+	ldr	r3, [r2, #1700]
8930
9427
 	add	r3, r3, #1
8931
-	str	r3, [r4, #1692]
8932
9428
 	cmp	r3, #2048
9429
+	str	r3, [r2, #1700]
8933
9430
 	movcs	r7, #0
8934
-	strcs	r7, [r4, #1692]
9431
+	strcs	r7, [r2, #1700]
8935
9432
 	movcs	fp, r7
8936
-	bcc	.L1500
8937
-.L1498:
8938
-	mov	r4, #0
9433
+	bcc	.L1491
9434
+.L1493:
9435
+	mov	r9, #0
8939
9436
 	mvn	r8, #0
8940
-	mov	ip, r4
8941
-	mov	r5, r4
8942
-	str	r4, [sp, #4]
8943
-.L1506:
8944
-	uxtb	r0, r9
8945
-	str	ip, [sp, #12]
9437
+	mov	r6, r9
9438
+	mov	r4, r9
9439
+	str	r9, [sp, #8]
9440
+.L1501:
9441
+	uxtb	r0, r10
8946
9442
 	bl	NandcSetDdrPara
8947
9443
 	mov	r3, r7
8948
-	mov	r0, r10
8949
9444
 	mov	r2, fp
8950
-	ldr	r1, [sp]
9445
+	ldm	sp, {r0, r1}
8951
9446
 	bl	FlashReadRawPage
8952
-	add	r3, r6, #1
9447
+	add	r3, r5, #1
8953
9448
 	cmp	r0, r3
8954
-	ldr	ip, [sp, #12]
8955
-	bhi	.L1502
9449
+	bhi	.L1497
8956
9450
 	cmp	r0, #2
8957
-	bhi	.L1512
8958
-	add	r5, r5, #1
8959
-	cmp	r5, #9
8960
-	bls	.L1512
8961
-	rsb	r4, r5, r9
8962
-	mov	r6, r0
9451
+	bhi	.L1507
9452
+	add	r4, r4, #1
9453
+	cmp	r4, #9
9454
+	bls	.L1507
9455
+	mov	r3, r6
9456
+	mov	r5, r0
9457
+	sub	r6, r10, r4
8963
9458
 	mov	r8, #0
8964
-	b	.L1504
8965
-.L1502:
8966
-	ldr	r3, [sp, #4]
8967
-	cmp	r3, r5
8968
-	bcs	.L1513
8969
-	cmp	r5, #7
8970
-	rsb	ip, r5, r4
8971
-	bhi	.L1514
8972
-	str	r5, [sp, #4]
8973
-	b	.L1513
8974
-.L1512:
8975
-	mov	r8, #0
8976
-	mov	r4, r9
8977
-	mov	r6, r0
8978
-	mov	r7, r8
8979
-	mov	fp, r8
8980
-	b	.L1503
8981
-.L1513:
8982
-	mov	r5, #0
8983
-.L1503:
8984
-	add	r9, r9, #2
8985
-	cmp	r9, #69
8986
-	bls	.L1506
8987
-.L1504:
8988
-	ldr	r3, [sp, #4]
8989
-	cmp	r3, r5
8990
-	movcs	r4, ip
8991
-	b	.L1505
8992
-.L1514:
8993
-	mov	r4, ip
8994
-.L1505:
8995
-	cmp	r4, #0
8996
-	beq	.L1507
8997
-	ldr	r0, .L1523+12
8998
-	mov	r1, r4
9459
+.L1499:
9460
+	ldr	r2, [sp, #8]
9461
+	cmp	r4, r2
9462
+	movls	r6, r3
9463
+.L1500:
9464
+	cmp	r6, #0
9465
+	beq	.L1502
9466
+	mov	r1, r6
9467
+	ldr	r0, .L1517+12
8999
9468
 	bl	printk
9000
-	uxtb	r0, r4
9469
+	uxtb	r0, r6
9001
9470
 	bl	NandcSetDdrPara
9002
-.L1507:
9471
+.L1502:
9003
9472
 	cmn	r8, #1
9004
-	bne	.L1500
9005
-	ldr	r0, .L1523+16
9006
-	mov	r1, r10
9007
-	ldr	r2, [sp]
9473
+	bne	.L1491
9474
+	ldm	sp, {r1, r2}
9475
+	ldr	r0, .L1517+16
9008
9476
 	bl	printk
9009
9477
 	ldr	r3, [sp, #56]
9010
9478
 	cmp	r3, #0
9011
-	beq	.L1508
9012
-	ldr	r3, [sp, #8]
9479
+	beq	.L1503
9480
+	ldr	r3, [sp, #12]
9013
9481
 	ubfx	r0, r3, #8, #8
9014
9482
 	bl	NandcSetDdrPara
9015
-.L1500:
9016
-	mov	r0, r6
9017
-	add	sp, sp, #20
9018
-	@ sp needed
9019
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
9020
-.L1524:
9483
+	b	.L1491
9484
+.L1497:
9485
+	ldr	r3, [sp, #8]
9486
+	cmp	r4, r3
9487
+	bls	.L1508
9488
+	cmp	r4, #7
9489
+	sub	r6, r9, r4
9490
+	bhi	.L1500
9491
+	str	r4, [sp, #8]
9492
+.L1508:
9493
+	mov	r4, #0
9494
+	b	.L1498
9495
+.L1507:
9496
+	mov	r8, #0
9497
+	mov	r9, r10
9498
+	mov	r5, r0
9499
+	mov	r7, r8
9500
+	mov	fp, r8
9501
+.L1498:
9502
+	add	r10, r10, #2
9503
+	cmp	r10, #69
9504
+	bls	.L1501
9505
+	mov	r3, r6
9506
+	mov	r6, r9
9507
+	b	.L1499
9508
+.L1518:
9021
9509
 	.align	2
9022
-.L1523:
9510
+.L1517:
9023
9511
 	.word	.LANCHOR0
9024
9512
 	.word	.LC90
9025
9513
 	.word	.LANCHOR2
..
..
@@ -9029,110 +9517,110 @@
9029
9517
 	.size	FlashDdrTunningRead, .-FlashDdrTunningRead
9030
9518
 	.align	2
9031
9519
 	.global	FlashReadPage
9520
+	.syntax unified
9521
+	.arm
9522
+	.fpu softvfp
9032
9523
 	.type	FlashReadPage, %function
9033
9524
 FlashReadPage:
9034
9525
 	.fnstart
9035
9526
 	@ args = 0, pretend = 0, frame = 0
9036
9527
 	@ frame_needed = 0, uses_anonymous_args = 0
9037
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
9528
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
9038
9529
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9039
9530
 	.pad #12
9040
9531
 	mov	r5, r0
9041
9532
 	mov	r6, r1
9042
-	mov	r8, r2
9043
-	mov	r7, r3
9533
+	mov	r7, r2
9534
+	mov	r8, r3
9044
9535
 	bl	FlashReadRawPage
9045
9536
 	cmn	r0, #1
9046
9537
 	mov	r4, r0
9047
-	bne	.L1526
9048
-	ldr	r9, .L1546
9049
-	ldrb	fp, [r9, #8]	@ zero_extendqisi2
9538
+	bne	.L1520
9539
+	ldr	r9, .L1539
9540
+	ldrb	fp, [r9, #44]	@ zero_extendqisi2
9050
9541
 	mov	r10, r9
9051
9542
 	cmp	fp, #0
9052
-	bne	.L1527
9053
-.L1529:
9054
-	ldrb	r3, [r10, #2252]	@ zero_extendqisi2
9055
-	ldr	r9, .L1546
9543
+	bne	.L1521
9544
+.L1523:
9545
+	ldrb	r3, [r10, #2256]	@ zero_extendqisi2
9056
9546
 	cmp	r3, #0
9057
-	beq	.L1526
9058
-	b	.L1545
9059
-.L1527:
9060
-	mov	r3, #0
9061
-	mov	r0, r5
9062
-	strb	r3, [r9, #8]
9547
+	beq	.L1520
9548
+	ldr	r3, [r10, #88]
9549
+	mov	r2, r7
9063
9550
 	mov	r1, r6
9064
-	mov	r2, r8
9065
-	mov	r3, r7
9066
-	bl	FlashReadRawPage
9067
-	strb	fp, [r9, #8]
9068
-	cmn	r0, #1
9069
-	movne	r4, r0
9070
-	beq	.L1529
9071
-	b	.L1526
9072
-.L1545:
9073
-	ldr	r3, [r9, #80]
9074
9551
 	mov	r0, r5
9075
-	mov	r1, r6
9076
-	mov	r2, r8
9077
-	ldr	r10, [r3, #304]
9552
+	ldr	r9, [r3, #304]
9078
9553
 	mov	r3, #1
9079
9554
 	str	r3, [sp]
9080
-	mov	r3, r7
9555
+	mov	r3, r8
9081
9556
 	bl	FlashDdrTunningRead
9082
9557
 	cmn	r0, #1
9083
9558
 	mov	r4, r0
9084
-	beq	.L1530
9085
-	ldrb	r3, [r9, #2312]	@ zero_extendqisi2
9559
+	beq	.L1524
9560
+	ldrb	r3, [r10, #2316]	@ zero_extendqisi2
9086
9561
 	cmp	r0, r3, lsr #1
9087
-	bls	.L1526
9088
-.L1530:
9089
-	ubfx	r0, r10, #8, #8
9562
+	bls	.L1520
9563
+.L1524:
9564
+	ubfx	r0, r9, #8, #8
9090
9565
 	bl	NandcSetDdrPara
9091
-.L1526:
9092
-	ldr	r9, .L1546+4
9093
-	ldr	ip, [r9, #1696]
9094
-	adds	r3, ip, #0
9566
+	b	.L1520
9567
+.L1521:
9568
+	mov	r3, #0
9569
+	mov	r2, r7
9570
+	strb	r3, [r9, #44]
9571
+	mov	r1, r6
9572
+	mov	r3, r8
9573
+	mov	r0, r5
9574
+	bl	FlashReadRawPage
9575
+	cmn	r0, #1
9576
+	strb	fp, [r9, #44]
9577
+	movne	r4, r0
9578
+	beq	.L1523
9579
+.L1520:
9580
+	ldr	r9, .L1539+4
9581
+	ldr	r10, [r9, #1704]
9582
+	adds	r3, r10, #0
9095
9583
 	movne	r3, #1
9096
9584
 	cmn	r4, #1
9097
9585
 	movne	r3, #0
9098
9586
 	cmp	r3, #0
9099
-	beq	.L1531
9587
+	beq	.L1519
9588
+	mov	r3, r8
9589
+	mov	r2, r7
9100
9590
 	mov	r1, r6
9101
-	mov	r2, r8
9102
-	mov	r3, r7
9103
9591
 	mov	r0, r5
9104
-	blx	ip
9105
-	mov	r2, r5
9592
+	blx	r10
9106
9593
 	mov	r3, r6
9107
9594
 	mov	r4, r0
9108
-	ldr	r0, .L1546+8
9109
-	mov	r1, r4
9595
+	mov	r1, r0
9596
+	mov	r2, r5
9597
+	ldr	r0, .L1539+8
9110
9598
 	bl	printk
9111
9599
 	cmn	r4, #1
9112
-	bne	.L1531
9113
-	ldr	r3, .L1546
9114
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
9600
+	bne	.L1519
9601
+	ldr	r3, .L1539
9602
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
9115
9603
 	cmp	r3, #0
9116
-	beq	.L1531
9604
+	beq	.L1519
9117
9605
 	mov	r0, r5
9118
9606
 	bl	flash_enter_slc_mode
9119
-	ldr	ip, [r9, #1696]
9120
-	mov	r0, r5
9607
+	ldr	r4, [r9, #1704]
9608
+	mov	r3, r8
9609
+	mov	r2, r7
9121
9610
 	mov	r1, r6
9122
-	mov	r2, r8
9123
-	mov	r3, r7
9124
-	blx	ip
9611
+	mov	r0, r5
9612
+	blx	r4
9125
9613
 	mov	r4, r0
9126
9614
 	mov	r0, r5
9127
9615
 	bl	flash_exit_slc_mode
9128
-.L1531:
9616
+.L1519:
9129
9617
 	mov	r0, r4
9130
9618
 	add	sp, sp, #12
9131
9619
 	@ sp needed
9132
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
9133
-.L1547:
9620
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
9621
+.L1540:
9134
9622
 	.align	2
9135
-.L1546:
9623
+.L1539:
9136
9624
 	.word	.LANCHOR0
9137
9625
 	.word	.LANCHOR2
9138
9626
 	.word	.LC93
..
..
@@ -9140,587 +9628,601 @@
9140
9628
 	.size	FlashReadPage, .-FlashReadPage
9141
9629
 	.align	2
9142
9630
 	.global	FlashDdrParaScan
9631
+	.syntax unified
9632
+	.arm
9633
+	.fpu softvfp
9143
9634
 	.type	FlashDdrParaScan, %function
9144
9635
 FlashDdrParaScan:
9145
9636
 	.fnstart
9146
9637
 	@ args = 0, pretend = 0, frame = 0
9147
9638
 	@ frame_needed = 0, uses_anonymous_args = 0
9148
-	stmfd	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
9639
+	push	{r0, r1, r4, r5, r6, r7, r8, lr}
9149
9640
 	.save {r4, r5, r6, r7, r8, lr}
9150
9641
 	.pad #8
9151
-	mov	r7, r0
9152
-	ldr	r5, .L1558
9153
-	mov	r6, r1
9642
+	mov	r6, r0
9643
+	ldr	r5, .L1551
9154
9644
 	mov	r4, #0
9155
-	ldrb	r0, [r5, #2229]	@ zero_extendqisi2
9645
+	mov	r7, r1
9646
+	ldrb	r0, [r5, #2233]	@ zero_extendqisi2
9156
9647
 	bl	FlashSetInterfaceMode
9157
-	ldrb	r0, [r5, #2229]	@ zero_extendqisi2
9648
+	ldrb	r0, [r5, #2233]	@ zero_extendqisi2
9158
9649
 	bl	NandcSetMode
9159
-	mov	r1, r6
9160
-	mov	r2, r4
9161
9650
 	mov	r3, r4
9162
-	mov	r0, r7
9651
+	mov	r2, r4
9652
+	mov	r1, r7
9163
9653
 	str	r4, [sp]
9654
+	mov	r0, r6
9164
9655
 	bl	FlashDdrTunningRead
9165
9656
 	mov	r3, r4
9166
-	mov	r1, r6
9167
-	mov	r2, r4
9168
9657
 	mov	r8, r0
9169
-	mov	r0, r7
9658
+	mov	r2, r4
9659
+	mov	r1, r7
9660
+	mov	r0, r6
9170
9661
 	bl	FlashReadRawPage
9662
+	cmn	r8, #1
9663
+	cmnne	r0, #1
9171
9664
 	mov	r3, r5
9172
-	cmn	r0, #1
9173
-	cmnne	r8, #1
9174
-	bne	.L1549
9175
-	ldrb	r2, [r5, #2229]	@ zero_extendqisi2
9665
+	bne	.L1542
9666
+	ldrb	r2, [r5, #2233]	@ zero_extendqisi2
9176
9667
 	tst	r2, #1
9177
-	beq	.L1549
9668
+	beq	.L1542
9178
9669
 	mov	r0, #1
9179
9670
 	bl	FlashSetInterfaceMode
9180
9671
 	mov	r0, #1
9181
9672
 	bl	NandcSetMode
9182
-	strb	r4, [r5, #2252]
9183
-	b	.L1550
9184
-.L1549:
9185
-	mov	r2, #1
9186
-	strb	r2, [r3, #2252]
9187
-.L1550:
9673
+	strb	r4, [r5, #2256]
9674
+.L1543:
9188
9675
 	mov	r0, #0
9189
9676
 	add	sp, sp, #8
9190
9677
 	@ sp needed
9191
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
9192
-.L1559:
9678
+	pop	{r4, r5, r6, r7, r8, pc}
9679
+.L1542:
9680
+	mov	r2, #1
9681
+	strb	r2, [r3, #2256]
9682
+	b	.L1543
9683
+.L1552:
9193
9684
 	.align	2
9194
-.L1558:
9685
+.L1551:
9195
9686
 	.word	.LANCHOR0
9196
9687
 	.fnend
9197
9688
 	.size	FlashDdrParaScan, .-FlashDdrParaScan
9198
9689
 	.align	2
9199
9690
 	.global	FlashLoadPhyInfo
9691
+	.syntax unified
9692
+	.arm
9693
+	.fpu softvfp
9200
9694
 	.type	FlashLoadPhyInfo, %function
9201
9695
 FlashLoadPhyInfo:
9202
9696
 	.fnstart
9203
9697
 	@ args = 0, pretend = 0, frame = 16
9204
9698
 	@ frame_needed = 0, uses_anonymous_args = 0
9205
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9699
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
9206
9700
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9701
+	mov	r3, #60
9207
9702
 	.pad #20
9208
9703
 	sub	sp, sp, #20
9209
-	ldr	r3, .L1576
9210
-	mov	r4, #0
9211
-	ldr	r7, .L1576+4
9212
-	mov	r9, #4
9213
-	ldr	r5, .L1576+8
9214
-	mvn	r8, #0
9215
-	ldr	r0, [r3]	@ unaligned
9216
-	ldr	r3, [r7, #4]
9217
-	str	r4, [r5, #1704]
9218
-	mov	r6, r5
9219
-	str	r0, [sp, #12]	@ unaligned
9220
-	mov	r0, r4
9704
+	ldr	r6, .L1568
9705
+	mov	r5, #0
9706
+	mov	r8, #4
9707
+	strb	r3, [sp, #12]
9708
+	mov	r3, #40
9709
+	strb	r3, [sp, #13]
9710
+	mov	r3, #24
9711
+	strb	r3, [sp, #14]
9712
+	mov	r3, #16
9713
+	ldr	r4, .L1568+4
9714
+	mvn	r7, #0
9715
+	strb	r3, [sp, #15]
9716
+	mov	r0, r5
9717
+	ldr	r3, [r6, #40]
9718
+	str	r5, [r4, #1712]
9221
9719
 	str	r3, [sp, #4]
9222
-	ldr	r3, [r5, #1688]
9223
-	str	r3, [r5, #1700]
9720
+	ldr	r3, [r4, #1696]
9721
+	str	r3, [r4, #1708]
9224
9722
 	bl	flash_enter_slc_mode
9225
-.L1561:
9226
-	add	fp, r4, #1
9227
-	mov	r10, #0
9228
-.L1563:
9229
-	add	r3, sp, #12
9230
-	ldrb	r0, [r3, r10]	@ zero_extendqisi2
9723
+.L1554:
9724
+	add	fp, r5, #1
9725
+	mov	r9, #0
9726
+	add	r10, sp, #12
9727
+.L1556:
9728
+	ldrb	r0, [r10, r9]	@ zero_extendqisi2
9231
9729
 	bl	FlashBchSel
9232
-	mov	r0, #0
9233
-	mov	r1, r4
9234
-	ldr	r2, [r5, #1688]
9235
-	mov	r3, r0
9730
+	mov	r3, #0
9731
+	ldr	r2, [r4, #1696]
9732
+	mov	r1, r5
9733
+	mov	r0, r3
9236
9734
 	bl	FlashReadRawPage
9237
9735
 	cmn	r0, #1
9238
-	bne	.L1562
9239
-	mov	r0, #0
9736
+	bne	.L1555
9737
+	mov	r3, #0
9738
+	ldr	r2, [r4, #1696]
9240
9739
 	mov	r1, fp
9241
-	ldr	r2, [r6, #1688]
9242
-	mov	r3, r0
9740
+	mov	r0, r3
9243
9741
 	bl	FlashReadRawPage
9244
9742
 	cmn	r0, #1
9245
-	bne	.L1562
9246
-	add	r10, r10, #1
9247
-	cmp	r10, #4
9248
-	beq	.L1564
9249
-	b	.L1563
9250
-.L1565:
9251
-	add	r0, fp, #12
9252
-	movw	r1, #2036
9253
-	bl	js_hash
9254
-	ldr	r3, [fp, #8]
9255
-	cmp	r3, r0
9256
-	mvnne	r8, #0
9257
-	bne	.L1564
9258
-	ldr	r8, .L1576+12
9259
-	add	r1, fp, #160
9260
-	mov	r2, #32
9743
+	bne	.L1555
9744
+	add	r9, r9, #1
9745
+	cmp	r9, #4
9746
+	bne	.L1556
9747
+.L1557:
9748
+	ldr	r3, [sp, #4]
9749
+	subs	r8, r8, #1
9750
+	add	r5, r5, r3
9751
+	bne	.L1554
9261
9752
 	mov	r0, r8
9262
-	bl	ftl_memcpy
9263
-	ldr	r1, [r6, #1700]
9753
+	b	.L1567
9754
+.L1558:
9755
+	movw	r1, #2036
9756
+	add	r0, r9, #12
9757
+	bl	js_hash
9758
+	ldr	r3, [r9, #8]
9759
+	cmp	r3, r0
9760
+	mvnne	r7, #0
9761
+	bne	.L1557
9264
9762
 	mov	r2, #32
9265
-	ldr	r0, .L1576+16
9763
+	add	r1, r9, #160
9764
+	ldr	r0, .L1568+8
9765
+	bl	ftl_memcpy
9766
+	ldr	r1, [r4, #1708]
9767
+	mov	r2, #32
9768
+	ldr	r0, .L1568+12
9266
9769
 	add	r1, r1, #192
9267
9770
 	bl	ftl_memcpy
9268
-	ldr	r1, [r6, #1700]
9771
+	ldr	r1, [r4, #1708]
9269
9772
 	mov	r2, #852
9270
-	ldr	r0, .L1576+20
9773
+	ldr	r0, .L1568+16
9271
9774
 	add	r1, r1, #224
9272
9775
 	bl	ftl_memcpy
9273
-	ldrh	r0, [r8, #10]
9776
+	ldr	r3, .L1568+8
9777
+	ldrh	r0, [r3, #10]
9274
9778
 	bl	FlashBlockAlignInit
9275
-	ldr	r8, [r6, #1700]
9276
-	str	r4, [r6, #1704]
9277
-	mov	r0, r4
9278
-	ldr	r1, [r7, #4]
9279
-	ldr	r3, [r8, #1076]
9280
-	strb	r3, [r7, #2252]
9779
+	ldr	r7, [r4, #1708]
9780
+	mov	r0, r5
9781
+	str	r5, [r4, #1712]
9782
+	ldr	r1, [r6, #40]
9783
+	ldr	r3, [r7, #1076]
9784
+	strb	r3, [r6, #2256]
9281
9785
 	bl	__aeabi_uidiv
9282
9786
 	add	r0, r0, #1
9283
9787
 	cmp	r0, #1
9284
-	strhi	r0, [r6, #1708]
9285
9788
 	movls	r3, #2
9286
-	strls	r3, [r6, #1708]
9287
-	ldrh	r3, [r8, #14]
9288
-	mov	r8, #0
9289
-	strb	r3, [r5, #1712]
9290
-.L1564:
9291
-	ldr	r3, [sp, #4]
9292
-	subs	r9, r9, #1
9293
-	add	r4, r4, r3
9294
-	bne	.L1561
9295
-	mov	r0, r9
9296
-.L1575:
9789
+	strhi	r0, [r4, #1716]
9790
+	strls	r3, [r4, #1716]
9791
+	ldrh	r3, [r7, #14]
9792
+	mov	r7, #0
9793
+	strb	r3, [r4, #1720]
9794
+	b	.L1557
9795
+.L1555:
9796
+	ldr	r9, [r4, #1708]
9797
+	ldr	r2, .L1568+20
9798
+	ldr	r3, [r9]
9799
+	cmp	r3, r2
9800
+	bne	.L1557
9801
+	cmp	r7, #0
9802
+	bne	.L1558
9803
+	ldr	r1, [r6, #40]
9804
+	mov	r0, r5
9805
+	bl	__aeabi_uidiv
9806
+	add	r0, r0, #1
9807
+	str	r0, [r4, #1716]
9808
+	mov	r0, r7
9809
+.L1567:
9297
9810
 	bl	flash_exit_slc_mode
9298
-	mov	r0, r8
9811
+	mov	r0, r7
9299
9812
 	add	sp, sp, #20
9300
9813
 	@ sp needed
9301
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
9302
-.L1562:
9303
-	ldr	fp, [r5, #1700]
9304
-	ldr	r2, .L1576+24
9305
-	ldr	r3, [fp]
9306
-	cmp	r3, r2
9307
-	bne	.L1564
9308
-	cmp	r8, #0
9309
-	bne	.L1565
9310
-	mov	r0, r4
9311
-	ldr	r1, [r7, #4]
9312
-	bl	__aeabi_uidiv
9313
-	ldr	r3, .L1576+8
9314
-	add	r0, r0, #1
9315
-	str	r0, [r3, #1708]
9316
-	mov	r0, r8
9317
-	b	.L1575
9318
-.L1577:
9814
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
9815
+.L1569:
9319
9816
 	.align	2
9320
-.L1576:
9321
-	.word	.LANCHOR3+11
9817
+.L1568:
9322
9818
 	.word	.LANCHOR0
9323
9819
 	.word	.LANCHOR2
9324
-	.word	.LANCHOR1+472
9325
-	.word	.LANCHOR0+48
9326
-	.word	.LANCHOR0+1210
9820
+	.word	.LANCHOR1+468
9821
+	.word	.LANCHOR0+52
9822
+	.word	.LANCHOR0+1216
9327
9823
 	.word	1312902724
9328
9824
 	.fnend
9329
9825
 	.size	FlashLoadPhyInfo, .-FlashLoadPhyInfo
9330
9826
 	.align	2
9331
9827
 	.global	ToshibaReadRetrial
9828
+	.syntax unified
9829
+	.arm
9830
+	.fpu softvfp
9332
9831
 	.type	ToshibaReadRetrial, %function
9333
9832
 ToshibaReadRetrial:
9334
9833
 	.fnstart
9335
9834
 	@ args = 0, pretend = 0, frame = 24
9336
9835
 	@ frame_needed = 0, uses_anonymous_args = 0
9337
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9836
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
9338
9837
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9838
+	mov	r8, r0
9839
+	ldr	r4, .L1598
9339
9840
 	.pad #28
9340
9841
 	sub	sp, sp, #28
9341
-	mov	r9, r0
9342
9842
 	mov	fp, r3
9843
+	str	r1, [sp, #12]
9343
9844
 	str	r2, [sp, #8]
9344
-	str	r1, [sp, #16]
9345
9845
 	bl	NandcWaitFlashReady
9346
-	ldr	r4, .L1607
9347
-	add	r3, r4, r9, asl #3
9348
-	ldrb	r2, [r3, #16]	@ zero_extendqisi2
9349
-	ldr	r6, [r3, #12]
9350
-	ldrb	r3, [r4, #1208]	@ zero_extendqisi2
9351
-	add	r7, r2, #8
9846
+	add	r3, r4, r8, lsl #3
9847
+	ldr	r6, [r4, r8, lsl #3]
9848
+	ldrb	r1, [r3, #4]	@ zero_extendqisi2
9849
+	ldrb	r3, [r4, #84]	@ zero_extendqisi2
9850
+	add	r7, r1, #8
9352
9851
 	sub	r3, r3, #67
9353
-	add	r7, r6, r7, asl #8
9852
+	add	r7, r6, r7, lsl #8
9354
9853
 	cmp	r3, #1
9355
-	mov	r3, r2, asl #8
9356
-	str	r3, [sp, #12]
9357
-	movls	r3, #0
9358
-	strls	r3, [sp, #4]
9359
-	bls	.L1579
9360
-	ldrb	r5, [r4, #2252]	@ zero_extendqisi2
9854
+	lsl	r3, r1, #8
9855
+	movls	r5, #0
9856
+	str	r3, [sp, #16]
9857
+	bls	.L1571
9858
+	ldrb	r5, [r4, #2256]	@ zero_extendqisi2
9361
9859
 	cmp	r5, #0
9362
-	streq	r5, [sp, #4]
9363
-	beq	.L1580
9860
+	beq	.L1572
9861
+	mov	r5, #1
9364
9862
 	mov	r0, #0
9365
-	str	r2, [sp, #20]
9366
9863
 	bl	NandcSetDdrMode
9367
-	mov	r3, #1
9368
-	ldr	r2, [sp, #20]
9369
-	str	r3, [sp, #4]
9370
-.L1580:
9371
-	ldr	r3, [sp, #12]
9372
-	mov	r1, #92
9864
+.L1572:
9865
+	lsl	r3, r1, #8
9866
+	mov	r2, #92
9373
9867
 	add	r3, r6, r3
9374
-	str	r1, [r3, #2056]
9375
-	mov	r1, #197
9376
-	str	r1, [r3, #2056]
9377
-.L1579:
9378
-	mov	r8, #1
9379
-	mvn	r10, #0
9380
-	mov	r3, r2, asl #8
9868
+	str	r2, [r3, #2056]
9869
+	mov	r2, #197
9870
+	str	r2, [r3, #2056]
9871
+.L1571:
9872
+	mvn	r3, #0
9873
+	mov	r9, #1
9874
+	str	r3, [sp, #4]
9875
+	lsl	r3, r1, #8
9381
9876
 	str	r3, [sp, #20]
9382
-.L1581:
9383
-	ldr	r3, .L1607+4
9384
-	ldrb	r3, [r3, #1713]	@ zero_extendqisi2
9877
+.L1573:
9878
+	ldr	r3, .L1598+4
9879
+	ldrb	r3, [r3, #1721]	@ zero_extendqisi2
9385
9880
 	add	r3, r3, #1
9386
-	cmp	r8, r3
9387
-	bcs	.L1606
9388
-	ldrb	r3, [r4, #1208]	@ zero_extendqisi2
9881
+	cmp	r9, r3
9882
+	bcc	.L1582
9883
+	ldr	r10, [sp, #4]
9884
+.L1581:
9885
+	ldrb	r2, [r4, #84]	@ zero_extendqisi2
9886
+	mov	r1, #0
9389
9887
 	mov	r0, r7
9390
-	uxtb	r1, r8
9888
+	sub	r2, r2, #67
9889
+	cmp	r2, #1
9890
+	bhi	.L1583
9891
+	bl	SandiskSetRRPara
9892
+.L1584:
9893
+	ldr	r3, [sp, #16]
9894
+	mov	r2, #255
9895
+	add	r6, r6, r3
9896
+	str	r2, [r6, #2056]
9897
+	ldrb	r2, [r4, #2316]	@ zero_extendqisi2
9898
+	add	r2, r2, r2, lsl #1
9899
+	cmp	r10, r2, asr #2
9900
+	bcc	.L1585
9901
+	cmn	r10, #1
9902
+	movne	r10, #256
9903
+.L1585:
9904
+	mov	r0, r8
9905
+	bl	NandcWaitFlashReady
9906
+	cmp	r5, #0
9907
+	beq	.L1570
9908
+	mov	r0, #4
9909
+	bl	NandcSetDdrMode
9910
+.L1570:
9911
+	mov	r0, r10
9912
+	add	sp, sp, #28
9913
+	@ sp needed
9914
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
9915
+.L1582:
9916
+	ldrb	r3, [r4, #84]	@ zero_extendqisi2
9917
+	mov	r0, r7
9918
+	uxtb	r1, r9
9391
9919
 	sub	r3, r3, #67
9392
9920
 	cmp	r3, #1
9393
-	bhi	.L1582
9921
+	bhi	.L1574
9394
9922
 	bl	SandiskSetRRPara
9395
-	b	.L1583
9396
-.L1582:
9397
-	bl	ToshibaSetRRPara
9398
-.L1583:
9399
-	ldrb	r3, [r4, #1208]	@ zero_extendqisi2
9923
+.L1575:
9924
+	ldrb	r3, [r4, #84]	@ zero_extendqisi2
9400
9925
 	cmp	r3, #34
9401
-	bne	.L1584
9402
-	ldr	r3, .L1607+4
9403
-	ldrb	r3, [r3, #1713]	@ zero_extendqisi2
9926
+	bne	.L1576
9927
+	ldr	r3, .L1598+4
9928
+	ldrb	r3, [r3, #1721]	@ zero_extendqisi2
9404
9929
 	sub	r3, r3, #3
9405
-	cmp	r8, r3
9930
+	cmp	r9, r3
9406
9931
 	ldreq	r3, [sp, #20]
9407
9932
 	moveq	r2, #179
9408
9933
 	addeq	r3, r6, r3
9409
9934
 	streq	r2, [r3, #2056]
9410
-.L1584:
9411
-	ldr	r3, [sp, #12]
9935
+.L1576:
9936
+	ldr	r3, [sp, #16]
9412
9937
 	mov	r2, #38
9938
+	cmp	r5, #0
9413
9939
 	add	r3, r6, r3
9414
9940
 	str	r2, [r3, #2056]
9415
9941
 	mov	r2, #93
9416
9942
 	str	r2, [r3, #2056]
9417
-	ldr	r3, [sp, #4]
9418
-	cmp	r3, #0
9419
-	beq	.L1585
9943
+	beq	.L1577
9420
9944
 	mov	r0, #4
9421
9945
 	bl	NandcSetDdrMode
9422
-	mov	r0, r9
9423
9946
 	mov	r3, fp
9424
-	ldr	r1, [sp, #16]
9425
9947
 	ldr	r2, [sp, #8]
9948
+	ldr	r1, [sp, #12]
9949
+	mov	r0, r8
9426
9950
 	bl	FlashReadRawPage
9427
-	mov	r5, r0
9951
+	mov	r10, r0
9428
9952
 	mov	r0, #0
9429
9953
 	bl	NandcSetDdrMode
9430
-	b	.L1586
9431
-.L1585:
9432
-	mov	r0, r9
9433
-	ldr	r1, [sp, #16]
9434
-	ldr	r2, [sp, #8]
9435
-	mov	r3, fp
9436
-	bl	FlashReadRawPage
9437
-	mov	r5, r0
9438
-.L1586:
9439
-	cmn	r5, #1
9440
-	beq	.L1587
9441
-	ldrb	r2, [r4, #2312]	@ zero_extendqisi2
9954
+.L1578:
9442
9955
 	cmn	r10, #1
9443
-	moveq	r10, r5
9444
-	add	r2, r2, r2, asl #1
9445
-	cmp	r5, r2, asr #2
9446
-	bcc	.L1589
9956
+	beq	.L1579
9957
+	ldrb	r2, [r4, #2316]	@ zero_extendqisi2
9958
+	ldr	r3, [sp, #4]
9959
+	add	r2, r2, r2, lsl #1
9960
+	cmn	r3, #1
9961
+	moveq	r3, r10
9962
+	cmp	r10, r2, asr #2
9963
+	str	r3, [sp, #4]
9964
+	bcc	.L1581
9447
9965
 	mov	fp, #0
9448
9966
 	str	fp, [sp, #8]
9449
-.L1587:
9450
-	add	r8, r8, #1
9451
-	b	.L1581
9452
-.L1606:
9453
-	mov	r5, r10
9454
-.L1589:
9455
-	ldrb	r2, [r4, #1208]	@ zero_extendqisi2
9456
-	mov	r0, r7
9457
-	mov	r1, #0
9458
-	sub	r2, r2, #67
9459
-	cmp	r2, #1
9460
-	bhi	.L1591
9461
-	bl	SandiskSetRRPara
9462
-	b	.L1592
9463
-.L1591:
9967
+.L1579:
9968
+	add	r9, r9, #1
9969
+	b	.L1573
9970
+.L1574:
9464
9971
 	bl	ToshibaSetRRPara
9465
-.L1592:
9466
-	ldr	r3, [sp, #12]
9467
-	mov	r2, #255
9468
-	add	r6, r6, r3
9469
-	str	r2, [r6, #2056]
9470
-	ldrb	r2, [r4, #2312]	@ zero_extendqisi2
9471
-	add	r2, r2, r2, asl #1
9472
-	cmp	r5, r2, asr #2
9473
-	bcc	.L1593
9474
-	cmn	r5, #1
9475
-	movne	r5, #256
9476
-.L1593:
9477
-	mov	r0, r9
9478
-	bl	NandcWaitFlashReady
9479
-	ldr	r3, [sp, #4]
9480
-	cmp	r3, #0
9481
-	beq	.L1594
9482
-	mov	r0, #4
9483
-	bl	NandcSetDdrMode
9484
-.L1594:
9485
-	mov	r0, r5
9486
-	add	sp, sp, #28
9487
-	@ sp needed
9488
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
9489
-.L1608:
9972
+	b	.L1575
9973
+.L1577:
9974
+	mov	r3, fp
9975
+	ldr	r2, [sp, #8]
9976
+	ldr	r1, [sp, #12]
9977
+	mov	r0, r8
9978
+	bl	FlashReadRawPage
9979
+	mov	r10, r0
9980
+	b	.L1578
9981
+.L1583:
9982
+	bl	ToshibaSetRRPara
9983
+	b	.L1584
9984
+.L1599:
9490
9985
 	.align	2
9491
-.L1607:
9986
+.L1598:
9492
9987
 	.word	.LANCHOR0
9493
9988
 	.word	.LANCHOR2
9494
9989
 	.fnend
9495
9990
 	.size	ToshibaReadRetrial, .-ToshibaReadRetrial
9496
9991
 	.align	2
9497
9992
 	.global	SamsungReadRetrial
9993
+	.syntax unified
9994
+	.arm
9995
+	.fpu softvfp
9498
9996
 	.type	SamsungReadRetrial, %function
9499
9997
 SamsungReadRetrial:
9500
9998
 	.fnstart
9501
-	@ args = 0, pretend = 0, frame = 8
9999
+	@ args = 0, pretend = 0, frame = 0
9502
10000
 	@ frame_needed = 0, uses_anonymous_args = 0
9503
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
9504
-	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9505
-	.pad #12
9506
-	mov	r9, r0
9507
-	ldr	r5, .L1623
9508
-	mov	r10, r2
9509
-	mov	r8, r3
10001
+	push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
10002
+	.save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
10003
+	mov	r8, r0
10004
+	ldr	r5, .L1614
10005
+	mov	r9, r3
9510
10006
 	mov	fp, r1
10007
+	mov	r10, r2
9511
10008
 	bl	NandcWaitFlashReady
9512
-	add	r2, r5, r9, asl #3
9513
-	ldr	ip, .L1623+4
9514
10009
 	mov	r7, #1
9515
-	ldrb	r3, [r2, #16]	@ zero_extendqisi2
9516
10010
 	mvn	r4, #0
9517
-	ldr	r6, [r2, #12]
9518
-	add	r3, r3, #8
9519
-	add	r6, r6, r3, asl #8
9520
-.L1610:
9521
-	ldrb	r3, [ip, #1713]	@ zero_extendqisi2
10011
+	add	r3, r5, r8, lsl #3
10012
+	ldrb	r6, [r3, #4]	@ zero_extendqisi2
10013
+	add	r3, r6, #8
10014
+	ldr	r6, [r5, r8, lsl #3]
10015
+	add	r6, r6, r3, lsl #8
10016
+.L1601:
10017
+	ldr	r3, .L1614+4
10018
+	ldrb	r3, [r3, #1721]	@ zero_extendqisi2
9522
10019
 	add	r3, r3, #1
9523
10020
 	cmp	r7, r3
9524
-	bcs	.L1613
9525
-	mov	r0, r6
9526
-	uxtb	r1, r7
9527
-	str	ip, [sp, #4]
9528
-	bl	SamsungSetRRPara
9529
-	mov	r0, r9
9530
-	mov	r1, fp
9531
-	mov	r2, r10
9532
-	mov	r3, r8
9533
-	bl	FlashReadRawPage
9534
-	cmn	r0, #1
9535
-	ldr	ip, [sp, #4]
9536
-	beq	.L1611
9537
-	ldrb	r3, [r5, #2312]	@ zero_extendqisi2
9538
-	cmn	r4, #1
9539
-	moveq	r4, r0
9540
-	add	r3, r3, r3, asl #1
9541
-	cmp	r0, r3, asr #2
9542
-	bcc	.L1616
9543
-	mov	r8, #0
9544
-	mov	r10, r8
9545
-.L1611:
9546
-	add	r7, r7, #1
9547
-	b	.L1610
9548
-.L1616:
9549
-	mov	r4, r0
9550
-.L1613:
9551
-	mov	r0, r6
10021
+	bcc	.L1605
10022
+.L1604:
9552
10023
 	mov	r1, #0
10024
+	mov	r0, r6
9553
10025
 	bl	SamsungSetRRPara
9554
-	ldrb	r3, [r5, #2312]	@ zero_extendqisi2
9555
-	add	r3, r3, r3, asl #1
10026
+	ldrb	r3, [r5, #2316]	@ zero_extendqisi2
10027
+	add	r3, r3, r3, lsl #1
9556
10028
 	cmp	r4, r3, asr #2
9557
-	bcc	.L1615
10029
+	bcc	.L1600
9558
10030
 	cmn	r4, #1
9559
10031
 	movne	r4, #256
9560
-.L1615:
10032
+.L1600:
9561
10033
 	mov	r0, r4
9562
-	add	sp, sp, #12
9563
-	@ sp needed
9564
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
9565
-.L1624:
10034
+	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
10035
+.L1605:
10036
+	uxtb	r1, r7
10037
+	mov	r0, r6
10038
+	bl	SamsungSetRRPara
10039
+	mov	r3, r9
10040
+	mov	r2, r10
10041
+	mov	r1, fp
10042
+	mov	r0, r8
10043
+	bl	FlashReadRawPage
10044
+	cmn	r0, #1
10045
+	beq	.L1602
10046
+	ldrb	r3, [r5, #2316]	@ zero_extendqisi2
10047
+	cmn	r4, #1
10048
+	moveq	r4, r0
10049
+	add	r3, r3, r3, lsl #1
10050
+	cmp	r0, r3, asr #2
10051
+	bcc	.L1608
10052
+	mov	r9, #0
10053
+	mov	r10, r9
10054
+.L1602:
10055
+	add	r7, r7, #1
10056
+	b	.L1601
10057
+.L1608:
10058
+	mov	r4, r0
10059
+	b	.L1604
10060
+.L1615:
9566
10061
 	.align	2
9567
-.L1623:
10062
+.L1614:
9568
10063
 	.word	.LANCHOR0
9569
10064
 	.word	.LANCHOR2
9570
10065
 	.fnend
9571
10066
 	.size	SamsungReadRetrial, .-SamsungReadRetrial
9572
10067
 	.align	2
9573
10068
 	.global	MicronReadRetrial
10069
+	.syntax unified
10070
+	.arm
10071
+	.fpu softvfp
9574
10072
 	.type	MicronReadRetrial, %function
9575
10073
 MicronReadRetrial:
9576
10074
 	.fnstart
9577
-	@ args = 0, pretend = 0, frame = 24
10075
+	@ args = 0, pretend = 0, frame = 32
9578
10076
 	@ frame_needed = 0, uses_anonymous_args = 0
9579
-.L1627:
9580
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10077
+.L1618:
10078
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
9581
10079
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9582
-	mov	r8, r3
9583
-	ldr	r3, .L1651
9584
-	mov	fp, r2
9585
-	.pad #36
9586
-	sub	sp, sp, #36
9587
-	mov	r6, r0
9588
-	mov	r10, #0
9589
-	ldrb	r5, [r3, #2312]	@ zero_extendqisi2
9590
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
9591
-	str	r1, [sp, #20]
10080
+	mov	r7, r3
10081
+	ldr	r3, .L1642
10082
+	mov	r10, r2
10083
+	.pad #44
10084
+	sub	sp, sp, #44
10085
+	mov	r5, r0
10086
+	ldr	fp, .L1642
10087
+	ldrb	r2, [r3, #2316]	@ zero_extendqisi2
10088
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
10089
+	str	r1, [sp, #28]
9592
10090
 	cmp	r3, #0
9593
-	addeq	r5, r5, r5, asl #1
9594
-	ldrne	r2, .L1651+4
9595
-	ubfxeq	r5, r5, #2, #8
9596
-	smullne	r2, r3, r5, r2
9597
-	uxtbne	r5, r3
9598
-	ldr	r3, .L1651
9599
-	add	r3, r3, r0, asl #3
9600
-	str	r3, [sp, #24]
9601
-.L1637:
9602
-	mov	r0, r6
10091
+	ldrne	r3, .L1642+4
10092
+	addeq	r2, r2, r2, lsl #1
10093
+	asreq	r3, r2, #2
10094
+	smullne	r2, r3, r2, r3
10095
+	str	r3, [sp, #12]
10096
+	mov	r3, #0
10097
+	str	r3, [sp, #16]
10098
+	add	r3, fp, r0, lsl #3
10099
+	str	r3, [sp, #36]
10100
+.L1628:
10101
+	mov	r0, r5
9603
10102
 	mov	r9, #0
9604
10103
 	bl	NandcWaitFlashReady
10104
+	ldr	r3, [fp, r5, lsl #3]
9605
10105
 	mvn	r4, #0
9606
-	ldr	r3, [sp, #24]
9607
-	ldr	r3, [r3, #12]
9608
-	str	r3, [sp, #12]
9609
-	ldr	r3, [sp, #24]
9610
-	ldrb	r3, [r3, #16]	@ zero_extendqisi2
9611
-	str	r3, [sp, #16]
9612
-	ldr	r2, [sp, #16]
9613
-	ldr	r3, [sp, #12]
9614
-	add	r7, r3, r2, asl #8
9615
-.L1628:
9616
-	ldr	r3, .L1651+8
9617
-	ldrb	r3, [r3, #1713]	@ zero_extendqisi2
10106
+	str	r3, [sp, #20]
10107
+	ldr	r3, [sp, #36]
10108
+	ldrb	r3, [r3, #4]	@ zero_extendqisi2
10109
+	str	r3, [sp, #24]
10110
+	ldr	r2, [sp, #24]
10111
+	ldr	r3, [sp, #20]
10112
+	add	r6, r3, r2, lsl #8
10113
+.L1619:
10114
+	ldr	r3, .L1642+8
10115
+	ldrb	r3, [r3, #1721]	@ zero_extendqisi2
9618
10116
 	cmp	r9, r3
9619
-	bcs	.L1631
10117
+	bcc	.L1623
10118
+.L1622:
10119
+	ldr	r3, [sp, #20]
10120
+	mov	r0, #200
10121
+	ldr	r2, [sp, #24]
10122
+	add	r6, r3, r2, lsl #8
10123
+	mov	r3, #239
10124
+	str	r3, [r6, #2056]
10125
+	mov	r3, #137
10126
+	str	r3, [r6, #2052]
10127
+	bl	ndelay
10128
+	mov	r3, #0
10129
+	str	r3, [r6, #2048]
10130
+	str	r3, [r6, #2048]
10131
+	str	r3, [r6, #2048]
10132
+	str	r3, [r6, #2048]
10133
+	ldr	r3, [sp, #12]
10134
+	cmp	r4, r3
10135
+	bcc	.L1624
10136
+	cmn	r4, #1
10137
+	movne	r4, #256
10138
+.L1624:
10139
+	cmn	r4, #1
10140
+	movne	r6, #0
10141
+	moveq	r6, #1
10142
+	cmp	r4, #256
10143
+	movne	r1, r6
10144
+	orreq	r1, r6, #1
10145
+	cmp	r1, #0
10146
+	beq	.L1625
10147
+	mov	r3, r9
10148
+	str	r4, [sp]
10149
+	ldr	r2, [sp, #28]
10150
+	mov	r1, r9
10151
+	ldr	r0, .L1642+12
10152
+	bl	printk
10153
+	ldr	r3, [sp, #16]
10154
+	cmp	r3, #0
10155
+	bne	.L1626
10156
+	ldrb	r3, [fp, #152]	@ zero_extendqisi2
10157
+	cmp	r3, #0
10158
+	moveq	r6, #0
10159
+	andne	r6, r6, #1
10160
+	cmp	r6, #0
10161
+	beq	.L1616
10162
+	mov	r1, #3
10163
+	mov	r0, r5
10164
+	bl	micron_auto_read_calibration_config
10165
+	mov	r3, #1
10166
+	str	r3, [sp, #16]
10167
+	b	.L1628
10168
+.L1623:
9620
10169
 	mov	r3, #239
9621
10170
 	mov	r0, #200
9622
-	str	r3, [r7, #2056]
10171
+	str	r3, [r6, #2056]
9623
10172
 	mov	r3, #137
9624
-	str	r3, [r7, #2052]
9625
-	bl	NandcDelayns
9626
-	mov	ip, #0
10173
+	str	r3, [r6, #2052]
10174
+	mov	r8, #0
10175
+	bl	ndelay
9627
10176
 	add	r3, r9, #1
9628
-	mov	r0, r6
9629
-	str	r3, [r7, #2048]
9630
-	mov	r2, fp
9631
-	str	ip, [r7, #2048]
9632
-	str	ip, [r7, #2048]
9633
-	str	ip, [r7, #2048]
9634
-	str	r3, [sp, #8]
9635
-	mov	r3, r8
9636
-	ldr	r1, [sp, #20]
9637
-	str	ip, [sp, #28]
10177
+	mov	r2, r10
10178
+	str	r3, [r6, #2048]
10179
+	mov	r0, r5
10180
+	str	r8, [r6, #2048]
10181
+	str	r3, [sp, #32]
10182
+	mov	r3, r7
10183
+	str	r8, [r6, #2048]
10184
+	ldr	r1, [sp, #28]
10185
+	str	r8, [r6, #2048]
9638
10186
 	bl	FlashReadRawPage
9639
10187
 	cmn	r0, #1
9640
-	beq	.L1629
9641
-	cmn	r4, #1
9642
-	ldr	ip, [sp, #28]
9643
-	moveq	r4, r0
9644
-	cmp	r0, r5
9645
-	bcc	.L1639
9646
-	mov	r8, ip
9647
-	mov	fp, ip
9648
-.L1629:
9649
-	ldr	r9, [sp, #8]
9650
-	b	.L1628
9651
-.L1639:
9652
-	mov	r4, r0
9653
-	mov	r8, ip
9654
-	mov	fp, ip
9655
-.L1631:
9656
-	ldr	r2, [sp, #16]
9657
-	mov	r0, #200
10188
+	beq	.L1620
9658
10189
 	ldr	r3, [sp, #12]
9659
-	add	r7, r3, r2, asl #8
9660
-	mov	r3, #239
9661
-	str	r3, [r7, #2056]
9662
-	mov	r3, #137
9663
-	str	r3, [r7, #2052]
9664
-	bl	NandcDelayns
9665
-	cmp	r4, r5
9666
-	mov	r3, #0
9667
-	str	r3, [r7, #2048]
9668
-	str	r3, [r7, #2048]
9669
-	str	r3, [r7, #2048]
9670
-	str	r3, [r7, #2048]
9671
-	bcc	.L1633
9672
10190
 	cmn	r4, #1
9673
-	movne	r4, #256
9674
-.L1633:
9675
-	cmn	r4, #1
9676
-	movne	r7, #0
9677
-	moveq	r7, #1
9678
-	cmp	r4, #256
9679
-	movne	r1, r7
9680
-	orreq	r1, r7, #1
9681
-	cmp	r1, #0
9682
-	beq	.L1634
9683
-	str	r4, [sp]
9684
-	mov	r1, r9
9685
-	ldr	r0, .L1651+12
9686
-	mov	r3, r9
9687
-	ldr	r2, [sp, #20]
9688
-	bl	printk
9689
-	cmp	r10, #0
9690
-	bne	.L1635
9691
-	ldr	r3, .L1651
9692
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
9693
-	cmp	r3, #0
9694
-	moveq	r7, #0
9695
-	andne	r7, r7, #1
9696
-	cmp	r7, #0
9697
-	beq	.L1644
9698
-	mov	r0, r6
9699
-	mov	r1, #3
9700
-	bl	micron_auto_read_calibration_config
9701
-	mov	r10, #1
9702
-	b	.L1637
9703
-.L1635:
9704
-	mov	r0, r6
10191
+	moveq	r4, r0
10192
+	cmp	r0, r3
10193
+	bcc	.L1630
10194
+	mov	r7, r8
10195
+	mov	r10, r8
10196
+.L1620:
10197
+	ldr	r9, [sp, #32]
10198
+	b	.L1619
10199
+.L1630:
10200
+	mov	r4, r0
10201
+	mov	r7, r8
10202
+	mov	r10, r8
10203
+	b	.L1622
10204
+.L1626:
9705
10205
 	mov	r1, #0
10206
+	mov	r0, r5
9706
10207
 	bl	micron_auto_read_calibration_config
9707
10208
 	cmn	r4, #1
9708
10209
 	movne	r4, #256
9709
-	b	.L1644
9710
-.L1634:
9711
-	cmp	r10, #0
9712
-	beq	.L1644
9713
-	mov	r0, r6
10210
+.L1616:
10211
+	mov	r0, r4
10212
+	add	sp, sp, #44
10213
+	@ sp needed
10214
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
10215
+.L1625:
10216
+	ldr	r3, [sp, #16]
10217
+	cmp	r3, #0
10218
+	beq	.L1616
10219
+	mov	r0, r5
9714
10220
 	mov	r4, #256
9715
10221
 	bl	micron_auto_read_calibration_config
9716
-.L1644:
9717
-	mov	r0, r4
9718
-	add	sp, sp, #36
9719
-	@ sp needed
9720
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
9721
-.L1652:
10222
+	b	.L1616
10223
+.L1643:
9722
10224
 	.align	2
9723
-.L1651:
10225
+.L1642:
9724
10226
 	.word	.LANCHOR0
9725
10227
 	.word	1431655766
9726
10228
 	.word	.LANCHOR2
..
..
@@ -9729,296 +10231,299 @@
9729
10231
 	.size	MicronReadRetrial, .-MicronReadRetrial
9730
10232
 	.align	2
9731
10233
 	.global	HynixReadRetrial
10234
+	.syntax unified
10235
+	.arm
10236
+	.fpu softvfp
9732
10237
 	.type	HynixReadRetrial, %function
9733
10238
 HynixReadRetrial:
9734
10239
 	.fnstart
9735
10240
 	@ args = 0, pretend = 0, frame = 8
9736
10241
 	@ frame_needed = 0, uses_anonymous_args = 0
9737
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
10242
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
9738
10243
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9739
10244
 	.pad #12
9740
-	mov	r8, r3
9741
-	ldr	r5, .L1671
9742
-	mov	r10, r2
9743
-	mov	r7, r0
9744
-	mov	fp, r1
9745
-	add	r2, r5, r0
10245
+	mov	r9, r3
10246
+	ldr	r5, .L1662
10247
+	mov	r8, #0
9746
10248
 	mvn	r6, #0
9747
-	ldr	r3, [r5, #44]
9748
-	ldrb	r4, [r2, #1222]	@ zero_extendqisi2
9749
-	ldrb	r9, [r5, #1212]	@ zero_extendqisi2
10249
+	mov	fp, r2
10250
+	mov	r7, r0
10251
+	str	r1, [sp, #4]
10252
+	ldr	r3, [r5, #48]
10253
+	add	r2, r5, r0
10254
+	ldrb	r4, [r2, #1228]	@ zero_extendqisi2
10255
+	ldrb	r10, [r5, #1218]	@ zero_extendqisi2
9750
10256
 	ldrb	r3, [r3, #19]	@ zero_extendqisi2
9751
10257
 	sub	r3, r3, #7
9752
10258
 	cmp	r3, #1
9753
-	ldrlsb	r4, [r2, #1230]	@ zero_extendqisi2
10259
+	ldrbls	r4, [r2, #1236]	@ zero_extendqisi2
9754
10260
 	bl	NandcWaitFlashReady
9755
-	mov	ip, #0
9756
-.L1655:
9757
-	cmp	ip, r9
9758
-	bcs	.L1659
9759
-	add	r4, r4, #1
9760
-	mov	r0, r7
9761
-	ldrb	r1, [r5, #1211]	@ zero_extendqisi2
9762
-	uxtb	r4, r4
9763
-	ldr	r2, .L1671+4
9764
-	cmp	r4, r9
9765
-	str	ip, [sp, #4]
9766
-	movcs	r4, #0
9767
-	mov	r3, r4
9768
-	bl	HynixSetRRPara
9769
-	mov	r0, r7
9770
-	mov	r1, fp
9771
-	mov	r2, r10
9772
-	mov	r3, r8
9773
-	bl	FlashReadRawPage
9774
-	cmn	r0, #1
9775
-	ldr	ip, [sp, #4]
9776
-	beq	.L1657
9777
-	ldrb	r3, [r5, #2312]	@ zero_extendqisi2
9778
-	cmn	r6, #1
9779
-	moveq	r6, r0
9780
-	add	r3, r3, r3, asl #1
9781
-	cmp	r0, r3, asr #2
9782
-	bcc	.L1664
9783
-	mov	r8, #0
9784
-	mov	r10, r8
9785
-.L1657:
9786
-	add	ip, ip, #1
9787
-	b	.L1655
9788
-.L1664:
9789
-	mov	r6, r0
9790
-.L1659:
9791
-	ldr	r3, [r5, #44]
10261
+.L1646:
10262
+	cmp	r8, r10
10263
+	bcc	.L1651
10264
+.L1650:
10265
+	ldr	r3, [r5, #48]
9792
10266
 	add	r7, r5, r7
9793
10267
 	ldrb	r3, [r3, #19]	@ zero_extendqisi2
9794
10268
 	sub	r3, r3, #7
9795
10269
 	cmp	r3, #1
9796
-	ldrb	r3, [r5, #2312]	@ zero_extendqisi2
9797
-	strlsb	r4, [r7, #1230]
9798
-	strhib	r4, [r7, #1222]
9799
-	add	r3, r3, r3, asl #1
10270
+	ldrb	r3, [r5, #2316]	@ zero_extendqisi2
10271
+	strbls	r4, [r7, #1236]
10272
+	strbhi	r4, [r7, #1228]
10273
+	add	r3, r3, r3, lsl #1
9800
10274
 	cmp	r6, r3, asr #2
9801
-	bcc	.L1663
10275
+	bcc	.L1644
9802
10276
 	cmn	r6, #1
9803
10277
 	movne	r6, #256
9804
-.L1663:
10278
+.L1644:
9805
10279
 	mov	r0, r6
9806
10280
 	add	sp, sp, #12
9807
10281
 	@ sp needed
9808
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
9809
-.L1672:
10282
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
10283
+.L1651:
10284
+	add	r4, r4, #1
10285
+	ldr	r2, .L1662+4
10286
+	uxtb	r4, r4
10287
+	ldrb	r1, [r5, #1217]	@ zero_extendqisi2
10288
+	mov	r0, r7
10289
+	cmp	r10, r4
10290
+	movls	r4, #0
10291
+	mov	r3, r4
10292
+	bl	HynixSetRRPara
10293
+	mov	r3, r9
10294
+	mov	r2, fp
10295
+	ldr	r1, [sp, #4]
10296
+	mov	r0, r7
10297
+	bl	FlashReadRawPage
10298
+	cmn	r0, #1
10299
+	beq	.L1648
10300
+	ldrb	r3, [r5, #2316]	@ zero_extendqisi2
10301
+	cmn	r6, #1
10302
+	moveq	r6, r0
10303
+	add	r3, r3, r3, lsl #1
10304
+	cmp	r0, r3, asr #2
10305
+	bcc	.L1655
10306
+	mov	r9, #0
10307
+	mov	fp, r9
10308
+.L1648:
10309
+	add	r8, r8, #1
10310
+	b	.L1646
10311
+.L1655:
10312
+	mov	r6, r0
10313
+	b	.L1650
10314
+.L1663:
9810
10315
 	.align	2
9811
-.L1671:
10316
+.L1662:
9812
10317
 	.word	.LANCHOR0
9813
-	.word	.LANCHOR0+1214
10318
+	.word	.LANCHOR0+1220
9814
10319
 	.fnend
9815
10320
 	.size	HynixReadRetrial, .-HynixReadRetrial
9816
10321
 	.align	2
10322
+	.syntax unified
10323
+	.arm
10324
+	.fpu softvfp
9817
10325
 	.type	samsung_read_retrial, %function
9818
10326
 samsung_read_retrial:
9819
10327
 	.fnstart
9820
10328
 	@ args = 0, pretend = 0, frame = 16
9821
10329
 	@ frame_needed = 0, uses_anonymous_args = 0
9822
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10330
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
9823
10331
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9824
10332
 	.pad #28
9825
10333
 	sub	sp, sp, #28
9826
10334
 	mov	r10, r0
9827
10335
 	mov	fp, r2
9828
-	mov	r8, r3
9829
-	str	r1, [sp, #12]
10336
+	mov	r9, r3
10337
+	str	r1, [sp, #16]
9830
10338
 	bl	NandcWaitFlashReady
9831
-	ldr	r3, .L1703
9832
-	add	r2, r3, r10, asl #3
9833
-	ldr	r4, [r2, #12]
9834
-	ldrb	r2, [r2, #16]	@ zero_extendqisi2
9835
-	str	r2, [sp, #8]
9836
-	ldrb	r2, [r3, #2228]	@ zero_extendqisi2
9837
-	str	r3, [sp, #16]
10339
+	ldr	r3, .L1694
10340
+	ldr	r2, [r3, r10, lsl #3]
10341
+	str	r3, [sp, #20]
10342
+	str	r2, [sp, #12]
10343
+	add	r2, r3, r10, lsl #3
10344
+	ldrb	r6, [r2, #4]	@ zero_extendqisi2
10345
+	ldrb	r2, [r3, #2232]	@ zero_extendqisi2
9838
10346
 	cmp	r2, #0
9839
-	bne	.L1674
9840
-	ldr	r3, [sp, #8]
9841
-	mvn	r5, #0
9842
-	mov	r6, #1
9843
-	mov	r9, r3, asl #8
9844
-	add	r7, r4, r9
9845
-.L1678:
10347
+	bne	.L1665
10348
+	ldr	r3, [sp, #12]
10349
+	lsl	r8, r6, #8
10350
+	mvn	r4, #0
10351
+	mov	r7, #1
10352
+	add	r5, r3, r8
10353
+.L1669:
9846
10354
 	mov	r3, #239
9847
-	str	r3, [r7, #2056]
10355
+	mov	r6, #0
10356
+	str	r3, [r5, #2056]
9848
10357
 	mov	r3, #141
9849
-	str	r3, [r7, #2052]
9850
-	ldr	r3, .L1703+4
9851
-	mov	ip, #0
9852
-	mov	r0, r10
9853
-	ldr	r1, [sp, #12]
10358
+	str	r3, [r5, #2052]
9854
10359
 	mov	r2, fp
9855
-	str	ip, [sp, #20]
9856
-	ldrsb	r3, [r6, r3]
9857
-	str	r3, [r7, #2048]
9858
-	mov	r3, r8
9859
-	str	ip, [r7, #2048]
9860
-	str	ip, [r7, #2048]
9861
-	str	ip, [r7, #2048]
10360
+	ldr	r3, .L1694+4
10361
+	mov	r0, r10
10362
+	ldr	r1, [sp, #16]
10363
+	ldrsb	r3, [r7, r3]
10364
+	str	r3, [r5, #2048]
10365
+	mov	r3, r9
10366
+	str	r6, [r5, #2048]
10367
+	str	r6, [r5, #2048]
10368
+	str	r6, [r5, #2048]
9862
10369
 	bl	FlashReadRawPage
9863
10370
 	cmn	r0, #1
9864
-	beq	.L1675
9865
-	ldr	r3, [sp, #16]
9866
-	cmn	r5, #1
9867
-	moveq	r5, r0
9868
-	ldrb	r3, [r3, #2312]	@ zero_extendqisi2
9869
-	add	r3, r3, r3, asl #1
10371
+	beq	.L1666
10372
+	ldr	r3, [sp, #20]
10373
+	cmn	r4, #1
10374
+	moveq	r4, r0
10375
+	ldrb	r3, [r3, #2316]	@ zero_extendqisi2
10376
+	add	r3, r3, r3, lsl #1
9870
10377
 	cmp	r0, r3, asr #2
9871
-	bcc	.L1686
9872
-	ldr	ip, [sp, #20]
9873
-	mov	r8, ip
9874
-	mov	fp, ip
9875
-.L1675:
9876
-	add	r6, r6, #1
9877
-	cmp	r6, #26
9878
-	bne	.L1678
9879
-	b	.L1677
9880
-.L1686:
9881
-	mov	r5, r0
9882
-.L1677:
9883
-	add	r9, r4, r9
10378
+	bcc	.L1677
10379
+	mov	r9, r6
10380
+	mov	fp, r6
10381
+.L1666:
10382
+	add	r7, r7, #1
10383
+	cmp	r7, #26
10384
+	bne	.L1669
10385
+.L1668:
10386
+	ldr	r3, [sp, #12]
10387
+	add	r8, r3, r8
9884
10388
 	mov	r3, #239
9885
-	str	r3, [r9, #2056]
9886
-	ldr	r3, [sp, #8]
9887
-	add	r4, r4, r3, asl #8
10389
+	str	r3, [r8, #2056]
9888
10390
 	mov	r3, #141
9889
-	b	.L1702
9890
-.L1674:
9891
-	ldr	r3, [sp, #8]
9892
-	mvn	r5, #0
9893
-	ldr	r7, .L1703+8
9894
-	mov	r6, #1
9895
-	mov	ip, r3, asl #8
9896
-	add	r9, r4, ip
9897
-.L1683:
9898
-	mov	r3, #239
9899
-	str	r3, [r9, #2056]
9900
-	mov	r3, #137
9901
-	str	r3, [r9, #2052]
9902
-	ldrb	r3, [r7, #4]	@ zero_extendqisi2
9903
-	mov	r0, r10
9904
-	ldr	r1, [sp, #12]
9905
-	mov	r2, fp
9906
-	str	ip, [sp, #20]
9907
-	str	r3, [r9, #2048]
9908
-	ldrb	r3, [r7, #5]	@ zero_extendqisi2
9909
-	str	r3, [r9, #2048]
9910
-	ldrb	r3, [r7, #6]	@ zero_extendqisi2
9911
-	str	r3, [r9, #2048]
9912
-	ldrb	r3, [r7, #7]	@ zero_extendqisi2
9913
-	str	r3, [r9, #2048]
9914
-	mov	r3, r8
9915
-	bl	FlashReadRawPage
9916
-	cmn	r0, #1
9917
-	ldr	ip, [sp, #20]
9918
-	beq	.L1680
9919
-	ldr	r3, [sp, #16]
9920
-	cmn	r5, #1
9921
-	moveq	r5, r0
9922
-	ldrb	r3, [r3, #2312]	@ zero_extendqisi2
9923
-	add	r3, r3, r3, asl #1
9924
-	cmp	r0, r3, asr #2
9925
-	bcc	.L1687
9926
-	mov	r8, #0
9927
-	mov	fp, r8
9928
-.L1680:
9929
-	add	r6, r6, #1
9930
-	add	r7, r7, #4
9931
-	cmp	r6, #26
9932
-	bne	.L1683
9933
-	b	.L1682
9934
-.L1687:
9935
-	mov	r5, r0
9936
-.L1682:
9937
-	add	ip, r4, ip
9938
-	mov	r3, #239
9939
-	str	r3, [ip, #2056]
9940
-	ldr	r3, [sp, #8]
9941
-	add	r4, r4, r3, asl #8
9942
-	mov	r3, #137
9943
-.L1702:
9944
-	str	r3, [r4, #2052]
10391
+.L1693:
10392
+	str	r3, [r5, #2052]
9945
10393
 	mov	r3, #0
9946
-	str	r3, [r4, #2048]
9947
-	str	r3, [r4, #2048]
9948
-	str	r3, [r4, #2048]
9949
-	str	r3, [r4, #2048]
9950
-	ldr	r3, [sp, #16]
9951
-	ldrb	r3, [r3, #2312]	@ zero_extendqisi2
9952
-	add	r3, r3, r3, asl #1
9953
-	cmp	r5, r3, asr #2
9954
-	bcc	.L1684
9955
-	cmn	r5, #1
9956
-	movne	r5, #256
9957
-.L1684:
9958
-	cmn	r5, #1
9959
-	cmpne	r5, #256
9960
-	bne	.L1685
9961
-	str	r5, [sp]
9962
-	mov	r1, r6
9963
-	ldr	r0, .L1703+12
9964
-	mov	r3, r6
9965
-	ldr	r2, [sp, #12]
10394
+	str	r3, [r5, #2048]
10395
+	str	r3, [r5, #2048]
10396
+	str	r3, [r5, #2048]
10397
+	str	r3, [r5, #2048]
10398
+	ldr	r3, .L1694
10399
+	ldrb	r3, [r3, #2316]	@ zero_extendqisi2
10400
+	add	r3, r3, r3, lsl #1
10401
+	cmp	r4, r3, asr #2
10402
+	bcc	.L1675
10403
+	cmn	r4, #1
10404
+	movne	r4, #256
10405
+.L1675:
10406
+	cmn	r4, #1
10407
+	cmpne	r4, #256
10408
+	bne	.L1676
10409
+	str	r4, [sp]
10410
+	mov	r3, r7
10411
+	ldr	r2, [sp, #16]
10412
+	mov	r1, r7
10413
+	ldr	r0, .L1694+8
9966
10414
 	bl	printk
9967
-.L1685:
10415
+.L1676:
9968
10416
 	mov	r0, r10
9969
10417
 	bl	NandcWaitFlashReady
9970
-	mov	r0, r5
10418
+	mov	r0, r4
9971
10419
 	add	sp, sp, #28
9972
10420
 	@ sp needed
9973
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
9974
-.L1704:
10421
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
10422
+.L1677:
10423
+	mov	r4, r0
10424
+	b	.L1668
10425
+.L1665:
10426
+	ldr	r3, [sp, #12]
10427
+	lsl	r6, r6, #8
10428
+	ldr	r8, .L1694+12
10429
+	mvn	r4, #0
10430
+	mov	r7, #1
10431
+	add	r5, r3, r6
10432
+.L1674:
10433
+	mov	r3, #239
10434
+	mov	r2, fp
10435
+	str	r3, [r5, #2056]
10436
+	mov	r3, #137
10437
+	str	r3, [r5, #2052]
10438
+	mov	r0, r10
10439
+	ldrb	r3, [r8, #4]	@ zero_extendqisi2
10440
+	ldr	r1, [sp, #16]
10441
+	str	r3, [r5, #2048]
10442
+	ldrb	r3, [r8, #5]	@ zero_extendqisi2
10443
+	str	r3, [r5, #2048]
10444
+	ldrb	r3, [r8, #6]	@ zero_extendqisi2
10445
+	str	r3, [r5, #2048]
10446
+	ldrb	r3, [r8, #7]	@ zero_extendqisi2
10447
+	str	r3, [r5, #2048]
10448
+	mov	r3, r9
10449
+	bl	FlashReadRawPage
10450
+	cmn	r0, #1
10451
+	beq	.L1671
10452
+	ldr	r3, .L1694
10453
+	cmn	r4, #1
10454
+	moveq	r4, r0
10455
+	ldrb	r3, [r3, #2316]	@ zero_extendqisi2
10456
+	add	r3, r3, r3, lsl #1
10457
+	cmp	r0, r3, asr #2
10458
+	bcc	.L1678
10459
+	mov	r9, #0
10460
+	mov	fp, r9
10461
+.L1671:
10462
+	add	r7, r7, #1
10463
+	add	r8, r8, #4
10464
+	cmp	r7, #26
10465
+	bne	.L1674
10466
+.L1673:
10467
+	ldr	r3, [sp, #12]
10468
+	add	r6, r3, r6
10469
+	mov	r3, #239
10470
+	str	r3, [r6, #2056]
10471
+	mov	r3, #137
10472
+	b	.L1693
10473
+.L1678:
10474
+	mov	r4, r0
10475
+	b	.L1673
10476
+.L1695:
9975
10477
 	.align	2
9976
-.L1703:
10478
+.L1694:
9977
10479
 	.word	.LANCHOR0
9978
-	.word	.LANCHOR3+16
9979
-	.word	.LANCHOR3+44
10480
+	.word	.LANCHOR3+11
9980
10481
 	.word	.LC95
10482
+	.word	.LANCHOR3+37
9981
10483
 	.fnend
9982
10484
 	.size	samsung_read_retrial, .-samsung_read_retrial
9983
10485
 	.align	2
9984
10486
 	.global	FlashProgPage
10487
+	.syntax unified
10488
+	.arm
10489
+	.fpu softvfp
9985
10490
 	.type	FlashProgPage, %function
9986
10491
 FlashProgPage:
9987
10492
 	.fnstart
9988
10493
 	@ args = 0, pretend = 0, frame = 0
9989
10494
 	@ frame_needed = 0, uses_anonymous_args = 0
9990
-	stmfd	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
10495
+	push	{r0, r1, r4, r5, r6, r7, r8, lr}
9991
10496
 	.save {r4, r5, r6, r7, r8, lr}
9992
10497
 	.pad #8
9993
10498
 	mov	r8, r3
9994
-	ldr	r3, .L1709
10499
+	ldr	r3, .L1700
9995
10500
 	subs	r4, r0, #0
9996
10501
 	mov	r5, r1
9997
10502
 	mov	r7, r2
9998
-	ldrb	r6, [r3, #481]	@ zero_extendqisi2
9999
-	bne	.L1706
10000
-	ldr	r2, .L1709+4
10001
-	ldrb	r3, [r2, #1]	@ zero_extendqisi2
10002
-	ldr	r1, [r2, #4]
10003
-	mul	r1, r1, r3
10004
-	cmp	r5, r1
10005
-	bcs	.L1706
10006
-	ldrb	r3, [r2]	@ zero_extendqisi2
10503
+	ldrb	r6, [r3, #477]	@ zero_extendqisi2
10504
+	bne	.L1697
10505
+	ldr	r1, .L1700+4
10506
+	ldrb	r3, [r1, #37]	@ zero_extendqisi2
10507
+	ldr	r0, [r1, #40]
10508
+	mul	r0, r0, r3
10509
+	cmp	r0, r5
10510
+	bls	.L1697
10511
+	ldrb	r3, [r1, #36]	@ zero_extendqisi2
10007
10512
 	cmp	r3, #0
10008
10513
 	movne	r6, #4
10009
-.L1706:
10514
+.L1697:
10010
10515
 	mov	r0, r4
10011
10516
 	bl	NandcWaitFlashReady
10012
10517
 	mov	r0, r4
10013
10518
 	bl	NandcFlashCs
10014
-	mov	r0, r4
10015
10519
 	mov	r1, r5
10016
-	bl	FlashProgFirstCmd
10017
-	mov	r2, r6
10018
-	mov	r3, r7
10019
10520
 	mov	r0, r4
10020
-	mov	r1, #1
10521
+	bl	FlashProgFirstCmd
10522
+	mov	r3, r7
10523
+	mov	r2, r6
10021
10524
 	str	r8, [sp]
10525
+	mov	r1, #1
10526
+	mov	r0, r4
10022
10527
 	bl	NandcXferData
10023
10528
 	mov	r1, r5
10024
10529
 	mov	r0, r4
..
..
@@ -10028,287 +10533,288 @@
10028
10533
 	mov	r1, r5
10029
10534
 	mov	r0, r4
10030
10535
 	bl	FlashReadStatus
10031
-	mov	r5, r0
10536
+	mov	r1, r0
10032
10537
 	mov	r0, r4
10033
10538
 	bl	NandcFlashDeCs
10034
-	and	r0, r5, #1
10539
+	and	r0, r1, #1
10035
10540
 	add	sp, sp, #8
10036
10541
 	@ sp needed
10037
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
10038
-.L1710:
10542
+	pop	{r4, r5, r6, r7, r8, pc}
10543
+.L1701:
10039
10544
 	.align	2
10040
-.L1709:
10545
+.L1700:
10041
10546
 	.word	.LANCHOR1
10042
10547
 	.word	.LANCHOR0
10043
10548
 	.fnend
10044
10549
 	.size	FlashProgPage, .-FlashProgPage
10045
10550
 	.align	2
10046
10551
 	.global	FlashSavePhyInfo
10552
+	.syntax unified
10553
+	.arm
10554
+	.fpu softvfp
10047
10555
 	.type	FlashSavePhyInfo, %function
10048
10556
 FlashSavePhyInfo:
10049
10557
 	.fnstart
10050
-	@ args = 0, pretend = 0, frame = 8
10558
+	@ args = 0, pretend = 0, frame = 0
10051
10559
 	@ frame_needed = 0, uses_anonymous_args = 0
10052
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
10053
-	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10054
-	.pad #12
10055
-	ldr	r4, .L1725
10056
-	ldr	r5, .L1725+4
10057
-	ldr	r8, .L1725+8
10058
-	ldr	r3, [r4, #1688]
10059
-	mov	fp, r4
10060
-	ldrb	r0, [r4, #1714]	@ zero_extendqisi2
10061
-	mov	r10, r5
10062
-	str	r3, [r4, #1700]
10560
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
10561
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
10562
+	ldr	r4, .L1716
10563
+	ldr	r5, .L1716+4
10564
+	ldr	r3, [r4, #1696]
10565
+	ldrb	r0, [r4, #1722]	@ zero_extendqisi2
10566
+	ldr	r8, .L1716+8
10567
+	str	r3, [r4, #1708]
10063
10568
 	bl	FlashBchSel
10064
-	mov	r1, #0
10065
10569
 	mov	r2, #2048
10066
-	ldr	r0, [r4, #1688]
10570
+	mov	r1, #0
10571
+	ldr	r0, [r4, #1696]
10067
10572
 	bl	ftl_memset
10068
-	ldr	r3, [r4, #1700]
10069
-	ldr	r1, .L1725+12
10573
+	ldr	r3, [r4, #1708]
10070
10574
 	mov	r2, #32
10575
+	ldr	r1, .L1716+12
10071
10576
 	str	r8, [r3]
10072
-	ldr	r0, [r4, #1700]
10073
-	ldrb	r3, [r5, #2230]	@ zero_extendqisi2
10577
+	ldr	r0, [r4, #1708]
10578
+	ldrb	r3, [r5, #2234]	@ zero_extendqisi2
10074
10579
 	add	r0, r0, #16
10075
10580
 	strh	r3, [r0, #-4]	@ movhi
10076
-	ldrb	r3, [r5, #1]	@ zero_extendqisi2
10581
+	ldrb	r3, [r5, #37]	@ zero_extendqisi2
10077
10582
 	strh	r3, [r0, #-2]	@ movhi
10078
-	ldrb	r3, [r5, #2252]	@ zero_extendqisi2
10583
+	ldrb	r3, [r5, #2256]	@ zero_extendqisi2
10079
10584
 	str	r3, [r0, #1060]
10080
10585
 	bl	ftl_memcpy
10081
-	ldr	r0, [r4, #1700]
10082
-	ldr	r1, .L1725+16
10586
+	ldr	r0, [r4, #1708]
10083
10587
 	mov	r2, #8
10588
+	ldr	r1, .L1716+16
10084
10589
 	add	r0, r0, #80
10085
10590
 	bl	ftl_memcpy
10086
-	ldr	r0, [r4, #1700]
10087
-	ldr	r1, .L1725+20
10591
+	ldr	r0, [r4, #1708]
10088
10592
 	mov	r2, #32
10593
+	ldr	r1, .L1716+20
10089
10594
 	add	r0, r0, #96
10090
10595
 	bl	ftl_memcpy
10091
-	ldr	r0, [r4, #1700]
10092
-	ldr	r1, .L1725+24
10596
+	ldr	r0, [r4, #1708]
10093
10597
 	mov	r2, #32
10598
+	ldr	r1, .L1716+24
10094
10599
 	add	r0, r0, #160
10095
10600
 	bl	ftl_memcpy
10096
-	ldr	r0, [r4, #1700]
10097
-	add	r1, r5, #48
10601
+	ldr	r0, [r4, #1708]
10098
10602
 	mov	r2, #32
10603
+	add	r1, r5, #52
10099
10604
 	add	r0, r0, #192
10100
10605
 	bl	ftl_memcpy
10101
-	ldr	r0, [r4, #1700]
10606
+	ldr	r0, [r4, #1708]
10102
10607
 	mov	r2, #852
10103
-	ldr	r1, .L1725+28
10608
+	add	r1, r5, #1216
10104
10609
 	add	r0, r0, #224
10105
10610
 	bl	ftl_memcpy
10106
-	ldr	r6, [r4, #1700]
10611
+	ldr	r6, [r4, #1708]
10107
10612
 	movw	r1, #2036
10108
10613
 	add	r0, r6, #12
10109
10614
 	bl	js_hash
10110
10615
 	movw	r3, #1592
10111
-	str	r3, [r6, #4]
10112
-	ldr	r3, [r4, #1716]
10113
-	str	r3, [r4, #1700]
10114
10616
 	str	r0, [r6, #8]
10115
-	mov	r0, #0
10116
-	bl	flash_enter_slc_mode
10617
+	str	r3, [r6, #4]
10117
10618
 	mov	r6, #0
10619
+	ldr	r3, [r4, #1724]
10118
10620
 	mov	r7, r6
10119
-.L1717:
10120
-	ldr	r1, [r5, #4]
10121
10621
 	mov	r0, #0
10122
-	mov	r2, r0
10622
+	str	r3, [r4, #1708]
10623
+	bl	flash_enter_slc_mode
10624
+.L1708:
10625
+	ldr	r1, [r5, #40]
10626
+	mov	r2, #0
10627
+	mov	r0, r2
10123
10628
 	mul	r1, r1, r7
10124
10629
 	bl	FlashEraseBlock
10125
-	ldrb	r9, [r5, #144]	@ zero_extendqisi2
10630
+	ldrb	r9, [r5, #152]	@ zero_extendqisi2
10126
10631
 	cmp	r9, #0
10127
-	beq	.L1712
10632
+	beq	.L1703
10128
10633
 	mov	r9, #0
10129
-.L1713:
10130
-	ldr	r1, [r5, #4]
10131
-	mov	r0, #0
10132
-	ldr	r2, [r4, #1688]
10133
-	mov	r3, r0
10634
+.L1704:
10635
+	ldr	r1, [r5, #40]
10636
+	mov	r3, #0
10637
+	ldr	r2, [r4, #1696]
10638
+	mov	r0, r3
10134
10639
 	mla	r1, r1, r7, r9
10135
10640
 	add	r9, r9, #1
10136
10641
 	bl	FlashProgPage
10137
10642
 	cmp	r9, #10
10138
-	bne	.L1713
10139
-	b	.L1714
10140
-.L1712:
10141
-	ldr	r1, [r10, #4]
10142
-	mov	r3, r9
10143
-	ldr	r2, [r4, #1688]
10144
-	mov	r0, r9
10145
-	mul	r1, r1, r7
10146
-	bl	FlashProgPage
10147
-	ldr	r1, [r10, #4]
10148
-	mov	r0, r9
10149
-	ldr	r2, [r4, #1688]
10150
-	mov	r3, r9
10151
-	mul	r1, r1, r7
10152
-	add	r1, r1, #1
10153
-	bl	FlashProgPage
10154
-.L1714:
10155
-	ldr	r1, [r5, #4]
10156
-	mov	r0, #0
10157
-	ldr	r2, [r4, #1716]
10158
-	mov	r3, r0
10643
+	bne	.L1704
10644
+.L1705:
10645
+	ldr	r1, [r5, #40]
10646
+	mov	r3, #0
10647
+	ldr	r2, [r4, #1724]
10648
+	mov	r0, r3
10649
+	add	r10, r7, #1
10159
10650
 	mul	r1, r1, r7
10160
10651
 	bl	FlashReadRawPage
10161
-	add	r2, r7, #1
10162
10652
 	cmn	r0, #1
10163
-	beq	.L1715
10164
-	ldr	r9, [fp, #1700]
10653
+	beq	.L1706
10654
+	ldr	r9, [r4, #1708]
10165
10655
 	ldr	r3, [r9]
10166
10656
 	cmp	r3, r8
10167
-	bne	.L1715
10168
-	add	r0, r9, #12
10657
+	bne	.L1706
10169
10658
 	movw	r1, #2036
10170
-	str	r2, [sp, #4]
10659
+	add	r0, r9, #12
10171
10660
 	bl	js_hash
10172
10661
 	ldr	r3, [r9, #8]
10173
10662
 	cmp	r3, r0
10174
-	ldr	r2, [sp, #4]
10175
-	bne	.L1715
10176
-	ldr	r3, [r10, #4]
10663
+	bne	.L1706
10664
+	ldr	r3, [r5, #40]
10177
10665
 	cmp	r6, #1
10178
-	str	r2, [fp, #1708]
10179
-	mul	r7, r3, r7
10180
-	str	r7, [fp, #1704]
10181
-	beq	.L1718
10666
+	str	r10, [r4, #1716]
10667
+	mul	r7, r7, r3
10668
+	str	r7, [r4, #1712]
10669
+	beq	.L1709
10182
10670
 	mov	r6, #1
10183
-.L1715:
10184
-	cmp	r2, #4
10185
-	mov	r7, r2
10186
-	bne	.L1717
10187
-	b	.L1716
10188
-.L1718:
10189
-	mov	r6, #2
10190
-.L1716:
10671
+.L1706:
10672
+	cmp	r10, #4
10673
+	mov	r7, r10
10674
+	bne	.L1708
10675
+.L1707:
10191
10676
 	mov	r0, #0
10192
10677
 	bl	flash_exit_slc_mode
10193
10678
 	clz	r0, r6
10194
-	mov	r0, r0, lsr #5
10679
+	lsr	r0, r0, #5
10195
10680
 	rsb	r0, r0, #0
10196
-	add	sp, sp, #12
10197
-	@ sp needed
10198
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
10199
-.L1726:
10681
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
10682
+.L1703:
10683
+	ldr	r1, [r5, #40]
10684
+	mov	r3, r9
10685
+	ldr	r2, [r4, #1696]
10686
+	mov	r0, r9
10687
+	mul	r1, r1, r7
10688
+	bl	FlashProgPage
10689
+	ldr	r1, [r5, #40]
10690
+	mov	r3, r9
10691
+	ldr	r2, [r4, #1696]
10692
+	mov	r0, r9
10693
+	mul	r1, r1, r7
10694
+	add	r1, r1, #1
10695
+	bl	FlashProgPage
10696
+	b	.L1705
10697
+.L1709:
10698
+	mov	r6, #2
10699
+	b	.L1707
10700
+.L1717:
10200
10701
 	.align	2
10201
-.L1725:
10702
+.L1716:
10202
10703
 	.word	.LANCHOR2
10203
10704
 	.word	.LANCHOR0
10204
10705
 	.word	1312902724
10205
-	.word	.LANCHOR0+2068
10206
-	.word	.LANCHOR0+2232
10207
-	.word	.LANCHOR0+1172
10208
-	.word	.LANCHOR1+472
10209
-	.word	.LANCHOR0+1210
10706
+	.word	.LANCHOR0+2072
10707
+	.word	.LANCHOR0+2236
10708
+	.word	.LANCHOR0+1180
10709
+	.word	.LANCHOR1+468
10210
10710
 	.fnend
10211
10711
 	.size	FlashSavePhyInfo, .-FlashSavePhyInfo
10212
10712
 	.align	2
10213
10713
 	.global	FlashReadIdbDataRaw
10714
+	.syntax unified
10715
+	.arm
10716
+	.fpu softvfp
10214
10717
 	.type	FlashReadIdbDataRaw, %function
10215
10718
 FlashReadIdbDataRaw:
10216
10719
 	.fnstart
10217
10720
 	@ args = 0, pretend = 0, frame = 16
10218
10721
 	@ frame_needed = 0, uses_anonymous_args = 0
10219
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10722
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
10220
10723
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10221
-	mov	r9, r0
10222
-	ldr	r3, .L1747
10724
+	mov	r3, #60
10223
10725
 	.pad #20
10224
10726
 	sub	sp, sp, #20
10225
-	ldr	r4, .L1747+4
10226
-	ldr	r0, [r3]	@ unaligned
10227
-	ldr	r3, [r4, #2248]
10228
-	ldrb	r10, [r4, #2312]	@ zero_extendqisi2
10727
+	ldr	r4, .L1737
10728
+	mov	r10, r0
10729
+	strb	r3, [sp, #12]
10730
+	mov	r3, #40
10731
+	strb	r3, [sp, #13]
10732
+	mov	r3, #24
10733
+	strb	r3, [sp, #14]
10734
+	mov	r3, #16
10735
+	strb	r3, [sp, #15]
10736
+	ldrb	r3, [r4, #2316]	@ zero_extendqisi2
10737
+	str	r3, [sp, #4]
10738
+	ldr	r3, [r4, #2252]
10229
10739
 	cmp	r3, #0
10230
-	str	r0, [sp, #12]	@ unaligned
10231
-	beq	.L1728
10740
+	beq	.L1719
10232
10741
 	mov	r0, #0
10233
10742
 	bl	flash_enter_slc_mode
10234
-.L1728:
10235
-	mov	r0, r9
10236
-	mov	r1, #0
10237
-	mov	r2, #2048
10743
+.L1719:
10744
+	ldr	r6, .L1737+4
10238
10745
 	mvn	r8, #0
10239
-	bl	ftl_memset
10240
10746
 	mov	r5, #2
10241
-.L1729:
10242
-	ldrb	r3, [r4, #1]	@ zero_extendqisi2
10243
-	cmp	r5, r3
10244
-	bcs	.L1733
10245
-	ldr	fp, .L1747+8
10246
-	mov	r7, #0
10247
-.L1731:
10248
-	add	r3, sp, #12
10249
-	ldr	r6, .L1747+8
10250
-	ldrb	ip, [r7, r3]	@ zero_extendqisi2
10251
-	mov	r0, ip
10252
-	str	ip, [sp, #4]
10253
-	bl	FlashBchSel
10254
-	ldr	r1, [r4, #4]
10255
-	mov	r0, #0
10256
-	ldr	r2, [fp, #1688]
10257
-	mov	r3, r0
10258
-	mul	r1, r1, r5
10259
-	bl	FlashReadRawPage
10260
-	cmn	r0, #1
10261
-	ldr	ip, [sp, #4]
10262
-	bne	.L1730
10263
-	add	r7, r7, #1
10264
-	cmp	r7, #4
10265
-	bne	.L1731
10266
-	b	.L1732
10267
-.L1730:
10268
-	ldr	r3, [r6, #1688]
10269
-	ldr	r2, .L1747+12
10270
-	ldr	r3, [r3]
10271
-	cmp	r3, r2
10272
-	bne	.L1732
10273
-	mov	r1, ip
10274
-	ldr	r0, .L1747+16
10275
-	bl	printk
10276
10747
 	mov	r2, #2048
10277
-	mov	r0, r9
10278
-	ldr	r1, [r6, #1688]
10279
-	bl	ftl_memcpy
10280
-	ldr	r3, [r6, #1688]
10281
-	ldr	r2, .L1747+4
10282
-	ldr	r3, [r3, #512]
10283
-	strb	r3, [r2, #1]
10284
-	ldr	r3, [r6, #1708]
10285
-	cmp	r3, r5
10286
-	bls	.L1736
10287
-	str	r5, [r6, #1708]
10288
-	bl	FlashSavePhyInfo
10289
-	mov	r8, #0
10290
-.L1732:
10291
-	add	r5, r5, #1
10292
-	b	.L1729
10293
-.L1736:
10294
-	mov	r8, #0
10295
-.L1733:
10748
+	mov	r1, #0
10296
10749
 	mov	r0, r10
10750
+	bl	ftl_memset
10751
+.L1720:
10752
+	ldrb	r3, [r4, #37]	@ zero_extendqisi2
10753
+	cmp	r5, r3
10754
+	bcc	.L1725
10755
+.L1724:
10756
+	ldr	r0, [sp, #4]
10297
10757
 	bl	FlashBchSel
10298
-	ldr	r3, [r4, #2248]
10758
+	ldr	r3, [r4, #2252]
10299
10759
 	cmp	r3, #0
10300
-	beq	.L1740
10760
+	beq	.L1718
10301
10761
 	mov	r0, #0
10302
10762
 	bl	flash_exit_slc_mode
10303
-.L1740:
10763
+.L1718:
10304
10764
 	mov	r0, r8
10305
10765
 	add	sp, sp, #20
10306
10766
 	@ sp needed
10307
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
10308
-.L1748:
10767
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
10768
+.L1725:
10769
+	mov	r7, #0
10770
+	add	fp, sp, #12
10771
+.L1722:
10772
+	ldrb	r9, [r7, fp]	@ zero_extendqisi2
10773
+	mov	r0, r9
10774
+	bl	FlashBchSel
10775
+	ldr	r1, [r4, #40]
10776
+	mov	r3, #0
10777
+	ldr	r2, [r6, #1696]
10778
+	mov	r0, r3
10779
+	mul	r1, r1, r5
10780
+	bl	FlashReadRawPage
10781
+	cmn	r0, #1
10782
+	bne	.L1721
10783
+	add	r7, r7, #1
10784
+	cmp	r7, #4
10785
+	bne	.L1722
10786
+.L1723:
10787
+	add	r5, r5, #1
10788
+	b	.L1720
10789
+.L1728:
10790
+	mov	r8, #0
10791
+	b	.L1724
10792
+.L1721:
10793
+	ldr	r3, [r6, #1696]
10794
+	ldr	r2, .L1737+8
10795
+	ldr	r3, [r3]
10796
+	cmp	r3, r2
10797
+	bne	.L1723
10798
+	mov	r1, r9
10799
+	ldr	r0, .L1737+12
10800
+	bl	printk
10801
+	mov	r2, #2048
10802
+	ldr	r1, [r6, #1696]
10803
+	mov	r0, r10
10804
+	bl	ftl_memcpy
10805
+	ldr	r3, [r6, #1696]
10806
+	ldr	r3, [r3, #512]
10807
+	strb	r3, [r4, #37]
10808
+	ldr	r3, [r6, #1716]
10809
+	cmp	r5, r3
10810
+	bcs	.L1728
10811
+	str	r5, [r6, #1716]
10812
+	mov	r8, #0
10813
+	bl	FlashSavePhyInfo
10814
+	b	.L1723
10815
+.L1738:
10309
10816
 	.align	2
10310
-.L1747:
10311
-	.word	.LANCHOR3+11
10817
+.L1737:
10312
10818
 	.word	.LANCHOR0
10313
10819
 	.word	.LANCHOR2
10314
10820
 	.word	-52655045
..
..
@@ -10317,846 +10823,823 @@
10317
10823
 	.size	FlashReadIdbDataRaw, .-FlashReadIdbDataRaw
10318
10824
 	.align	2
10319
10825
 	.global	FlashInit
10826
+	.syntax unified
10827
+	.arm
10828
+	.fpu softvfp
10320
10829
 	.type	FlashInit, %function
10321
10830
 FlashInit:
10322
10831
 	.fnstart
10323
-	@ args = 0, pretend = 0, frame = 0
10832
+	@ args = 0, pretend = 0, frame = 8
10324
10833
 	@ frame_needed = 0, uses_anonymous_args = 0
10325
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10834
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
10326
10835
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10327
-	mov	r5, r0
10328
-	.pad #20
10329
-	sub	sp, sp, #20
10836
+	mov	r7, r0
10837
+	ldr	r5, .L1837
10838
+	.pad #28
10839
+	sub	sp, sp, #28
10840
+	mov	r0, #32768
10841
+	mov	r6, #0
10842
+	bl	ftl_malloc
10843
+	str	r0, [r5, #1696]
10330
10844
 	mov	r0, #32768
10331
10845
 	bl	ftl_malloc
10332
-	ldr	r8, .L1848
10333
-	ldr	r4, .L1848+4
10334
-	mov	r7, #0
10335
-	add	r9, r4, #12
10336
-	str	r0, [r8, #1688]
10337
-	mov	r0, #32768
10338
-	bl	ftl_malloc
10339
-	str	r0, [r8, #1716]
10846
+	str	r0, [r5, #1724]
10340
10847
 	mov	r0, #4096
10341
-	bl	ftl_malloc
10342
-	str	r0, [r8, #1720]
10848
+	bl	ftl_dma32_malloc
10849
+	str	r0, [r5, #1728]
10343
10850
 	mov	r0, #32768
10344
10851
 	bl	ftl_malloc
10345
-	str	r0, [r8, #1724]
10852
+	ldr	r4, .L1837+4
10853
+	mov	r8, r6
10854
+	str	r0, [r5, #1732]
10346
10855
 	mov	r0, #4096
10347
-	bl	ftl_malloc
10856
+	bl	ftl_dma32_malloc
10857
+	ldr	fp, .L1837+8
10348
10858
 	mov	r3, #50
10349
-	str	r7, [r8, #1708]
10350
-	strb	r3, [r4, #1]
10351
-	strb	r3, [r8, #1712]
10859
+	str	r0, [r5, #1736]
10860
+	mov	r0, r7
10861
+	ldr	r7, .L1837+12
10862
+	strb	r3, [r4, #37]
10863
+	strb	r3, [r5, #1720]
10352
10864
 	mov	r3, #128
10353
-	strb	r7, [r4, #2252]
10354
-	str	r3, [r4, #4]
10865
+	str	r3, [r4, #40]
10355
10866
 	mov	r3, #60
10356
-	str	r7, [r8, #1692]
10357
-	strb	r7, [r4]
10358
-	strb	r7, [r8, #1732]
10359
-	strb	r3, [r8, #1714]
10360
-	str	r0, [r8, #1728]
10361
-	mov	r0, r5
10867
+	str	r6, [r5, #1716]
10868
+	strb	r6, [r4, #2256]
10869
+	str	r6, [r5, #1700]
10870
+	strb	r6, [r4, #36]
10871
+	strb	r6, [r5, #1740]
10872
+	strb	r3, [r5, #1722]
10362
10873
 	bl	NandcInit
10363
-	ldr	r5, .L1848+8
10364
-.L1755:
10365
-	add	r3, r9, r7, asl #3
10366
-	uxtb	fp, r7
10367
-	ldr	r6, [r9, r7, asl #3]
10368
-	ldrb	r10, [r3, #4]	@ zero_extendqisi2
10369
-	mov	r0, fp
10874
+.L1745:
10875
+	add	r2, r4, r6, lsl #3
10876
+	uxtb	r9, r6
10877
+	ldr	r10, [r4, r6, lsl #3]
10878
+	ldrb	r2, [r2, #4]	@ zero_extendqisi2
10879
+	mov	r0, r9
10880
+	str	r2, [sp, #20]
10370
10881
 	bl	FlashReset
10371
-	mov	r0, fp
10882
+	mov	r0, r9
10372
10883
 	bl	NandcFlashCs
10884
+	ldr	r2, [sp, #20]
10373
10885
 	mov	r3, #144
10374
-	add	r6, r6, r10, asl #8
10375
10886
 	mov	r0, #200
10376
-	mov	r10, #0
10377
-	str	r3, [r6, #2056]
10378
-	str	r10, [r6, #2052]
10379
-	bl	NandcDelayns
10380
-	ldr	r2, [r6, #2048]
10887
+	add	r10, r10, r2, lsl #8
10888
+	str	r3, [r10, #2056]
10889
+	str	r8, [r10, #2052]
10890
+	bl	ndelay
10891
+	ldr	r2, [r10, #2048]
10381
10892
 	uxtb	r2, r2
10382
-	strb	r2, [r5]
10383
-	ldr	r1, [r6, #2048]
10893
+	strb	r2, [r7]
10384
10894
 	cmp	r2, #44
10385
-	strb	r1, [r5, #1]
10386
-	ldr	r1, [r6, #2048]
10387
-	strb	r1, [r5, #2]
10388
-	ldr	r1, [r6, #2048]
10389
-	strb	r1, [r5, #3]
10390
-	ldr	r1, [r6, #2048]
10391
-	strb	r1, [r5, #4]
10392
-	ldr	r1, [r6, #2048]
10393
-	strb	r1, [r5, #5]
10394
-	bne	.L1750
10895
+	ldr	r1, [r10, #2048]
10896
+	strb	r1, [r7, #1]
10897
+	ldr	r1, [r10, #2048]
10898
+	strb	r1, [r7, #2]
10899
+	ldr	r1, [r10, #2048]
10900
+	strb	r1, [r7, #3]
10901
+	ldr	r1, [r10, #2048]
10902
+	strb	r1, [r7, #4]
10903
+	ldr	r1, [r10, #2048]
10904
+	strb	r1, [r7, #5]
10905
+	bne	.L1740
10395
10906
 	mov	r2, #239
10396
10907
 	mov	r0, #200
10397
-	str	r2, [r6, #2056]
10908
+	str	r2, [r10, #2056]
10398
10909
 	mov	r2, #1
10399
-	str	r2, [r6, #2052]
10400
-	bl	NandcDelayns
10910
+	str	r2, [r10, #2052]
10911
+	bl	ndelay
10401
10912
 	mov	r2, #4
10402
-	str	r2, [r6, #2048]
10403
-	str	r10, [r6, #2048]
10404
-	str	r10, [r6, #2048]
10405
-	str	r10, [r6, #2048]
10406
-.L1750:
10407
-	mov	r0, fp
10913
+	str	r2, [r10, #2048]
10914
+	str	r8, [r10, #2048]
10915
+	str	r8, [r10, #2048]
10916
+	str	r8, [r10, #2048]
10917
+.L1740:
10918
+	mov	r0, r9
10408
10919
 	bl	NandcFlashDeCs
10409
-	ldrb	r2, [r5]	@ zero_extendqisi2
10920
+	ldrb	r2, [r7]	@ zero_extendqisi2
10410
10921
 	sub	r3, r2, #1
10411
10922
 	uxtb	r3, r3
10412
10923
 	cmp	r3, #253
10413
-	bhi	.L1751
10414
-	ldrb	r1, [r5, #2]	@ zero_extendqisi2
10415
-	ldrb	r3, [r5, #1]	@ zero_extendqisi2
10416
-	ldr	r0, .L1848+12
10417
-	str	r1, [sp]
10418
-	ldrb	r1, [r5, #3]	@ zero_extendqisi2
10419
-	str	r1, [sp, #4]
10420
-	ldrb	r1, [r5, #4]	@ zero_extendqisi2
10421
-	str	r1, [sp, #8]
10422
-	ldrb	r1, [r5, #5]	@ zero_extendqisi2
10924
+	bhi	.L1741
10925
+	ldrb	r1, [r7, #5]	@ zero_extendqisi2
10926
+	mov	r0, fp
10927
+	ldrb	r3, [r7, #1]	@ zero_extendqisi2
10423
10928
 	str	r1, [sp, #12]
10424
-	add	r1, r7, #1
10929
+	ldrb	r1, [r7, #4]	@ zero_extendqisi2
10930
+	str	r1, [sp, #8]
10931
+	ldrb	r1, [r7, #3]	@ zero_extendqisi2
10932
+	str	r1, [sp, #4]
10933
+	ldrb	r1, [r7, #2]	@ zero_extendqisi2
10934
+	str	r1, [sp]
10935
+	add	r1, r6, #1
10425
10936
 	bl	printk
10426
-.L1751:
10427
-	cmp	r7, #0
10428
-	bne	.L1752
10429
-	ldrb	r3, [r4, #2068]	@ zero_extendqisi2
10937
+.L1741:
10938
+	cmp	r6, #0
10939
+	bne	.L1742
10940
+	ldrb	r3, [r4, #2072]	@ zero_extendqisi2
10430
10941
 	sub	r3, r3, #1
10431
10942
 	uxtb	r3, r3
10432
10943
 	cmp	r3, #253
10433
-	bhi	.L1802
10434
-	ldr	r3, .L1848+4
10435
-	ldrb	r3, [r3, #2069]	@ zero_extendqisi2
10944
+	bhi	.L1792
10945
+	ldrb	r3, [r4, #2073]	@ zero_extendqisi2
10436
10946
 	cmp	r3, #255
10437
-	beq	.L1802
10438
-.L1752:
10439
-	ldrb	r3, [r5]	@ zero_extendqisi2
10440
-	add	r7, r7, #1
10441
-	add	r5, r5, #8
10947
+	beq	.L1792
10948
+.L1742:
10949
+	ldrb	r3, [r7]	@ zero_extendqisi2
10950
+	add	r6, r6, #1
10951
+	add	r7, r7, #8
10442
10952
 	cmp	r3, #181
10443
10953
 	moveq	r3, #44
10444
-	streqb	r3, [r5, #-8]
10445
-	cmp	r7, #4
10446
-	bne	.L1755
10447
-	ldrb	r3, [r4, #2068]	@ zero_extendqisi2
10954
+	strbeq	r3, [r7, #-8]
10955
+	cmp	r6, #4
10956
+	bne	.L1745
10957
+	ldrb	r3, [r4, #2072]	@ zero_extendqisi2
10448
10958
 	cmp	r3, #173
10449
-	beq	.L1756
10450
-	ldr	r3, .L1848+4
10451
-	ldr	r0, [r3, #2256]
10959
+	beq	.L1746
10960
+	ldr	r0, [r4, #2260]
10452
10961
 	bl	NandcSetDdrMode
10453
-.L1756:
10962
+.L1746:
10454
10963
 	mov	r2, #852
10455
-	ldr	r0, .L1848+16
10456
10964
 	mov	r1, #0
10457
-	ldr	r5, .L1848+20
10965
+	ldr	r0, .L1837+16
10458
10966
 	bl	ftl_memset
10459
-	ldr	r2, [r4, #2264]
10460
-	ldr	r0, .L1848+24
10461
-	cmp	r2, r5
10462
-	add	r3, r0, #472
10463
-	str	r3, [r4, #44]
10967
+	ldr	r6, .L1837+20
10968
+	ldr	r2, .L1837+24
10969
+	ldr	r0, [r4, #2268]
10970
+	add	r3, r2, #468
10971
+	cmp	r0, r6
10972
+	str	r3, [r4, #48]
10464
10973
 	mov	r3, #0
10465
-	strb	r3, [r4, #8]
10466
-	bne	.L1757
10467
-	ldrb	r3, [r0, #491]	@ zero_extendqisi2
10974
+	strb	r3, [r4, #44]
10975
+	bne	.L1747
10976
+	ldrb	r3, [r2, #487]	@ zero_extendqisi2
10468
10977
 	cmp	r3, #50
10469
-	ldrne	r3, .L1848+4
10470
-	movne	r1, #1
10471
-	strne	r1, [r3, #2248]
10472
-.L1757:
10473
-	ldrb	r6, [r4, #2069]	@ zero_extendqisi2
10474
-	sub	ip, r6, #218
10475
-	cmp	r6, #161
10476
-	cmpne	r6, #241
10477
-	clz	ip, ip
10478
-	and	r1, r6, #253
10479
-	moveq	r3, #1
10480
-	movne	r3, #0
10481
-	mov	ip, ip, lsr #5
10482
-	orr	r3, ip, r3
10483
-	cmp	r1, #209
10484
-	orreq	r3, r3, #1
10485
-	cmp	r3, #0
10486
-	bne	.L1758
10487
-	cmp	r6, #220
10488
-	bne	.L1759
10489
-	ldr	r3, .L1848+4
10490
-	ldrb	r3, [r3, #2071]	@ zero_extendqisi2
10491
-	cmp	r3, #149
10492
-	bne	.L1759
10493
-.L1758:
10494
-	mov	lr, #16
10495
-	strb	lr, [r4, #1]
10496
-	strb	lr, [r8, #1714]
10978
+	movne	r3, #1
10979
+	strne	r3, [r4, #2252]
10980
+.L1747:
10981
+	ldrb	r3, [r4, #2073]	@ zero_extendqisi2
10982
+	cmp	r3, #241
10983
+	cmpne	r3, #161
10984
+	and	ip, r3, #253
10985
+	moveq	r1, #1
10986
+	movne	r1, #0
10987
+	cmp	r3, #218
10988
+	orreq	r1, r1, #1
10989
+	cmp	ip, #209
10990
+	orreq	r1, r1, #1
10991
+	cmp	r1, #0
10992
+	bne	.L1748
10993
+	cmp	r3, #220
10994
+	bne	.L1749
10995
+	ldrb	r1, [r4, #2075]	@ zero_extendqisi2
10996
+	cmp	r1, #149
10997
+	bne	.L1749
10998
+.L1748:
10999
+	mov	ip, #16
10497
11000
 	mov	r1, #1
10498
-	ldrb	lr, [r4, #2068]	@ zero_extendqisi2
10499
-	strb	r1, [r4]
10500
-	cmp	lr, #152
10501
-	ldr	r3, .L1848
10502
-	strb	lr, [r0, #3417]
10503
-	strb	r6, [r0, #3418]
10504
-	bne	.L1761
10505
-	ldr	r7, .L1848+4
10506
-	movw	lr, #2072
10507
-	ldrsb	lr, [r7, lr]
10508
-	cmp	lr, #0
10509
-	strltb	r1, [r3, #1732]
10510
-	movge	r1, #24
10511
-	strgeb	r1, [r3, #1714]
10512
-.L1761:
10513
-	movw	r3, #2049
10514
-	cmp	r2, r5
10515
-	cmpne	r2, r3
10516
-	moveq	r3, #16
10517
-	streqb	r3, [r8, #1714]
10518
-	cmp	ip, #0
10519
-	ldrne	r3, .L1848+28
10520
-	movne	r2, #2048
10521
-	strneh	r2, [r3, #14]	@ movhi
10522
-	mvnne	r3, #37
10523
-	bne	.L1842
10524
-.L1765:
10525
-	cmp	r6, #220
10526
-	bne	.L1767
10527
-	ldr	r3, .L1848+28
10528
-	mov	r2, #4096
10529
-	strh	r2, [r3, #14]	@ movhi
10530
-	mvn	r3, #35
10531
-.L1842:
10532
-	strb	r3, [r0, #3418]
10533
-	b	.L1766
10534
-.L1767:
10535
-	cmp	r6, #211
10536
-	ldreq	r3, .L1848+28
10537
-	moveq	r2, #4096
10538
-	streqh	r2, [r3, #14]	@ movhi
10539
-	moveq	r3, #2
10540
-	streqb	r3, [r0, #3429]
10541
-.L1766:
10542
-	ldr	r1, .L1848+32
11001
+	strb	ip, [r4, #37]
11002
+	strb	ip, [r5, #1722]
11003
+	ldrb	ip, [r4, #2072]	@ zero_extendqisi2
11004
+	strb	r1, [r4, #36]
11005
+	strb	r3, [r2, #3414]
11006
+	cmp	ip, #152
11007
+	strb	ip, [r2, #3413]
11008
+	bne	.L1751
11009
+	ldrb	ip, [r4, #2076]	@ zero_extendqisi2
11010
+	lsrs	ip, ip, #7
11011
+	moveq	r1, #24
11012
+	strbne	r1, [r5, #1740]
11013
+	strbeq	r1, [r5, #1722]
11014
+.L1751:
11015
+	movw	r1, #2049
11016
+	cmp	r0, r1
11017
+	cmpne	r0, r6
11018
+	moveq	r1, #16
11019
+	strbeq	r1, [r5, #1722]
11020
+	cmp	r3, #218
11021
+	bne	.L1755
11022
+	ldr	r3, .L1837+28
11023
+	mov	r1, #2048
11024
+	strh	r1, [r3, #14]	@ movhi
11025
+	mvn	r3, #37
11026
+.L1831:
11027
+	strb	r3, [r2, #3414]
11028
+.L1756:
10543
11029
 	mov	r2, #32
10544
-	ldr	r0, .L1848+36
11030
+	ldr	r1, .L1837+32
11031
+	ldr	r0, .L1837+36
10545
11032
 	bl	ftl_memcpy
10546
-	ldr	r0, .L1848+40
11033
+	ldr	r1, .L1837+28
10547
11034
 	mov	r2, #32
10548
-	add	r1, r0, #2944
11035
+	sub	r0, r1, #2944
10549
11036
 	bl	ftl_memcpy
10550
-.L1759:
10551
-	ldrb	r3, [r4]	@ zero_extendqisi2
10552
-	ldr	r6, .L1848+4
11037
+.L1749:
11038
+	ldrb	r3, [r4, #36]	@ zero_extendqisi2
10553
11039
 	cmp	r3, #0
10554
-	bne	.L1768
11040
+	bne	.L1759
10555
11041
 	bl	FlashLoadPhyInfoInRam
10556
11042
 	cmp	r0, #0
10557
-	bne	.L1770
10558
-	ldr	r3, [r6, #44]
11043
+	bne	.L1761
11044
+	ldr	r3, [r4, #48]
10559
11045
 	ldrh	r3, [r3, #16]
10560
-	mov	r3, r3, lsr #8
11046
+	lsr	r3, r3, #8
10561
11047
 	tst	r3, #1
10562
11048
 	and	r0, r3, #7
10563
-	strb	r0, [r6, #2229]
10564
-	bne	.L1770
11049
+	strb	r0, [r4, #2233]
11050
+	bne	.L1761
10565
11051
 	mov	r3, #1
10566
-	strb	r3, [r6, #2252]
11052
+	strb	r3, [r4, #2256]
10567
11053
 	bl	FlashSetInterfaceMode
10568
-	ldrb	r0, [r6, #2229]	@ zero_extendqisi2
11054
+	ldrb	r0, [r4, #2233]	@ zero_extendqisi2
10569
11055
 	bl	NandcSetMode
10570
-.L1770:
10571
-	ldr	r3, [r4, #44]
10572
-	ldr	r6, .L1848+4
11056
+.L1761:
11057
+	ldr	r3, [r4, #48]
10573
11058
 	ldrb	r3, [r3, #26]	@ zero_extendqisi2
10574
-	strb	r3, [r4, #144]
11059
+	strb	r3, [r4, #152]
10575
11060
 	bl	FlashLoadPhyInfo
10576
11061
 	cmp	r0, #0
10577
-	beq	.L1768
10578
-	ldr	r3, [r6, #2256]
11062
+	beq	.L1759
11063
+	ldr	r3, [r4, #2260]
10579
11064
 	cmp	r3, #0
10580
-	beq	.L1773
11065
+	beq	.L1764
10581
11066
 	mov	r0, #1
10582
11067
 	bl	FlashSetInterfaceMode
10583
11068
 	mov	r0, #1
10584
-	b	.L1843
10585
-.L1773:
10586
-	ldrb	r0, [r6, #2229]	@ zero_extendqisi2
10587
-	bl	FlashSetInterfaceMode
10588
-	ldrb	r0, [r6, #2229]	@ zero_extendqisi2
10589
-.L1843:
11069
+.L1832:
10590
11070
 	bl	NandcSetMode
10591
11071
 	bl	FlashLoadPhyInfo
10592
11072
 	cmp	r0, #0
10593
-	beq	.L1768
11073
+	beq	.L1759
10594
11074
 	mov	r0, #1
10595
-	ldr	r6, .L1848+4
10596
11075
 	bl	FlashSetInterfaceMode
10597
11076
 	mov	r0, #1
10598
11077
 	bl	NandcSetMode
10599
-	ldr	r3, [r4, #44]
10600
-	ldr	r0, .L1848+44
11078
+	ldr	r3, [r4, #48]
11079
+	ldr	r0, .L1837+40
10601
11080
 	ldrh	r1, [r3, #14]
10602
11081
 	bl	printk
10603
11082
 	bl	FlashLoadPhyInfoInRam
10604
11083
 	cmn	r0, #1
10605
-	beq	.L1816
11084
+	beq	.L1739
10606
11085
 	bl	FlashDieInfoInit
10607
-	ldr	r3, [r6, #44]
11086
+	ldr	r3, [r4, #48]
10608
11087
 	ldrb	r0, [r3, #19]	@ zero_extendqisi2
10609
11088
 	bl	FlashGetReadRetryDefault
10610
-	ldr	r3, .L1848+48
10611
-	ldr	r2, [r6, #44]
11089
+	ldr	r3, .L1837+44
11090
+	ldr	r2, [r4, #48]
10612
11091
 	ldrh	r3, [r3, #-2]
10613
11092
 	ldrb	r1, [r2, #9]	@ zero_extendqisi2
10614
11093
 	add	r3, r3, #4080
10615
11094
 	add	r3, r3, #15
10616
11095
 	cmp	r1, r3, asr #12
10617
11096
 	ldrh	r3, [r2, #14]
10618
-	blt	.L1775
11097
+	blt	.L1766
10619
11098
 	add	r0, r3, #255
10620
11099
 	cmp	r1, r0, asr #8
10621
-	bge	.L1776
10622
-.L1775:
11100
+	bge	.L1767
11101
+.L1766:
10623
11102
 	bic	r3, r3, #255
10624
11103
 	strh	r3, [r2, #14]	@ movhi
10625
-.L1776:
10626
-	ldrb	r3, [r4, #2229]	@ zero_extendqisi2
11104
+.L1767:
11105
+	ldrb	r3, [r4, #2233]	@ zero_extendqisi2
10627
11106
 	tst	r3, #6
10628
-	beq	.L1777
11107
+	beq	.L1768
10629
11108
 	bl	FlashSavePhyInfo
10630
11109
 	mov	r0, #0
10631
11110
 	bl	flash_enter_slc_mode
11111
+	ldr	r1, [r5, #1712]
10632
11112
 	mov	r0, #0
10633
-	ldr	r1, [r8, #1704]
10634
11113
 	bl	FlashDdrParaScan
10635
11114
 	mov	r0, #0
10636
11115
 	bl	flash_exit_slc_mode
10637
-.L1777:
10638
-	bl	FlashSavePhyInfo
10639
11116
 .L1768:
10640
-	ldr	r2, [r4, #44]
10641
-	ldr	r7, .L1848+4
10642
-	ldr	r6, .L1848
10643
-	ldrb	r3, [r2, #26]	@ zero_extendqisi2
10644
-	ldrh	r0, [r2, #10]
10645
-	ldrb	r9, [r2, #18]	@ zero_extendqisi2
10646
-	strb	r3, [r4, #144]
10647
-	ldrh	r3, [r2, #16]
10648
-	ubfx	r1, r3, #7, #1
10649
-	strb	r1, [r4, #8]
10650
-	ubfx	r1, r3, #3, #1
10651
-	strb	r1, [r8, #1733]
10652
-	ubfx	r1, r3, #4, #1
11117
+	bl	FlashSavePhyInfo
11118
+.L1759:
11119
+	ldr	r7, [r4, #48]
11120
+	ldrb	r3, [r7, #26]	@ zero_extendqisi2
11121
+	ldrb	r1, [r7, #12]	@ zero_extendqisi2
11122
+	ldrh	r0, [r7, #10]
11123
+	strb	r3, [r4, #152]
11124
+	ldrh	r3, [r7, #16]
11125
+	ubfx	r2, r3, #7, #1
11126
+	strb	r2, [r4, #44]
11127
+	ubfx	r2, r3, #3, #1
11128
+	strb	r2, [r5, #1741]
11129
+	ubfx	r2, r3, #4, #1
10653
11130
 	ubfx	r3, r3, #8, #3
10654
-	strb	r1, [r4, #2240]
10655
-	strb	r3, [r4, #2229]
11131
+	strb	r2, [r4, #2244]
11132
+	strb	r3, [r4, #2233]
10656
11133
 	mov	r3, #0
10657
-	ldrb	r1, [r2, #12]	@ zero_extendqisi2
10658
-	str	r3, [r8, #1696]
11134
+	str	r3, [r5, #1704]
10659
11135
 	bl	__aeabi_idiv
10660
11136
 	mov	r1, r0
10661
-	mov	r0, r9
11137
+	ldrb	r0, [r7, #18]	@ zero_extendqisi2
10662
11138
 	bl	BuildFlashLsbPageTable
10663
11139
 	bl	FlashDieInfoInit
10664
-	ldr	r3, [r4, #44]
11140
+	ldr	r3, [r4, #48]
10665
11141
 	ldrh	r2, [r3, #16]
10666
11142
 	tst	r2, #64
10667
-	beq	.L1779
11143
+	beq	.L1770
10668
11144
 	ldrb	r0, [r3, #19]	@ zero_extendqisi2
10669
-	ldrb	r3, [r7, #1211]	@ zero_extendqisi2
10670
-	strb	r0, [r7, #1208]
10671
-	strb	r3, [r7, #1209]
10672
-	ldrb	r3, [r7, #1212]	@ zero_extendqisi2
10673
-	strb	r3, [r6, #1713]
11145
+	ldrb	r3, [r4, #1217]	@ zero_extendqisi2
11146
+	strb	r0, [r4, #84]
11147
+	strb	r3, [r4, #85]
11148
+	ldrb	r3, [r4, #1218]	@ zero_extendqisi2
11149
+	strb	r3, [r5, #1721]
10674
11150
 	sub	r3, r0, #1
10675
11151
 	cmp	r3, #7
10676
-	bhi	.L1780
10677
-	ldr	r3, .L1848+52
10678
-	str	r3, [r6, #1696]
11152
+	bhi	.L1771
11153
+	ldr	r3, .L1837+48
11154
+	str	r3, [r5, #1704]
10679
11155
 	sub	r3, r0, #5
10680
11156
 	cmp	r0, #8
10681
11157
 	cmpne	r3, #1
10682
-	sub	r6, r0, #8
10683
-	clz	r6, r6
10684
11158
 	movls	r3, #1
10685
-	strls	r3, [r7, #2304]
11159
+	strls	r3, [r4, #2308]
10686
11160
 	cmp	r0, #7
10687
-	mov	r6, r6, lsr #5
10688
-	ldreq	r6, .L1848+56
10689
-	beq	.L1783
10690
-	ldr	r3, .L1848+56
10691
-	cmp	r6, #0
10692
-	sub	r2, r3, #8
10693
-	movne	r6, r3
10694
-	moveq	r6, r2
10695
-.L1783:
10696
-	sub	r2, r6, #1
10697
-	add	r6, r6, #31
10698
-	mov	r3, #0
10699
-.L1784:
10700
-	ldrsb	r1, [r2, #1]!
10701
-	cmp	r1, #0
10702
-	addeq	r3, r3, #1
10703
-	cmp	r2, r6
10704
-	bne	.L1784
10705
-	cmp	r3, #27
10706
-	bls	.L1779
11161
+	ldr	r3, .L1837+16
11162
+	beq	.L1793
11163
+	cmp	r0, #8
11164
+	addne	r3, r3, #20
11165
+	bne	.L1773
11166
+.L1793:
11167
+	add	r3, r3, #28
11168
+.L1773:
11169
+	sub	r1, r3, #1
11170
+	mov	r2, #0
11171
+	add	r3, r3, #31
11172
+.L1775:
11173
+	ldrsb	ip, [r1, #1]!
11174
+	cmp	ip, #0
11175
+	addeq	r2, r2, #1
11176
+	cmp	r3, r1
11177
+	bne	.L1775
11178
+	cmp	r2, #27
11179
+	bls	.L1770
10707
11180
 	bl	FlashGetReadRetryDefault
10708
11181
 	bl	FlashSavePhyInfo
10709
-	b	.L1779
10710
-.L1780:
10711
-	sub	r3, r0, #17
10712
-	cmp	r3, #2
10713
-	bhi	.L1786
10714
-	ldr	r3, .L1848+60
10715
-	cmp	r0, #19
10716
-	str	r3, [r6, #1696]
10717
-	moveq	r3, #15
10718
-	bne	.L1847
10719
-	b	.L1845
10720
-.L1786:
10721
-	sub	r3, r0, #65
10722
-	cmp	r0, #33
10723
-	cmpne	r3, #1
10724
-	bhi	.L1788
10725
-	ldr	r3, .L1848+64
10726
-	str	r3, [r6, #1696]
10727
-	mov	r3, #4
10728
-	strb	r3, [r7, #1209]
10729
-.L1847:
10730
-	mov	r3, #7
10731
-.L1845:
10732
-	strb	r3, [r6, #1713]
10733
-	b	.L1779
10734
-.L1788:
10735
-	sub	r2, r0, #67
10736
-	sub	r3, r0, #34
10737
-	cmp	r2, #1
10738
-	movhi	r2, #0
10739
-	movls	r2, #1
10740
-	cmp	r3, #1
10741
-	movhi	r3, r2
10742
-	orrls	r3, r2, #1
10743
-	cmp	r3, #0
10744
-	beq	.L1789
10745
-	ldr	r3, .L1848+64
10746
-	cmp	r0, #68
10747
-	cmpne	r0, #35
10748
-	str	r3, [r6, #1696]
10749
-	movne	r3, #7
10750
-	moveq	r3, #17
11182
+.L1770:
11183
+	ldr	r3, [r4, #2268]
11184
+	cmp	r3, r6
11185
+	bne	.L1785
11186
+	ldrb	r2, [r4, #152]	@ zero_extendqisi2
10751
11187
 	cmp	r2, #0
10752
-	strb	r3, [r6, #1713]
10753
-	movne	r3, #4
10754
-	moveq	r3, #5
10755
-	strb	r3, [r4, #1209]
10756
-	b	.L1779
10757
-.L1789:
10758
-	cmp	r0, #49
10759
-	ldreq	r3, .L1848+68
10760
-	streq	r3, [r6, #1696]
10761
-	beq	.L1779
10762
-	cmp	r0, #50
10763
-	streq	r3, [r7, #2248]
10764
-	ldreq	r2, .L1848+72
10765
-	streq	r2, [r6, #1696]
10766
-.L1779:
10767
-	ldr	r2, [r4, #2264]
10768
-	ldr	r3, .L1848+4
10769
-	cmp	r2, r5
10770
-	bne	.L1794
10771
-	ldrb	r1, [r3, #144]	@ zero_extendqisi2
10772
-	cmp	r1, #0
10773
-	ldrne	r3, [r3, #44]
11188
+	ldrne	r2, [r4, #48]
10774
11189
 	movne	r1, #0
10775
-	strneb	r1, [r3, #18]
10776
-.L1794:
10777
-	ldrb	r1, [r4, #2068]	@ zero_extendqisi2
10778
-	ldr	r3, .L1848+4
10779
-	cmp	r1, #44
10780
-	bne	.L1795
10781
-	ldrb	r1, [r3, #2252]	@ zero_extendqisi2
10782
-	cmp	r1, #0
10783
-	beq	.L1795
10784
-	cmp	r2, r5
10785
-	bne	.L1796
10786
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
11190
+	strbne	r1, [r2, #18]
11191
+.L1785:
11192
+	ldrb	r2, [r4, #2072]	@ zero_extendqisi2
11193
+	cmp	r2, #44
11194
+	bne	.L1786
11195
+	ldrb	r2, [r4, #2256]	@ zero_extendqisi2
11196
+	cmp	r2, #0
11197
+	beq	.L1786
11198
+	cmp	r3, r6
11199
+	bne	.L1787
11200
+	ldrb	r3, [r4, #152]	@ zero_extendqisi2
10787
11201
 	cmp	r3, #0
10788
-	bne	.L1795
10789
-.L1796:
10790
-	mov	r0, #1
11202
+	bne	.L1786
11203
+.L1787:
10791
11204
 	mov	r3, #0
10792
-	strb	r3, [r4, #2252]
11205
+	mov	r0, #1
11206
+	strb	r3, [r4, #2256]
10793
11207
 	bl	FlashSetInterfaceMode
10794
11208
 	mov	r0, #1
10795
11209
 	bl	NandcSetMode
10796
-.L1795:
10797
-	ldrb	r3, [r4, #2229]	@ zero_extendqisi2
11210
+.L1786:
11211
+	ldrb	r3, [r4, #2233]	@ zero_extendqisi2
10798
11212
 	tst	r3, #6
10799
-	beq	.L1797
10800
-	ldr	r2, .L1848+4
10801
-	ldrb	r2, [r2, #2252]	@ zero_extendqisi2
11213
+	beq	.L1788
11214
+	ldrb	r2, [r4, #2256]	@ zero_extendqisi2
10802
11215
 	cmp	r2, #0
10803
-	bne	.L1798
11216
+	bne	.L1789
10804
11217
 	tst	r3, #1
10805
-	bne	.L1797
10806
-.L1798:
11218
+	bne	.L1788
11219
+.L1789:
10807
11220
 	mov	r0, #0
10808
11221
 	bl	flash_enter_slc_mode
11222
+	ldr	r1, [r5, #1712]
10809
11223
 	mov	r0, #0
10810
-	ldr	r1, [r8, #1704]
10811
11224
 	bl	FlashDdrParaScan
10812
11225
 	mov	r0, #0
10813
11226
 	bl	flash_exit_slc_mode
10814
-.L1797:
10815
-	ldr	r3, [r4, #44]
10816
-	mov	r7, #16
10817
-	ldr	r6, .L1848+4
11227
+.L1788:
11228
+	ldr	r3, [r4, #48]
11229
+	mov	r6, #16
10818
11230
 	ldrb	r0, [r3, #20]	@ zero_extendqisi2
10819
11231
 	bl	FlashBchSel
10820
-	ldr	r0, .L1848+76
11232
+	ldr	r0, .L1837+52
10821
11233
 	bl	FlashReadIdbDataRaw
10822
-	ldr	r0, .L1848+80
10823
-	strb	r7, [r4, #1]
11234
+	ldr	r0, .L1837+56
11235
+	strb	r6, [r4, #37]
10824
11236
 	bl	FlashTimingCfg
10825
-	ldr	r5, [r4, #44]
10826
-	ldrb	r2, [r4, #2069]	@ zero_extendqisi2
11237
+	ldr	r5, [r4, #48]
11238
+	ldrb	r2, [r4, #2073]	@ zero_extendqisi2
10827
11239
 	ldrb	r3, [r5, #12]	@ zero_extendqisi2
10828
-	ldrh	r8, [r5, #14]
10829
-	strh	r3, [r4, #124]	@ movhi
10830
-	ldrb	r3, [r5, #7]	@ zero_extendqisi2
10831
-	str	r3, [r4, #120]
10832
-	mov	r3, r2, asl r7
10833
-	orr	r2, r3, r2, asl #8
10834
-	ldrb	r3, [r4, #2068]	@ zero_extendqisi2
10835
-	orr	r3, r2, r3
10836
-	ldrb	r2, [r4, #2071]	@ zero_extendqisi2
10837
-	orr	r3, r3, r2, asl #24
10838
-	str	r3, [r4, #116]
10839
-	ldrb	r3, [r4, #2230]	@ zero_extendqisi2
10840
-	strh	r3, [r4, #126]	@ movhi
10841
-	ldrb	r3, [r5, #13]	@ zero_extendqisi2
10842
-	strh	r8, [r4, #130]	@ movhi
10843
-	strh	r3, [r4, #128]	@ movhi
10844
-	ldrh	r3, [r5, #10]
11240
+	ldrh	r7, [r5, #14]
10845
11241
 	strh	r3, [r4, #132]	@ movhi
11242
+	ldrb	r3, [r5, #7]	@ zero_extendqisi2
11243
+	str	r3, [r4, #128]
11244
+	lsl	r3, r2, r6
11245
+	orr	r3, r3, r2, lsl #8
11246
+	ldrb	r2, [r4, #2072]	@ zero_extendqisi2
11247
+	orr	r3, r3, r2
11248
+	ldrb	r2, [r4, #2075]	@ zero_extendqisi2
11249
+	orr	r3, r3, r2, lsl #24
11250
+	str	r3, [r4, #124]
11251
+	ldrb	r3, [r4, #2234]	@ zero_extendqisi2
11252
+	strh	r3, [r4, #134]	@ movhi
11253
+	ldrb	r3, [r5, #13]	@ zero_extendqisi2
11254
+	strh	r7, [r4, #138]	@ movhi
11255
+	strh	r3, [r4, #136]	@ movhi
11256
+	ldrh	r3, [r5, #10]
11257
+	strh	r3, [r4, #140]	@ movhi
10846
11258
 	ldrb	r1, [r5, #12]	@ zero_extendqisi2
10847
11259
 	ldrh	r0, [r5, #10]
10848
11260
 	bl	__aeabi_idiv
10849
-	strh	r0, [r4, #134]	@ movhi
11261
+	strh	r0, [r4, #142]	@ movhi
10850
11262
 	ldrb	r2, [r5, #9]	@ zero_extendqisi2
10851
-	strh	r2, [r4, #136]	@ movhi
10852
-	ldrb	r1, [r5, #9]	@ zero_extendqisi2
10853
-	ldrh	r3, [r5, #10]
10854
-	smulbb	r3, r1, r3
11263
+	strh	r2, [r4, #144]	@ movhi
11264
+	ldrh	r1, [r5, #10]
11265
+	ldrb	r3, [r5, #9]	@ zero_extendqisi2
11266
+	smulbb	r3, r3, r1
10855
11267
 	mov	r1, #512
10856
-	strh	r1, [r4, #140]	@ movhi
10857
-	ldrb	r1, [r4, #1]	@ zero_extendqisi2
10858
-	strh	r1, [r4, #142]	@ movhi
11268
+	strh	r1, [r4, #148]	@ movhi
11269
+	ldrb	r1, [r4, #37]	@ zero_extendqisi2
10859
11270
 	uxth	r3, r3
10860
-	ldrb	r1, [r4]	@ zero_extendqisi2
10861
-	strh	r3, [r4, #138]	@ movhi
11271
+	strh	r1, [r4, #150]	@ movhi
11272
+	ldrb	r1, [r4, #36]	@ zero_extendqisi2
11273
+	strh	r3, [r4, #146]	@ movhi
10862
11274
 	cmp	r1, #1
10863
-	bne	.L1800
10864
-	mov	r3, r3, asl #1
10865
-	mov	r8, r8, lsr #1
10866
-	mov	r2, r2, asl #1
10867
-	strh	r3, [r6, #138]	@ movhi
10868
-	strb	r7, [r6, #1]
11275
+	bne	.L1790
11276
+	lsl	r3, r3, #1
11277
+	lsr	r1, r7, #1
11278
+	lsl	r2, r2, #1
11279
+	strb	r6, [r4, #37]
11280
+	strh	r3, [r4, #146]	@ movhi
10869
11281
 	mov	r3, #8
10870
-	strh	r8, [r6, #130]	@ movhi
10871
-	strh	r2, [r6, #136]	@ movhi
10872
-	strh	r3, [r6, #142]	@ movhi
10873
-.L1800:
11282
+	strh	r1, [r4, #138]	@ movhi
11283
+	strh	r2, [r4, #144]	@ movhi
11284
+	strh	r3, [r4, #150]	@ movhi
11285
+.L1790:
10874
11286
 	ldrb	r0, [r5, #20]	@ zero_extendqisi2
10875
11287
 	bl	FlashBchSel
10876
11288
 	bl	ftl_flash_suspend
10877
11289
 	mov	r0, #0
10878
-	b	.L1816
10879
-.L1802:
10880
-	mvn	r0, #1
10881
-.L1816:
10882
-	add	sp, sp, #20
11290
+.L1739:
11291
+	add	sp, sp, #28
10883
11292
 	@ sp needed
10884
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
10885
-.L1849:
11293
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
11294
+.L1755:
11295
+	cmp	r3, #220
11296
+	ldreq	r3, .L1837+28
11297
+	moveq	r1, #4096
11298
+	strheq	r1, [r3, #14]	@ movhi
11299
+	mvneq	r3, #35
11300
+	beq	.L1831
11301
+.L1757:
11302
+	cmp	r3, #211
11303
+	ldreq	r3, .L1837+28
11304
+	moveq	r1, #4096
11305
+	strheq	r1, [r3, #14]	@ movhi
11306
+	moveq	r3, #2
11307
+	strbeq	r3, [r2, #3425]
11308
+	b	.L1756
11309
+.L1764:
11310
+	ldrb	r0, [r4, #2233]	@ zero_extendqisi2
11311
+	bl	FlashSetInterfaceMode
11312
+	ldrb	r0, [r4, #2233]	@ zero_extendqisi2
11313
+	b	.L1832
11314
+.L1771:
11315
+	sub	r3, r0, #17
11316
+	cmp	r3, #2
11317
+	bhi	.L1777
11318
+	ldr	r3, .L1837+60
11319
+	cmp	r0, #19
11320
+	str	r3, [r5, #1704]
11321
+	moveq	r3, #15
11322
+	beq	.L1834
11323
+.L1836:
11324
+	mov	r3, #7
11325
+.L1834:
11326
+	strb	r3, [r5, #1721]
11327
+	b	.L1770
11328
+.L1777:
11329
+	sub	r3, r0, #65
11330
+	cmp	r0, #33
11331
+	cmpne	r3, #1
11332
+	ldrls	r3, .L1837+64
11333
+	strls	r3, [r5, #1704]
11334
+	movls	r3, #4
11335
+	strbls	r3, [r4, #85]
11336
+	bls	.L1836
11337
+.L1779:
11338
+	sub	r3, r0, #67
11339
+	sub	r2, r0, #34
11340
+	uxtb	r3, r3
11341
+	cmp	r3, #1
11342
+	cmphi	r2, #1
11343
+	movls	r2, #1
11344
+	movhi	r2, #0
11345
+	bhi	.L1780
11346
+	ldr	r2, .L1837+64
11347
+	cmp	r0, #68
11348
+	cmpne	r0, #35
11349
+	str	r2, [r5, #1704]
11350
+	movne	r2, #7
11351
+	moveq	r2, #17
11352
+	cmp	r3, #1
11353
+	movls	r3, #4
11354
+	movhi	r3, #5
11355
+	strb	r2, [r5, #1721]
11356
+	strb	r3, [r4, #85]
11357
+	b	.L1770
11358
+.L1780:
11359
+	cmp	r0, #49
11360
+	ldreq	r3, .L1837+68
11361
+	streq	r3, [r5, #1704]
11362
+	beq	.L1770
11363
+	cmp	r0, #50
11364
+	ldreq	r3, .L1837+72
11365
+	streq	r2, [r4, #2252]
11366
+	streq	r3, [r5, #1704]
11367
+	b	.L1770
11368
+.L1792:
11369
+	mvn	r0, #1
11370
+	b	.L1739
11371
+.L1838:
10886
11372
 	.align	2
10887
-.L1848:
11373
+.L1837:
10888
11374
 	.word	.LANCHOR2
10889
11375
 	.word	.LANCHOR0
10890
-	.word	.LANCHOR0+2068
10891
11376
 	.word	.LC97
10892
-	.word	.LANCHOR0+1210
11377
+	.word	.LANCHOR0+2072
11378
+	.word	.LANCHOR0+1216
10893
11379
 	.word	1446522928
10894
11380
 	.word	.LANCHOR1
10895
-	.word	.LANCHOR1+3416
10896
-	.word	.LANCHOR1+3292
10897
-	.word	.LANCHOR0+48
10898
-	.word	.LANCHOR1+472
11381
+	.word	.LANCHOR1+3412
11382
+	.word	.LANCHOR1+3288
11383
+	.word	.LANCHOR0+52
10899
11384
 	.word	.LC98
10900
11385
 	.word	.LANCHOR2-568
10901
11386
 	.word	HynixReadRetrial
10902
-	.word	.LANCHOR0+1238
11387
+	.word	.LANCHOR2-364
11388
+	.word	150000
10903
11389
 	.word	MicronReadRetrial
10904
11390
 	.word	ToshibaReadRetrial
10905
11391
 	.word	SamsungReadRetrial
10906
11392
 	.word	samsung_read_retrial
10907
-	.word	.LANCHOR2-364
10908
-	.word	150000
10909
11393
 	.fnend
10910
11394
 	.size	FlashInit, .-FlashInit
10911
11395
 	.align	2
10912
11396
 	.global	FlashPageProgMsbFFData
11397
+	.syntax unified
11398
+	.arm
11399
+	.fpu softvfp
10913
11400
 	.type	FlashPageProgMsbFFData, %function
10914
11401
 FlashPageProgMsbFFData:
10915
11402
 	.fnstart
10916
11403
 	@ args = 0, pretend = 0, frame = 0
10917
11404
 	@ frame_needed = 0, uses_anonymous_args = 0
10918
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
11405
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
10919
11406
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
10920
-	mov	r7, r1
10921
-	ldr	r1, .L1867
11407
+	mov	r8, r0
11408
+	ldr	r5, .L1855
11409
+	mov	r9, r1
10922
11410
 	mov	r4, r2
10923
-	mov	r6, r0
10924
-	ldrb	r2, [r1, #144]	@ zero_extendqisi2
10925
-	mov	r5, r1
10926
-	ldr	r3, [r1, #44]
10927
-	cmp	r2, #0
11411
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
11412
+	cmp	r3, #0
11413
+	beq	.L1840
11414
+	ldr	r3, [r5, #2252]
11415
+	cmp	r3, #0
11416
+	popne	{r4, r5, r6, r7, r8, r9, r10, pc}
11417
+.L1840:
11418
+	ldr	r3, [r5, #48]
10928
11419
 	ldrb	r3, [r3, #19]	@ zero_extendqisi2
10929
-	beq	.L1851
10930
-	ldr	r2, [r1, #2248]
10931
-	cmp	r2, #0
10932
-	ldmnefd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
10933
-.L1851:
10934
11420
 	sub	r2, r3, #5
10935
11421
 	cmp	r3, #50
10936
11422
 	cmpne	r2, #2
10937
-	bls	.L1852
11423
+	bls	.L1841
10938
11424
 	sub	r2, r3, #19
10939
-	tst	r2, #239
10940
-	moveq	r2, #1
10941
-	movne	r2, #0
10942
-	cmp	r3, #68
10943
-	movne	r3, r2
10944
-	orreq	r3, r2, #1
10945
-	cmp	r3, #0
10946
-	ldmeqfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
10947
-.L1852:
10948
-	ldr	r8, .L1867+4
10949
-	movw	r10, #65535
10950
-	ldr	r9, .L1867+8
10951
-.L1854:
10952
-	ldr	r3, [r5, #44]
11425
+	and	r2, r2, #239
11426
+	cmp	r2, #0
11427
+	cmpne	r3, #68
11428
+	popne	{r4, r5, r6, r7, r8, r9, r10, pc}
11429
+.L1841:
11430
+	ldr	r6, .L1855+4
11431
+	sub	r7, r6, #2608
11432
+	sub	r7, r7, #12
11433
+.L1843:
11434
+	ldr	r3, [r5, #48]
10953
11435
 	ldrh	r3, [r3, #10]
10954
11436
 	cmp	r3, r4
10955
-	bls	.L1866
10956
-	mov	r3, r4, asl #1
10957
-	ldrh	r3, [r9, r3]
10958
-	cmp	r3, r10
10959
-	ldmnefd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
10960
-	mov	r1, #255
11437
+	bhi	.L1844
11438
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
11439
+.L1844:
11440
+	lsl	r3, r4, #1
11441
+	ldrh	r2, [r7, r3]
11442
+	movw	r3, #65535
11443
+	cmp	r2, r3
11444
+	popne	{r4, r5, r6, r7, r8, r9, r10, pc}
10961
11445
 	mov	r2, #32768
10962
-	ldr	r0, [r8, #1716]
11446
+	mov	r1, #255
11447
+	ldr	r0, [r6, #1724]
10963
11448
 	bl	ftl_memset
10964
-	ldr	r2, [r8, #1716]
10965
-	add	r1, r4, r7
11449
+	ldr	r3, [r6, #1724]
11450
+	add	r1, r4, r9
11451
+	mov	r0, r8
10966
11452
 	add	r4, r4, #1
10967
-	mov	r0, r6
10968
-	mov	r3, r2
10969
11453
 	uxth	r4, r4
11454
+	mov	r2, r3
10970
11455
 	bl	FlashProgPage
10971
-	b	.L1854
10972
-.L1866:
10973
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
10974
-.L1868:
11456
+	b	.L1843
11457
+.L1856:
10975
11458
 	.align	2
10976
-.L1867:
11459
+.L1855:
10977
11460
 	.word	.LANCHOR0
10978
11461
 	.word	.LANCHOR2
10979
-	.word	.LANCHOR2-2620
10980
11462
 	.fnend
10981
11463
 	.size	FlashPageProgMsbFFData, .-FlashPageProgMsbFFData
10982
11464
 	.align	2
10983
11465
 	.global	FlashReadSlc2KPages
11466
+	.syntax unified
11467
+	.arm
11468
+	.fpu softvfp
10984
11469
 	.type	FlashReadSlc2KPages, %function
10985
11470
 FlashReadSlc2KPages:
10986
11471
 	.fnstart
10987
11472
 	@ args = 0, pretend = 0, frame = 24
10988
11473
 	@ frame_needed = 0, uses_anonymous_args = 0
10989
-	ldr	r3, .L1920
10990
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11474
+	ldr	r3, .L1906
11475
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
10991
11476
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11477
+	mov	r4, r0
11478
+	ldr	r8, .L1906+4
11479
+	mov	r9, #0
10992
11480
 	.pad #36
10993
11481
 	sub	sp, sp, #36
10994
-	ldrb	r3, [r3, #481]	@ zero_extendqisi2
10995
-	mov	r4, r0
10996
-	mov	r8, #0
11482
+	ldr	fp, .L1906+8
11483
+	ldrb	r3, [r3, #477]	@ zero_extendqisi2
10997
11484
 	str	r1, [sp, #16]
10998
11485
 	str	r2, [sp, #20]
10999
11486
 	str	r3, [sp, #12]
11000
-.L1870:
11487
+.L1858:
11001
11488
 	ldr	r3, [sp, #16]
11002
-	cmp	r8, r3
11003
-	beq	.L1919
11489
+	cmp	r9, r3
11490
+	bne	.L1878
11491
+	mov	r0, #0
11492
+	add	sp, sp, #36
11493
+	@ sp needed
11494
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
11495
+.L1878:
11004
11496
 	ldr	r3, [sp, #16]
11005
11497
 	add	r2, sp, #28
11006
-	mov	r0, r4
11007
11498
 	ldr	r1, [sp, #20]
11008
-	rsb	r3, r8, r3
11009
-	ldr	r9, .L1920+4
11499
+	mov	r0, r4
11500
+	sub	r3, r3, r9
11010
11501
 	uxtb	r3, r3
11011
11502
 	str	r3, [sp]
11012
11503
 	add	r3, sp, #24
11013
-	mov	fp, r9
11014
11504
 	bl	LogAddr2PhyAddr
11015
-	ldrb	r2, [r9, #2230]	@ zero_extendqisi2
11505
+	ldrb	r2, [r8, #2234]	@ zero_extendqisi2
11016
11506
 	ldr	r3, [sp, #24]
11017
-	cmp	r3, r2
11018
-	mvncs	r3, #0
11019
-	strcs	r3, [r4]
11020
-	bcs	.L1872
11021
-	add	r3, r9, r3
11507
+	cmp	r2, r3
11508
+	mvnls	r3, #0
11509
+	strls	r3, [r4]
11510
+	bls	.L1860
11511
+	add	r3, r8, r3
11022
11512
 	mov	r7, #0
11023
-	ldrb	r5, [r3, #2232]	@ zero_extendqisi2
11024
-	mov	r0, r5
11513
+	ldrb	r6, [r3, #2236]	@ zero_extendqisi2
11514
+	mov	r0, r6
11025
11515
 	bl	NandcWaitFlashReady
11026
-	mov	r0, r5
11516
+	mov	r0, r6
11027
11517
 	bl	NandcFlashCs
11028
-.L1873:
11518
+.L1861:
11029
11519
 	ldr	r1, [sp, #28]
11030
-	mov	r0, r5
11520
+	mov	r0, r6
11031
11521
 	bl	FlashReadCmd
11032
-	mov	r0, r5
11522
+	mov	r0, r6
11033
11523
 	bl	NandcWaitFlashReady
11034
11524
 	ldr	r3, [r4, #12]
11035
-	mov	r0, r5
11036
11525
 	mov	r1, #0
11037
-	str	r3, [sp]
11038
11526
 	ldr	r2, [sp, #12]
11527
+	mov	r0, r6
11528
+	str	r3, [sp]
11039
11529
 	ldr	r3, [r4, #8]
11040
11530
 	bl	NandcXferData
11041
-	ldr	r3, .L1920+8
11042
-	ldrb	r3, [r3, #1732]	@ zero_extendqisi2
11531
+	ldrb	r3, [fp, #1740]	@ zero_extendqisi2
11532
+	mov	r5, r0
11043
11533
 	cmp	r3, #0
11044
-	mov	r6, r0
11045
-	beq	.L1874
11046
-	mov	r0, r5
11534
+	beq	.L1862
11535
+	mov	r0, r6
11047
11536
 	bl	flash_read_ecc
11048
11537
 	cmp	r0, #5
11049
-	movhi	r6, #256
11050
-.L1874:
11538
+	movhi	r5, #256
11539
+.L1862:
11051
11540
 	cmp	r7, #9
11052
-	cmnls	r6, #1
11541
+	cmnls	r5, #1
11053
11542
 	moveq	r3, #1
11054
11543
 	movne	r3, #0
11055
11544
 	addeq	r7, r7, #1
11056
-	beq	.L1873
11057
-.L1875:
11545
+	beq	.L1861
11546
+.L1863:
11058
11547
 	cmp	r7, #0
11059
11548
 	mov	r7, r3
11060
-	movne	r6, #256
11061
-.L1877:
11062
-	ldr	r3, [sp, #28]
11063
-	mov	r0, r5
11064
-	ldr	r1, [fp, #4]
11549
+	movne	r5, #256
11550
+.L1865:
11551
+	ldr	r3, [r8, #40]
11552
+	mov	r0, r6
11553
+	ldr	r1, [sp, #28]
11065
11554
 	add	r1, r1, r3
11066
11555
 	bl	FlashReadCmd
11067
-	mov	r0, r5
11556
+	mov	r0, r6
11068
11557
 	bl	NandcWaitFlashReady
11069
11558
 	ldr	r3, [r4, #8]
11070
-	ldr	r2, [r4, #12]
11071
-	mov	r0, r5
11072
-	cmp	r3, #0
11073
11559
 	mov	r1, #0
11560
+	ldr	r2, [r4, #12]
11561
+	mov	r0, r6
11562
+	cmp	r3, #0
11074
11563
 	addne	r3, r3, #2048
11075
11564
 	cmp	r2, #0
11076
11565
 	addne	r2, r2, #8
11077
11566
 	str	r2, [sp]
11078
11567
 	ldr	r2, [sp, #12]
11079
11568
 	bl	NandcXferData
11080
-	ldr	r3, .L1920+8
11081
-	ldrb	r2, [r3, #1732]	@ zero_extendqisi2
11082
-	cmp	r2, #0
11569
+	ldrb	r2, [fp, #1740]	@ zero_extendqisi2
11083
11570
 	mov	r10, r0
11084
-	beq	.L1880
11085
-	mov	r0, r5
11571
+	cmp	r2, #0
11572
+	beq	.L1868
11573
+	mov	r0, r6
11086
11574
 	bl	flash_read_ecc
11087
11575
 	cmp	r0, #5
11088
11576
 	movhi	r10, #256
11089
-.L1880:
11577
+.L1868:
11090
11578
 	cmp	r7, #9
11091
11579
 	cmnls	r10, #1
11092
11580
 	addeq	r7, r7, #1
11093
-	beq	.L1877
11094
-.L1881:
11581
+	beq	.L1865
11582
+.L1869:
11095
11583
 	cmp	r7, #0
11096
-	mov	r0, r5
11584
+	mov	r0, r6
11097
11585
 	movne	r10, #256
11098
11586
 	bl	NandcFlashDeCs
11099
-	ldrb	r2, [r9, #2312]	@ zero_extendqisi2
11100
-	cmp	r10, r6
11101
-	movcs	r3, r10
11102
-	movcc	r3, r6
11103
-	add	r2, r2, r2, asl #1
11104
-	cmp	r3, r2, asr #2
11105
-	bls	.L1883
11106
-	cmn	r3, #1
11107
-	movne	r3, #256
11108
-.L1883:
11109
-	cmp	r3, #256
11110
-	cmnne	r3, #1
11587
+	ldrb	r3, [r8, #2316]	@ zero_extendqisi2
11588
+	cmp	r5, r10
11589
+	movcc	r5, r10
11590
+	add	r3, r3, r3, lsl #1
11591
+	cmp	r5, r3, asr #2
11592
+	bls	.L1871
11593
+	cmn	r5, #1
11594
+	movne	r5, #256
11595
+.L1871:
11596
+	cmp	r5, #256
11597
+	cmnne	r5, #1
11111
11598
 	movne	r3, #0
11112
-	str	r3, [r4]
11599
+	streq	r5, [r4]
11600
+	strne	r3, [r4]
11113
11601
 	ldr	r3, [r4, #12]
11114
11602
 	cmp	r3, #0
11115
-	beq	.L1886
11603
+	beq	.L1874
11116
11604
 	ldr	r2, [r3, #12]
11117
11605
 	cmn	r2, #1
11118
-	bne	.L1886
11606
+	bne	.L1874
11119
11607
 	ldr	r2, [r3, #8]
11120
11608
 	cmn	r2, #1
11121
-	bne	.L1886
11609
+	bne	.L1874
11122
11610
 	ldr	r3, [r3]
11123
11611
 	cmn	r3, #1
11124
11612
 	strne	r2, [r4]
11125
-.L1886:
11613
+.L1874:
11126
11614
 	ldr	r3, [r4]
11127
11615
 	cmn	r3, #1
11128
-	bne	.L1872
11616
+	bne	.L1860
11129
11617
 	ldr	r1, [r4, #4]
11130
-	ldr	r0, .L1920+12
11131
-	ldrb	r2, [r9, #2312]	@ zero_extendqisi2
11618
+	ldrb	r2, [r8, #2316]	@ zero_extendqisi2
11619
+	ldr	r0, .L1906+12
11132
11620
 	bl	printk
11133
11621
 	ldr	r1, [r4, #8]
11134
11622
 	cmp	r1, #0
11135
-	beq	.L1888
11136
-	ldr	r0, .L1920+16
11137
-	mov	r2, #4
11623
+	beq	.L1876
11138
11624
 	mov	r3, #8
11625
+	mov	r2, #4
11626
+	ldr	r0, .L1906+16
11139
11627
 	bl	rknand_print_hex
11140
-.L1888:
11628
+.L1876:
11141
11629
 	ldr	r1, [r4, #12]
11142
11630
 	cmp	r1, #0
11143
-	beq	.L1872
11144
-	mov	r2, #4
11145
-	ldr	r0, .L1920+20
11146
-	mov	r3, r2
11631
+	beq	.L1860
11632
+	mov	r3, #4
11633
+	ldr	r0, .L1906+20
11634
+	mov	r2, r3
11147
11635
 	bl	rknand_print_hex
11148
-.L1872:
11149
-	add	r8, r8, #1
11636
+.L1860:
11637
+	add	r9, r9, #1
11150
11638
 	add	r4, r4, #36
11151
-	b	.L1870
11152
-.L1919:
11153
-	mov	r0, #0
11154
-	add	sp, sp, #36
11155
-	@ sp needed
11156
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
11157
-.L1921:
11639
+	b	.L1858
11640
+.L1907:
11158
11641
 	.align	2
11159
-.L1920:
11642
+.L1906:
11160
11643
 	.word	.LANCHOR1
11161
11644
 	.word	.LANCHOR0
11162
11645
 	.word	.LANCHOR2
..
..
@@ -11167,2042 +11650,2030 @@
11167
11650
 	.size	FlashReadSlc2KPages, .-FlashReadSlc2KPages
11168
11651
 	.align	2
11169
11652
 	.global	FlashReadPages
11653
+	.syntax unified
11654
+	.arm
11655
+	.fpu softvfp
11170
11656
 	.type	FlashReadPages, %function
11171
11657
 FlashReadPages:
11172
11658
 	.fnstart
11173
11659
 	@ args = 0, pretend = 0, frame = 40
11174
11660
 	@ frame_needed = 0, uses_anonymous_args = 0
11175
-	ldr	r3, .L1997
11176
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11661
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
11177
11662
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11178
11663
 	.pad #52
11179
11664
 	sub	sp, sp, #52
11180
-	ldr	r6, .L1997+4
11181
-	ldrb	r3, [r3, #481]	@ zero_extendqisi2
11182
-	str	r1, [sp, #20]
11183
-	ldrb	r8, [r6]	@ zero_extendqisi2
11184
-	str	r3, [sp, #16]
11185
-	ldrb	r3, [r6, #8]	@ zero_extendqisi2
11186
-	cmp	r8, #0
11187
-	str	r2, [sp, #24]
11188
-	str	r3, [sp, #28]
11189
-	beq	.L1959
11665
+	ldr	r4, .L1979
11666
+	str	r1, [sp, #24]
11667
+	ldrb	r9, [r4, #36]	@ zero_extendqisi2
11668
+	str	r2, [sp, #28]
11669
+	cmp	r9, #0
11670
+	bne	.L1909
11671
+	ldr	r3, .L1979+4
11672
+	mov	fp, r0
11673
+	ldr	r10, .L1979+8
11674
+	str	r9, [sp, #8]
11675
+	ldrb	r3, [r3, #477]	@ zero_extendqisi2
11676
+	str	r3, [sp, #20]
11677
+	ldrb	r3, [r4, #44]	@ zero_extendqisi2
11678
+	str	r3, [sp, #36]
11679
+.L1910:
11680
+	ldr	r3, [sp, #8]
11681
+	ldr	r2, [sp, #24]
11682
+	cmp	r3, r2
11683
+	bcc	.L1943
11684
+	mov	r0, #0
11685
+	b	.L1908
11686
+.L1909:
11190
11687
 	bl	FlashReadSlc2KPages
11191
-	b	.L1992
11192
-.L1959:
11193
-	ldr	r10, .L1997+8
11194
-	mov	r9, r0
11195
-	mov	fp, r8
11196
-.L1923:
11197
-	ldr	r3, [sp, #20]
11198
-	cmp	fp, r3
11199
-	bcs	.L1995
11688
+.L1908:
11689
+	add	sp, sp, #52
11690
+	@ sp needed
11691
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
11692
+.L1943:
11693
+	ldr	r2, [sp, #8]
11200
11694
 	mov	r3, #36
11201
-	add	r2, sp, #44
11202
-	mul	r3, r3, fp
11203
-	ldr	r1, [sp, #24]
11204
-	add	r7, r9, r3
11205
-	str	r3, [sp, #8]
11206
-	mov	r0, r7
11207
-	ldr	r3, [r7, #4]
11695
+	ldr	r1, [sp, #28]
11696
+	mul	r3, r3, r2
11697
+	add	r8, fp, r3
11208
11698
 	str	r3, [sp, #12]
11209
-	ldr	r3, [sp, #20]
11210
-	rsb	r3, fp, r3
11699
+	ldr	r3, [sp, #24]
11700
+	mov	r0, r8
11701
+	ldr	r7, [r8, #4]
11702
+	sub	r3, r3, r2
11703
+	add	r2, sp, #44
11211
11704
 	uxtb	r3, r3
11212
11705
 	str	r3, [sp]
11213
11706
 	add	r3, sp, #40
11214
11707
 	bl	LogAddr2PhyAddr
11215
-	ldrb	r2, [r6, #2230]	@ zero_extendqisi2
11708
+	ldrb	r2, [r4, #2234]	@ zero_extendqisi2
11709
+	mov	r6, r0
11216
11710
 	ldr	r3, [sp, #40]
11217
-	mov	r5, r0
11218
-	cmp	r3, r2
11219
-	ldrcs	r2, [sp, #8]
11220
-	mvncs	r3, #0
11221
-	strcs	r3, [r9, r2]
11222
-	bcs	.L1926
11223
-	add	r3, r6, r3
11224
-	ldrb	r4, [r3, #2232]	@ zero_extendqisi2
11225
-	ldrb	r3, [r10, #1733]	@ zero_extendqisi2
11711
+	cmp	r2, r3
11712
+	ldrls	r2, [sp, #12]
11713
+	mvnls	r3, #0
11714
+	strls	r3, [fp, r2]
11715
+	bls	.L1913
11716
+	add	r3, r4, r3
11717
+	ldrb	r5, [r3, #2236]	@ zero_extendqisi2
11718
+	ldrb	r3, [r10, #1741]	@ zero_extendqisi2
11719
+	mov	r0, r5
11226
11720
 	cmp	r3, #0
11227
-	mov	r0, r4
11228
-	moveq	r5, #0
11721
+	moveq	r6, #0
11229
11722
 	bl	NandcWaitFlashReady
11230
-	ldr	r3, .L1997+4
11231
-	ldr	r3, [r3, #44]
11723
+	ldr	r3, [r4, #48]
11232
11724
 	ldrb	r2, [r3, #19]	@ zero_extendqisi2
11233
11725
 	sub	r3, r2, #1
11234
11726
 	cmp	r3, #7
11235
-	bhi	.L1928
11727
+	bhi	.L1915
11236
11728
 	sub	r2, r2, #7
11237
-	add	r1, r6, r4
11729
+	add	r1, r4, r5
11238
11730
 	cmp	r2, #1
11239
-	ldr	r2, .L1997+4
11240
-	ldrb	r3, [r1, #1222]	@ zero_extendqisi2
11241
-	add	r2, r2, r4
11242
-	ldrlsb	r3, [r1, #1230]	@ zero_extendqisi2
11243
-	ldrb	r2, [r2, #2064]	@ zero_extendqisi2
11731
+	add	r2, r4, r5
11732
+	ldrb	r3, [r1, #1228]	@ zero_extendqisi2
11733
+	ldrb	r2, [r2, #2068]	@ zero_extendqisi2
11734
+	ldrbls	r3, [r1, #1236]	@ zero_extendqisi2
11244
11735
 	cmp	r2, r3
11245
-	beq	.L1928
11246
-	mov	r0, r4
11247
-	ldrb	r1, [r6, #1211]	@ zero_extendqisi2
11248
-	ldr	r2, .L1997+12
11736
+	beq	.L1915
11737
+	ldr	r2, .L1979+12
11738
+	mov	r0, r5
11739
+	ldrb	r1, [r4, #1217]	@ zero_extendqisi2
11249
11740
 	bl	HynixSetRRPara
11250
-.L1928:
11251
-	mov	r0, r4
11741
+.L1915:
11742
+	mov	r0, r5
11743
+	lsr	r7, r7, #31
11252
11744
 	bl	NandcFlashCs
11253
-	mov	r0, r4
11254
-	ldr	r3, [sp, #12]
11255
-	ldr	r2, [sp, #24]
11256
-	mov	r3, r3, lsr #31
11257
-	cmp	r2, #1
11258
-	orreq	r3, r3, #1
11259
-	str	r3, [sp, #12]
11745
+	ldr	r3, [sp, #28]
11746
+	mov	r0, r5
11747
+	cmp	r3, #1
11748
+	orreq	r7, r7, #1
11749
+	cmp	r7, #0
11750
+	str	r7, [sp, #16]
11751
+	beq	.L1917
11752
+	ldrb	r3, [r4, #152]	@ zero_extendqisi2
11260
11753
 	cmp	r3, #0
11261
-	beq	.L1930
11262
-	ldr	r3, .L1997+4
11263
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
11264
-	cmp	r3, #0
11265
-	beq	.L1930
11754
+	beq	.L1917
11266
11755
 	bl	flash_enter_slc_mode
11267
-	b	.L1931
11268
-.L1930:
11269
-	bl	flash_exit_slc_mode
11270
-.L1931:
11756
+.L1923:
11271
11757
 	ldr	r1, [sp, #44]
11272
11758
 	cmn	r1, #1
11273
-	cmpeq	r4, #255
11759
+	cmpeq	r5, #255
11274
11760
 	moveq	r3, #0
11275
11761
 	movne	r3, #1
11276
-	moveq	r5, r3
11277
-	beq	.L1933
11278
-	cmp	r5, #0
11279
-	beq	.L1934
11280
-	ldr	r2, [r6, #4]
11281
-	mov	r0, r4
11762
+	moveq	r6, r3
11763
+	beq	.L1919
11764
+	cmp	r6, #0
11765
+	beq	.L1920
11766
+	ldr	r2, [r4, #40]
11767
+	mov	r0, r5
11282
11768
 	add	r2, r1, r2
11283
11769
 	bl	FlashReadDpCmd
11284
-	b	.L1935
11285
-.L1934:
11286
-	mov	r0, r4
11287
-	bl	FlashReadCmd
11288
-.L1935:
11289
-	mov	r0, r4
11770
+.L1921:
11771
+	mov	r0, r5
11290
11772
 	bl	NandcWaitFlashReady
11291
-	cmp	r5, #0
11292
-	beq	.L1933
11293
-	mov	r0, r4
11773
+	cmp	r6, #0
11774
+	beq	.L1919
11294
11775
 	ldr	r1, [sp, #44]
11776
+	mov	r0, r5
11295
11777
 	bl	FlashReadDpDataOutCmd
11296
-.L1933:
11297
-	ldr	r3, [r7, #12]
11298
-	mov	r0, r4
11299
-	ldr	r2, [sp, #16]
11778
+.L1919:
11779
+	ldr	r3, [r8, #12]
11300
11780
 	mov	r1, #0
11781
+	ldr	r2, [sp, #20]
11782
+	mov	r0, r5
11301
11783
 	str	r3, [sp]
11302
-	ldr	r3, [r7, #8]
11784
+	ldr	r3, [r8, #8]
11303
11785
 	bl	NandcXferData
11304
-	ldrb	r2, [r6, #8]	@ zero_extendqisi2
11305
-	adds	r2, r2, #0
11786
+	ldrb	r3, [r4, #44]	@ zero_extendqisi2
11787
+	mov	r7, r0
11788
+	adds	r2, r3, #0
11306
11789
 	movne	r2, #1
11307
11790
 	cmn	r0, #1
11308
-	mov	ip, r0
11309
11791
 	movne	r2, #0
11310
11792
 	cmp	r2, #0
11311
-	movne	r3, #0
11312
-	strneb	r3, [r6, #8]
11313
-	movne	r5, r3
11314
-	bne	.L1931
11315
-.L1936:
11316
-	cmp	r5, #0
11317
-	beq	.L1937
11318
-	ldr	r3, .L1997+4
11319
-	str	r0, [sp, #32]
11320
-	mov	r0, r4
11321
-	str	r2, [sp, #36]
11322
-	ldr	r1, [r3, #4]
11323
-	ldr	r3, [sp, #44]
11793
+	str	r2, [sp, #32]
11794
+	beq	.L1922
11795
+	mov	r3, #0
11796
+	mov	r6, #0
11797
+	strb	r3, [r4, #44]
11798
+	b	.L1923
11799
+.L1917:
11800
+	bl	flash_exit_slc_mode
11801
+	b	.L1923
11802
+.L1920:
11803
+	mov	r0, r5
11804
+	bl	FlashReadCmd
11805
+	b	.L1921
11806
+.L1922:
11807
+	cmp	r6, #0
11808
+	beq	.L1924
11809
+	ldr	r3, [r4, #40]
11810
+	mov	r0, r5
11811
+	ldr	r1, [sp, #44]
11324
11812
 	add	r1, r1, r3
11325
11813
 	bl	FlashReadDpDataOutCmd
11326
-	mov	r0, r4
11327
-	ldr	r3, [sp, #8]
11328
-	ldr	r2, [sp, #36]
11814
+	ldr	r3, [sp, #12]
11815
+	mov	r0, r5
11816
+	ldr	r1, [sp, #32]
11329
11817
 	add	r3, r3, #36
11330
-	add	r3, r9, r3
11331
-	ldr	r1, [r3, #12]
11332
-	str	r1, [sp]
11333
-	mov	r1, r2
11818
+	add	r3, fp, r3
11819
+	ldr	r2, [r3, #12]
11820
+	str	r2, [sp]
11821
+	ldr	r2, [sp, #20]
11334
11822
 	ldr	r3, [r3, #8]
11335
-	ldr	r2, [sp, #16]
11336
11823
 	bl	NandcXferData
11337
11824
 	cmn	r0, #1
11338
-	ldr	ip, [sp, #32]
11339
-	mov	r8, r0
11340
-	moveq	r5, #0
11341
-.L1937:
11342
-	mov	r0, r4
11343
-	str	ip, [sp, #32]
11825
+	mov	r9, r0
11826
+	moveq	r6, #0
11827
+.L1924:
11828
+	mov	r0, r5
11344
11829
 	bl	NandcFlashDeCs
11345
-	ldr	ip, [sp, #32]
11346
-	ldrb	r3, [sp, #28]	@ zero_extendqisi2
11347
-	cmn	ip, #1
11348
-	strb	r3, [r6, #8]
11349
-	bne	.L1944
11350
-	ldrb	r3, [r6, #2252]	@ zero_extendqisi2
11830
+	ldrb	r3, [sp, #36]	@ zero_extendqisi2
11831
+	cmn	r7, #1
11832
+	strb	r3, [r4, #44]
11833
+	bne	.L1925
11834
+	ldrb	r3, [r4, #2256]	@ zero_extendqisi2
11351
11835
 	cmp	r3, #0
11352
-	bne	.L1939
11353
-.L1943:
11354
-	ldr	r5, [r10, #1696]
11355
-	cmp	r5, #0
11356
-	bne	.L1940
11357
-	b	.L1996
11358
-.L1939:
11359
-	ldr	r3, [r6, #80]
11360
-	mov	r0, r4
11836
+	bne	.L1926
11837
+.L1930:
11838
+	ldr	r6, [r10, #1704]
11839
+	cmp	r6, #0
11840
+	bne	.L1927
11841
+	ldr	r3, [r8, #12]
11842
+	mov	r0, r5
11843
+	ldr	r2, [r8, #8]
11361
11844
 	ldr	r1, [sp, #44]
11362
-	ldr	r5, [r3, #304]
11845
+	bl	FlashReadRawPage
11846
+	mov	r7, r0
11847
+.L1931:
11848
+	cmp	r7, #256
11849
+	cmnne	r7, #1
11850
+	ldreq	r3, [sp, #12]
11851
+	movne	r3, #0
11852
+	ldrne	r2, [sp, #12]
11853
+	streq	r7, [fp, r3]
11854
+	strne	r3, [fp, r2]
11855
+	ldr	r3, [sp, #12]
11856
+	ldr	r3, [fp, r3]
11857
+	cmn	r3, #1
11858
+	bne	.L1938
11859
+	ldr	r1, [r8, #4]
11860
+	ldrb	r2, [r4, #2316]	@ zero_extendqisi2
11861
+	ldr	r0, .L1979+16
11862
+	bl	printk
11863
+	ldr	r1, [r8, #12]
11864
+	cmp	r1, #0
11865
+	beq	.L1938
11866
+	mov	r3, #4
11867
+	ldr	r0, .L1979+20
11868
+	mov	r2, r3
11869
+	bl	rknand_print_hex
11870
+.L1938:
11871
+	cmp	r6, #0
11872
+	beq	.L1940
11873
+	ldrb	r3, [r4, #2316]	@ zero_extendqisi2
11874
+	add	r3, r3, r3, lsl #1
11875
+	cmp	r9, r3, asr #2
11876
+	bls	.L1941
11877
+	ldr	r3, [r10, #1704]
11878
+	cmp	r3, #0
11879
+	moveq	r9, #256
11880
+.L1941:
11881
+	ldr	r3, [sp, #12]
11882
+	cmp	r9, #256
11883
+	cmnne	r9, #1
11884
+	movne	r2, #0
11885
+	add	r3, r3, #36
11886
+	streq	r9, [fp, r3]
11887
+	strne	r2, [fp, r3]
11888
+.L1940:
11889
+	ldr	r3, [sp, #8]
11890
+	add	r3, r3, r6
11891
+	str	r3, [sp, #8]
11892
+	ldr	r3, [sp, #16]
11893
+	cmp	r3, #0
11894
+	beq	.L1913
11895
+	ldrb	r3, [r4, #152]	@ zero_extendqisi2
11896
+	cmp	r3, #0
11897
+	beq	.L1913
11898
+	mov	r0, r5
11899
+	bl	flash_exit_slc_mode
11900
+.L1913:
11901
+	ldr	r3, [sp, #8]
11902
+	add	r3, r3, #1
11903
+	str	r3, [sp, #8]
11904
+	b	.L1910
11905
+.L1926:
11906
+	ldr	r3, [r4, #88]
11907
+	mov	r0, r5
11908
+	ldr	r1, [sp, #44]
11909
+	ldr	r6, [r3, #304]
11363
11910
 	mov	r3, #1
11364
11911
 	str	r3, [sp]
11365
-	ldr	r2, [r7, #8]
11366
-	ldr	r3, [r7, #12]
11912
+	ldr	r3, [r8, #12]
11913
+	ldr	r2, [r8, #8]
11367
11914
 	bl	FlashDdrTunningRead
11368
11915
 	cmn	r0, #1
11369
-	mov	ip, r0
11370
-	beq	.L1942
11371
-	ldrb	r3, [r6, #2312]	@ zero_extendqisi2
11916
+	mov	r7, r0
11917
+	beq	.L1929
11918
+	ldrb	r3, [r4, #2316]	@ zero_extendqisi2
11372
11919
 	cmp	r0, r3, lsr #1
11373
-	bls	.L1962
11374
-.L1942:
11375
-	ubfx	r0, r5, #8, #8
11376
-	str	ip, [sp, #32]
11920
+	bls	.L1946
11921
+.L1929:
11922
+	ubfx	r0, r6, #8, #8
11377
11923
 	bl	NandcSetDdrPara
11378
-	ldr	ip, [sp, #32]
11379
-	cmn	ip, #1
11380
-	beq	.L1943
11381
-	b	.L1962
11382
-.L1940:
11383
-	mov	r0, r4
11924
+	cmn	r7, #1
11925
+	beq	.L1930
11926
+.L1946:
11927
+	mov	r6, #0
11928
+.L1925:
11929
+	ldrb	r3, [r4, #2316]	@ zero_extendqisi2
11930
+	add	r3, r3, r3, lsl #1
11931
+	cmp	r7, r3, asr #2
11932
+	bls	.L1931
11933
+	ldr	r3, [r10, #1704]
11934
+	cmp	r3, #0
11935
+	moveq	r7, #256
11936
+	b	.L1931
11937
+.L1927:
11938
+	ldr	r3, [r8, #12]
11939
+	mov	r0, r5
11940
+	ldr	r2, [r8, #8]
11384
11941
 	ldr	r1, [sp, #44]
11385
-	ldr	r2, [r7, #8]
11386
-	ldr	r3, [r7, #12]
11387
-	blx	r5
11942
+	blx	r6
11388
11943
 	cmn	r0, #1
11389
-	mov	ip, r0
11390
-	bne	.L1964
11391
-	ldr	r3, [r6, #44]
11944
+	mov	r7, r0
11945
+	bne	.L1948
11946
+	ldr	r3, [r4, #48]
11392
11947
 	ldrb	r3, [r3, #19]	@ zero_extendqisi2
11393
11948
 	sub	r3, r3, #1
11394
11949
 	cmp	r3, #7
11395
-	bhi	.L1946
11396
-	mov	r0, r4
11397
-	ldrb	r1, [r6, #1211]	@ zero_extendqisi2
11398
-	ldr	r2, .L1997+12
11950
+	bhi	.L1932
11399
11951
 	mov	r3, #0
11952
+	ldr	r2, .L1979+12
11953
+	ldrb	r1, [r4, #1217]	@ zero_extendqisi2
11954
+	mov	r0, r5
11400
11955
 	bl	HynixSetRRPara
11401
-.L1946:
11956
+.L1932:
11957
+	ldr	r3, [r8, #12]
11958
+	mov	r0, r5
11959
+	ldr	r2, [r8, #8]
11402
11960
 	ldr	r1, [sp, #44]
11403
-	mov	r0, r4
11404
-	ldr	r2, [r7, #8]
11405
-	ldr	r3, [r7, #12]
11406
11961
 	bl	FlashReadRawPage
11407
-	ldr	r1, [r7, #4]
11408
-	ldrb	r2, [r6, #2312]	@ zero_extendqisi2
11409
-	mov	ip, r0
11410
-	ldr	r0, .L1997+16
11411
-	mov	r3, ip
11412
-	str	ip, [sp, #32]
11962
+	ldrb	r2, [r4, #2316]	@ zero_extendqisi2
11963
+	mov	r7, r0
11964
+	mov	r3, r0
11965
+	ldr	r1, [r8, #4]
11966
+	ldr	r0, .L1979+24
11413
11967
 	bl	printk
11414
-	ldr	ip, [sp, #32]
11415
-	cmn	ip, #1
11416
-	bne	.L1964
11417
-	ldrb	r5, [r6, #144]	@ zero_extendqisi2
11418
-	cmp	r5, #0
11419
-	beq	.L1945
11420
-	ldr	r3, [sp, #12]
11421
-	mov	r0, r4
11968
+	cmn	r7, #1
11969
+	bne	.L1948
11970
+	ldrb	r6, [r4, #152]	@ zero_extendqisi2
11971
+	cmp	r6, #0
11972
+	beq	.L1931
11973
+	ldr	r3, [sp, #16]
11974
+	mov	r0, r5
11422
11975
 	cmp	r3, #0
11423
-	beq	.L1947
11976
+	beq	.L1933
11424
11977
 	bl	flash_enter_slc_mode
11425
-	b	.L1948
11426
-.L1947:
11427
-	bl	flash_exit_slc_mode
11978
+.L1934:
11979
+	ldr	r6, [r10, #1704]
11980
+	mov	r0, r5
11981
+	ldr	r3, [r8, #12]
11982
+	ldr	r2, [r8, #8]
11983
+	ldr	r1, [sp, #44]
11984
+	blx	r6
11985
+	mov	r7, r0
11428
11986
 .L1948:
11429
-	ldr	ip, [r10, #1696]
11430
-	mov	r0, r4
11431
-	ldr	r1, [sp, #44]
11432
-	ldr	r2, [r7, #8]
11433
-	ldr	r3, [r7, #12]
11434
-	blx	ip
11435
-	mov	ip, r0
11436
-	b	.L1964
11437
-.L1996:
11438
-	mov	r0, r4
11439
-	ldr	r1, [sp, #44]
11440
-	ldr	r2, [r7, #8]
11441
-	ldr	r3, [r7, #12]
11442
-	bl	FlashReadRawPage
11443
-	mov	ip, r0
11444
-	b	.L1945
11445
-.L1962:
11446
-	mov	r5, #0
11447
-.L1944:
11448
-	ldrb	r3, [r6, #2312]	@ zero_extendqisi2
11449
-	add	r3, r3, r3, asl #1
11450
-	cmp	ip, r3, asr #2
11451
-	bls	.L1945
11452
-	ldr	r3, [r10, #1696]
11453
-	cmp	r3, #0
11454
-	moveq	ip, #256
11455
-	b	.L1945
11456
-.L1964:
11457
-	mov	r5, #0
11458
-.L1945:
11459
-	cmp	ip, #256
11460
-	cmnne	ip, #1
11461
-	ldreq	r3, [sp, #8]
11462
-	movne	r3, #0
11463
-	ldrne	r2, [sp, #8]
11464
-	streq	ip, [r9, r3]
11465
-	strne	r3, [r9, r2]
11466
-	ldr	r3, [sp, #8]
11467
-	ldr	r3, [r9, r3]
11468
-	cmn	r3, #1
11469
-	bne	.L1952
11470
-	ldr	r1, [r7, #4]
11471
-	ldr	r0, .L1997+20
11472
-	ldrb	r2, [r6, #2312]	@ zero_extendqisi2
11473
-	bl	printk
11474
-	ldr	r1, [r7, #12]
11475
-	cmp	r1, #0
11476
-	beq	.L1952
11477
-	mov	r2, #4
11478
-	ldr	r0, .L1997+24
11479
-	mov	r3, r2
11480
-	bl	rknand_print_hex
11481
-.L1952:
11482
-	cmp	r5, #0
11483
-	beq	.L1954
11484
-	ldrb	r3, [r6, #2312]	@ zero_extendqisi2
11485
-	add	r3, r3, r3, asl #1
11486
-	cmp	r8, r3, asr #2
11487
-	bls	.L1955
11488
-	ldr	r3, [r10, #1696]
11489
-	cmp	r3, #0
11490
-	moveq	r8, #256
11491
-.L1955:
11492
-	ldr	r3, [sp, #8]
11493
-	cmp	r8, #256
11494
-	cmnne	r8, #1
11495
-	add	r3, r3, #36
11496
-	movne	r2, #0
11497
-	streq	r8, [r9, r3]
11498
-	strne	r2, [r9, r3]
11499
-.L1954:
11500
-	ldr	r3, [sp, #12]
11501
-	add	fp, fp, r5
11502
-	cmp	r3, #0
11503
-	beq	.L1926
11504
-	ldrb	r3, [r6, #144]	@ zero_extendqisi2
11505
-	cmp	r3, #0
11506
-	beq	.L1926
11507
-	mov	r0, r4
11987
+	mov	r6, #0
11988
+	b	.L1931
11989
+.L1933:
11508
11990
 	bl	flash_exit_slc_mode
11509
-.L1926:
11510
-	add	fp, fp, #1
11511
-	b	.L1923
11512
-.L1995:
11513
-	mov	r0, #0
11514
-.L1992:
11515
-	add	sp, sp, #52
11516
-	@ sp needed
11517
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
11518
-.L1998:
11991
+	b	.L1934
11992
+.L1980:
11519
11993
 	.align	2
11520
-.L1997:
11521
-	.word	.LANCHOR1
11994
+.L1979:
11522
11995
 	.word	.LANCHOR0
11996
+	.word	.LANCHOR1
11523
11997
 	.word	.LANCHOR2
11524
-	.word	.LANCHOR0+1214
11525
-	.word	.LC102
11998
+	.word	.LANCHOR0+1220
11526
11999
 	.word	.LC99
11527
12000
 	.word	.LC101
12001
+	.word	.LC102
11528
12002
 	.fnend
11529
12003
 	.size	FlashReadPages, .-FlashReadPages
11530
12004
 	.align	2
11531
12005
 	.global	FlashLoadFactorBbt
12006
+	.syntax unified
12007
+	.arm
12008
+	.fpu softvfp
11532
12009
 	.type	FlashLoadFactorBbt, %function
11533
12010
 FlashLoadFactorBbt:
11534
12011
 	.fnstart
11535
12012
 	@ args = 0, pretend = 0, frame = 56
11536
12013
 	@ frame_needed = 0, uses_anonymous_args = 0
11537
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12014
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
11538
12015
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11539
12016
 	mov	r2, #16
11540
-	ldr	r4, .L2012
12017
+	ldr	r8, .L1993
11541
12018
 	.pad #60
11542
12019
 	sub	sp, sp, #60
11543
-	ldr	r0, .L2012+4
11544
12020
 	mov	r1, #0
11545
-	ldr	r10, .L2012+8
11546
-	mov	r5, #0
11547
-	ldrh	r3, [r4, #130]
11548
12021
 	mvn	fp, #0
11549
-	ldrh	r6, [r4, #128]
12022
+	ldr	r10, .L1993+4
12023
+	mov	r5, #0
12024
+	ldrh	r3, [r8, #136]
11550
12025
 	mov	r9, r5
11551
-	mov	r8, r4
12026
+	ldrh	r6, [r8, #138]
12027
+	ldr	r0, .L1993+8
11552
12028
 	smulbb	r6, r6, r3
11553
12029
 	bl	ftl_memset
11554
-	ldr	r3, [r10, #1720]
12030
+	ldr	r3, [r10, #1728]
11555
12031
 	uxth	r6, r6
11556
-	add	r2, r6, fp
11557
-	str	r3, [sp, #32]
11558
-	uxth	r3, r2
11559
12032
 	str	r5, [sp, #28]
11560
-	str	r3, [sp, #4]
11561
-.L2000:
11562
-	ldrb	r3, [r8, #2230]	@ zero_extendqisi2
12033
+	str	r3, [sp, #32]
12034
+	add	r3, r6, fp
12035
+	uxth	r3, r3
12036
+	str	r3, [sp, #8]
12037
+.L1982:
12038
+	ldrb	r3, [r8, #2234]	@ zero_extendqisi2
11563
12039
 	uxtb	r7, r5
11564
12040
 	cmp	r3, r7
11565
-	bls	.L2011
11566
-	mul	ip, r6, r7
11567
-	ldr	r4, [sp, #4]
11568
-	sub	r3, r6, #12
11569
-.L2001:
11570
-	cmp	r4, r3
11571
-	ble	.L2003
11572
-	add	r2, ip, r4
11573
-	mov	r1, #1
11574
-	add	r0, sp, #20
11575
-	str	r3, [sp, #12]
11576
-	mov	r2, r2, asl #10
11577
-	str	r2, [sp, #24]
11578
-	mov	r2, r1
11579
-	str	ip, [sp, #8]
11580
-	bl	FlashReadPages
11581
-	ldr	r2, [sp, #20]
11582
-	ldr	ip, [sp, #8]
11583
-	cmn	r2, #1
11584
-	ldr	r3, [sp, #12]
11585
-	beq	.L2002
11586
-	ldr	r2, [r10, #1720]
11587
-	ldrh	r1, [r2]
11588
-	movw	r2, #61664
11589
-	cmp	r1, r2
11590
-	bne	.L2002
11591
-	mov	r1, r7
11592
-	ldr	r0, .L2012+12
11593
-	mov	r2, r4
11594
-	mov	r7, r7, asl #1
11595
-	bl	printk
11596
-	ldr	r3, .L2012+4
11597
-	add	r9, r9, #1
11598
-	strh	r4, [r3, r7]	@ movhi
11599
-	uxth	r9, r9
11600
-	b	.L2003
11601
-.L2002:
11602
-	sub	r4, r4, #1
11603
-	uxth	r4, r4
11604
-	b	.L2001
11605
-.L2003:
11606
-	ldrb	r3, [r8, #2230]	@ zero_extendqisi2
11607
-	add	r5, r5, #1
11608
-	cmp	r3, r9
11609
-	moveq	fp, #0
11610
-	b	.L2000
11611
-.L2011:
12041
+	bhi	.L1988
11612
12042
 	mov	r0, fp
11613
12043
 	add	sp, sp, #60
11614
12044
 	@ sp needed
11615
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
11616
-.L2013:
12045
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
12046
+.L1988:
12047
+	ldr	r4, [sp, #8]
12048
+	mul	r3, r7, r6
12049
+	sub	r2, r6, #12
12050
+	str	r2, [sp, #4]
12051
+.L1983:
12052
+	ldr	r2, [sp, #4]
12053
+	cmp	r4, r2
12054
+	ble	.L1985
12055
+	add	r2, r4, r3
12056
+	add	r0, sp, #20
12057
+	lsl	r2, r2, #10
12058
+	str	r3, [sp, #12]
12059
+	str	r2, [sp, #24]
12060
+	mov	r2, #1
12061
+	mov	r1, r2
12062
+	bl	FlashReadPages
12063
+	ldr	r2, [sp, #20]
12064
+	ldr	r3, [sp, #12]
12065
+	cmn	r2, #1
12066
+	beq	.L1984
12067
+	ldr	r2, [r10, #1728]
12068
+	ldrh	r1, [r2]
12069
+	movw	r2, #61664
12070
+	cmp	r1, r2
12071
+	bne	.L1984
12072
+	mov	r1, r7
12073
+	mov	r2, r4
12074
+	ldr	r0, .L1993+12
12075
+	add	r9, r9, #1
12076
+	bl	printk
12077
+	uxth	r9, r9
12078
+	ldr	r3, .L1993+8
12079
+	lsl	r7, r7, #1
12080
+	strh	r4, [r3, r7]	@ movhi
12081
+.L1985:
12082
+	ldrb	r3, [r8, #2234]	@ zero_extendqisi2
12083
+	add	r5, r5, #1
12084
+	cmp	r3, r9
12085
+	moveq	fp, #0
12086
+	b	.L1982
12087
+.L1984:
12088
+	sub	r4, r4, #1
12089
+	uxth	r4, r4
12090
+	b	.L1983
12091
+.L1994:
11617
12092
 	.align	2
11618
-.L2012:
12093
+.L1993:
11619
12094
 	.word	.LANCHOR0
11620
-	.word	.LANCHOR2+1736
11621
12095
 	.word	.LANCHOR2
12096
+	.word	.LANCHOR2+1742
11622
12097
 	.word	.LC103
11623
12098
 	.fnend
11624
12099
 	.size	FlashLoadFactorBbt, .-FlashLoadFactorBbt
11625
12100
 	.align	2
11626
12101
 	.global	FlashProgSlc2KPages
12102
+	.syntax unified
12103
+	.arm
12104
+	.fpu softvfp
11627
12105
 	.type	FlashProgSlc2KPages, %function
11628
12106
 FlashProgSlc2KPages:
11629
12107
 	.fnstart
11630
-	@ args = 0, pretend = 0, frame = 56
12108
+	@ args = 0, pretend = 0, frame = 48
11631
12109
 	@ frame_needed = 0, uses_anonymous_args = 0
11632
-	ldr	r3, .L2044
11633
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12110
+	ldr	r3, .L2023
12111
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
11634
12112
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11635
-	.pad #68
11636
-	sub	sp, sp, #68
11637
-	ldr	r8, .L2044+4
11638
-	mov	r6, r1
11639
-	ldrb	r3, [r3, #481]	@ zero_extendqisi2
11640
-	mov	r9, r2
12113
+	mov	r10, r1
12114
+	ldr	r9, .L2023+4
12115
+	.pad #60
12116
+	sub	sp, sp, #60
12117
+	mov	r8, r2
11641
12118
 	mov	r4, r0
11642
-	mov	r10, r0
12119
+	ldrb	fp, [r3, #477]	@ zero_extendqisi2
12120
+	mov	r6, r0
11643
12121
 	mov	r7, #0
11644
-	mov	fp, r8
11645
-	str	r3, [sp, #12]
11646
-.L2015:
12122
+.L1996:
12123
+	cmp	r7, r10
12124
+	bne	.L2002
12125
+	ldr	r5, .L2023+8
12126
+	mov	r6, #0
12127
+	ldr	r9, .L2023+12
12128
+.L2003:
11647
12129
 	cmp	r7, r6
11648
-	beq	.L2042
11649
-	rsb	r3, r7, r6
11650
-	add	r2, sp, #20
11651
-	mov	r0, r10
11652
-	mov	r1, r9
12130
+	bne	.L2010
12131
+	mov	r0, #0
12132
+	add	sp, sp, #60
12133
+	@ sp needed
12134
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
12135
+.L2002:
12136
+	sub	r3, r10, r7
12137
+	add	r2, sp, #12
11653
12138
 	uxtb	r3, r3
12139
+	mov	r1, r8
12140
+	mov	r0, r6
11654
12141
 	str	r3, [sp]
11655
-	add	r3, sp, #24
12142
+	add	r3, sp, #16
11656
12143
 	bl	LogAddr2PhyAddr
11657
-	ldrb	r2, [r8, #2230]	@ zero_extendqisi2
11658
-	ldr	r3, [sp, #24]
11659
-	cmp	r3, r2
11660
-	mvncs	r3, #0
11661
-	strcs	r3, [r10]
11662
-	bcs	.L2017
11663
-	add	r3, r8, r3
11664
-	ldrb	r5, [r3, #2232]	@ zero_extendqisi2
12144
+	ldrb	r2, [r9, #2234]	@ zero_extendqisi2
12145
+	ldr	r3, [sp, #16]
12146
+	cmp	r2, r3
12147
+	mvnls	r3, #0
12148
+	strls	r3, [r6]
12149
+	bls	.L1998
12150
+	add	r3, r9, r3
12151
+	ldrb	r5, [r3, #2236]	@ zero_extendqisi2
11665
12152
 	mov	r0, r5
11666
12153
 	bl	NandcWaitFlashReady
11667
12154
 	mov	r0, r5
11668
12155
 	bl	NandcFlashCs
11669
12156
 	mov	r0, r5
11670
-	ldr	r1, [sp, #20]
12157
+	ldr	r1, [sp, #12]
11671
12158
 	bl	FlashProgFirstCmd
11672
-	ldr	r3, [r10, #12]
12159
+	ldr	r3, [r6, #12]
12160
+	mov	r2, fp
11673
12161
 	mov	r1, #1
11674
12162
 	mov	r0, r5
11675
-	ldr	r2, [sp, #12]
11676
12163
 	str	r3, [sp]
11677
-	ldr	r3, [r10, #8]
12164
+	ldr	r3, [r6, #8]
11678
12165
 	bl	NandcXferData
11679
12166
 	mov	r0, r5
11680
-	ldr	r1, [sp, #20]
12167
+	ldr	r1, [sp, #12]
11681
12168
 	bl	FlashProgSecondCmd
11682
12169
 	mov	r0, r5
11683
12170
 	bl	NandcWaitFlashReady
11684
12171
 	mov	r0, r5
11685
-	ldr	r1, [sp, #20]
12172
+	ldr	r1, [sp, #12]
11686
12173
 	bl	FlashReadStatus
11687
-	ldr	r3, [sp, #20]
11688
12174
 	sbfx	r0, r0, #0, #1
11689
-	str	r0, [r10]
12175
+	ldr	r1, [sp, #12]
12176
+	str	r0, [r6]
11690
12177
 	mov	r0, r5
11691
-	ldr	r1, [r8, #4]
12178
+	ldr	r3, [r9, #40]
11692
12179
 	add	r1, r1, r3
11693
12180
 	bl	FlashProgFirstCmd
11694
-	ldr	r3, [r10, #8]
11695
-	ldr	r2, [r10, #12]
12181
+	ldr	r3, [r6, #8]
11696
12182
 	mov	r1, #1
11697
-	cmp	r3, #0
12183
+	ldr	r2, [r6, #12]
11698
12184
 	mov	r0, r5
12185
+	cmp	r3, #0
11699
12186
 	addne	r3, r3, #2048
11700
12187
 	cmp	r2, #0
11701
12188
 	addne	r2, r2, #8
11702
12189
 	str	r2, [sp]
11703
-	ldr	r2, [sp, #12]
12190
+	mov	r2, fp
11704
12191
 	bl	NandcXferData
11705
-	ldr	r1, [fp, #4]
12192
+	ldr	r3, [r9, #40]
11706
12193
 	mov	r0, r5
11707
-	ldr	r3, [sp, #20]
12194
+	ldr	r1, [sp, #12]
11708
12195
 	add	r1, r1, r3
11709
12196
 	bl	FlashProgSecondCmd
11710
12197
 	mov	r0, r5
11711
12198
 	bl	NandcWaitFlashReady
11712
12199
 	mov	r0, r5
11713
-	ldr	r1, [sp, #20]
12200
+	ldr	r1, [sp, #12]
11714
12201
 	bl	FlashReadStatus
11715
12202
 	tst	r0, #1
11716
12203
 	mov	r0, r5
11717
12204
 	mvnne	r3, #0
11718
-	strne	r3, [r10]
12205
+	strne	r3, [r6]
11719
12206
 	bl	NandcFlashDeCs
11720
-.L2017:
12207
+.L1998:
11721
12208
 	add	r7, r7, #1
11722
-	add	r10, r10, #36
11723
-	b	.L2015
11724
-.L2042:
11725
-	ldr	r5, .L2044+8
11726
-	mov	r7, #0
11727
-	mov	r8, r5
11728
-.L2022:
11729
-	cmp	r7, r6
11730
-	beq	.L2043
12209
+	add	r6, r6, #36
12210
+	b	.L1996
12211
+.L2010:
11731
12212
 	ldr	r3, [r4]
11732
12213
 	cmn	r3, #1
11733
-	bne	.L2023
12214
+	bne	.L2004
11734
12215
 	ldr	r1, [r4, #4]
11735
-	ldr	r0, .L2044+12
12216
+	ldr	r0, .L2023+16
11736
12217
 	bl	printk
11737
-	b	.L2024
11738
-.L2023:
11739
-	rsb	r3, r7, r6
11740
-	mov	r1, r9
11741
-	add	r2, sp, #20
11742
-	mov	r0, r4
12218
+.L2005:
12219
+	add	r6, r6, #1
12220
+	add	r4, r4, #36
12221
+	b	.L2003
12222
+.L2004:
12223
+	sub	r3, r7, r6
12224
+	add	r2, sp, #12
11743
12225
 	uxtb	r3, r3
12226
+	mov	r1, r8
12227
+	mov	r0, r4
11744
12228
 	str	r3, [sp]
11745
-	add	r3, sp, #24
12229
+	add	r3, sp, #16
11746
12230
 	bl	LogAddr2PhyAddr
11747
-	ldr	r2, [r5, #1724]
12231
+	ldr	r2, [r5, #1732]
11748
12232
 	mov	r3, #0
11749
12233
 	mov	lr, r4
12234
+	add	ip, sp, #20
11750
12235
 	str	r3, [r2]
11751
-	ldr	r2, [r5, #1728]
12236
+	ldr	r2, [r5, #1736]
11752
12237
 	str	r3, [r2]
11753
12238
 	ldmia	lr!, {r0, r1, r2, r3}
11754
-	add	ip, sp, #28
11755
12239
 	stmia	ip!, {r0, r1, r2, r3}
11756
12240
 	ldmia	lr!, {r0, r1, r2, r3}
11757
12241
 	stmia	ip!, {r0, r1, r2, r3}
11758
-	add	r0, sp, #28
12242
+	mov	r2, r8
11759
12243
 	ldr	r3, [lr]
11760
12244
 	mov	r1, #1
11761
-	mov	r2, r9
12245
+	add	r0, sp, #20
11762
12246
 	str	r3, [ip]
11763
-	ldr	r3, [r5, #1724]
11764
-	str	r3, [sp, #36]
11765
-	ldr	r3, [r5, #1728]
11766
-	str	r3, [sp, #40]
12247
+	ldr	r3, [r5, #1732]
12248
+	str	r3, [sp, #28]
12249
+	ldr	r3, [r5, #1736]
12250
+	str	r3, [sp, #32]
11767
12251
 	bl	FlashReadPages
11768
-	ldr	r10, [sp, #28]
12252
+	ldr	r10, [sp, #20]
11769
12253
 	cmn	r10, #1
11770
-	bne	.L2025
11771
-	ldr	r0, .L2044+16
12254
+	bne	.L2006
11772
12255
 	ldr	r1, [r4, #4]
12256
+	ldr	r0, .L2023+20
11773
12257
 	bl	printk
11774
12258
 	str	r10, [r4]
11775
-.L2025:
11776
-	ldr	r10, [sp, #28]
12259
+.L2006:
12260
+	ldr	r10, [sp, #20]
11777
12261
 	cmp	r10, #256
11778
-	bne	.L2026
11779
-	ldr	r0, .L2044+20
12262
+	bne	.L2007
11780
12263
 	ldr	r1, [r4, #4]
12264
+	ldr	r0, .L2023+24
11781
12265
 	bl	printk
11782
12266
 	str	r10, [r4]
11783
-.L2026:
12267
+.L2007:
11784
12268
 	ldr	r3, [r4, #12]
11785
12269
 	cmp	r3, #0
11786
-	beq	.L2027
12270
+	beq	.L2008
11787
12271
 	ldr	r2, [r3]
11788
-	ldr	r3, [r8, #1728]
12272
+	ldr	r3, [r5, #1736]
11789
12273
 	ldr	r3, [r3]
11790
12274
 	cmp	r2, r3
11791
-	beq	.L2027
11792
-	ldr	r0, .L2044+24
12275
+	beq	.L2008
11793
12276
 	ldr	r1, [r4, #4]
12277
+	ldr	r0, .L2023+28
11794
12278
 	bl	printk
11795
12279
 	mvn	r3, #0
11796
12280
 	str	r3, [r4]
11797
-.L2027:
12281
+.L2008:
11798
12282
 	ldr	r3, [r4, #8]
11799
12283
 	cmp	r3, #0
11800
-	beq	.L2024
12284
+	beq	.L2005
11801
12285
 	ldr	r2, [r3]
11802
-	ldr	r3, [r8, #1724]
12286
+	ldr	r3, [r5, #1732]
11803
12287
 	ldr	r3, [r3]
11804
12288
 	cmp	r2, r3
11805
-	beq	.L2024
11806
-	ldr	r0, .L2044+28
12289
+	beq	.L2005
11807
12290
 	ldr	r1, [r4, #4]
12291
+	mov	r0, r9
11808
12292
 	bl	printk
11809
12293
 	mvn	r3, #0
11810
12294
 	str	r3, [r4]
12295
+	b	.L2005
11811
12296
 .L2024:
11812
-	add	r7, r7, #1
11813
-	add	r4, r4, #36
11814
-	b	.L2022
11815
-.L2043:
11816
-	mov	r0, #0
11817
-	add	sp, sp, #68
11818
-	@ sp needed
11819
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
11820
-.L2045:
11821
12297
 	.align	2
11822
-.L2044:
12298
+.L2023:
11823
12299
 	.word	.LANCHOR1
11824
12300
 	.word	.LANCHOR0
11825
12301
 	.word	.LANCHOR2
12302
+	.word	.LC108
11826
12303
 	.word	.LC104
11827
12304
 	.word	.LC105
11828
12305
 	.word	.LC106
11829
12306
 	.word	.LC107
11830
-	.word	.LC108
11831
12307
 	.fnend
11832
12308
 	.size	FlashProgSlc2KPages, .-FlashProgSlc2KPages
11833
12309
 	.align	2
11834
12310
 	.global	FtlLoadFactoryBbt
12311
+	.syntax unified
12312
+	.arm
12313
+	.fpu softvfp
11835
12314
 	.type	FtlLoadFactoryBbt, %function
11836
12315
 FtlLoadFactoryBbt:
11837
12316
 	.fnstart
11838
12317
 	@ args = 0, pretend = 0, frame = 8
11839
12318
 	@ frame_needed = 0, uses_anonymous_args = 0
11840
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
12319
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
11841
12320
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11842
12321
 	.pad #12
11843
12322
 	mov	r7, #0
11844
-	ldr	r5, .L2058
11845
-	ldr	r6, .L2058+4
12323
+	ldr	r5, .L2036
12324
+	ldr	r6, .L2036+4
11846
12325
 	ldr	r3, [r5, #-524]
11847
-	sub	r9, r6, #76
11848
12326
 	ldr	r8, [r5, #-500]
11849
12327
 	sub	r10, r6, #120
11850
-	mov	fp, r9
11851
-	str	r3, [r5, #1760]
11852
-	str	r8, [r5, #1764]
11853
-.L2047:
12328
+	sub	r9, r6, #78
12329
+	str	r3, [r5, #1768]
12330
+	str	r8, [r5, #1772]
12331
+.L2026:
11854
12332
 	ldrh	r3, [r10]
11855
12333
 	cmp	r7, r3
11856
-	bcs	.L2057
11857
-	ldrh	r4, [r9]
11858
-	mvn	r3, #0
11859
-	movw	ip, #61664
11860
-	strh	r3, [r6, #2]!	@ movhi
11861
-	add	r4, r4, r3
11862
-	uxth	r4, r4
11863
-.L2048:
11864
-	ldrh	r3, [fp]
11865
-	sub	r2, r3, #16
11866
-	cmp	r4, r2
11867
-	ble	.L2050
11868
-	mla	r3, r3, r7, r4
11869
-	mov	r1, #1
11870
-	ldr	r0, .L2058+8
11871
-	mov	r2, r1
11872
-	str	ip, [sp, #4]
11873
-	mov	r3, r3, asl #10
11874
-	str	r3, [r5, #1756]
11875
-	bl	FlashReadPages
11876
-	ldr	r3, [r5, #1752]
11877
-	cmn	r3, #1
11878
-	ldr	ip, [sp, #4]
11879
-	beq	.L2049
11880
-	ldrh	r3, [r8]
11881
-	cmp	r3, ip
11882
-	streqh	r4, [r6]	@ movhi
11883
-	beq	.L2050
11884
-.L2049:
11885
-	sub	r4, r4, #1
11886
-	uxth	r4, r4
11887
-	b	.L2048
11888
-.L2050:
11889
-	add	r7, r7, #1
11890
-	b	.L2047
11891
-.L2057:
12334
+	bcc	.L2031
11892
12335
 	mov	r0, #0
11893
12336
 	add	sp, sp, #12
11894
12337
 	@ sp needed
11895
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
11896
-.L2059:
12338
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
12339
+.L2031:
12340
+	ldrh	r4, [r9]
12341
+	mvn	r3, #0
12342
+	ldr	fp, .L2036+8
12343
+	strh	r3, [r6, #2]!	@ movhi
12344
+	add	r4, r4, r3
12345
+	movw	r3, #61664
12346
+	uxth	r4, r4
12347
+.L2027:
12348
+	ldrh	r2, [r9]
12349
+	sub	r1, r2, #16
12350
+	cmp	r4, r1
12351
+	ble	.L2029
12352
+	mla	r2, r7, r2, r4
12353
+	str	r3, [sp, #4]
12354
+	mov	r0, fp
12355
+	lsl	r2, r2, #10
12356
+	str	r2, [r5, #1764]
12357
+	mov	r2, #1
12358
+	mov	r1, r2
12359
+	bl	FlashReadPages
12360
+	ldr	r2, [r5, #1760]
12361
+	ldr	r3, [sp, #4]
12362
+	cmn	r2, #1
12363
+	beq	.L2028
12364
+	ldrh	r2, [r8]
12365
+	cmp	r2, r3
12366
+	bne	.L2028
12367
+	strh	r4, [r6]	@ movhi
12368
+.L2029:
12369
+	add	r7, r7, #1
12370
+	b	.L2026
12371
+.L2028:
12372
+	sub	r4, r4, #1
12373
+	uxth	r4, r4
12374
+	b	.L2027
12375
+.L2037:
11897
12376
 	.align	2
11898
-.L2058:
12377
+.L2036:
11899
12378
 	.word	.LANCHOR2
11900
-	.word	.LANCHOR0+2462
11901
-	.word	.LANCHOR2+1752
12379
+	.word	.LANCHOR0+2466
12380
+	.word	.LANCHOR2+1760
11902
12381
 	.fnend
11903
12382
 	.size	FtlLoadFactoryBbt, .-FtlLoadFactoryBbt
11904
12383
 	.align	2
11905
12384
 	.global	FtlGetLastWrittenPage
12385
+	.syntax unified
12386
+	.arm
12387
+	.fpu softvfp
11906
12388
 	.type	FtlGetLastWrittenPage, %function
11907
12389
 FtlGetLastWrittenPage:
11908
12390
 	.fnstart
11909
12391
 	@ args = 0, pretend = 0, frame = 104
11910
12392
 	@ frame_needed = 0, uses_anonymous_args = 0
12393
+	ldr	r3, .L2051
11911
12394
 	cmp	r1, #1
11912
-	ldr	r3, .L2073
11913
-	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
12395
+	movweq	r2, #2392
12396
+	movwne	r2, #2390
12397
+	push	{r4, r5, r6, r7, r8, lr}
11914
12398
 	.save {r4, r5, r6, r7, r8, lr}
11915
-	movweq	r2, #2390
11916
-	movwne	r2, #2388
12399
+	lsl	r8, r0, #10
12400
+	ldrh	r5, [r3, r2]
11917
12401
 	.pad #104
11918
12402
 	sub	sp, sp, #104
11919
-	ldrh	r4, [r3, r2]
11920
-	mov	r8, r1
11921
12403
 	add	r3, sp, #40
11922
-	mov	r6, r0, asl #10
11923
-	sub	r5, r4, #1
12404
+	mov	r2, r1
11924
12405
 	str	r3, [sp, #16]
11925
-	add	r0, sp, #4
12406
+	mov	r7, r1
12407
+	sub	r5, r5, #1
12408
+	mov	r6, #0
12409
+	sxth	r5, r5
11926
12410
 	mov	r1, #1
11927
-	uxth	r5, r5
11928
-	mov	r2, r8
11929
-	mov	r7, #0
11930
-	str	r7, [sp, #12]
11931
-	sxth	r3, r5
11932
-	orr	r3, r3, r6
12411
+	add	r0, sp, #4
12412
+	str	r6, [sp, #12]
12413
+	orr	r3, r5, r8
11933
12414
 	str	r3, [sp, #8]
11934
12415
 	bl	FlashReadPages
11935
12416
 	ldr	r3, [sp, #40]
11936
12417
 	cmn	r3, #1
11937
-	bne	.L2063
11938
-.L2064:
11939
-	sxth	r4, r7
11940
-	sxth	r3, r5
11941
-	cmp	r4, r3
11942
-	bgt	.L2063
11943
-	add	r4, r4, r3
11944
-	add	r0, sp, #4
12418
+	bne	.L2041
12419
+.L2042:
12420
+	cmp	r6, r5
12421
+	ble	.L2045
12422
+.L2041:
12423
+	mov	r0, r5
12424
+	add	sp, sp, #104
12425
+	@ sp needed
12426
+	pop	{r4, r5, r6, r7, r8, pc}
12427
+.L2045:
12428
+	add	r3, r6, r5
12429
+	mov	r2, r7
12430
+	add	r3, r3, r3, lsr #31
11945
12431
 	mov	r1, #1
11946
-	mov	r2, r8
11947
-	add	r4, r4, r4, lsr #31
11948
-	mov	r4, r4, asr #1
12432
+	add	r0, sp, #4
12433
+	asr	r4, r3, #1
11949
12434
 	sxth	r3, r4
11950
-	orr	r3, r3, r6
12435
+	orr	r3, r3, r8
11951
12436
 	str	r3, [sp, #8]
11952
12437
 	bl	FlashReadPages
11953
12438
 	ldr	r3, [sp, #40]
11954
12439
 	cmn	r3, #1
11955
-	bne	.L2065
12440
+	bne	.L2043
11956
12441
 	ldr	r3, [sp, #44]
11957
12442
 	cmn	r3, #1
11958
-	bne	.L2065
12443
+	bne	.L2043
11959
12444
 	ldr	r3, [sp, #4]
11960
12445
 	cmn	r3, #1
11961
12446
 	subne	r4, r4, #1
11962
-	uxthne	r5, r4
11963
-	bne	.L2064
11964
-.L2065:
11965
-	add	r3, r4, #1
11966
-	uxth	r7, r3
11967
-	b	.L2064
11968
-.L2063:
11969
-	sxth	r0, r5
11970
-	add	sp, sp, #104
11971
-	@ sp needed
11972
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
11973
-.L2074:
12447
+	sxthne	r5, r4
12448
+	bne	.L2042
12449
+.L2043:
12450
+	add	r4, r4, #1
12451
+	sxth	r6, r4
12452
+	b	.L2042
12453
+.L2052:
11974
12454
 	.align	2
11975
-.L2073:
12455
+.L2051:
11976
12456
 	.word	.LANCHOR0
11977
12457
 	.fnend
11978
12458
 	.size	FtlGetLastWrittenPage, .-FtlGetLastWrittenPage
11979
12459
 	.align	2
11980
12460
 	.global	FtlLoadBbt
12461
+	.syntax unified
12462
+	.arm
12463
+	.fpu softvfp
11981
12464
 	.type	FtlLoadBbt, %function
11982
12465
 FtlLoadBbt:
11983
12466
 	.fnstart
11984
12467
 	@ args = 0, pretend = 0, frame = 0
11985
12468
 	@ frame_needed = 0, uses_anonymous_args = 0
11986
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
11987
-	.save {r3, r4, r5, r6, r7, r8, r9, lr}
11988
-	ldr	r4, .L2108
11989
-	ldr	r7, .L2108+4
11990
-	ldr	r8, .L2108+8
12469
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
12470
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
12471
+	ldr	r4, .L2085
12472
+	ldr	r5, .L2085+4
11991
12473
 	ldr	r3, [r4, #-524]
11992
-	mov	r9, r4
11993
-	ldr	r6, [r4, #-500]
11994
-	str	r3, [r4, #1760]
11995
-	str	r6, [r4, #1764]
12474
+	add	r8, r4, #1760
12475
+	ldr	r7, [r4, #-500]
12476
+	ldr	r9, .L2085+8
12477
+	str	r3, [r4, #1768]
12478
+	str	r7, [r4, #1772]
11996
12479
 	bl	FtlBbtMemInit
11997
-	movw	r3, #2386
11998
-	ldrh	r5, [r7, r3]
11999
-	sub	r5, r5, #1
12000
-	uxth	r5, r5
12001
-.L2076:
12002
-	ldrh	r3, [r8]
12480
+	movw	r3, #2388
12481
+	ldrh	r6, [r5, r3]
12482
+	sub	r6, r6, #1
12483
+	uxth	r6, r6
12484
+.L2054:
12485
+	ldrh	r3, [r9]
12003
12486
 	sub	r3, r3, #48
12004
-	cmp	r5, r3
12005
-	ble	.L2079
12006
-	mov	r1, #1
12007
-	ldr	r0, .L2108+12
12008
-	mov	r2, r1
12009
-	mov	r3, r5, asl #10
12010
-	str	r3, [r4, #1756]
12487
+	cmp	r6, r3
12488
+	ble	.L2057
12489
+	lsl	r3, r6, #10
12490
+	mov	r2, #1
12491
+	mov	r1, r2
12492
+	mov	r0, r8
12493
+	str	r3, [r4, #1764]
12011
12494
 	bl	FlashReadPages
12012
-	ldr	r3, [r4, #1752]
12495
+	ldr	r3, [r4, #1760]
12013
12496
 	cmn	r3, #1
12014
-	bne	.L2077
12015
-	ldr	r3, [r9, #1756]
12016
-	mov	r1, #1
12017
-	ldr	r0, .L2108+12
12018
-	mov	r2, r1
12497
+	bne	.L2055
12498
+	ldr	r3, [r4, #1764]
12499
+	mov	r2, #1
12500
+	mov	r1, r2
12501
+	mov	r0, r8
12019
12502
 	add	r3, r3, #1
12020
-	str	r3, [r9, #1756]
12503
+	str	r3, [r4, #1764]
12021
12504
 	bl	FlashReadPages
12022
-.L2077:
12023
-	ldr	r3, [r4, #1752]
12505
+.L2055:
12506
+	ldr	r3, [r4, #1760]
12024
12507
 	cmn	r3, #1
12025
-	beq	.L2078
12026
-	ldrh	r2, [r6]
12508
+	beq	.L2056
12509
+	ldrh	r2, [r7]
12027
12510
 	movw	r3, #61649
12028
12511
 	cmp	r2, r3
12029
-	bne	.L2078
12030
-	movw	r3, #2452
12031
-	strh	r5, [r7, r3]	@ movhi
12032
-	ldr	r3, [r6, #4]
12033
-	str	r3, [r7, #2460]
12034
-	ldr	r3, .L2108+16
12035
-	ldrh	r2, [r6, #8]
12512
+	bne	.L2056
12513
+	movw	r3, #2456
12514
+	strh	r6, [r5, r3]	@ movhi
12515
+	ldr	r3, [r7, #4]
12516
+	str	r3, [r5, #2464]
12517
+	ldr	r3, .L2085+12
12518
+	ldrh	r2, [r7, #8]
12036
12519
 	strh	r2, [r3, #4]	@ movhi
12037
-	b	.L2079
12038
-.L2078:
12039
-	sub	r5, r5, #1
12040
-	uxth	r5, r5
12041
-	b	.L2076
12042
-.L2079:
12043
-	movw	r9, #2452
12520
+.L2057:
12521
+	movw	r8, #2456
12044
12522
 	movw	r2, #65535
12045
-	ldrh	r3, [r7, r9]
12046
-	ldr	r8, .L2108+4
12523
+	ldrh	r3, [r5, r8]
12524
+	ldr	r6, .L2085+12
12047
12525
 	cmp	r3, r2
12048
-	ldr	r5, .L2108+16
12049
-	beq	.L2093
12050
-	ldrh	r3, [r5, #4]
12526
+	beq	.L2071
12527
+	ldrh	r3, [r6, #4]
12051
12528
 	cmp	r3, r2
12052
-	beq	.L2083
12053
-	mov	r1, #1
12054
-	ldr	r0, .L2108+12
12055
-	mov	r2, r1
12056
-	mov	r3, r3, asl #10
12057
-	str	r3, [r4, #1756]
12529
+	beq	.L2061
12530
+	lsl	r3, r3, #10
12531
+	mov	r2, #1
12532
+	mov	r1, r2
12533
+	ldr	r0, .L2085+16
12534
+	str	r3, [r4, #1764]
12058
12535
 	bl	FlashReadPages
12059
-	ldr	r3, [r4, #1752]
12536
+	ldr	r3, [r4, #1760]
12060
12537
 	cmn	r3, #1
12061
-	beq	.L2083
12062
-	ldrh	r2, [r6]
12538
+	beq	.L2061
12539
+	ldrh	r2, [r7]
12063
12540
 	movw	r3, #61649
12064
12541
 	cmp	r2, r3
12065
-	bne	.L2083
12066
-	ldr	r3, [r6, #4]
12067
-	ldr	r2, [r8, #2460]
12542
+	bne	.L2061
12543
+	ldr	r3, [r7, #4]
12544
+	ldr	r2, [r5, #2464]
12068
12545
 	cmp	r3, r2
12069
-	strhi	r3, [r8, #2460]
12070
-	ldrhih	r2, [r5, #4]
12071
-	ldrhih	r3, [r6, #8]
12072
-	strhih	r2, [r8, r9]	@ movhi
12073
-	strhih	r3, [r5, #4]	@ movhi
12074
-.L2083:
12075
-	movw	r3, #2452
12546
+	ldrhhi	r2, [r6, #4]
12547
+	strhi	r3, [r5, #2464]
12548
+	ldrhhi	r3, [r7, #8]
12549
+	strhhi	r2, [r5, r8]	@ movhi
12550
+	strhhi	r3, [r6, #4]	@ movhi
12551
+.L2061:
12552
+	ldr	r9, .L2085+16
12553
+	movw	r3, #2456
12076
12554
 	mov	r1, #1
12077
-	ldrh	r0, [r7, r3]
12078
-	movw	r8, #61649
12555
+	ldrh	r0, [r5, r3]
12556
+	movw	r10, #61649
12079
12557
 	bl	FtlGetLastWrittenPage
12080
-	uxth	r7, r0
12558
+	sxth	r8, r0
12081
12559
 	add	r0, r0, #1
12082
-	strh	r0, [r5, #2]	@ movhi
12083
-.L2085:
12084
-	sxth	r3, r7
12085
-	cmp	r3, #0
12086
-	blt	.L2090
12087
-	ldrh	r2, [r5]
12088
-	mov	r1, #1
12089
-	ldr	r0, .L2108+12
12090
-	orr	r3, r3, r2, asl #10
12091
-	str	r3, [r4, #1756]
12092
-	ldr	r3, [r4, #-524]
12093
-	mov	r2, r1
12094
-	str	r3, [r4, #1760]
12095
-	bl	FlashReadPages
12096
-	ldr	r3, [r4, #1752]
12097
-	cmn	r3, #1
12098
-	beq	.L2086
12560
+	strh	r0, [r6, #2]	@ movhi
12561
+.L2063:
12562
+	cmp	r8, #0
12563
+	blt	.L2068
12099
12564
 	ldrh	r3, [r6]
12100
-	cmp	r3, r8
12101
-	bne	.L2086
12102
-.L2090:
12103
-	ldrh	r2, [r6, #10]
12104
-	ldrh	r0, [r6, #12]
12105
-	ldr	r3, .L2108+4
12106
-	strh	r2, [r5, #6]	@ movhi
12107
-	movw	r2, #65535
12108
-	cmp	r0, r2
12109
-	bne	.L2087
12110
-	b	.L2088
12111
-.L2086:
12112
-	sub	r7, r7, #1
12113
-	uxth	r7, r7
12114
-	b	.L2085
12115
-.L2087:
12116
-	ldr	r2, [r3, #2316]
12117
-	cmp	r0, r2
12118
-	beq	.L2088
12119
-	movw	r1, #2330
12120
-	ldrh	r3, [r3, r1]
12121
-	mov	r3, r3, lsr #2
12565
+	mov	r2, #1
12566
+	mov	r1, r2
12567
+	mov	r0, r9
12568
+	orr	r3, r8, r3, lsl #10
12569
+	str	r3, [r4, #1764]
12570
+	ldr	r3, [r4, #-524]
12571
+	str	r3, [r4, #1768]
12572
+	bl	FlashReadPages
12573
+	ldr	r3, [r4, #1760]
12574
+	cmn	r3, #1
12575
+	beq	.L2064
12576
+	ldrh	r3, [r7]
12577
+	cmp	r3, r10
12578
+	bne	.L2064
12579
+.L2068:
12580
+	ldrh	r3, [r7, #10]
12581
+	ldrh	r0, [r7, #12]
12582
+	strh	r3, [r6, #6]	@ movhi
12583
+	movw	r3, #65535
12122
12584
 	cmp	r0, r3
12123
-	cmpcc	r2, r3
12124
-	bcs	.L2088
12125
-	bl	FtlSysBlkNumInit
12126
-.L2088:
12127
-	ldr	r6, .L2108+20
12585
+	bne	.L2065
12586
+.L2066:
12587
+	ldr	r6, .L2085+20
12128
12588
 	mov	r5, #0
12129
-	ldr	r8, .L2108+24
12589
+	ldr	r8, .L2085+24
12130
12590
 	sub	r7, r6, #134
12131
-.L2091:
12591
+.L2069:
12132
12592
 	ldrh	r3, [r7]
12133
12593
 	cmp	r5, r3
12134
-	bcs	.L2107
12135
-	ldrh	r2, [r8]
12136
-	ldr	r1, [r4, #1760]
12137
-	ldr	r0, [r6, #4]!
12138
-	mov	r2, r2, asl #2
12139
-	mla	r1, r5, r2, r1
12140
-	bl	ftl_memcpy
12141
-	add	r5, r5, #1
12142
-	b	.L2091
12143
-.L2107:
12594
+	bcc	.L2070
12144
12595
 	mov	r0, #0
12145
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
12146
-.L2093:
12596
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
12597
+.L2056:
12598
+	sub	r6, r6, #1
12599
+	uxth	r6, r6
12600
+	b	.L2054
12601
+.L2064:
12602
+	sub	r8, r8, #1
12603
+	sxth	r8, r8
12604
+	b	.L2063
12605
+.L2065:
12606
+	ldr	r2, [r5, #2320]
12607
+	cmp	r0, r2
12608
+	beq	.L2066
12609
+	movw	r3, #2334
12610
+	ldrh	r3, [r5, r3]
12611
+	lsr	r3, r3, #2
12612
+	cmp	r2, r3
12613
+	cmpcc	r0, r3
12614
+	bcs	.L2066
12615
+	bl	FtlSysBlkNumInit
12616
+	b	.L2066
12617
+.L2070:
12618
+	ldrh	r2, [r8]
12619
+	ldr	r1, [r4, #1768]
12620
+	ldr	r0, [r6, #4]!
12621
+	lsl	r2, r2, #2
12622
+	mla	r1, r5, r2, r1
12623
+	add	r5, r5, #1
12624
+	bl	ftl_memcpy
12625
+	b	.L2069
12626
+.L2071:
12147
12627
 	mvn	r0, #0
12148
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
12149
-.L2109:
12628
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
12629
+.L2086:
12150
12630
 	.align	2
12151
-.L2108:
12631
+.L2085:
12152
12632
 	.word	.LANCHOR2
12153
12633
 	.word	.LANCHOR0
12154
-	.word	.LANCHOR0+2386
12155
-	.word	.LANCHOR2+1752
12156
-	.word	.LANCHOR0+2452
12157
-	.word	.LANCHOR0+2476
12634
+	.word	.LANCHOR0+2388
12635
+	.word	.LANCHOR0+2456
12636
+	.word	.LANCHOR2+1760
12637
+	.word	.LANCHOR0+2480
12158
12638
 	.word	.LANCHOR2-436
12159
12639
 	.fnend
12160
12640
 	.size	FtlLoadBbt, .-FtlLoadBbt
12161
12641
 	.align	2
12162
12642
 	.global	FtlScanSysBlk
12643
+	.syntax unified
12644
+	.arm
12645
+	.fpu softvfp
12163
12646
 	.type	FtlScanSysBlk, %function
12164
12647
 FtlScanSysBlk:
12165
12648
 	.fnstart
12166
-	@ args = 0, pretend = 0, frame = 32
12649
+	@ args = 0, pretend = 0, frame = 24
12167
12650
 	@ frame_needed = 0, uses_anonymous_args = 0
12168
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12651
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
12169
12652
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12170
-	mov	r5, #0
12171
-	ldr	r7, .L2196
12172
-	mov	r1, r5
12173
-	ldr	r4, .L2196+4
12174
-	.pad #36
12175
-	sub	sp, sp, #36
12176
-	movw	r6, #2408
12177
-	ldr	r2, [r7, #2416]
12178
-	sub	r3, r4, #388
12653
+	mov	r6, #0
12654
+	ldr	r5, .L2166
12655
+	movw	r3, #2438
12656
+	mov	r1, r6
12657
+	.pad #28
12658
+	sub	sp, sp, #28
12659
+	ldr	r4, .L2166+4
12660
+	movw	r8, #2412
12661
+	ldr	r2, [r5, #2420]
12662
+	strh	r6, [r5, r3]	@ movhi
12663
+	sub	r7, r4, #388
12179
12664
 	ldr	r0, [r4, #-444]
12180
-	mov	r8, r4
12181
-	strh	r5, [r3]	@ movhi
12182
-	movw	r3, #2434
12183
-	mov	r2, r2, asl #2
12184
-	strh	r5, [r7, r3]	@ movhi
12665
+	strh	r6, [r7]	@ movhi
12666
+	lsl	r2, r2, #2
12185
12667
 	bl	ftl_memset
12186
-	ldr	r2, [r7, #2416]
12187
-	mov	r1, r5
12668
+	ldr	r2, [r5, #2420]
12669
+	mov	r1, r6
12188
12670
 	ldr	r0, [r4, #-472]
12189
-	mov	r2, r2, asl #1
12671
+	lsl	r2, r2, #1
12190
12672
 	bl	ftl_memset
12191
-	ldrh	r2, [r7, r6]
12192
-	mov	r1, r5
12673
+	ldrh	r2, [r5, r8]
12674
+	mov	r1, r6
12193
12675
 	ldr	r0, [r4, #-460]
12194
-	mov	r2, r2, asl #2
12676
+	lsl	r2, r2, #2
12195
12677
 	bl	ftl_memset
12196
-	ldrh	r2, [r7, r6]
12197
-	ldr	r0, [r7, #2436]
12198
-	mov	r1, r5
12199
-	mov	r2, r2, asl #1
12678
+	ldrh	r2, [r5, r8]
12679
+	mov	r1, r6
12680
+	ldr	r0, [r5, #2440]
12681
+	lsl	r2, r2, #1
12200
12682
 	bl	ftl_memset
12201
-	ldr	r0, .L2196+8
12202
-	mov	r1, #255
12683
+	sub	r0, r4, #3296
12203
12684
 	mov	r2, #16
12685
+	mov	r1, #255
12686
+	sub	r0, r0, #4
12204
12687
 	bl	ftl_memset
12205
-	movw	r3, #2328
12206
-	ldrh	r3, [r7, r3]
12207
-	str	r7, [sp, #16]
12208
-	mov	r7, r4
12209
-	str	r3, [sp, #4]
12210
-.L2111:
12211
-	ldr	r3, .L2196+12
12212
-	ldr	r2, [sp, #4]
12213
-	ldr	r1, .L2196
12688
+	movw	r3, #2332
12689
+	str	r7, [sp]
12690
+	ldrh	fp, [r5, r3]
12691
+	str	r5, [sp, #4]
12692
+.L2088:
12693
+	ldr	r3, .L2166+8
12694
+	ldr	r2, .L2166
12214
12695
 	ldrh	r3, [r3]
12215
-	cmp	r3, r2
12216
-	mov	r0, r1
12217
-	bls	.L2152
12218
-	add	r3, r1, #2320
12219
-	add	r1, r1, #2400
12220
-	ldr	r0, [r4, #-2692]
12221
-	mov	r5, #0
12222
-	ldrh	ip, [r3]
12223
-	sub	r6, r1, #52
12224
-	ldr	r3, [r4, #-536]
12225
-	mov	fp, r5
12226
-	ldr	r2, [r4, #-2696]
12227
-	mov	r9, #36
12696
+	cmp	r3, fp
12697
+	bls	.L2128
12698
+	ldr	r1, [r4, #-2692]
12699
+	mov	r6, #0
12700
+	ldr	r3, .L2166+12
12701
+	mov	r5, r6
12702
+	ldr	r7, [r4, #-536]
12703
+	mov	r8, #36
12704
+	str	r1, [sp, #8]
12705
+	ldr	r1, .L2166+16
12706
+	ldrh	r2, [r3]
12707
+	ldr	r3, [r4, #-2696]
12228
12708
 	ldrh	r10, [r1]
12229
-	str	r0, [sp, #8]
12230
-.L2153:
12231
-	uxth	r1, r5
12232
-	cmp	r1, ip
12233
-	bcs	.L2191
12234
-	ldr	r1, [sp, #4]
12235
-	ldrb	r0, [r6, r5]	@ zero_extendqisi2
12236
-	str	r2, [sp, #28]
12237
-	str	r3, [sp, #24]
12238
-	str	ip, [sp, #20]
12709
+	sub	r9, r1, #52
12710
+	b	.L2129
12711
+.L2090:
12712
+	mov	r1, fp
12713
+	ldrb	r0, [r9, r6]	@ zero_extendqisi2
12714
+	str	r3, [sp, #20]
12715
+	str	r2, [sp, #16]
12239
12716
 	bl	V2P_block
12240
12717
 	str	r0, [sp, #12]
12241
12718
 	bl	FtlBbmIsBadBlock
12242
12719
 	cmp	r0, #0
12720
+	ldr	r2, [sp, #16]
12721
+	ldr	r3, [sp, #20]
12722
+	bne	.L2089
12243
12723
 	ldr	r1, [sp, #12]
12244
-	ldr	ip, [sp, #20]
12245
-	ldr	r3, [sp, #24]
12246
-	ldr	r2, [sp, #28]
12247
-	bne	.L2112
12248
-	mla	r0, r9, fp, r3
12249
-	mov	r1, r1, asl #10
12250
-	stmib	r0, {r1, r2}
12251
-	mul	r1, r10, fp
12252
-	add	lr, r1, #3
12253
-	cmp	r1, #0
12254
-	movlt	r1, lr
12255
-	ldr	lr, [sp, #8]
12256
-	bic	r1, r1, #3
12257
-	add	r1, lr, r1
12258
-	str	r1, [r0, #12]
12259
-	add	r0, fp, #1
12260
-	uxth	fp, r0
12261
-.L2112:
12724
+	mla	r0, r8, r5, r7
12725
+	lsl	r1, r1, #10
12726
+	stmib	r0, {r1, r3}
12727
+	mul	r1, r10, r5
12262
12728
 	add	r5, r5, #1
12263
-	b	.L2153
12264
-.L2191:
12265
-	cmp	fp, #0
12266
-	beq	.L2115
12267
-	ldr	r0, [r4, #-536]
12268
-	mov	r1, fp
12729
+	uxth	r5, r5
12730
+	add	ip, r1, #3
12731
+	cmp	r1, #0
12732
+	movlt	r1, ip
12733
+	ldr	ip, [sp, #8]
12734
+	bic	r1, r1, #3
12735
+	add	r1, ip, r1
12736
+	str	r1, [r0, #12]
12737
+.L2089:
12738
+	add	r6, r6, #1
12739
+.L2129:
12740
+	uxth	r1, r6
12741
+	cmp	r2, r1
12742
+	bhi	.L2090
12743
+	cmp	r5, #0
12744
+	bne	.L2091
12745
+.L2127:
12746
+	add	r3, fp, #1
12747
+	uxth	fp, r3
12748
+	b	.L2088
12749
+.L2091:
12750
+	mov	r8, #0
12269
12751
 	mov	r2, #1
12752
+	mov	r1, r5
12753
+	mov	r0, r7
12270
12754
 	bl	FlashReadPages
12271
-	mov	r3, #0
12272
-.L2189:
12273
-	str	r3, [sp, #8]
12274
-	ldrh	r3, [sp, #8]
12275
-	cmp	r3, fp
12276
-	bcs	.L2115
12277
-	ldr	r3, [sp, #8]
12755
+.L2092:
12756
+	uxth	r3, r8
12757
+	cmp	r5, r3
12758
+	bls	.L2127
12278
12759
 	mov	r9, #36
12279
-	mul	r9, r9, r3
12280
12760
 	ldr	r3, [r4, #-536]
12761
+	mul	r9, r9, r8
12281
12762
 	add	r2, r3, r9
12282
12763
 	ldr	r3, [r3, r9]
12283
-	ldr	r5, [r2, #4]
12764
+	ldr	r6, [r2, #4]
12765
+	ldr	r7, [r2, #12]
12284
12766
 	cmn	r3, #1
12285
-	ldr	r6, [r2, #12]
12286
-	ubfx	r5, r5, #10, #16
12287
-	bne	.L2118
12767
+	ubfx	r6, r6, #10, #16
12768
+	bne	.L2095
12288
12769
 	mov	r10, #16
12289
-	movw	ip, #65535
12290
-.L2117:
12770
+.L2097:
12291
12771
 	ldr	r0, [r4, #-536]
12292
-	mov	r1, #1
12293
-	mov	r2, r1
12294
-	str	ip, [sp, #12]
12772
+	mov	r2, #1
12773
+	mov	r1, r2
12295
12774
 	add	r0, r0, r9
12296
12775
 	ldr	r3, [r0, #4]
12297
12776
 	add	r3, r3, #1
12298
12777
 	str	r3, [r0, #4]
12299
12778
 	bl	FlashReadPages
12300
-	ldrh	r3, [r6]
12301
-	ldr	ip, [sp, #12]
12302
-	cmp	r3, ip
12303
-	ldreq	r3, [r8, #-536]
12304
-	mvneq	r2, #0
12305
-	streq	r2, [r3, r9]
12306
-	beq	.L2118
12307
-.L2119:
12308
-	ldr	r3, [r7, #-536]
12779
+	ldrh	r3, [r7]
12780
+	movw	r2, #65535
12781
+	cmp	r3, r2
12782
+	ldr	r3, [r4, #-536]
12783
+	bne	.L2094
12784
+	mvn	r2, #0
12785
+	str	r2, [r3, r9]
12786
+	ldr	r3, [r4, #-536]
12787
+	ldr	r3, [r3, r9]
12788
+	cmp	r3, r2
12789
+	beq	.L2096
12790
+.L2095:
12791
+	ldr	r2, [r4, #-3332]
12792
+	ldr	r3, [r7, #4]
12793
+	cmn	r2, #1
12794
+	beq	.L2098
12795
+	cmp	r2, r3
12796
+	bhi	.L2099
12797
+.L2098:
12798
+	cmn	r3, #1
12799
+	addne	r2, r3, #1
12800
+	strne	r2, [r4, #-3332]
12801
+.L2099:
12802
+	ldrh	r2, [r7]
12803
+	movw	r1, #61604
12804
+	cmp	r2, r1
12805
+	beq	.L2101
12806
+	bhi	.L2102
12807
+	movw	r3, #61574
12808
+	cmp	r2, r3
12809
+	beq	.L2103
12810
+.L2100:
12811
+	add	r8, r8, #1
12812
+	b	.L2092
12813
+.L2094:
12309
12814
 	ldr	r3, [r3, r9]
12310
12815
 	cmn	r3, #1
12311
-	bne	.L2118
12816
+	bne	.L2095
12312
12817
 	sub	r10, r10, #1
12313
12818
 	uxth	r10, r10
12314
12819
 	cmp	r10, #0
12315
-	bne	.L2117
12316
-.L2118:
12317
-	ldr	r3, [r7, #-536]
12318
-	ldr	r3, [r3, r9]
12319
-	cmn	r3, #1
12320
-	beq	.L2121
12321
-	ldr	r2, [r7, #-3332]
12322
-	ldr	r3, [r6, #4]
12323
-	cmn	r2, #1
12324
-	beq	.L2122
12325
-	cmp	r2, r3
12326
-	bhi	.L2123
12327
-.L2122:
12328
-	cmn	r3, #1
12329
-	addne	r2, r3, #1
12330
-	strne	r2, [r8, #-3332]
12331
-.L2123:
12332
-	ldrh	r2, [r6]
12333
-	movw	r1, #61604
12334
-	cmp	r2, r1
12335
-	beq	.L2125
12336
-	bhi	.L2126
12337
-	movw	r3, #61574
12338
-	cmp	r2, r3
12339
-	bne	.L2124
12340
-	ldr	r2, .L2196+16
12341
-	ldr	lr, [r8, #-460]
12342
-	ldrh	ip, [r2]
12343
-	ldrh	r1, [r2, #26]
12344
-	sub	r0, ip, #1
12345
-	rsb	r2, r1, r0
12346
-	str	r2, [sp, #12]
12347
-	uxth	r3, r0
12348
-	b	.L2139
12349
-.L2126:
12820
+	bne	.L2097
12821
+.L2096:
12822
+	ldr	r3, .L2166
12823
+	ldrb	r1, [r3, #152]	@ zero_extendqisi2
12824
+	cmp	r1, #0
12825
+	bne	.L2165
12826
+.L2125:
12827
+	mov	r0, r6
12828
+	bl	FtlFreeSysBlkQueueIn
12829
+	b	.L2100
12830
+.L2102:
12350
12831
 	movw	r3, #61634
12351
12832
 	cmp	r2, r3
12352
-	beq	.L2128
12833
+	beq	.L2104
12353
12834
 	movw	r3, #65535
12354
12835
 	cmp	r2, r3
12355
-	moveq	r0, r5
12356
-	beq	.L2190
12357
-	b	.L2124
12358
-.L2128:
12359
-	ldr	r3, [sp, #16]
12360
-	ldr	ip, .L2196+20
12361
-	ldr	r9, [r4, #-444]
12362
-	ldr	lr, [r3, #2416]
12363
-	ldrh	r2, [ip]
12364
-	uxth	r1, lr
12365
-	sub	r3, r1, #1
12366
-	rsb	r1, r2, r1
12367
-	sub	r1, r1, #1
12368
-	uxth	r3, r3
12369
-	sxth	r1, r1
12370
-	str	r1, [sp, #20]
12371
-.L2130:
12372
-	ldr	r1, [sp, #20]
12373
-	sxth	r0, r3
12374
-	cmp	r0, r1
12375
-	ble	.L2192
12376
-	mov	r10, r0, asl #2
12377
-	ldr	r1, [r6, #4]
12378
-	str	r10, [sp, #12]
12379
-	ldr	r10, [r9, r0, asl #2]
12380
-	cmp	r1, r10
12381
-	bls	.L2131
12382
-	ldr	r1, [r9]
12383
-	cmp	r1, #0
12384
-	bne	.L2132
12385
-	cmp	r2, lr
12386
-	addne	r2, r2, #1
12387
-	strneh	r2, [ip]	@ movhi
12388
-.L2132:
12389
-	uxth	r9, r3
12836
+	bne	.L2100
12837
+.L2165:
12390
12838
 	mov	r1, #0
12391
-.L2133:
12392
-	uxth	r2, r1
12393
-	cmp	r2, r9
12394
-	bcs	.L2193
12395
-	ldr	lr, [r7, #-444]
12396
-	sxth	r2, r2
12397
-	add	r1, r1, #1
12398
-	add	r10, lr, r2, asl #2
12399
-	ldr	r10, [r10, #4]
12400
-	str	r10, [lr, r2, asl #2]
12401
-	mov	r2, r2, asl #1
12402
-	ldr	lr, [r7, #-472]
12403
-	add	r10, lr, r2
12404
-	ldrh	r10, [r10, #2]
12405
-	strh	r10, [lr, r2]	@ movhi
12406
-	b	.L2133
12407
-.L2193:
12839
+	b	.L2125
12840
+.L2104:
12841
+	ldr	r3, [sp, #4]
12842
+	ldr	r2, [sp]
12843
+	ldr	ip, [r4, #-444]
12844
+	ldr	r0, [r3, #2420]
12845
+	ldrh	r2, [r2]
12846
+	uxth	r1, r0
12847
+	sub	r3, r1, #1
12848
+	sub	r1, r1, r2
12849
+	sub	r1, r1, #1
12850
+	sxth	r3, r3
12851
+	sxth	r1, r1
12852
+.L2106:
12853
+	cmp	r3, r1
12854
+	bgt	.L2112
12855
+	cmp	r3, #0
12856
+	bge	.L2142
12857
+	b	.L2100
12858
+.L2112:
12859
+	ldr	r10, [r7, #4]
12860
+	lsl	lr, r3, #2
12861
+	ldr	r9, [ip, r3, lsl #2]
12862
+	cmp	r10, r9
12863
+	bls	.L2107
12864
+	ldr	r1, [ip]
12865
+	cmp	r1, #0
12866
+	bne	.L2108
12867
+	cmp	r0, r2
12868
+	ldrne	r1, .L2166+20
12869
+	addne	r2, r2, #1
12870
+	strhne	r2, [r1]	@ movhi
12871
+.L2108:
12872
+	uxth	ip, r3
12873
+	mov	r1, #0
12874
+.L2109:
12875
+	uxth	r0, r1
12876
+	sxth	r2, r1
12877
+	cmp	r0, ip
12878
+	bcc	.L2110
12879
+	ldr	r1, [r7, #4]
12880
+	cmp	r3, #0
12408
12881
 	ldr	r2, [r4, #-444]
12409
-	mov	r0, r0, asl #1
12410
-	ldr	r1, [r6, #4]
12411
-	ldr	lr, [sp, #12]
12412
12882
 	str	r1, [r2, lr]
12413
-	ldr	r2, [r4, #-472]
12414
-	strh	r5, [r2, r0]	@ movhi
12415
-	sxth	r0, r3
12416
-	cmp	r0, #0
12417
-	bge	.L2135
12418
-	b	.L2124
12419
-.L2131:
12420
-	sub	r3, r3, #1
12421
-	uxth	r3, r3
12422
-	b	.L2130
12423
-.L2192:
12424
-	cmp	r0, #0
12425
-	bge	.L2166
12426
-	b	.L2124
12427
-.L2135:
12428
-	ldr	r1, .L2196
12429
-	ldrh	r2, [ip]
12430
-	ldr	r1, [r1, #2416]
12431
-	rsb	r1, r2, r1
12883
+	lsl	r2, r3, #1
12884
+	ldr	r1, [r4, #-472]
12885
+	strh	r6, [r1, r2]	@ movhi
12886
+	blt	.L2100
12887
+	ldr	r2, [sp]
12888
+	ldr	r1, .L2166
12889
+	ldrh	r2, [r2]
12890
+	ldr	r1, [r1, #2420]
12891
+	sub	r1, r1, r2
12432
12892
 	sub	r1, r1, #1
12433
12893
 	sxth	r1, r1
12434
-	cmp	r0, r1
12435
-	bgt	.L2124
12436
-.L2166:
12437
-	add	r2, r2, #1
12438
-	ldr	r1, [r6, #4]
12439
-	strh	r2, [ip]	@ movhi
12440
-	sxth	r3, r3
12441
-	ldr	r2, [r4, #-444]
12442
-	str	r1, [r2, r3, asl #2]
12443
-	mov	r3, r3, asl #1
12444
-	ldr	r2, [r4, #-472]
12445
-	b	.L2187
12446
-.L2145:
12447
-	ldr	r9, [lr, r2, asl #2]
12448
-	mov	r10, r2, asl #2
12449
-	ldr	r0, [r6, #4]
12450
-	cmp	r0, r9
12451
-	bhi	.L2194
12452
-	sub	r3, r3, #1
12453
-	uxth	r3, r3
12454
-.L2139:
12455
-	ldr	r0, [sp, #12]
12456
-	sxth	r2, r3
12457
-	cmp	r2, r0
12458
-	bgt	.L2145
12459
-	b	.L2144
12460
-.L2194:
12461
-	ldr	r0, [lr]
12462
-	cmp	r0, #0
12463
-	bne	.L2141
12464
-	cmp	r1, ip
12465
-	addne	r1, r1, #1
12466
-	ldrne	r0, .L2196+24
12467
-	strneh	r1, [r0]	@ movhi
12468
-.L2141:
12469
-	uxth	lr, r3
12470
-	mov	r0, #0
12894
+	cmp	r3, r1
12895
+	bgt	.L2100
12471
12896
 .L2142:
12472
-	uxth	r1, r0
12473
-	cmp	r1, lr
12474
-	bcs	.L2195
12475
-	ldr	ip, [r4, #-460]
12476
-	sxth	r1, r1
12477
-	add	r0, r0, #1
12478
-	add	r9, ip, r1, asl #2
12897
+	ldr	r1, [sp]
12898
+	add	r2, r2, #1
12899
+	strh	r2, [r1]	@ movhi
12900
+	ldr	r2, [r4, #-444]
12901
+	ldr	r1, [r7, #4]
12902
+	str	r1, [r2, r3, lsl #2]
12903
+	lsl	r3, r3, #1
12904
+	ldr	r2, [r4, #-472]
12905
+.L2163:
12906
+	strh	r6, [r2, r3]	@ movhi
12907
+	b	.L2100
12908
+.L2110:
12909
+	ldr	r0, [r4, #-444]
12910
+	add	r1, r1, #1
12911
+	add	r9, r0, r2, lsl #2
12479
12912
 	ldr	r9, [r9, #4]
12480
-	str	r9, [ip, r1, asl #2]
12481
-	mov	r1, r1, asl #1
12482
-	ldr	ip, .L2196
12483
-	ldr	ip, [ip, #2436]
12484
-	add	r9, ip, r1
12913
+	str	r9, [r0, r2, lsl #2]
12914
+	lsl	r2, r2, #1
12915
+	ldr	r0, [r4, #-472]
12916
+	add	r9, r0, r2
12485
12917
 	ldrh	r9, [r9, #2]
12486
-	strh	r9, [ip, r1]	@ movhi
12487
-	b	.L2142
12488
-.L2195:
12489
-	ldr	r1, [r8, #-460]
12490
-	mov	r2, r2, asl #1
12491
-	ldr	r0, [r6, #4]
12492
-	str	r0, [r1, r10]
12493
-	ldr	r1, .L2196
12494
-	ldr	r1, [r1, #2436]
12495
-	strh	r5, [r1, r2]	@ movhi
12496
-.L2144:
12918
+	strh	r9, [r0, r2]	@ movhi
12919
+	b	.L2109
12920
+.L2107:
12921
+	sub	r3, r3, #1
12497
12922
 	sxth	r3, r3
12923
+	b	.L2106
12924
+.L2103:
12925
+	ldr	r3, .L2166+24
12926
+	ldr	r1, .L2166+28
12927
+	ldr	lr, [r4, #-460]
12928
+	ldrh	r2, [r3]
12929
+	ldrh	r1, [r1]
12930
+	sub	r0, r2, #1
12931
+	sxth	r3, r0
12932
+	sub	r0, r0, r1
12933
+.L2115:
12934
+	cmp	r3, r0
12935
+	ble	.L2120
12936
+	ldr	r10, [r7, #4]
12937
+	lsl	ip, r3, #2
12938
+	ldr	r9, [lr, r3, lsl #2]
12939
+	cmp	r10, r9
12940
+	bls	.L2116
12941
+	sub	r2, r2, r1
12942
+	ldr	r0, [lr]
12943
+	clz	r2, r2
12944
+	uxth	r9, r3
12945
+	lsr	r2, r2, #5
12946
+	cmp	r0, #0
12947
+	orrne	r2, r2, #1
12948
+	ldr	r0, .L2166
12949
+	cmp	r2, #0
12950
+	ldreq	r2, .L2166+28
12951
+	addeq	r1, r1, #1
12952
+	strheq	r1, [r2]	@ movhi
12953
+	mov	r1, #0
12954
+.L2118:
12955
+	uxth	lr, r1
12956
+	sxth	r2, r1
12957
+	cmp	lr, r9
12958
+	bcc	.L2119
12959
+	ldr	r1, [r7, #4]
12960
+	ldr	r2, [r4, #-460]
12961
+	str	r1, [r2, ip]
12962
+	lsl	r2, r3, #1
12963
+	ldr	r1, [r0, #2440]
12964
+	strh	r6, [r1, r2]	@ movhi
12965
+.L2120:
12498
12966
 	cmp	r3, #0
12499
-	blt	.L2124
12500
-	ldr	r0, .L2196+24
12967
+	blt	.L2100
12968
+	ldr	r0, .L2166+28
12501
12969
 	ldrh	r2, [r0, #-26]
12502
12970
 	ldrh	r1, [r0]
12503
12971
 	sub	r2, r2, #1
12504
-	rsb	r2, r1, r2
12972
+	sub	r2, r2, r1
12505
12973
 	sxth	r2, r2
12506
12974
 	cmp	r3, r2
12507
-	bgt	.L2124
12975
+	bgt	.L2100
12508
12976
 	add	r1, r1, #1
12509
-	ldr	r2, [r8, #-460]
12977
+	ldr	r2, [r4, #-460]
12510
12978
 	strh	r1, [r0]	@ movhi
12511
-	ldr	r1, [r6, #4]
12512
-	str	r1, [r2, r3, asl #2]
12513
-	mov	r3, r3, asl #1
12514
-	ldr	r2, .L2196
12515
-	ldr	r2, [r2, #2436]
12516
-.L2187:
12517
-	strh	r5, [r2, r3]	@ movhi
12518
-	b	.L2124
12519
-.L2125:
12520
-	ldr	r2, .L2196+8
12979
+	ldr	r1, [r7, #4]
12980
+	str	r1, [r2, r3, lsl #2]
12981
+	lsl	r3, r3, #1
12982
+	ldr	r2, [sp, #4]
12983
+	ldr	r2, [r2, #2440]
12984
+	b	.L2163
12985
+.L2119:
12986
+	ldr	lr, [r4, #-460]
12987
+	add	r1, r1, #1
12988
+	add	r10, lr, r2, lsl #2
12989
+	ldr	r10, [r10, #4]
12990
+	str	r10, [lr, r2, lsl #2]
12991
+	lsl	r2, r2, #1
12992
+	ldr	lr, [r0, #2440]
12993
+	add	r10, lr, r2
12994
+	ldrh	r10, [r10, #2]
12995
+	strh	r10, [lr, r2]	@ movhi
12996
+	b	.L2118
12997
+.L2116:
12998
+	sub	r3, r3, #1
12999
+	sxth	r3, r3
13000
+	b	.L2115
13001
+.L2101:
13002
+	ldr	r2, .L2166+32
12521
13003
 	movw	r1, #65535
12522
-	ldrh	r0, [r2]
13004
+	mov	r9, r2
13005
+	ldrh	r0, [r9], #4
12523
13006
 	cmp	r0, r1
12524
-	streqh	r5, [r2]	@ movhi
12525
-	beq	.L2188
13007
+	strheq	r6, [r2]	@ movhi
13008
+	beq	.L2164
12526
13009
 	ldrh	r0, [r2, #4]
12527
13010
 	cmp	r0, r1
12528
-	beq	.L2147
13011
+	beq	.L2123
12529
13012
 	mov	r1, #1
12530
13013
 	bl	FtlFreeSysBlkQueueIn
12531
-.L2147:
12532
-	ldr	r3, [r6, #4]
12533
-	ldr	r2, [r8, #-3292]
13014
+.L2123:
13015
+	ldr	r3, [r7, #4]
13016
+	ldr	r2, [r4, #-3292]
12534
13017
 	cmp	r2, r3
12535
-	ldr	r3, .L2196+8
12536
-	strcsh	r5, [r3, #4]	@ movhi
12537
-	bcs	.L2124
12538
-	ldrh	r2, [r3]
12539
-	strh	r5, [r3]	@ movhi
12540
-	strh	r2, [r3, #4]	@ movhi
12541
-	ldr	r3, [r6, #4]
12542
-.L2188:
12543
-	str	r3, [r7, #-3292]
12544
-	b	.L2124
12545
-.L2121:
12546
-	ldr	r3, .L2196
12547
-	mov	r0, r5
12548
-	ldrb	r1, [r3, #144]	@ zero_extendqisi2
12549
-	cmp	r1, #0
12550
-	beq	.L2149
12551
-.L2190:
12552
-	mov	r1, #0
12553
-.L2149:
12554
-	bl	FtlFreeSysBlkQueueIn
12555
-.L2124:
12556
-	ldr	r3, [sp, #8]
12557
-	add	r3, r3, #1
12558
-	b	.L2189
12559
-.L2115:
12560
-	ldr	r3, [sp, #4]
12561
-	add	r5, r3, #1
12562
-	uxth	r3, r5
12563
-	str	r3, [sp, #4]
12564
-	b	.L2111
12565
-.L2152:
12566
-	ldr	r3, .L2196+4
12567
-	ldr	ip, [r3, #-472]
12568
-	ldrh	r2, [ip]
12569
-	cmp	r2, #0
12570
-	beq	.L2154
12571
-.L2157:
12572
-	ldr	r0, [r0, #2436]
12573
-	ldr	r3, .L2196
12574
-	ldrh	r2, [r0]
12575
-	cmp	r2, #0
12576
-	beq	.L2155
12577
-	b	.L2178
12578
-.L2154:
12579
-	sub	r3, r3, #388
12580
-	ldrh	r3, [r3]
13018
+	strhcs	r6, [r9]	@ movhi
13019
+	bcs	.L2100
13020
+	ldrh	r3, [r9, #-4]
13021
+	strh	r6, [r9, #-4]	@ movhi
13022
+	strh	r3, [r9]	@ movhi
13023
+	ldr	r3, [r7, #4]
13024
+.L2164:
13025
+	str	r3, [r4, #-3292]
13026
+	b	.L2100
13027
+.L2128:
13028
+	ldr	r0, [r4, #-472]
13029
+	ldrh	r3, [r0]
12581
13030
 	cmp	r3, #0
12582
-	ldrne	lr, [r1, #2416]
12583
-	beq	.L2157
12584
-.L2158:
12585
-	uxth	r3, r2
12586
-	sxth	r1, r3
12587
-	cmp	r1, lr
12588
-	bcs	.L2157
12589
-	mov	r5, r1, asl #1
12590
-	add	r2, r2, #1
12591
-	ldrh	r5, [ip, r5]
12592
-	cmp	r5, #0
12593
-	beq	.L2158
12594
-	mov	r6, #0
12595
-.L2159:
12596
-	ldr	ip, [r0, #2416]
12597
-	sxth	r2, r3
12598
-	cmp	r2, ip
12599
-	bcs	.L2157
12600
-	ldr	lr, [r4, #-472]
12601
-	mov	ip, r2, asl #1
12602
-	rsb	r5, r1, r2
12603
-	add	r3, r3, #1
12604
-	ldrh	r8, [lr, ip]
12605
-	mov	r7, r5, asl #1
12606
-	uxth	r3, r3
12607
-	strh	r8, [lr, r7]	@ movhi
12608
-	ldr	lr, [r4, #-444]
12609
-	ldr	r2, [lr, r2, asl #2]
12610
-	str	r2, [lr, r5, asl #2]
12611
-	ldr	r2, [r4, #-472]
12612
-	strh	r6, [r2, ip]	@ movhi
12613
-	b	.L2159
12614
-.L2155:
12615
-	movw	r1, #2434
12616
-	ldrh	r1, [r3, r1]
13031
+	beq	.L2130
13032
+.L2133:
13033
+	ldr	r0, [r2, #2440]
13034
+	ldrh	r1, [r0]
12617
13035
 	cmp	r1, #0
12618
-	movwne	r1, #2408
12619
-	ldrneh	ip, [r3, r1]
12620
-	beq	.L2178
12621
-.L2162:
12622
-	uxth	r3, r2
13036
+	beq	.L2131
13037
+.L2153:
13038
+	mov	r0, #0
13039
+	add	sp, sp, #28
13040
+	@ sp needed
13041
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
13042
+.L2130:
13043
+	ldr	r1, .L2166+20
13044
+	ldrh	r1, [r1]
13045
+	cmp	r1, #0
13046
+	ldrne	ip, [r2, #2420]
13047
+	beq	.L2133
13048
+.L2134:
12623
13049
 	sxth	r1, r3
12624
13050
 	cmp	r1, ip
12625
-	bge	.L2178
12626
-	mov	lr, r1, asl #1
12627
-	add	r2, r2, #1
13051
+	bcs	.L2133
13052
+	lsl	lr, r1, #1
13053
+	add	r3, r3, #1
12628
13054
 	ldrh	lr, [r0, lr]
12629
13055
 	cmp	lr, #0
12630
-	beq	.L2162
12631
-	ldr	r0, .L2196
12632
-	mov	r7, #0
12633
-	ldr	r6, .L2196+16
12634
-.L2163:
12635
-	ldrh	ip, [r6]
12636
-	sxth	r2, r3
12637
-	cmp	r2, ip
12638
-	bge	.L2178
12639
-	ldr	lr, [r0, #2436]
12640
-	mov	ip, r2, asl #1
12641
-	rsb	r5, r1, r2
13056
+	beq	.L2134
13057
+	mov	r3, r1
13058
+	mov	r5, #0
13059
+.L2135:
13060
+	ldr	r0, [r2, #2420]
13061
+	cmp	r3, r0
13062
+	bcs	.L2133
13063
+	ldr	ip, [r4, #-472]
13064
+	lsl	r0, r3, #1
13065
+	sub	lr, r3, r1
13066
+	lsl	r6, lr, #1
13067
+	ldrh	r7, [ip, r0]
13068
+	strh	r7, [ip, r6]	@ movhi
13069
+	ldr	ip, [r4, #-444]
13070
+	ldr	r6, [ip, r3, lsl #2]
12642
13071
 	add	r3, r3, #1
12643
-	ldrh	r9, [lr, ip]
12644
-	mov	r8, r5, asl #1
12645
-	uxth	r3, r3
12646
-	strh	r9, [lr, r8]	@ movhi
12647
-	ldr	lr, [r4, #-460]
12648
-	ldr	r2, [lr, r2, asl #2]
12649
-	str	r2, [lr, r5, asl #2]
12650
-	ldr	r2, [r0, #2436]
12651
-	strh	r7, [r2, ip]	@ movhi
12652
-	b	.L2163
12653
-.L2178:
12654
-	mov	r0, #0
12655
-	add	sp, sp, #36
12656
-	@ sp needed
12657
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
12658
-.L2197:
13072
+	sxth	r3, r3
13073
+	str	r6, [ip, lr, lsl #2]
13074
+	ldr	ip, [r4, #-472]
13075
+	strh	r5, [ip, r0]	@ movhi
13076
+	b	.L2135
13077
+.L2131:
13078
+	movw	r3, #2438
13079
+	ldrh	r3, [r2, r3]
13080
+	cmp	r3, #0
13081
+	movwne	r3, #2412
13082
+	ldrhne	ip, [r2, r3]
13083
+	beq	.L2153
13084
+.L2138:
13085
+	sxth	r3, r1
13086
+	cmp	r3, ip
13087
+	mov	lr, r3
13088
+	bge	.L2153
13089
+	lsl	r5, r3, #1
13090
+	add	r1, r1, #1
13091
+	ldrh	r5, [r0, r5]
13092
+	cmp	r5, #0
13093
+	beq	.L2138
13094
+	ldr	r5, .L2166+24
13095
+	mov	r6, #0
13096
+.L2139:
13097
+	ldrh	r1, [r5]
13098
+	cmp	r3, r1
13099
+	bge	.L2153
13100
+	ldr	r0, [r2, #2440]
13101
+	lsl	r1, r3, #1
13102
+	sub	ip, r3, lr
13103
+	lsl	r7, ip, #1
13104
+	ldrh	r8, [r0, r1]
13105
+	strh	r8, [r0, r7]	@ movhi
13106
+	ldr	r0, [r4, #-460]
13107
+	ldr	r7, [r0, r3, lsl #2]
13108
+	add	r3, r3, #1
13109
+	sxth	r3, r3
13110
+	str	r7, [r0, ip, lsl #2]
13111
+	ldr	r0, [r2, #2440]
13112
+	strh	r6, [r0, r1]	@ movhi
13113
+	b	.L2139
13114
+.L2167:
12659
13115
 	.align	2
12660
-.L2196:
13116
+.L2166:
12661
13117
 	.word	.LANCHOR0
12662
13118
 	.word	.LANCHOR2
12663
-	.word	.LANCHOR2-3300
12664
-	.word	.LANCHOR0+2330
12665
-	.word	.LANCHOR0+2408
13119
+	.word	.LANCHOR0+2334
13120
+	.word	.LANCHOR0+2324
13121
+	.word	.LANCHOR0+2402
12666
13122
 	.word	.LANCHOR2-388
12667
-	.word	.LANCHOR0+2434
13123
+	.word	.LANCHOR0+2412
13124
+	.word	.LANCHOR0+2438
13125
+	.word	.LANCHOR2-3300
12668
13126
 	.fnend
12669
13127
 	.size	FtlScanSysBlk, .-FtlScanSysBlk
12670
13128
 	.align	2
12671
13129
 	.global	FtlLoadSysInfo
13130
+	.syntax unified
13131
+	.arm
13132
+	.fpu softvfp
12672
13133
 	.type	FtlLoadSysInfo, %function
12673
13134
 FtlLoadSysInfo:
12674
13135
 	.fnstart
12675
13136
 	@ args = 0, pretend = 0, frame = 8
12676
13137
 	@ frame_needed = 0, uses_anonymous_args = 0
12677
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13138
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
12678
13139
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12679
13140
 	mov	r1, #0
12680
-	ldr	r4, .L2227
13141
+	ldr	r4, .L2197
12681
13142
 	.pad #36
12682
13143
 	sub	sp, sp, #36
12683
-	ldr	r6, .L2227+4
12684
-	sub	r7, r4, #3296
13144
+	ldr	r5, .L2197+4
12685
13145
 	ldr	r3, [r4, #-524]
12686
-	ldr	r0, [r4, #-3544]
12687
-	str	r3, [r4, #1760]
13146
+	sub	r7, r4, #3296
13147
+	ldr	r0, [r4, #-3540]
13148
+	str	r3, [r4, #1768]
12688
13149
 	ldr	r3, [r4, #-500]
12689
-	str	r3, [r4, #1764]
12690
-	movw	r3, #2328
12691
-	ldrh	r2, [r6, r3]
12692
-	mov	r2, r2, asl #1
13150
+	str	r3, [r4, #1772]
13151
+	movw	r3, #2332
13152
+	ldrh	r2, [r5, r3]
13153
+	lsl	r2, r2, #1
12693
13154
 	bl	ftl_memset
12694
13155
 	ldrh	r0, [r7, #-4]
12695
13156
 	movw	r3, #65535
12696
13157
 	cmp	r0, r3
12697
-	bne	.L2199
12698
-.L2210:
13158
+	bne	.L2169
13159
+.L2180:
12699
13160
 	mvn	r0, #0
12700
-	b	.L2200
12701
-.L2199:
13161
+.L2168:
13162
+	add	sp, sp, #36
13163
+	@ sp needed
13164
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
13165
+.L2169:
12702
13166
 	mov	r1, #1
13167
+	add	fp, r5, #2400
12703
13168
 	bl	FtlGetLastWrittenPage
12704
-	ldr	r3, .L2227+8
12705
-	ldrh	r9, [r7, #-4]
12706
-	mov	r7, r4
12707
-	uxth	r5, r0
13169
+	ldrsh	r9, [r7, #-4]
13170
+	sub	r8, r7, #4
13171
+	sxth	r6, r0
12708
13172
 	add	r0, r0, #1
12709
-	strh	r0, [r3, #2]	@ movhi
12710
-.L2201:
12711
-	sxth	r3, r5
12712
-	cmp	r3, #0
12713
-	blt	.L2209
12714
-	sxth	fp, r9
12715
-	mov	r1, #1
12716
-	ldr	r0, .L2227+12
12717
-	mov	r2, r1
12718
-	orr	r3, r3, fp, asl #10
12719
-	str	r3, [r4, #1756]
13173
+	strh	r0, [r8, #2]	@ movhi
13174
+.L2171:
13175
+	cmp	r6, #0
13176
+	blt	.L2179
13177
+	orr	r3, r6, r9, lsl #10
13178
+	mov	r2, #1
13179
+	mov	r1, r2
13180
+	ldr	r0, .L2197+8
13181
+	str	r3, [r4, #1764]
12720
13182
 	ldr	r3, [r4, #-524]
12721
-	str	r3, [r4, #1760]
13183
+	str	r3, [r4, #1768]
12722
13184
 	bl	FlashReadPages
12723
-	ldrb	r3, [r6]	@ zero_extendqisi2
13185
+	ldrb	r3, [r5, #36]	@ zero_extendqisi2
12724
13186
 	cmp	r3, #0
12725
-	beq	.L2202
12726
-	ldr	r8, [r7, #1764]
13187
+	beq	.L2172
13188
+	ldr	r8, [r4, #1772]
12727
13189
 	ldr	r3, [r8, #12]
12728
13190
 	cmp	r3, #0
12729
-	beq	.L2202
12730
-	ldr	r2, [r7, #1760]
12731
-	ldr	r10, .L2227+16
12732
13191
 	str	r3, [sp, #28]
13192
+	beq	.L2172
13193
+	ldr	r2, [r4, #1768]
13194
+	ldrh	r1, [fp]
12733
13195
 	mov	r0, r2
12734
13196
 	str	r2, [sp, #24]
12735
-	ldrh	r1, [r10]
12736
13197
 	bl	js_hash
12737
13198
 	ldr	r3, [sp, #28]
12738
13199
 	cmp	r3, r0
12739
-	beq	.L2202
12740
-	cmp	r5, #0
13200
+	beq	.L2172
13201
+	cmp	r6, #0
13202
+	bne	.L2173
13203
+	mov	r10, r7
12741
13204
 	ldr	r2, [sp, #24]
12742
-	bne	.L2203
12743
-	ldr	ip, .L2227+8
12744
-	ldrh	r1, [ip, #4]
12745
-	cmp	fp, r1
12746
-	beq	.L2203
12747
-	ldr	r0, [r8]
12748
-	ldrh	r1, [ip]
12749
-	str	ip, [sp, #24]
12750
-	str	r0, [sp]
12751
-	ldr	r0, [r8, #4]
12752
-	str	r0, [sp, #4]
12753
-	ldr	r0, [r8, #8]
13205
+	ldrh	r1, [r10], #-4
13206
+	cmp	r9, r1
13207
+	beq	.L2173
13208
+	ldr	r2, [r2]
13209
+	ldrh	r1, [r7, #-4]
12754
13210
 	str	r3, [sp, #12]
12755
-	str	r0, [sp, #8]
12756
-	ldr	r3, [r2]
12757
-	ldr	r0, .L2227+20
12758
-	str	r3, [sp, #16]
12759
-	ldr	r2, [r7, #1752]
12760
-	ldr	r3, [r7, #1756]
13211
+	str	r2, [sp, #16]
13212
+	ldr	r3, [r8, #8]
13213
+	ldr	r2, [r4, #1760]
13214
+	ldr	r0, .L2197+12
13215
+	str	r3, [sp, #8]
13216
+	ldr	r3, [r8, #4]
13217
+	str	r3, [sp, #4]
13218
+	ldr	r3, [r8]
13219
+	str	r3, [sp]
13220
+	ldr	r3, [r4, #1764]
12761
13221
 	bl	printk
12762
-	ldrh	r5, [r10, #-8]
12763
-	ldr	ip, [sp, #24]
12764
-	ldrh	r9, [ip, #4]
12765
-	b	.L2205
12766
-.L2203:
13222
+	ldr	r3, .L2197+16
13223
+	ldrsh	r9, [r10, #4]
13224
+	ldrh	r6, [r3]
13225
+.L2175:
13226
+	sub	r6, r6, #1
13227
+	sxth	r6, r6
13228
+	b	.L2171
13229
+.L2173:
12767
13230
 	mvn	r3, #0
12768
-	str	r3, [r4, #1752]
12769
-.L2202:
12770
-	ldr	r3, [r4, #1752]
13231
+	str	r3, [r4, #1760]
13232
+.L2172:
13233
+	ldr	r3, [r4, #1760]
12771
13234
 	cmn	r3, #1
12772
-	beq	.L2205
12773
-	ldr	r3, [r7, #-524]
12774
-	ldr	r2, .L2227+24
13235
+	beq	.L2175
13236
+	ldr	r3, [r4, #-524]
13237
+	ldr	r2, .L2197+20
12775
13238
 	ldr	r3, [r3]
12776
13239
 	cmp	r3, r2
12777
-	bne	.L2205
12778
-	ldr	r3, [r7, #-500]
13240
+	bne	.L2175
13241
+	ldr	r3, [r4, #-500]
12779
13242
 	ldrh	r2, [r3]
12780
13243
 	movw	r3, #61604
12781
13244
 	cmp	r2, r3
12782
-	bne	.L2205
12783
-.L2209:
12784
-	ldr	r5, .L2227
13245
+	bne	.L2175
13246
+.L2179:
12785
13247
 	mov	r2, #48
12786
-	ldr	r1, [r4, #1760]
12787
-	movw	r8, #2328
12788
-	sub	r0, r5, #3600
12789
-	ldr	r7, .L2227+4
13248
+	ldr	r1, [r4, #1768]
13249
+	movw	r6, #2332
13250
+	ldr	r0, .L2197+24
12790
13251
 	bl	ftl_memcpy
12791
-	ldrh	r2, [r6, r8]
12792
-	ldr	r1, [r4, #1760]
12793
-	ldr	r0, [r4, #-3544]
13252
+	ldrh	r2, [r5, r6]
13253
+	ldr	r1, [r4, #1768]
13254
+	ldr	r0, [r4, #-3540]
13255
+	lsl	r2, r2, #1
12794
13256
 	add	r1, r1, #48
12795
-	mov	r2, r2, asl #1
12796
13257
 	bl	ftl_memcpy
12797
-	ldrh	r2, [r6, r8]
12798
-	ldr	r1, [r4, #1760]
12799
-	ldr	r0, [r4, #-3368]
12800
-	mov	r3, r2, asl #1
12801
-	mov	r2, r2, lsr #3
12802
-	add	r3, r3, #51
13258
+	ldrh	r1, [r5, r6]
13259
+	ldr	r3, [r4, #1768]
13260
+	ldr	r0, [r5, #32]
13261
+	lsr	r2, r1, #3
13262
+	lsl	r1, r1, #1
13263
+	add	r1, r1, #51
12803
13264
 	add	r2, r2, #4
12804
-	bic	r3, r3, #3
12805
-	add	r1, r1, r3
13265
+	bic	r1, r1, #3
13266
+	add	r1, r3, r1
12806
13267
 	bl	ftl_memcpy
12807
-	add	r3, r7, #2432
12808
-	ldrh	r3, [r3]
13268
+	movw	r3, #2436
13269
+	ldrh	r3, [r5, r3]
12809
13270
 	cmp	r3, #0
12810
-	beq	.L2207
12811
-	ldrh	r2, [r7, r8]
12812
-	ldr	r1, [r5, #1760]
12813
-	ldr	r0, [r5, #-448]
12814
-	mov	r3, r2, lsr #3
12815
-	add	r3, r3, r2, asl #1
12816
-	movw	r2, #2424
12817
-	ldrh	r2, [r7, r2]
13271
+	beq	.L2177
13272
+	ldrh	r1, [r5, r6]
13273
+	movw	r3, #2428
13274
+	ldrh	r2, [r5, r3]
13275
+	ldr	r0, [r4, #-448]
13276
+	lsr	r3, r1, #3
13277
+	lsl	r2, r2, #2
13278
+	add	r3, r3, r1, lsl #1
13279
+	ldr	r1, [r4, #1768]
12818
13280
 	add	r3, r3, #52
12819
13281
 	ubfx	r3, r3, #2, #14
12820
-	mov	r2, r2, asl #2
12821
-	add	r1, r1, r3, asl #2
13282
+	add	r1, r1, r3, lsl #2
12822
13283
 	bl	ftl_memcpy
12823
-	b	.L2207
12824
-.L2205:
12825
-	sub	r5, r5, #1
12826
-	uxth	r5, r5
12827
-	b	.L2201
12828
-.L2207:
12829
-	ldr	r2, [r4, #-3600]
12830
-	ldr	r3, .L2227+24
12831
-	ldr	r5, .L2227
13284
+.L2177:
13285
+	ldr	r2, [r4, #-3596]
13286
+	ldr	r3, .L2197+20
12832
13287
 	cmp	r2, r3
12833
-	bne	.L2210
12834
-	sub	r7, r5, #3600
12835
-	movw	r1, #2342
12836
-	ldrb	r0, [r5, #-3590]	@ zero_extendqisi2
12837
-	add	r3, r7, #300
12838
-	ldrh	r1, [r6, r1]
12839
-	sub	r8, r5, #3296
12840
-	ldrh	r2, [r7, #8]
12841
-	cmp	r0, r1
12842
-	strh	r2, [r3, #6]	@ movhi
12843
-	ldr	r3, .L2227+4
12844
-	bne	.L2210
12845
-	movw	r1, #2388
12846
-	movw	r0, #2394
12847
-	ldrh	r1, [r3, r1]
12848
-	ldrh	r0, [r3, r0]
12849
-	add	r3, r3, #2320
12850
-	str	r2, [r5, #1788]
12851
-	mul	r1, r2, r1
12852
-	str	r1, [r3, #128]
12853
-	mul	r1, r0, r1
12854
-	str	r1, [r3, #108]
12855
-	ldr	r1, .L2227+28
12856
-	ldrh	r0, [r1, #6]
12857
-	ldr	r1, [r3, #12]
12858
-	rsb	r0, r0, r1
12859
-	ldrh	r1, [r3]
12860
-	rsb	r0, r2, r0
13288
+	bne	.L2180
13289
+	ldr	r6, .L2197+24
13290
+	movw	r3, #2346
13291
+	ldrb	r1, [r4, #-3586]	@ zero_extendqisi2
13292
+	ldrh	r3, [r5, r3]
13293
+	ldrh	r2, [r6, #8]
13294
+	cmp	r1, r3
13295
+	strh	r2, [r7, #2]	@ movhi
13296
+	bne	.L2180
13297
+	movw	r3, #2390
13298
+	movw	r1, #2396
13299
+	ldrh	r3, [r5, r3]
13300
+	ldrh	r1, [r5, r1]
13301
+	ldr	r0, [r5, #2336]
13302
+	str	r2, [r4, #1796]
13303
+	mul	r3, r2, r3
13304
+	str	r3, [r5, #2452]
13305
+	mul	r3, r3, r1
13306
+	str	r3, [r5, #2432]
13307
+	ldr	r3, .L2197+28
13308
+	ldrh	r3, [r3, #6]
13309
+	sub	r0, r0, r3
13310
+	movw	r3, #2324
13311
+	ldrh	r1, [r5, r3]
13312
+	sub	r0, r0, r2
12861
13313
 	bl	__aeabi_uidiv
12862
-	sub	r3, r5, #3520
12863
-	add	r2, r7, #76
12864
-	sub	lr, r5, #3280
12865
-	sub	ip, r5, #3424
12866
-	strh	r0, [r8, #-8]	@ movhi
12867
-	mov	r8, ip
12868
-	ldrh	r0, [r7, #14]
12869
-	strh	r0, [r3, #-4]	@ movhi
12870
-	ldrh	r3, [r7, #16]
12871
-	mov	r1, r3, lsr #6
13314
+	ldrh	r3, [r6, #16]
13315
+	add	r2, r6, #76
13316
+	mov	r5, r2
13317
+	strh	r0, [r7, #-8]	@ movhi
13318
+	ldrh	r0, [r6, #14]
13319
+	add	r7, r2, #240
13320
+	lsr	r1, r3, #6
12872
13321
 	and	r3, r3, #63
12873
-	strb	r3, [r5, #-3518]
12874
-	ldrb	r3, [r5, #-3589]	@ zero_extendqisi2
12875
-	strh	r1, [r7, #78]	@ movhi
12876
-	ldrh	r1, [r7, #18]
12877
-	strb	r3, [r5, #-3516]
13322
+	strb	r3, [r4, #-3514]
13323
+	strh	r1, [r2, #2]	@ movhi
13324
+	ldrh	r1, [r6, #18]
13325
+	ldrb	r3, [r4, #-3585]	@ zero_extendqisi2
13326
+	strh	r0, [r2]	@ movhi
13327
+	strh	r1, [r5, #48]!	@ movhi
13328
+	ldrh	r1, [r6, #20]
13329
+	strb	r3, [r4, #-3512]
12878
13330
 	mvn	r3, #0
12879
-	strh	r3, [lr, #-4]	@ movhi
13331
+	strh	r3, [r7, #-4]	@ movhi
12880
13332
 	mov	r3, #0
12881
-	strh	r3, [r2, #242]	@ movhi
12882
-	sub	r2, r5, #3472
12883
-	strb	r3, [r5, #-3278]
12884
-	strh	r1, [r2, #-4]	@ movhi
12885
-	ldrh	r1, [r7, #20]
12886
-	strb	r3, [r5, #-3276]
12887
-	str	r3, [r5, #-3344]
12888
-	mov	r6, r1, lsr #6
13333
+	strh	r3, [r2, #238]	@ movhi
13334
+	lsr	ip, r1, #6
12889
13335
 	and	r1, r1, #63
12890
-	strb	r1, [r5, #-3470]
12891
-	ldrb	r1, [r5, #-3588]	@ zero_extendqisi2
12892
-	strh	r6, [r2, #-2]	@ movhi
13336
+	strb	r1, [r4, #-3466]
13337
+	ldrb	r1, [r4, #-3584]	@ zero_extendqisi2
13338
+	strh	ip, [r5, #2]	@ movhi
13339
+	strb	r3, [r4, #-3278]
13340
+	strb	r1, [r4, #-3464]
13341
+	ldrh	r1, [r6, #22]
13342
+	strb	r3, [r4, #-3276]
13343
+	strh	r1, [r2, #96]!	@ movhi
13344
+	ldrh	r1, [r6, #24]
12893
13345
 	mov	r6, r2
12894
-	strb	r1, [r5, #-3468]
12895
-	ldrh	r1, [r7, #22]
12896
-	strh	r1, [ip, #-4]	@ movhi
12897
-	ldrh	r1, [r7, #24]
12898
-	mov	r7, r1, lsr #6
13346
+	lsr	ip, r1, #6
12899
13347
 	and	r1, r1, #63
12900
-	strb	r1, [r5, #-3422]
12901
-	ldrb	r1, [r5, #-3587]	@ zero_extendqisi2
12902
-	strh	r7, [r2, #46]	@ movhi
12903
-	mov	r7, lr
12904
-	strb	r1, [r5, #-3420]
12905
-	str	r3, [r5, #-3356]
12906
-	ldr	r1, [r5, #-3568]
12907
-	str	r3, [r5, #-3364]
12908
-	str	r3, [r5, #-3348]
12909
-	str	r3, [r5, #-3320]
12910
-	str	r3, [r5, #-3312]
12911
-	str	r3, [r5, #-3352]
12912
-	ldr	r3, [r5, #-3560]
12913
-	str	r1, [r5, #-3324]
12914
-	ldr	r1, [r5, #-3332]
13348
+	strb	r1, [r4, #-3418]
13349
+	ldrb	r1, [r4, #-3583]	@ zero_extendqisi2
13350
+	strh	ip, [r2, #2]	@ movhi
13351
+	strb	r1, [r4, #-3416]
13352
+	str	r3, [r4, #-3344]
13353
+	ldr	r1, [r4, #-3564]
13354
+	str	r3, [r4, #-3356]
13355
+	str	r3, [r4, #-3364]
13356
+	str	r3, [r4, #-3348]
13357
+	str	r1, [r4, #-3324]
13358
+	str	r3, [r4, #-3320]
13359
+	ldr	r1, [r4, #-3332]
13360
+	str	r3, [r4, #-3312]
13361
+	str	r3, [r4, #-3352]
13362
+	ldr	r3, [r4, #-3556]
12915
13363
 	ldr	r2, [r4, #-3328]
12916
13364
 	cmp	r3, r1
12917
-	strhi	r3, [r5, #-3332]
12918
-	ldr	r3, [r4, #-3564]
13365
+	strhi	r3, [r4, #-3332]
13366
+	ldr	r3, [r4, #-3560]
12919
13367
 	cmp	r3, r2
12920
-	ldrhi	r2, .L2227
12921
-	strhi	r3, [r2, #-3328]
13368
+	strhi	r3, [r4, #-3328]
12922
13369
 	movw	r3, #65535
12923
13370
 	cmp	r0, r3
12924
-	beq	.L2213
12925
-	ldr	r0, .L2227+32
13371
+	beq	.L2183
13372
+	ldr	r0, .L2197+32
12926
13373
 	bl	make_superblock
12927
-.L2213:
12928
-	ldrh	r2, [r6, #-4]
13374
+.L2183:
13375
+	ldrh	r2, [r5]
12929
13376
 	movw	r3, #65535
12930
13377
 	cmp	r2, r3
12931
-	beq	.L2214
12932
-	ldr	r0, .L2227+36
13378
+	beq	.L2184
13379
+	ldr	r0, .L2197+36
12933
13380
 	bl	make_superblock
12934
-.L2214:
12935
-	ldrh	r2, [r8, #-4]
13381
+.L2184:
13382
+	ldrh	r2, [r6]
12936
13383
 	movw	r3, #65535
12937
13384
 	cmp	r2, r3
12938
-	beq	.L2215
12939
-	ldr	r0, .L2227+40
13385
+	beq	.L2185
13386
+	ldr	r0, .L2197+40
12940
13387
 	bl	make_superblock
12941
-.L2215:
13388
+.L2185:
12942
13389
 	ldrh	r2, [r7, #-4]
12943
13390
 	movw	r3, #65535
13391
+	sub	r0, r7, #4
12944
13392
 	cmp	r2, r3
12945
-	beq	.L2216
12946
-	ldr	r0, .L2227+44
13393
+	beq	.L2186
12947
13394
 	bl	make_superblock
12948
-.L2216:
13395
+.L2186:
12949
13396
 	mov	r0, #0
12950
-.L2200:
12951
-	add	sp, sp, #36
12952
-	@ sp needed
12953
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
12954
-.L2228:
13397
+	b	.L2168
13398
+.L2198:
12955
13399
 	.align	2
12956
-.L2227:
13400
+.L2197:
12957
13401
 	.word	.LANCHOR2
12958
13402
 	.word	.LANCHOR0
12959
-	.word	.LANCHOR2-3300
12960
-	.word	.LANCHOR2+1752
12961
-	.word	.LANCHOR0+2398
13403
+	.word	.LANCHOR2+1760
12962
13404
 	.word	.LC109
13405
+	.word	.LANCHOR0+2392
12963
13406
 	.word	1179929683
12964
-	.word	.LANCHOR0+2452
12965
-	.word	.LANCHOR2-3524
12966
-	.word	.LANCHOR2-3476
12967
-	.word	.LANCHOR2-3428
12968
-	.word	.LANCHOR2-3284
13407
+	.word	.LANCHOR2-3596
13408
+	.word	.LANCHOR0+2456
13409
+	.word	.LANCHOR2-3520
13410
+	.word	.LANCHOR2-3472
13411
+	.word	.LANCHOR2-3424
12969
13412
 	.fnend
12970
13413
 	.size	FtlLoadSysInfo, .-FtlLoadSysInfo
12971
13414
 	.align	2
12972
13415
 	.global	FtlDumpBlockInfo
13416
+	.syntax unified
13417
+	.arm
13418
+	.fpu softvfp
12973
13419
 	.type	FtlDumpBlockInfo, %function
12974
13420
 FtlDumpBlockInfo:
12975
13421
 	.fnstart
12976
-	@ args = 0, pretend = 0, frame = 72
13422
+	@ args = 0, pretend = 0, frame = 64
12977
13423
 	@ frame_needed = 0, uses_anonymous_args = 0
12978
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13424
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
12979
13425
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12980
-	movw	r3, #2388
12981
-	ldr	r5, .L2243
12982
-	.pad #100
12983
-	sub	sp, sp, #100
13426
+	movw	r3, #2390
13427
+	ldr	r5, .L2211
13428
+	.pad #92
13429
+	sub	sp, sp, #92
12984
13430
 	ubfx	r0, r0, #10, #16
12985
-	mov	r4, r1
12986
-	ldr	r7, .L2243+4
12987
-	ldrh	r9, [r5, r3]
13431
+	mov	r9, r1
13432
+	ldr	r7, .L2211+4
13433
+	ldrh	r8, [r5, r3]
12988
13434
 	bl	P2V_block_in_plane
12989
-	ldr	r1, .L2243+8
13435
+	ldr	r1, .L2211+8
12990
13436
 	mov	r6, r0
12991
-	ldr	r0, .L2243+12
13437
+	ldr	r0, .L2211+12
12992
13438
 	bl	printk
12993
-	ldr	r2, [r7, #-3544]
12994
-	mov	r3, r6, asl #1
13439
+	ldr	r2, [r7, #-3540]
13440
+	lsl	r3, r6, #1
12995
13441
 	mov	r1, r6
12996
-	ldr	r0, .L2243+16
13442
+	ldr	r0, .L2211+16
12997
13443
 	ldrh	r2, [r2, r3]
12998
13444
 	bl	printk
12999
-	add	r0, sp, #96
13445
+	add	r0, sp, #88
13000
13446
 	strh	r6, [r0, #-48]!	@ movhi
13001
13447
 	bl	make_superblock
13002
-	ldrb	r2, [r5, #144]	@ zero_extendqisi2
13003
-	clz	r3, r4
13004
-	cmp	r2, #0
13005
-	mov	r3, r3, lsr #5
13006
-	moveq	r3, #0
13448
+	ldrb	r4, [r5, #152]	@ zero_extendqisi2
13449
+	str	r7, [sp, #36]
13450
+	adds	r3, r4, #0
13451
+	movne	r3, #1
13452
+	cmp	r9, #0
13453
+	movne	r3, #0
13007
13454
 	cmp	r3, #0
13008
13455
 	moveq	r4, r3
13009
-	str	r7, [sp, #44]
13010
-	beq	.L2230
13456
+	beq	.L2200
13011
13457
 	mov	r0, r6
13012
13458
 	bl	ftl_get_blk_mode
13013
13459
 	cmp	r0, #1
13014
13460
 	mov	r4, r0
13015
-	movweq	r3, #2390
13016
-	ldreqh	r9, [r5, r3]
13017
-.L2230:
13018
-	movw	r3, #2388
13019
-	ldr	r0, .L2243+20
13020
-	mov	r1, r4
13021
-	mov	r2, r9
13022
-	ldrh	r3, [r5, r3]
13461
+	movweq	r3, #2392
13462
+	ldrheq	r8, [r5, r3]
13463
+.L2200:
13464
+	movw	r3, #2390
13023
13465
 	mov	r6, #0
13466
+	mov	r9, #36
13467
+	ldrh	r3, [r5, r3]
13468
+	mov	r2, r8
13469
+	mov	r1, r4
13470
+	ldr	r0, .L2211+20
13024
13471
 	bl	printk
13025
-	ldr	r8, .L2243+4
13026
-.L2231:
13027
-	ldr	r3, .L2243+24
13028
-	add	r0, sp, #62
13029
-	movw	lr, #65535
13030
-	mov	r10, #36
13472
+.L2201:
13473
+	ldr	r3, .L2211+24
13474
+	add	ip, sp, #54
13475
+	movw	r10, #65535
13031
13476
 	ldrh	r3, [r3]
13032
13477
 	mov	r7, r3
13033
-	ldr	r3, [r8, #-536]
13034
-	str	r3, [sp, #28]
13035
-	ldr	r3, [r8, #-2696]
13478
+	ldr	r3, .L2211+4
13479
+	ldr	r2, [r3, #-2696]
13480
+	ldr	r0, [r3, #-536]
13481
+	ldr	r3, [r3, #-2692]
13482
+	str	r2, [sp, #24]
13483
+	ldr	r2, .L2211+28
13036
13484
 	str	r3, [sp, #32]
13037
-	ldr	r3, .L2243+28
13038
-	ldrh	r2, [r3]
13039
-	ldrh	ip, [r3, #2]
13040
-	str	r2, [sp, #36]
13041
-	ldr	r2, [r8, #-2692]
13042
-	str	r2, [sp, #40]
13485
+	ldrh	r1, [r2]
13486
+	ldrh	lr, [r2, #2]
13043
13487
 	mov	r2, #0
13044
13488
 	mov	r5, r2
13045
-.L2232:
13489
+	str	r1, [sp, #28]
13490
+.L2202:
13046
13491
 	uxth	r3, r2
13047
-	cmp	r3, r7
13048
-	bcs	.L2241
13049
-	ldrh	r3, [r0, #2]!
13050
-	cmp	r3, lr
13051
-	beq	.L2233
13052
-	ldr	r1, [sp, #28]
13053
-	orr	r3, r6, r3, asl #10
13054
-	mla	r1, r10, r5, r1
13492
+	cmp	r7, r3
13493
+	bhi	.L2204
13494
+	ldr	fp, .L2211+32
13495
+	mov	r10, #0
13496
+	mov	r2, r4
13497
+	mov	r1, r5
13498
+	bl	FlashReadPages
13499
+.L2205:
13500
+	uxth	r3, r10
13501
+	cmp	r5, r3
13502
+	bhi	.L2206
13503
+	add	r6, r6, #1
13504
+	uxth	r6, r6
13505
+	cmp	r8, r6
13506
+	bne	.L2201
13507
+.L2207:
13508
+	mov	r0, #0
13509
+	add	sp, sp, #92
13510
+	@ sp needed
13511
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
13512
+.L2204:
13513
+	ldrh	r3, [ip, #2]!
13514
+	cmp	r3, r10
13515
+	beq	.L2203
13516
+	mla	r1, r9, r5, r0
13517
+	orr	r3, r6, r3, lsl #10
13055
13518
 	str	r3, [r1, #4]
13056
-	ldr	r3, [sp, #36]
13519
+	ldr	r3, [sp, #28]
13057
13520
 	mul	r3, r3, r5
13521
+	add	fp, r3, #3
13522
+	cmp	r3, #0
13523
+	movlt	r3, fp
13524
+	ldr	fp, [sp, #24]
13525
+	bic	r3, r3, #3
13526
+	add	r3, fp, r3
13527
+	str	r3, [r1, #8]
13528
+	mul	r3, lr, r5
13529
+	add	r5, r5, #1
13530
+	uxth	r5, r5
13058
13531
 	add	fp, r3, #3
13059
13532
 	cmp	r3, #0
13060
13533
 	movlt	r3, fp
13061
13534
 	ldr	fp, [sp, #32]
13062
13535
 	bic	r3, r3, #3
13063
13536
 	add	r3, fp, r3
13064
-	str	r3, [r1, #8]
13065
-	mul	r3, ip, r5
13066
-	add	r5, r5, #1
13067
-	uxth	r5, r5
13068
-	add	fp, r3, #3
13069
-	cmp	r3, #0
13070
-	movlt	r3, fp
13071
-	ldr	fp, [sp, #40]
13072
-	bic	r3, r3, #3
13073
-	add	r3, fp, r3
13074
13537
 	str	r3, [r1, #12]
13075
-.L2233:
13538
+.L2203:
13076
13539
 	add	r2, r2, #1
13077
-	b	.L2232
13078
-.L2241:
13079
-	ldr	r0, [r8, #-536]
13080
-	mov	r1, r5
13081
-	mov	r2, r4
13082
-	mov	r10, #0
13083
-	bl	FlashReadPages
13084
-	mov	fp, #36
13085
-.L2235:
13086
-	uxth	r3, r10
13087
-	cmp	r3, r5
13088
-	bcs	.L2242
13089
-	ldr	r3, [sp, #44]
13090
-	mul	r2, fp, r10
13091
-	ldrh	r1, [sp, #48]
13092
-	ldr	lr, [r3, #-536]
13540
+	b	.L2202
13541
+.L2206:
13542
+	ldr	r3, [sp, #36]
13543
+	mul	r0, r9, r10
13544
+	ldrh	r1, [sp, #40]
13093
13545
 	add	r10, r10, #1
13094
-	add	ip, lr, r2
13095
-	ldr	r3, [ip, #12]
13096
-	ldr	r0, [ip, #8]
13097
-	ldr	r7, [r3]
13098
-	str	r7, [sp]
13099
-	ldr	r7, [r3, #4]
13100
-	str	r7, [sp, #4]
13101
-	ldr	r7, [r3, #8]
13102
-	str	r7, [sp, #8]
13103
-	ldr	r3, [r3, #12]
13104
-	str	r3, [sp, #12]
13105
-	ldr	r3, [r0]
13106
-	str	r3, [sp, #16]
13107
-	ldr	r3, [r0, #4]
13108
-	ldr	r0, .L2243+32
13109
-	str	r3, [sp, #20]
13110
-	ldr	r2, [lr, r2]
13111
-	ldr	r3, [ip, #4]
13546
+	ldr	ip, [r3, #-536]
13547
+	add	r2, ip, r0
13548
+	ldr	lr, [r2, #8]
13549
+	ldr	r3, [r2, #12]
13550
+	ldr	r7, [lr, #4]
13551
+	str	r7, [sp, #20]
13552
+	ldr	lr, [lr]
13553
+	str	lr, [sp, #16]
13554
+	ldr	lr, [r3, #12]
13555
+	str	lr, [sp, #12]
13556
+	ldr	lr, [r3, #8]
13557
+	str	lr, [sp, #8]
13558
+	ldr	lr, [r3, #4]
13559
+	str	lr, [sp, #4]
13560
+	ldr	r3, [r3]
13561
+	str	r3, [sp]
13562
+	ldr	r3, [r2, #4]
13563
+	ldr	r2, [ip, r0]
13564
+	mov	r0, fp
13112
13565
 	bl	printk
13113
-	b	.L2235
13114
-.L2242:
13115
-	add	r6, r6, #1
13116
-	uxth	r6, r6
13117
-	cmp	r6, r9
13118
-	bne	.L2231
13119
-.L2237:
13120
-	mov	r0, #0
13121
-	add	sp, sp, #100
13122
-	@ sp needed
13123
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
13124
-.L2244:
13566
+	b	.L2205
13567
+.L2212:
13125
13568
 	.align	2
13126
-.L2243:
13569
+.L2211:
13127
13570
 	.word	.LANCHOR0
13128
13571
 	.word	.LANCHOR2
13129
-	.word	.LANCHOR3+148
13572
+	.word	.LANCHOR3+141
13130
13573
 	.word	.LC110
13131
13574
 	.word	.LC111
13132
13575
 	.word	.LC112
13133
-	.word	.LANCHOR0+2320
13134
-	.word	.LANCHOR0+2398
13576
+	.word	.LANCHOR0+2324
13577
+	.word	.LANCHOR0+2400
13135
13578
 	.word	.LC113
13136
13579
 	.fnend
13137
13580
 	.size	FtlDumpBlockInfo, .-FtlDumpBlockInfo
13138
13581
 	.align	2
13139
13582
 	.global	FtlScanAllBlock
13583
+	.syntax unified
13584
+	.arm
13585
+	.fpu softvfp
13140
13586
 	.type	FtlScanAllBlock, %function
13141
13587
 FtlScanAllBlock:
13142
13588
 	.fnstart
13143
-	@ args = 0, pretend = 0, frame = 64
13589
+	@ args = 0, pretend = 0, frame = 56
13144
13590
 	@ frame_needed = 0, uses_anonymous_args = 0
13145
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13591
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
13146
13592
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13147
-	.pad #92
13148
-	sub	sp, sp, #92
13149
-	ldr	r0, .L2260
13150
-	mov	r7, #0
13151
-	ldr	r1, .L2260+4
13593
+	mov	r6, #0
13594
+	ldr	r5, .L2224
13595
+	.pad #84
13596
+	sub	sp, sp, #84
13597
+	ldr	r1, .L2224+4
13598
+	ldr	r0, .L2224+8
13152
13599
 	bl	printk
13153
-	ldr	r5, .L2260+8
13154
-	mov	r6, r5
13155
-.L2246:
13156
-	ldr	r3, .L2260+12
13157
-	uxth	r4, r7
13600
+.L2214:
13601
+	ldr	r3, .L2224+12
13602
+	uxth	r0, r6
13158
13603
 	ldrh	r3, [r3]
13159
-	cmp	r3, r4
13160
-	bls	.L2256
13161
-	add	r8, sp, #88
13162
-	mov	r0, r4
13604
+	cmp	r3, r0
13605
+	bhi	.L2222
13606
+	mov	r0, #0
13607
+	add	sp, sp, #84
13608
+	@ sp needed
13609
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
13610
+.L2222:
13611
+	add	r4, sp, #80
13163
13612
 	movw	r9, #65535
13613
+	strh	r0, [r4, #-48]!	@ movhi
13164
13614
 	mov	r10, #36
13165
-	strh	r4, [r8, #-48]!	@ movhi
13166
13615
 	bl	ftl_get_blk_mode
13167
-	ldr	ip, [r5, #-3544]
13168
-	mov	r2, r4, asl #1
13169
-	mov	r1, r4
13170
-	ldrh	r2, [ip, r2]
13616
+	uxth	r1, r6
13617
+	ldr	ip, [r5, #-3540]
13171
13618
 	mov	r3, r0
13172
-	ldr	r0, .L2260+16
13619
+	ldr	r0, .L2224+16
13620
+	lsl	r2, r1, #1
13621
+	ldrh	r2, [ip, r2]
13173
13622
 	bl	printk
13174
-	mov	r0, r8
13623
+	mov	r0, r4
13175
13624
 	bl	make_superblock
13176
-	ldr	r3, .L2260+20
13177
-	ldr	lr, [r5, #-2692]
13625
+	ldr	r3, .L2224+20
13626
+	add	ip, sp, #46
13627
+	ldr	r0, [r5, #-536]
13628
+	ldr	r7, [r5, #-2692]
13178
13629
 	ldrh	r2, [r3]
13179
-	ldrh	ip, [r3, #78]
13180
-	ldrh	r8, [r3, #80]
13181
-	str	r2, [sp, #28]
13182
-	add	r0, sp, #54
13183
-	ldr	r2, [r5, #-536]
13184
-	str	r2, [sp, #32]
13630
+	ldrh	lr, [r3, #76]
13631
+	ldrh	r8, [r3, #78]
13632
+	str	r2, [sp, #24]
13185
13633
 	ldr	r2, [r5, #-2696]
13186
-	str	r2, [sp, #36]
13634
+	str	r2, [sp, #28]
13187
13635
 	mov	r2, #0
13188
13636
 	mov	r4, r2
13189
-.L2247:
13190
-	ldr	r1, [sp, #28]
13637
+.L2215:
13638
+	ldr	r1, [sp, #24]
13191
13639
 	uxth	r3, r2
13192
-	cmp	r3, r1
13193
-	bcs	.L2257
13194
-	ldrh	r3, [r0, #2]!
13640
+	cmp	r1, r3
13641
+	bhi	.L2217
13642
+	ldr	r9, .L2224+24
13643
+	mov	r7, #0
13644
+	mov	r8, #36
13645
+	mov	r2, #0
13646
+	mov	r1, r4
13647
+	bl	FlashReadPages
13648
+.L2218:
13649
+	uxth	r3, r7
13650
+	cmp	r4, r3
13651
+	bhi	.L2219
13652
+	ldr	r9, .L2224+28
13653
+	mov	r7, #0
13654
+	mov	r8, #36
13655
+	mov	r2, #1
13656
+	mov	r1, r4
13657
+	ldr	r0, [r5, #-536]
13658
+	bl	FlashReadPages
13659
+.L2220:
13660
+	uxth	r3, r7
13661
+	cmp	r4, r3
13662
+	bhi	.L2221
13663
+	add	r6, r6, #1
13664
+	b	.L2214
13665
+.L2217:
13666
+	ldrh	r3, [ip, #2]!
13195
13667
 	cmp	r3, r9
13196
-	beq	.L2248
13197
-	ldr	r1, [sp, #32]
13198
-	mov	r3, r3, asl #10
13199
-	mla	r1, r10, r4, r1
13668
+	beq	.L2216
13669
+	mla	r1, r10, r4, r0
13670
+	lsl	r3, r3, #10
13200
13671
 	str	r3, [r1, #4]
13201
-	mul	r3, ip, r4
13672
+	mul	r3, lr, r4
13202
13673
 	add	fp, r3, #3
13203
13674
 	cmp	r3, #0
13204
13675
 	movlt	r3, fp
13205
-	ldr	fp, [sp, #36]
13676
+	ldr	fp, [sp, #28]
13206
13677
 	bic	r3, r3, #3
13207
13678
 	add	r3, fp, r3
13208
13679
 	str	r3, [r1, #8]
..
..
@@ -13213,673 +13684,764 @@
13213
13684
 	cmp	r3, #0
13214
13685
 	movlt	r3, fp
13215
13686
 	bic	r3, r3, #3
13216
-	add	r3, lr, r3
13687
+	add	r3, r7, r3
13217
13688
 	str	r3, [r1, #12]
13218
-.L2248:
13689
+.L2216:
13219
13690
 	add	r2, r2, #1
13220
-	b	.L2247
13221
-.L2257:
13222
-	ldr	r0, [r6, #-536]
13223
-	mov	r1, r4
13224
-	mov	r2, #0
13225
-	mov	r8, #0
13226
-	bl	FlashReadPages
13227
-	mov	r9, #36
13228
-.L2250:
13229
-	uxth	r3, r8
13230
-	cmp	r3, r4
13231
-	bcs	.L2258
13232
-	mul	r2, r9, r8
13233
-	ldr	lr, [r6, #-536]
13234
-	ldrh	r1, [sp, #40]
13235
-	add	r8, r8, #1
13236
-	add	ip, lr, r2
13237
-	ldr	r3, [ip, #12]
13238
-	ldr	r0, [ip, #8]
13239
-	ldr	r10, [r3]
13240
-	str	r10, [sp]
13241
-	ldr	r10, [r3, #4]
13242
-	str	r10, [sp, #4]
13243
-	ldr	r10, [r3, #8]
13244
-	str	r10, [sp, #8]
13245
-	ldr	r3, [r3, #12]
13246
-	str	r3, [sp, #12]
13247
-	ldr	r3, [r0]
13248
-	str	r3, [sp, #16]
13249
-	ldr	r3, [r0, #4]
13250
-	ldr	r0, .L2260+24
13251
-	str	r3, [sp, #20]
13252
-	ldr	r2, [lr, r2]
13253
-	ldr	r3, [ip, #4]
13254
-	bl	printk
13255
-	b	.L2250
13256
-.L2258:
13257
-	ldr	r0, [r6, #-536]
13258
-	mov	r1, r4
13259
-	mov	r2, #1
13260
-	mov	r8, #0
13261
-	bl	FlashReadPages
13262
-	mov	r9, #36
13263
-.L2252:
13264
-	uxth	r3, r8
13265
-	cmp	r3, r4
13266
-	bcs	.L2259
13267
-	mul	r2, r9, r8
13268
-	ldr	lr, [r6, #-536]
13269
-	ldrh	r1, [sp, #40]
13270
-	add	r8, r8, #1
13271
-	add	ip, lr, r2
13272
-	ldr	r3, [ip, #12]
13273
-	ldr	r0, [ip, #8]
13274
-	ldr	r10, [r3]
13275
-	str	r10, [sp]
13276
-	ldr	r10, [r3, #4]
13277
-	str	r10, [sp, #4]
13278
-	ldr	r10, [r3, #8]
13279
-	str	r10, [sp, #8]
13280
-	ldr	r3, [r3, #12]
13281
-	str	r3, [sp, #12]
13282
-	ldr	r3, [r0]
13283
-	str	r3, [sp, #16]
13284
-	ldr	r3, [r0, #4]
13285
-	ldr	r0, .L2260+28
13286
-	str	r3, [sp, #20]
13287
-	ldr	r2, [lr, r2]
13288
-	ldr	r3, [ip, #4]
13289
-	bl	printk
13290
-	b	.L2252
13291
-.L2259:
13691
+	b	.L2215
13692
+.L2219:
13693
+	mul	r0, r8, r7
13694
+	ldr	ip, [r5, #-536]
13695
+	ldrh	r1, [sp, #32]
13292
13696
 	add	r7, r7, #1
13293
-	b	.L2246
13294
-.L2256:
13295
-	mov	r0, #0
13296
-	add	sp, sp, #92
13297
-	@ sp needed
13298
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
13299
-.L2261:
13697
+	add	r2, ip, r0
13698
+	ldr	lr, [r2, #8]
13699
+	ldr	r3, [r2, #12]
13700
+	ldr	r10, [lr, #4]
13701
+	str	r10, [sp, #20]
13702
+	ldr	lr, [lr]
13703
+	str	lr, [sp, #16]
13704
+	ldr	lr, [r3, #12]
13705
+	str	lr, [sp, #12]
13706
+	ldr	lr, [r3, #8]
13707
+	str	lr, [sp, #8]
13708
+	ldr	lr, [r3, #4]
13709
+	str	lr, [sp, #4]
13710
+	ldr	r3, [r3]
13711
+	str	r3, [sp]
13712
+	ldr	r3, [r2, #4]
13713
+	ldr	r2, [ip, r0]
13714
+	mov	r0, r9
13715
+	bl	printk
13716
+	b	.L2218
13717
+.L2221:
13718
+	mul	r0, r8, r7
13719
+	ldr	ip, [r5, #-536]
13720
+	ldrh	r1, [sp, #32]
13721
+	add	r7, r7, #1
13722
+	add	r2, ip, r0
13723
+	ldr	lr, [r2, #8]
13724
+	ldr	r3, [r2, #12]
13725
+	ldr	r10, [lr, #4]
13726
+	str	r10, [sp, #20]
13727
+	ldr	lr, [lr]
13728
+	str	lr, [sp, #16]
13729
+	ldr	lr, [r3, #12]
13730
+	str	lr, [sp, #12]
13731
+	ldr	lr, [r3, #8]
13732
+	str	lr, [sp, #8]
13733
+	ldr	lr, [r3, #4]
13734
+	str	lr, [sp, #4]
13735
+	ldr	r3, [r3]
13736
+	str	r3, [sp]
13737
+	ldr	r3, [r2, #4]
13738
+	ldr	r2, [ip, r0]
13739
+	mov	r0, r9
13740
+	bl	printk
13741
+	b	.L2220
13742
+.L2225:
13300
13743
 	.align	2
13301
-.L2260:
13302
-	.word	.LC110
13303
-	.word	.LANCHOR3+168
13744
+.L2224:
13304
13745
 	.word	.LANCHOR2
13305
-	.word	.LANCHOR0+2330
13746
+	.word	.LANCHOR3+158
13747
+	.word	.LC110
13748
+	.word	.LANCHOR0+2334
13306
13749
 	.word	.LC114
13307
-	.word	.LANCHOR0+2320
13750
+	.word	.LANCHOR0+2324
13308
13751
 	.word	.LC115
13309
13752
 	.word	.LC116
13310
13753
 	.fnend
13311
13754
 	.size	FtlScanAllBlock, .-FtlScanAllBlock
13312
13755
 	.align	2
13313
13756
 	.global	ftl_scan_all_ppa
13757
+	.syntax unified
13758
+	.arm
13759
+	.fpu softvfp
13314
13760
 	.type	ftl_scan_all_ppa, %function
13315
13761
 ftl_scan_all_ppa:
13316
13762
 	.fnstart
13317
-	@ args = 0, pretend = 0, frame = 0
13763
+	@ args = 0, pretend = 0, frame = 8
13318
13764
 	@ frame_needed = 0, uses_anonymous_args = 0
13319
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
13320
-	.save {r4, r5, r6, r7, r8, r9, r10, lr}
13321
-	movw	r3, #2386
13322
-	ldr	r6, .L2281
13323
-	.pad #24
13324
-	sub	sp, sp, #24
13325
-	ldr	r5, .L2281+4
13326
-	ldrh	r4, [r6, r3]
13765
+	ldr	r3, .L2243
13766
+	movw	r2, #2388
13767
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
13768
+	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13769
+	.pad #36
13770
+	sub	sp, sp, #36
13771
+	ldr	r5, .L2243+4
13772
+	ldrh	r4, [r3, r2]
13773
+	add	r10, r5, #1760
13774
+	str	r3, [sp, #28]
13327
13775
 	sub	r4, r4, #16
13328
-.L2263:
13329
-	ldr	r7, .L2281+8
13330
-	ldrh	r3, [r7]
13776
+	lsl	r9, r4, #10
13777
+.L2227:
13778
+	ldr	r3, .L2243+8
13779
+	ldrh	r3, [r3]
13331
13780
 	cmp	r4, r3
13332
-	bge	.L2279
13333
-	uxth	r8, r4
13334
-	mov	r0, r8
13781
+	blt	.L2235
13782
+	ldr	r1, .L2243+12
13783
+	ldr	r0, .L2243+16
13784
+	add	sp, sp, #36
13785
+	@ sp needed
13786
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
13787
+	b	printk
13788
+.L2235:
13789
+	uxth	r7, r4
13790
+	mov	r0, r7
13335
13791
 	bl	ftl_get_blk_mode
13336
-	ldrb	r3, [r6, #144]	@ zero_extendqisi2
13792
+	ldr	r3, [sp, #28]
13793
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
13337
13794
 	cmp	r3, #0
13338
-	beq	.L2264
13339
-	ldrh	r3, [r7, #-58]
13795
+	beq	.L2228
13796
+	ldr	r3, .L2243+20
13797
+	ldrh	r2, [r3]
13798
+	cmp	r4, r2
13799
+	bge	.L2229
13800
+	ldrh	r3, [r3, #72]
13340
13801
 	cmp	r4, r3
13341
-	bge	.L2265
13342
-	ldrh	r3, [r7, #16]
13343
-	cmp	r4, r3
13344
-	blt	.L2265
13345
-.L2264:
13802
+	blt	.L2229
13803
+.L2228:
13346
13804
 	cmp	r0, #1
13347
-	bne	.L2266
13348
-.L2265:
13349
-	ldr	r3, .L2281+12
13350
-	mov	r9, #-2147483648
13351
-	ldrh	r7, [r3]
13352
-	b	.L2267
13353
-.L2266:
13354
-	ldr	r3, .L2281+16
13355
-	mov	r9, #0
13356
-	ldrh	r7, [r3]
13357
-.L2267:
13805
+	bne	.L2230
13806
+.L2229:
13807
+	ldr	r3, .L2243+24
13808
+	mov	r8, #-2147483648
13809
+	ldrh	r6, [r3]
13810
+.L2231:
13811
+	mov	r3, r8
13812
+	mov	r2, r6
13358
13813
 	mov	r1, r4
13359
-	mov	r2, r7
13360
-	mov	r3, r9
13361
-	ldr	r0, .L2281+20
13814
+	ldr	r0, .L2243+28
13362
13815
 	bl	printk
13363
-	mov	r0, r8
13816
+	mov	r0, r7
13364
13817
 	bl	FtlBbmIsBadBlock
13365
13818
 	cmp	r0, #0
13366
-	beq	.L2268
13367
-	ldr	r0, .L2281+24
13819
+	beq	.L2232
13820
+	mov	r3, r8
13821
+	mov	r2, r6
13368
13822
 	mov	r1, r4
13369
-	mov	r2, r7
13370
-	mov	r3, r9
13823
+	ldr	r0, .L2243+32
13371
13824
 	bl	printk
13372
-.L2268:
13373
-	mov	r10, r4, asl #10
13825
+.L2232:
13826
+	ldr	fp, .L2243+36
13827
+	mov	r7, #0
13828
+.L2233:
13829
+	cmp	r7, r6
13830
+	bne	.L2234
13831
+	add	r4, r4, #1
13832
+	add	r9, r9, #1024
13833
+	b	.L2227
13834
+.L2230:
13835
+	ldr	r3, .L2243+40
13374
13836
 	mov	r8, #0
13375
-.L2269:
13376
-	cmp	r8, r7
13377
-	beq	.L2280
13378
-	add	r3, r9, r10
13837
+	ldrh	r6, [r3]
13838
+	b	.L2231
13839
+.L2234:
13840
+	add	r3, r8, r9
13379
13841
 	mov	r2, #0
13380
-	add	r3, r3, r8
13381
-	str	r3, [r5, #1756]
13382
-	ldr	r3, [r5, #-524]
13842
+	add	r3, r3, r7
13383
13843
 	mov	r1, #1
13384
-	ldr	r0, .L2281+28
13385
-	add	r8, r8, #1
13386
-	str	r2, [r5, #1752]
13387
-	str	r3, [r5, #1760]
13388
-	ldr	r3, [r5, #-500]
13389
13844
 	str	r3, [r5, #1764]
13845
+	mov	r0, r10
13846
+	ldr	r3, [r5, #-524]
13847
+	add	r7, r7, #1
13848
+	str	r2, [r5, #1760]
13849
+	str	r3, [r5, #1768]
13850
+	ldr	r3, [r5, #-500]
13851
+	str	r3, [r5, #1772]
13390
13852
 	bl	FlashReadPages
13391
-	ldr	r3, [r5, #1764]
13853
+	ldr	r2, [r5, #1768]
13854
+	mov	r0, fp
13855
+	ldr	r3, [r5, #1772]
13856
+	ldr	r1, [r2, #4]
13857
+	str	r1, [sp, #16]
13858
+	ldr	r2, [r2]
13859
+	ldr	r1, [r5, #1764]
13860
+	str	r2, [sp, #12]
13861
+	ldr	r2, [r3, #12]
13862
+	str	r2, [sp, #8]
13863
+	ldr	r2, [r3, #8]
13864
+	str	r2, [sp, #4]
13865
+	ldr	r2, [r3, #4]
13866
+	str	r2, [sp]
13392
13867
 	ldr	r2, [r5, #1760]
13393
-	ldr	r0, .L2281+32
13394
-	ldr	r1, [r3, #4]
13395
-	str	r1, [sp]
13396
-	ldr	r1, [r3, #8]
13397
-	str	r1, [sp, #4]
13398
-	ldr	r1, [r3, #12]
13399
-	str	r1, [sp, #8]
13400
-	ldr	r1, [r2]
13401
-	str	r1, [sp, #12]
13402
-	ldr	r2, [r2, #4]
13403
-	ldr	r1, [r5, #1756]
13404
-	str	r2, [sp, #16]
13405
-	ldr	r2, [r5, #1752]
13406
13868
 	ldr	r3, [r3]
13407
13869
 	bl	printk
13408
-	b	.L2269
13409
-.L2280:
13410
-	add	r4, r4, #1
13411
-	b	.L2263
13412
-.L2279:
13413
-	ldr	r0, .L2281+36
13414
-	ldr	r1, .L2281+40
13415
-	add	sp, sp, #24
13416
-	@ sp needed
13417
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
13418
-	b	printk
13419
-.L2282:
13870
+	b	.L2233
13871
+.L2244:
13420
13872
 	.align	2
13421
-.L2281:
13873
+.L2243:
13422
13874
 	.word	.LANCHOR0
13423
13875
 	.word	.LANCHOR2
13424
-	.word	.LANCHOR0+2386
13425
-	.word	.LANCHOR0+2390
13426
13876
 	.word	.LANCHOR0+2388
13877
+	.word	.LANCHOR3+174
13878
+	.word	.LC120
13879
+	.word	.LANCHOR0+2332
13880
+	.word	.LANCHOR0+2392
13427
13881
 	.word	.LC117
13428
13882
 	.word	.LC118
13429
-	.word	.LANCHOR2+1752
13430
13883
 	.word	.LC119
13431
-	.word	.LC120
13432
-	.word	.LANCHOR3+184
13884
+	.word	.LANCHOR0+2390
13433
13885
 	.fnend
13434
13886
 	.size	ftl_scan_all_ppa, .-ftl_scan_all_ppa
13435
13887
 	.align	2
13436
13888
 	.global	FlashProgPages
13889
+	.syntax unified
13890
+	.arm
13891
+	.fpu softvfp
13437
13892
 	.type	FlashProgPages, %function
13438
13893
 FlashProgPages:
13439
13894
 	.fnstart
13440
-	@ args = 0, pretend = 0, frame = 64
13895
+	@ args = 0, pretend = 0, frame = 72
13441
13896
 	@ frame_needed = 0, uses_anonymous_args = 0
13442
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13897
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
13443
13898
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13444
-	.pad #76
13445
-	sub	sp, sp, #76
13446
-	ldr	r6, .L2339
13447
-	mov	r4, r0
13448
-	str	r1, [sp, #8]
13449
-	mov	r9, r2
13450
-	str	r3, [sp, #20]
13451
-	ldr	ip, [r6, #44]
13452
-	ldrb	r7, [r6]	@ zero_extendqisi2
13899
+	.pad #84
13900
+	sub	sp, sp, #84
13901
+	ldr	r5, .L2298
13902
+	str	r1, [sp, #12]
13903
+	ldr	ip, [r5, #48]
13904
+	ldrb	r8, [r5, #36]	@ zero_extendqisi2
13905
+	str	r3, [sp, #24]
13453
13906
 	ldrb	ip, [ip, #19]	@ zero_extendqisi2
13454
-	cmp	r7, #0
13455
-	str	ip, [sp, #16]
13456
-	ldr	ip, .L2339+4
13457
-	ldrb	ip, [ip, #481]	@ zero_extendqisi2
13458
-	str	ip, [sp, #12]
13459
-	beq	.L2284
13907
+	cmp	r8, #0
13908
+	str	ip, [sp, #20]
13909
+	bne	.L2246
13910
+	ldr	r3, .L2298+4
13911
+	mov	r4, r0
13912
+	mov	r9, r2
13913
+	ldrb	r3, [r3, #477]	@ zero_extendqisi2
13914
+	str	r3, [sp, #16]
13915
+	add	r3, r5, #1216
13916
+	add	r3, r3, #4
13917
+	str	r3, [sp, #28]
13918
+.L2247:
13919
+	ldr	r3, [sp, #12]
13920
+	cmp	r8, r3
13921
+	bcc	.L2260
13922
+	ldr	r7, .L2298+8
13923
+	mov	r6, #0
13924
+.L2261:
13925
+	ldrb	r3, [r5, #2234]	@ zero_extendqisi2
13926
+	cmp	r6, r3
13927
+	bcc	.L2263
13928
+	ldr	r3, [sp, #24]
13929
+	cmp	r3, #0
13930
+	bne	.L2264
13931
+.L2272:
13932
+	mov	r0, #0
13933
+	b	.L2245
13934
+.L2246:
13460
13935
 	bl	FlashProgSlc2KPages
13461
-	b	.L2285
13462
-.L2297:
13463
-	mov	r3, #36
13936
+.L2245:
13937
+	add	sp, sp, #84
13938
+	@ sp needed
13939
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
13940
+.L2260:
13941
+	ldr	r3, [sp, #12]
13942
+	mov	r7, #36
13943
+	mul	r7, r7, r8
13944
+	add	r2, sp, #36
13464
13945
 	mov	r1, r9
13465
-	mul	r8, r3, r7
13466
-	ldr	r3, [sp, #8]
13467
-	add	r2, sp, #28
13468
-	rsb	r3, r7, r3
13469
-	add	fp, r4, r8
13946
+	sub	r3, r3, r8
13470
13947
 	uxtb	r3, r3
13948
+	add	fp, r4, r7
13471
13949
 	str	r3, [sp]
13472
13950
 	mov	r0, fp
13473
-	add	r3, sp, #32
13951
+	add	r3, sp, #40
13474
13952
 	bl	LogAddr2PhyAddr
13475
-	ldrb	r3, [r6, #2230]	@ zero_extendqisi2
13953
+	ldrb	r3, [r5, #2234]	@ zero_extendqisi2
13476
13954
 	mov	r10, r0
13477
-	ldr	r0, [sp, #32]
13478
-	cmp	r0, r3
13479
-	mvncs	r3, #0
13480
-	strcs	r3, [r4, r8]
13481
-	bcc	.L2336
13482
-.L2287:
13483
-	add	r7, r7, #1
13484
-.L2284:
13485
-	ldr	r3, [sp, #8]
13486
-	ldr	r5, .L2339
13487
-	cmp	r7, r3
13488
-	bcc	.L2297
13489
-	b	.L2337
13490
-.L2336:
13491
-	ldrb	r3, [r6, #2240]	@ zero_extendqisi2
13955
+	ldr	r0, [sp, #40]
13956
+	cmp	r3, r0
13957
+	mvnls	r3, #0
13958
+	strls	r3, [r4, r7]
13959
+	bls	.L2250
13960
+	ldrb	r3, [r5, #2244]	@ zero_extendqisi2
13492
13961
 	cmp	r3, #0
13493
-	add	r3, r6, r0, asl #4
13494
-	ldr	r3, [r3, #2108]
13962
+	add	r3, r5, r0, lsl #4
13495
13963
 	moveq	r10, #0
13964
+	ldr	r3, [r3, #2112]
13496
13965
 	cmp	r3, #0
13497
-	beq	.L2289
13966
+	beq	.L2252
13498
13967
 	uxtb	r0, r0
13499
13968
 	bl	FlashWaitCmdDone
13500
-.L2289:
13501
-	ldr	r3, [sp, #32]
13969
+.L2252:
13970
+	ldr	r3, [sp, #40]
13502
13971
 	mov	r1, #0
13503
13972
 	cmp	r10, #0
13504
-	add	r2, r6, r3, asl #4
13505
-	str	r1, [r2, #2112]
13506
-	ldr	r1, [sp, #28]
13507
-	str	fp, [r2, #2108]
13508
-	str	r1, [r2, #2104]
13509
-	addne	r1, r8, #36
13973
+	add	r2, r5, r3, lsl #4
13974
+	str	r1, [r2, #2116]
13975
+	ldr	r1, [sp, #36]
13976
+	str	fp, [r2, #2112]
13977
+	str	r1, [r2, #2108]
13978
+	addne	r1, r7, #36
13510
13979
 	addne	r1, r4, r1
13511
-	strne	r1, [r2, #2112]
13512
-	add	r2, r6, r3
13513
-	add	r3, r6, r3, asl #4
13514
-	ldrb	r5, [r2, #2232]	@ zero_extendqisi2
13515
-	strb	r5, [r3, #2100]
13516
-	mov	r0, r5
13517
-	ldrb	r3, [r6, #2230]	@ zero_extendqisi2
13980
+	strne	r1, [r2, #2116]
13981
+	add	r2, r5, r3
13982
+	ldrb	r6, [r2, #2236]	@ zero_extendqisi2
13983
+	add	r3, r5, r3, lsl #4
13984
+	strb	r6, [r3, #2104]
13985
+	mov	r0, r6
13986
+	ldrb	r3, [r5, #2234]	@ zero_extendqisi2
13518
13987
 	cmp	r3, #1
13519
-	bne	.L2291
13988
+	bne	.L2254
13520
13989
 	bl	NandcWaitFlashReady
13521
-	b	.L2292
13522
-.L2291:
13523
-	bl	NandcFlashCs
13524
-	mov	r0, r5
13525
-	ldr	r3, [sp, #32]
13526
-	ldr	r1, [sp, #28]
13527
-	add	r3, r6, r3, asl #2
13528
-	ldr	r2, [r3, #1172]
13529
-	adds	r2, r2, #0
13530
-	movne	r2, #1
13531
-	bl	FlashWaitReadyEN
13532
-	mov	r0, r5
13533
-	bl	NandcFlashDeCs
13534
-.L2292:
13535
-	ldr	r3, [sp, #16]
13990
+.L2255:
13991
+	ldr	r3, [sp, #20]
13536
13992
 	sub	r3, r3, #1
13537
13993
 	cmp	r3, #7
13538
-	bhi	.L2293
13539
-	add	r3, r6, r5
13540
-	ldrb	r3, [r3, #2064]	@ zero_extendqisi2
13994
+	bhi	.L2256
13995
+	add	r3, r5, r6
13996
+	ldrb	r3, [r3, #2068]	@ zero_extendqisi2
13541
13997
 	cmp	r3, #0
13542
-	beq	.L2293
13543
-	mov	r0, r5
13544
-	ldrb	r1, [r6, #1211]	@ zero_extendqisi2
13545
-	ldr	r2, .L2339+8
13998
+	beq	.L2256
13546
13999
 	mov	r3, #0
14000
+	ldr	r2, [sp, #28]
14001
+	ldrb	r1, [r5, #1217]	@ zero_extendqisi2
14002
+	mov	r0, r6
13547
14003
 	bl	HynixSetRRPara
13548
-.L2293:
13549
-	mov	r0, r5
14004
+.L2256:
14005
+	mov	r0, r6
13550
14006
 	bl	NandcFlashCs
13551
14007
 	cmp	r9, #1
13552
-	mov	r0, r5
13553
-	bne	.L2294
13554
-	ldrb	r3, [r6, #144]	@ zero_extendqisi2
14008
+	mov	r0, r6
14009
+	bne	.L2257
14010
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
13555
14011
 	cmp	r3, #0
13556
-	beq	.L2294
14012
+	beq	.L2257
13557
14013
 	bl	flash_enter_slc_mode
13558
-	b	.L2295
13559
-.L2294:
13560
-	bl	flash_exit_slc_mode
13561
-.L2295:
13562
-	mov	r0, r5
13563
-	ldr	r1, [sp, #28]
14014
+.L2258:
14015
+	ldr	r1, [sp, #36]
14016
+	mov	r0, r6
13564
14017
 	bl	FlashProgFirstCmd
13565
14018
 	ldr	r3, [fp, #12]
13566
-	mov	r0, r5
13567
14019
 	mov	r1, #1
14020
+	ldr	r2, [sp, #16]
14021
+	mov	r0, r6
13568
14022
 	str	r3, [sp]
13569
-	ldr	r2, [sp, #12]
13570
14023
 	ldr	r3, [fp, #8]
13571
14024
 	bl	NandcXferData
13572
14025
 	cmp	r10, #0
13573
-	beq	.L2296
13574
-	mov	r0, r5
13575
-	ldr	r1, [sp, #28]
14026
+	beq	.L2259
14027
+	ldr	r1, [sp, #36]
14028
+	mov	r0, r6
13576
14029
 	bl	FlashProgDpFirstCmd
13577
-	mov	r0, r5
13578
-	add	r8, r8, #36
13579
-	add	r8, r4, r8
13580
-	ldr	r3, [sp, #32]
13581
-	ldr	r1, [sp, #28]
13582
-	add	r3, r6, r3, asl #2
13583
-	ldr	r2, [r3, #1172]
14030
+	ldr	r3, [sp, #40]
14031
+	mov	r0, r6
14032
+	ldr	r1, [sp, #36]
14033
+	add	r7, r7, #36
14034
+	add	r7, r4, r7
14035
+	add	r3, r5, r3, lsl #2
14036
+	ldr	r2, [r3, #1180]
13584
14037
 	adds	r2, r2, #0
13585
14038
 	movne	r2, #1
13586
14039
 	bl	FlashWaitReadyEN
13587
-	ldr	r1, [r6, #4]
13588
-	mov	r0, r5
13589
-	ldr	r3, [sp, #28]
14040
+	ldr	r3, [r5, #40]
14041
+	mov	r0, r6
14042
+	ldr	r1, [sp, #36]
13590
14043
 	add	r1, r1, r3
13591
14044
 	bl	FlashProgDpSecondCmd
13592
-	ldr	r3, [r8, #12]
13593
-	mov	r0, r5
14045
+	ldr	r3, [r7, #12]
13594
14046
 	mov	r1, #1
14047
+	ldr	r2, [sp, #16]
14048
+	mov	r0, r6
13595
14049
 	str	r3, [sp]
13596
-	ldr	r2, [sp, #12]
13597
-	ldr	r3, [r8, #8]
14050
+	ldr	r3, [r7, #8]
13598
14051
 	bl	NandcXferData
13599
-.L2296:
13600
-	mov	r0, r5
13601
-	ldr	r1, [sp, #28]
14052
+.L2259:
14053
+	ldr	r1, [sp, #36]
14054
+	mov	r0, r6
14055
+	add	r8, r8, r10
13602
14056
 	bl	FlashProgSecondCmd
13603
-	mov	r0, r5
14057
+	mov	r0, r6
13604
14058
 	bl	NandcFlashDeCs
13605
-	add	r7, r7, r10
13606
-	b	.L2287
13607
-.L2337:
13608
-	ldr	r8, .L2339+12
13609
-	mov	r6, #0
13610
-	mov	r7, r5
13611
-.L2298:
13612
-	ldrb	r3, [r5, #2230]	@ zero_extendqisi2
13613
-	cmp	r6, r3
13614
-	bcs	.L2338
14059
+.L2250:
14060
+	add	r8, r8, #1
14061
+	b	.L2247
14062
+.L2254:
14063
+	bl	NandcFlashCs
14064
+	ldr	r3, [sp, #40]
14065
+	mov	r0, r6
14066
+	ldr	r1, [sp, #36]
14067
+	add	r3, r5, r3, lsl #2
14068
+	ldr	r2, [r3, #1180]
14069
+	adds	r2, r2, #0
14070
+	movne	r2, #1
14071
+	bl	FlashWaitReadyEN
14072
+	mov	r0, r6
14073
+	bl	NandcFlashDeCs
14074
+	b	.L2255
14075
+.L2257:
14076
+	bl	flash_exit_slc_mode
14077
+	b	.L2258
14078
+.L2263:
13615
14079
 	uxtb	r0, r6
13616
14080
 	bl	FlashWaitCmdDone
13617
14081
 	cmp	r9, #1
13618
-	bne	.L2299
13619
-	ldrb	r3, [r7, #144]	@ zero_extendqisi2
14082
+	bne	.L2262
14083
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
13620
14084
 	cmp	r3, #0
13621
-	beq	.L2299
13622
-	ldrb	r0, [r8, r6, asl #4]	@ zero_extendqisi2
14085
+	beq	.L2262
14086
+	ldrb	r0, [r7, r6, lsl #4]	@ zero_extendqisi2
13623
14087
 	bl	flash_exit_slc_mode
13624
-.L2299:
14088
+.L2262:
13625
14089
 	add	r6, r6, #1
13626
-	b	.L2298
13627
-.L2338:
13628
-	ldr	r3, [sp, #20]
13629
-	cmp	r3, #0
13630
-	bne	.L2301
13631
-.L2309:
13632
-	mov	r0, #0
13633
-	b	.L2285
13634
-.L2301:
13635
-	ldr	r5, .L2339+16
14090
+	b	.L2261
14091
+.L2264:
14092
+	ldr	r5, .L2298+12
13636
14093
 	mov	r6, #0
13637
-	mov	r7, r5
13638
-.L2302:
13639
-	ldr	r3, [sp, #8]
14094
+	ldr	r7, .L2298+16
14095
+.L2265:
14096
+	ldr	r3, [sp, #12]
13640
14097
 	cmp	r6, r3
13641
-	beq	.L2309
14098
+	beq	.L2272
13642
14099
 	ldr	r3, [r4]
13643
14100
 	cmn	r3, #1
13644
-	bne	.L2303
14101
+	bne	.L2266
13645
14102
 	ldr	r1, [r4, #4]
13646
-	ldr	r0, .L2339+20
14103
+	ldr	r0, .L2298+20
13647
14104
 	bl	printk
13648
-	b	.L2304
13649
-.L2303:
13650
-	ldr	r3, [sp, #8]
13651
-	mov	r1, r9
13652
-	add	r2, sp, #28
13653
-	mov	r0, r4
13654
-	rsb	r3, r6, r3
13655
-	uxtb	r3, r3
13656
-	str	r3, [sp]
13657
-	add	r3, sp, #32
13658
-	bl	LogAddr2PhyAddr
13659
-	ldr	r2, [r5, #1724]
13660
-	mov	r3, #0
13661
-	mov	lr, r4
13662
-	str	r3, [r2]
13663
-	ldr	r2, [r5, #1728]
13664
-	str	r3, [r2]
13665
-	ldmia	lr!, {r0, r1, r2, r3}
13666
-	add	ip, sp, #36
13667
-	stmia	ip!, {r0, r1, r2, r3}
13668
-	ldmia	lr!, {r0, r1, r2, r3}
13669
-	stmia	ip!, {r0, r1, r2, r3}
13670
-	add	r0, sp, #36
13671
-	ldr	r3, [lr]
13672
-	mov	r1, #1
13673
-	mov	r2, r9
13674
-	str	r3, [ip]
13675
-	ldr	r3, [r5, #1724]
13676
-	str	r3, [sp, #44]
13677
-	ldr	r3, [r5, #1728]
13678
-	str	r3, [sp, #48]
13679
-	bl	FlashReadPages
13680
-	ldr	r8, [sp, #36]
13681
-	cmn	r8, #1
13682
-	bne	.L2305
13683
-	ldr	r0, .L2339+24
13684
-	ldr	r1, [r4, #4]
13685
-	bl	printk
13686
-	str	r8, [r4]
13687
-.L2305:
13688
-	ldr	r3, [r4, #12]
13689
-	cmp	r3, #0
13690
-	beq	.L2306
13691
-	ldr	r2, [r3]
13692
-	ldr	r3, [r7, #1728]
13693
-	ldr	r3, [r3]
13694
-	cmp	r2, r3
13695
-	beq	.L2306
13696
-	ldr	r0, .L2339+28
13697
-	ldr	r1, [r4, #4]
13698
-	bl	printk
13699
-	mvn	r3, #0
13700
-	str	r3, [r4]
13701
-.L2306:
13702
-	ldr	r3, [r4, #8]
13703
-	cmp	r3, #0
13704
-	beq	.L2304
13705
-	ldr	r2, [r3]
13706
-	ldr	r3, [r7, #1724]
13707
-	ldr	r3, [r3]
13708
-	cmp	r2, r3
13709
-	beq	.L2304
13710
-	ldr	r0, .L2339+32
13711
-	ldr	r1, [r4, #4]
13712
-	bl	printk
13713
-	mvn	r3, #0
13714
-	str	r3, [r4]
13715
-.L2304:
14105
+.L2267:
13716
14106
 	add	r6, r6, #1
13717
14107
 	add	r4, r4, #36
13718
-	b	.L2302
13719
-.L2285:
13720
-	add	sp, sp, #76
13721
-	@ sp needed
13722
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
13723
-.L2340:
14108
+	b	.L2265
14109
+.L2266:
14110
+	ldr	r3, [sp, #12]
14111
+	add	r2, sp, #36
14112
+	mov	r1, r9
14113
+	mov	r0, r4
14114
+	sub	r3, r3, r6
14115
+	uxtb	r3, r3
14116
+	str	r3, [sp]
14117
+	add	r3, sp, #40
14118
+	bl	LogAddr2PhyAddr
14119
+	ldr	r2, [r5, #1732]
14120
+	mov	r3, #0
14121
+	mov	lr, r4
14122
+	add	ip, sp, #44
14123
+	str	r3, [r2]
14124
+	ldr	r2, [r5, #1736]
14125
+	str	r3, [r2]
14126
+	ldmia	lr!, {r0, r1, r2, r3}
14127
+	stmia	ip!, {r0, r1, r2, r3}
14128
+	ldmia	lr!, {r0, r1, r2, r3}
14129
+	stmia	ip!, {r0, r1, r2, r3}
14130
+	mov	r2, r9
14131
+	ldr	r3, [lr]
14132
+	mov	r1, #1
14133
+	add	r0, sp, #44
14134
+	str	r3, [ip]
14135
+	ldr	r3, [r5, #1732]
14136
+	str	r3, [sp, #52]
14137
+	ldr	r3, [r5, #1736]
14138
+	str	r3, [sp, #56]
14139
+	bl	FlashReadPages
14140
+	ldr	r8, [sp, #44]
14141
+	cmn	r8, #1
14142
+	bne	.L2268
14143
+	ldr	r1, [r4, #4]
14144
+	ldr	r0, .L2298+24
14145
+	bl	printk
14146
+	str	r8, [r4]
14147
+.L2268:
14148
+	ldr	r3, [r4, #12]
14149
+	cmp	r3, #0
14150
+	beq	.L2269
14151
+	ldr	r2, [r3]
14152
+	ldr	r3, [r5, #1736]
14153
+	ldr	r3, [r3]
14154
+	cmp	r2, r3
14155
+	beq	.L2269
14156
+	ldr	r1, [r4, #4]
14157
+	ldr	r0, .L2298+28
14158
+	bl	printk
14159
+	mvn	r3, #0
14160
+	str	r3, [r4]
14161
+.L2269:
14162
+	ldr	r3, [r4, #8]
14163
+	cmp	r3, #0
14164
+	beq	.L2267
14165
+	ldr	r2, [r3]
14166
+	ldr	r3, [r5, #1732]
14167
+	ldr	r3, [r3]
14168
+	cmp	r2, r3
14169
+	beq	.L2267
14170
+	ldr	r1, [r4, #4]
14171
+	mov	r0, r7
14172
+	bl	printk
14173
+	mvn	r3, #0
14174
+	str	r3, [r4]
14175
+	b	.L2267
14176
+.L2299:
13724
14177
 	.align	2
13725
-.L2339:
14178
+.L2298:
13726
14179
 	.word	.LANCHOR0
13727
14180
 	.word	.LANCHOR1
13728
-	.word	.LANCHOR0+1214
13729
-	.word	.LANCHOR0+2100
14181
+	.word	.LANCHOR0+2104
13730
14182
 	.word	.LANCHOR2
14183
+	.word	.LC108
13731
14184
 	.word	.LC104
13732
14185
 	.word	.LC105
13733
14186
 	.word	.LC107
13734
-	.word	.LC108
13735
14187
 	.fnend
13736
14188
 	.size	FlashProgPages, .-FlashProgPages
13737
14189
 	.align	2
13738
14190
 	.global	FlashTestBlk
14191
+	.syntax unified
14192
+	.arm
14193
+	.fpu softvfp
13739
14194
 	.type	FlashTestBlk, %function
13740
14195
 FlashTestBlk:
13741
14196
 	.fnstart
13742
14197
 	@ args = 0, pretend = 0, frame = 104
13743
14198
 	@ frame_needed = 0, uses_anonymous_args = 0
13744
-	stmfd	sp!, {r4, r5, lr}
14199
+	push	{r4, r5, lr}
13745
14200
 	.save {r4, r5, lr}
13746
14201
 	.pad #108
13747
14202
 	sub	sp, sp, #108
13748
-	ldr	r5, .L2345
13749
-	ldr	r3, [r5, #1708]
14203
+	ldr	r5, .L2304
14204
+	ldr	r3, [r5, #1716]
13750
14205
 	cmp	r0, r3
13751
14206
 	movcc	r4, #0
13752
-	bcc	.L2342
13753
-	ldr	r3, [r5, #1716]
14207
+	bcc	.L2300
14208
+	ldr	r3, [r5, #1724]
13754
14209
 	mov	r4, r0
13755
-	mov	r1, #165
13756
-	add	r0, sp, #40
13757
14210
 	mov	r2, #32
14211
+	add	r0, sp, #40
14212
+	mov	r1, #165
13758
14213
 	str	r0, [sp, #16]
13759
14214
 	str	r3, [sp, #12]
13760
14215
 	bl	ftl_memset
13761
-	mov	r1, #90
13762
14216
 	mov	r2, #8
13763
-	ldr	r0, [r5, #1716]
13764
-	mov	r4, r4, asl #10
14217
+	mov	r1, #90
14218
+	ldr	r0, [r5, #1724]
13765
14219
 	bl	ftl_memset
13766
-	mov	r1, #1
13767
-	mov	r2, r1
13768
-	add	r0, sp, #4
13769
-	str	r4, [sp, #8]
13770
-	bl	FlashEraseBlocks
13771
-	mov	r1, #1
13772
-	mov	r2, r1
13773
-	mov	r3, r1
13774
-	add	r0, sp, #4
13775
-	bl	FlashProgPages
13776
-	mov	r1, #0
14220
+	lsl	r0, r4, #10
13777
14221
 	mov	r2, #1
14222
+	mov	r1, r2
14223
+	str	r0, [sp, #8]
14224
+	add	r0, sp, #4
14225
+	bl	FlashEraseBlocks
14226
+	mov	r3, #1
14227
+	add	r0, sp, #4
14228
+	mov	r2, r3
14229
+	mov	r1, r3
14230
+	bl	FlashProgPages
13778
14231
 	ldr	r4, [sp, #4]
14232
+	mov	r2, #1
14233
+	mov	r1, #0
13779
14234
 	add	r0, sp, #4
13780
14235
 	adds	r4, r4, #0
13781
14236
 	movne	r4, #1
13782
14237
 	rsb	r4, r4, #0
13783
14238
 	bl	FlashEraseBlocks
13784
-.L2342:
14239
+.L2300:
13785
14240
 	mov	r0, r4
13786
14241
 	add	sp, sp, #108
13787
14242
 	@ sp needed
13788
-	ldmfd	sp!, {r4, r5, pc}
13789
-.L2346:
14243
+	pop	{r4, r5, pc}
14244
+.L2305:
13790
14245
 	.align	2
13791
-.L2345:
14246
+.L2304:
13792
14247
 	.word	.LANCHOR2
13793
14248
 	.fnend
13794
14249
 	.size	FlashTestBlk, .-FlashTestBlk
13795
14250
 	.align	2
13796
14251
 	.global	FlashMakeFactorBbt
14252
+	.syntax unified
14253
+	.arm
14254
+	.fpu softvfp
13797
14255
 	.type	FlashMakeFactorBbt, %function
13798
14256
 FlashMakeFactorBbt:
13799
14257
 	.fnstart
13800
14258
 	@ args = 0, pretend = 0, frame = 80
13801
14259
 	@ frame_needed = 0, uses_anonymous_args = 0
13802
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14260
+	ldr	r2, .L2357
14261
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
13803
14262
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13804
14263
 	.pad #84
13805
14264
 	sub	sp, sp, #84
13806
-	ldr	r5, .L2403
13807
-	mov	r1, #1
13808
-	ldr	r4, .L2403+4
13809
-	ldr	r0, .L2403+8
13810
-	ldr	r3, [r5, #1720]
13811
-	ldrh	r8, [r4, #128]
13812
-	str	r3, [sp, #20]
13813
-	ldrh	r3, [r4, #130]
13814
-	smulbb	r8, r8, r3
13815
-	ldr	r3, [r4, #44]
13816
-	ldrb	r3, [r3, #24]	@ zero_extendqisi2
13817
-	uxth	r8, r8
14265
+	ldr	r5, .L2357
14266
+	mov	r4, r2
14267
+	ldr	r3, [r2, #1728]
13818
14268
 	str	r3, [sp, #24]
13819
-	ldrh	r3, [r4, #4]
13820
-	str	r3, [sp, #16]
13821
-	ldrb	r3, [r4]	@ zero_extendqisi2
13822
-	ldr	r4, .L2403+4
14269
+	ldr	r3, .L2357+4
14270
+	ldrh	r0, [r3, #136]
14271
+	ldrh	r1, [r3, #138]
14272
+	smulbb	r1, r1, r0
14273
+	ldr	r0, .L2357+8
14274
+	uxth	r1, r1
14275
+	str	r1, [sp, #4]
14276
+	ldr	r1, [r3, #48]
14277
+	ldrb	r1, [r1, #24]	@ zero_extendqisi2
14278
+	str	r1, [sp, #28]
14279
+	ldrh	r1, [r3, #40]
14280
+	ldrb	r3, [r3, #36]	@ zero_extendqisi2
14281
+	str	r1, [sp, #20]
13823
14282
 	cmp	r3, #1
13824
-	ldreq	r3, [sp, #16]
13825
-	moveq	r3, r3, asl #1
14283
+	moveq	r3, r1
14284
+	mov	r1, #1
14285
+	lsleq	r3, r3, #1
13826
14286
 	uxtheq	r3, r3
13827
-	streq	r3, [sp, #16]
14287
+	streq	r3, [sp, #20]
13828
14288
 	bl	printk
13829
-	ldr	r0, [r5, #1720]
13830
-	mov	r1, #0
14289
+	ldr	r0, [r4, #1728]
13831
14290
 	mov	r2, #4096
14291
+	mov	r1, #0
14292
+	ldr	r4, .L2357+4
13832
14293
 	bl	ftl_memset
13833
-	ldr	r5, .L2403
13834
-	mov	r3, r8, lsr #4
13835
-	str	r3, [sp, #28]
14294
+	ldr	r3, [sp, #4]
14295
+	lsr	r3, r3, #4
14296
+	str	r3, [sp, #32]
13836
14297
 	mov	r3, #0
13837
-	str	r3, [sp, #8]
13838
-.L2349:
13839
-	ldrb	r7, [sp, #8]	@ zero_extendqisi2
13840
-	ldrb	r3, [r4, #2230]	@ zero_extendqisi2
14298
+	str	r3, [sp, #12]
14299
+.L2308:
14300
+	ldrb	r7, [sp, #12]	@ zero_extendqisi2
14301
+	ldrb	r3, [r4, #2234]	@ zero_extendqisi2
13841
14302
 	cmp	r3, r7
13842
-	bls	.L2399
13843
-	ldr	r2, .L2403+12
13844
-	mov	r3, r7, asl #1
14303
+	bhi	.L2335
14304
+	add	sp, sp, #84
14305
+	@ sp needed
14306
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
14307
+.L2335:
14308
+	ldr	r2, .L2357+12
14309
+	lsl	r3, r7, #1
13845
14310
 	ldrh	r6, [r2, r3]
13846
14311
 	cmp	r6, #0
13847
-	bne	.L2379
13848
-	ldrh	r2, [r4, #136]
14312
+	bne	.L2309
14313
+	ldrh	r2, [r4, #144]
13849
14314
 	mov	r1, r6
13850
-	ldr	r0, [r5, #1688]
14315
+	ldr	r0, [r5, #1696]
14316
+	add	fp, r4, r7, lsl #2
14317
+	mov	r8, r6
13851
14318
 	mov	r9, r6
13852
-	mov	r2, r2, asl #9
14319
+	lsl	r2, r2, #9
13853
14320
 	bl	ftl_memset
13854
14321
 	add	r3, r4, r7
13855
-	ldrb	r10, [r3, #2232]	@ zero_extendqisi2
13856
-	mov	r3, r7, asl #2
13857
-	add	fp, r4, r3
13858
-	str	r6, [sp, #4]
13859
-	str	r3, [sp, #32]
13860
-.L2351:
13861
-	ldrh	r3, [sp, #4]
13862
-	cmp	r3, r8
13863
-	str	r3, [sp, #12]
13864
-	bcs	.L2361
14322
+	str	r6, [sp, #8]
14323
+	ldrb	r10, [r3, #2236]	@ zero_extendqisi2
14324
+.L2310:
14325
+	ldrh	r3, [sp, #8]
14326
+	ldr	r2, [sp, #4]
14327
+	str	r3, [sp, #16]
14328
+	cmp	r3, r2
14329
+	bcc	.L2321
14330
+.L2320:
14331
+	mov	r2, r8
14332
+	mov	r1, r7
14333
+	ldr	r0, .L2357+16
14334
+	bl	printk
14335
+	ldrb	r3, [r4, #2234]	@ zero_extendqisi2
14336
+	ldr	r2, [sp, #32]
14337
+	mul	r3, r2, r3
14338
+	cmp	r8, r3
14339
+	blt	.L2322
14340
+	ldrh	r2, [r4, #144]
14341
+	mov	r1, #0
14342
+	ldr	r0, [r5, #1696]
14343
+	lsl	r2, r2, #9
14344
+	bl	ftl_memset
14345
+.L2322:
14346
+	cmp	r7, #0
14347
+	bne	.L2324
14348
+	add	r3, r5, #1712
14349
+	ldr	r8, .L2357+20
14350
+	add	r3, r3, #4
14351
+	ldrh	r10, [r3]
14352
+	mov	r9, #1
14353
+.L2325:
14354
+	ldrb	r3, [r4, #37]	@ zero_extendqisi2
14355
+	cmp	r3, r10
14356
+	bhi	.L2327
14357
+	ldr	r3, [sp, #4]
14358
+	mov	r10, #1
14359
+	ldr	r9, .L2357+20
14360
+	sub	fp, r3, #1
14361
+	sub	r8, r3, #50
14362
+	uxth	fp, fp
14363
+.L2328:
14364
+	cmp	fp, r8
14365
+	bgt	.L2330
14366
+	ldrb	r3, [r4, #37]	@ zero_extendqisi2
14367
+	ldr	r2, [r5, #1716]
14368
+	sub	r3, r3, r2
14369
+	cmp	r6, r3
14370
+	bcc	.L2324
14371
+	ldrh	r2, [r4, #144]
14372
+	mov	r1, #0
14373
+	ldr	r0, [r5, #1696]
14374
+	lsl	r2, r2, #9
14375
+	bl	ftl_memset
14376
+.L2324:
14377
+	ldr	r3, [sp, #4]
14378
+	ldrb	r8, [sp, #12]	@ zero_extendqisi2
14379
+	ldr	r9, .L2357+12
14380
+	sub	r6, r3, #1
14381
+	ldr	fp, .L2357+24
14382
+	ldr	r10, .L2357+28
14383
+	uxth	r6, r6
14384
+	mul	r8, r3, r8
14385
+	add	r9, r9, r7, lsl #1
14386
+.L2332:
14387
+	mov	r1, r7
14388
+	mov	r2, r6
14389
+	mov	r0, fp
14390
+	bl	printk
14391
+	ldr	r1, [r5, #1696]
14392
+.L2333:
14393
+	lsr	r2, r6, #5
14394
+	and	r3, r6, #31
14395
+	ldr	r2, [r1, r2, lsl #2]
14396
+	lsr	r3, r2, r3
14397
+	ands	r3, r3, #1
14398
+	bne	.L2334
14399
+	ldr	r2, [sp, #24]
14400
+	add	r0, sp, #44
14401
+	strh	r6, [r9]	@ movhi
14402
+	strh	r10, [r2]	@ movhi
14403
+	strh	r6, [r2, #2]	@ movhi
14404
+	strh	r3, [r2, #8]	@ movhi
14405
+	mov	r2, #1
14406
+	ldr	r3, [r5, #1696]
14407
+	mov	r1, r2
14408
+	str	r3, [sp, #52]
14409
+	ldr	r3, [r5, #1728]
14410
+	str	r3, [sp, #56]
14411
+	add	r3, r6, r8
14412
+	lsl	r3, r3, #10
14413
+	str	r3, [sp, #48]
14414
+	bl	FlashEraseBlocks
14415
+	mov	r3, #1
14416
+	add	r0, sp, #44
14417
+	mov	r2, r3
14418
+	mov	r1, r3
14419
+	bl	FlashProgPages
14420
+	ldr	r3, [sp, #44]
14421
+	cmp	r3, #0
14422
+	beq	.L2309
14423
+	sub	r6, r6, #1
14424
+	uxth	r6, r6
14425
+	b	.L2332
14426
+.L2321:
13865
14427
 	mvn	r3, #0
13866
14428
 	strb	r3, [sp, #42]
13867
14429
 	strb	r3, [sp, #43]
13868
-	ldr	r3, [sp, #24]
14430
+	ldr	r3, [sp, #28]
13869
14431
 	tst	r3, #1
13870
-	beq	.L2353
13871
-	ldr	r3, [fp, #1172]
14432
+	beq	.L2312
14433
+	ldr	r3, [fp, #1180]
13872
14434
 	add	r2, sp, #42
13873
14435
 	mov	r0, r10
13874
-	add	r3, r6, r3
13875
-	str	r3, [sp, #36]
14436
+	add	r3, r9, r3
13876
14437
 	mov	r1, r3
14438
+	str	r3, [sp, #36]
13877
14439
 	bl	FlashReadSpare
13878
-	ldrb	r2, [r4]	@ zero_extendqisi2
13879
-	cmp	r2, #1
14440
+	ldrb	r2, [r4, #36]	@ zero_extendqisi2
13880
14441
 	ldr	r3, [sp, #36]
13881
-	bne	.L2353
13882
-	ldr	r1, [r4, #4]
14442
+	cmp	r2, #1
14443
+	bne	.L2312
14444
+	ldr	r1, [r4, #40]
13883
14445
 	add	r2, sp, #43
13884
14446
 	mov	r0, r10
13885
14447
 	add	r1, r3, r1
..
..
@@ -13888,1198 +14450,1097 @@
13888
14450
 	ldrb	r2, [sp, #43]	@ zero_extendqisi2
13889
14451
 	and	r3, r3, r2
13890
14452
 	strb	r3, [sp, #42]
13891
-.L2353:
13892
-	ldr	r3, [sp, #24]
14453
+.L2312:
14454
+	ldr	r3, [sp, #28]
13893
14455
 	tst	r3, #2
13894
-	beq	.L2355
13895
-	ldr	r3, [r4, #44]
13896
-	mov	r0, r10
14456
+	beq	.L2314
14457
+	ldr	r3, [r4, #48]
13897
14458
 	add	r2, sp, #43
14459
+	mov	r0, r10
13898
14460
 	ldrh	r1, [r3, #10]
13899
-	ldr	r3, [fp, #1172]
14461
+	ldr	r3, [fp, #1180]
13900
14462
 	sub	r1, r1, #1
13901
14463
 	add	r1, r1, r3
13902
-	add	r1, r1, r6
14464
+	add	r1, r1, r9
13903
14465
 	bl	FlashReadSpare
13904
-.L2355:
13905
-	ldr	r2, [r4, #44]
14466
+.L2314:
14467
+	ldr	r2, [r4, #48]
13906
14468
 	ldrb	r3, [r2, #7]	@ zero_extendqisi2
13907
-	cmp	r3, #1
13908
-	cmpne	r3, #8
14469
+	cmp	r3, #8
14470
+	cmpne	r3, #1
13909
14471
 	ldrb	r3, [sp, #42]	@ zero_extendqisi2
13910
-	beq	.L2356
14472
+	beq	.L2315
13911
14473
 	ldrb	r2, [r2, #18]	@ zero_extendqisi2
13912
14474
 	cmp	r2, #12
13913
-	bne	.L2357
13914
-.L2356:
14475
+	bne	.L2316
14476
+.L2315:
13915
14477
 	cmp	r3, #0
13916
-	ldrneb	r0, [sp, #43]	@ zero_extendqisi2
14478
+	ldrbne	r0, [sp, #43]	@ zero_extendqisi2
13917
14479
 	clzne	r0, r0
13918
-	movne	r0, r0, lsr #5
13919
-	bne	.L2358
13920
-	b	.L2378
13921
-.L2357:
14480
+	lsrne	r0, r0, #5
14481
+	bne	.L2317
14482
+.L2337:
14483
+	mov	r0, #1
14484
+	b	.L2317
14485
+.L2316:
13922
14486
 	cmp	r3, #255
13923
-	bne	.L2378
14487
+	bne	.L2337
13924
14488
 	ldrb	r0, [sp, #43]	@ zero_extendqisi2
13925
14489
 	subs	r0, r0, #255
13926
14490
 	movne	r0, #1
13927
-	b	.L2358
13928
-.L2378:
13929
-	mov	r0, #1
13930
-.L2358:
13931
-	ldr	r3, [sp, #24]
14491
+.L2317:
14492
+	ldr	r3, [sp, #28]
13932
14493
 	tst	r3, #4
13933
-	beq	.L2359
13934
-	ldr	r3, .L2403+4
14494
+	beq	.L2318
14495
+	ldr	r1, [fp, #1180]
13935
14496
 	mov	r0, r10
13936
-	ldr	r2, [sp, #32]
13937
-	add	r3, r3, r2
13938
-	ldr	r1, [r3, #1172]
13939
-	add	r1, r6, r1
14497
+	add	r1, r9, r1
13940
14498
 	bl	SandiskProgTestBadBlock
13941
-.L2359:
14499
+.L2318:
13942
14500
 	cmp	r0, #0
13943
-	beq	.L2360
14501
+	beq	.L2319
14502
+	ldr	r2, [sp, #8]
13944
14503
 	mov	r1, r7
13945
-	ldr	r2, [sp, #4]
13946
-	ldr	r0, .L2403+16
13947
-	add	r9, r9, #1
14504
+	ldr	r0, .L2357+32
14505
+	add	r8, r8, #1
13948
14506
 	bl	printk
13949
-	ldr	r1, [r5, #1688]
13950
-	mov	ip, #1
13951
-	uxth	r9, r9
13952
-	ldr	r3, [sp, #12]
13953
-	mov	r0, r3, lsr #5
13954
-	and	r3, r3, #31
13955
-	ldr	r2, [r1, r0, asl #2]
13956
-	orr	r3, r2, ip, asl r3
13957
-	ldr	r2, [sp, #28]
13958
-	str	r3, [r1, r0, asl #2]
13959
-	ldrb	r3, [r4, #2230]	@ zero_extendqisi2
13960
-	mul	r3, r3, r2
13961
-	cmp	r9, r3
13962
-	bgt	.L2361
13963
-.L2360:
13964
-	ldr	r3, [sp, #4]
13965
-	add	r3, r3, #1
13966
-	str	r3, [sp, #4]
13967
14507
 	ldr	r3, [sp, #16]
13968
-	add	r6, r6, r3
13969
-	b	.L2351
13970
-.L2361:
13971
-	mov	r2, r9
13972
-	ldr	r0, .L2403+20
13973
-	mov	r1, r7
13974
-	bl	printk
13975
-	ldrb	r3, [r4, #2230]	@ zero_extendqisi2
13976
-	ldr	r2, [sp, #28]
13977
-	mul	r3, r3, r2
13978
-	cmp	r9, r3
13979
-	blt	.L2363
13980
-	ldrh	r2, [r4, #136]
13981
-	mov	r1, #0
13982
-	ldr	r0, [r5, #1688]
13983
-	mov	r2, r2, asl #9
13984
-	bl	ftl_memset
13985
-.L2363:
13986
-	cmp	r7, #0
13987
-	bne	.L2365
13988
-	ldr	r3, [r5, #1708]
13989
-	mov	r6, r7
13990
-	mov	r9, #1
13991
-	uxth	r10, r3
13992
-.L2366:
13993
-	ldr	r3, .L2403+4
13994
-	ldrb	r3, [r3, #1]	@ zero_extendqisi2
13995
-	cmp	r3, r10
13996
-	bls	.L2400
13997
-	mov	r0, r10
13998
-	bl	FlashTestBlk
13999
-	cmp	r0, #0
14000
-	beq	.L2367
14001
-	mov	r1, r10
14002
-	ldr	r0, .L2403+24
14003
-	bl	printk
14004
-	ldr	r1, [r5, #1688]
14005
-	mov	r0, r10, lsr #5
14006
-	add	r6, r6, #1
14007
-	and	r3, r10, #31
14008
-	ldr	r2, [r1, r0, asl #2]
14009
-	uxth	r6, r6
14010
-	orr	r3, r2, r9, asl r3
14011
-	str	r3, [r1, r0, asl #2]
14012
-.L2367:
14013
-	add	r10, r10, #1
14014
-	uxth	r10, r10
14015
-	b	.L2366
14016
-.L2400:
14017
-	sub	fp, r8, #1
14018
-	sub	r9, r8, #50
14019
-	mov	r10, #1
14020
-	uxth	fp, fp
14021
-.L2369:
14022
-	cmp	fp, r9
14023
-	ble	.L2401
14024
-	mov	r0, fp
14025
-	bl	FlashTestBlk
14026
-	cmp	r0, #0
14027
-	beq	.L2370
14028
-	mov	r1, fp
14029
-	ldr	r0, .L2403+24
14030
-	bl	printk
14031
-	ldr	r1, [r5, #1688]
14032
-	mov	r0, fp, lsr #5
14033
-	and	r3, fp, #31
14034
-	ldr	r2, [r1, r0, asl #2]
14035
-	orr	r3, r2, r10, asl r3
14036
-	str	r3, [r1, r0, asl #2]
14037
-.L2370:
14038
-	sub	fp, fp, #1
14039
-	uxth	fp, fp
14040
-	b	.L2369
14041
-.L2401:
14042
-	ldr	r3, .L2403+4
14043
-	ldr	r2, [r5, #1708]
14044
-	ldrb	r3, [r3, #1]	@ zero_extendqisi2
14045
-	rsb	r3, r2, r3
14046
-	cmp	r6, r3
14047
-	bcc	.L2365
14048
-	ldrh	r2, [r4, #136]
14049
-	mov	r1, #0
14050
-	ldr	r0, [r5, #1688]
14051
-	mov	r2, r2, asl #9
14052
-	bl	ftl_memset
14053
-.L2365:
14054
-	ldrb	r6, [sp, #8]	@ zero_extendqisi2
14055
-	sub	r10, r8, #1
14056
-	ldr	r9, .L2403+12
14057
-	uxth	r10, r10
14058
-	mul	r6, r8, r6
14059
-	add	r9, r9, r7, asl #1
14060
-.L2373:
14061
-	mov	r1, r7
14062
-	ldr	r0, .L2403+28
14063
-	mov	r2, r10
14064
-	bl	printk
14065
-	ldr	r1, [r5, #1688]
14066
-.L2374:
14067
-	mov	r2, r10, lsr #5
14068
-	and	r3, r10, #31
14069
-	ldr	r2, [r1, r2, asl #2]
14070
-	mov	r3, r2, lsr r3
14071
-	ands	r3, r3, #1
14072
-	subne	r10, r10, #1
14073
-	uxthne	r10, r10
14074
-	bne	.L2374
14075
-.L2402:
14076
-	ldr	r1, [sp, #20]
14077
-	add	r0, sp, #44
14078
-	ldr	r2, .L2403+32
14079
-	strh	r10, [r9]	@ movhi
14080
-	strh	r10, [r1, #2]	@ movhi
14081
-	strh	r2, [r1]	@ movhi
14082
-	strh	r3, [r1, #8]	@ movhi
14083
-	mov	r1, #1
14084
-	ldr	r3, [r5, #1688]
14085
-	mov	r2, r1
14086
-	str	r3, [sp, #52]
14087
-	ldr	r3, [r5, #1720]
14088
-	str	r3, [sp, #56]
14089
-	add	r3, r10, r6
14090
-	mov	r3, r3, asl #10
14091
-	str	r3, [sp, #48]
14092
-	bl	FlashEraseBlocks
14093
-	mov	r1, #1
14094
-	mov	r3, r1
14095
-	mov	r2, r1
14096
-	add	r0, sp, #44
14097
-	bl	FlashProgPages
14098
-	ldr	r3, [sp, #44]
14099
-	cmp	r3, #0
14100
-	subne	r10, r10, #1
14101
-	uxthne	r10, r10
14102
-	bne	.L2373
14103
-.L2379:
14508
+	mov	ip, #1
14509
+	ldr	r2, [r5, #1696]
14510
+	uxth	r8, r8
14511
+	and	r0, r3, #31
14512
+	lsr	r1, r3, #5
14513
+	ldr	r3, [r2, r1, lsl #2]
14514
+	orr	r3, r3, ip, lsl r0
14515
+	str	r3, [r2, r1, lsl #2]
14516
+	ldr	r2, [sp, #32]
14517
+	ldrb	r3, [r4, #2234]	@ zero_extendqisi2
14518
+	mul	r3, r2, r3
14519
+	cmp	r8, r3
14520
+	bgt	.L2320
14521
+.L2319:
14104
14522
 	ldr	r3, [sp, #8]
14105
14523
 	add	r3, r3, #1
14106
14524
 	str	r3, [sp, #8]
14107
-	b	.L2349
14108
-.L2399:
14109
-	add	sp, sp, #84
14110
-	@ sp needed
14111
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
14112
-.L2404:
14525
+	ldr	r3, [sp, #20]
14526
+	add	r9, r9, r3
14527
+	b	.L2310
14528
+.L2327:
14529
+	mov	r0, r10
14530
+	bl	FlashTestBlk
14531
+	cmp	r0, #0
14532
+	beq	.L2326
14533
+	mov	r1, r10
14534
+	mov	r0, r8
14535
+	bl	printk
14536
+	ldr	r1, [r5, #1696]
14537
+	lsr	r0, r10, #5
14538
+	add	r6, r6, #1
14539
+	and	r3, r10, #31
14540
+	uxth	r6, r6
14541
+	ldr	r2, [r1, r0, lsl #2]
14542
+	orr	r3, r2, r9, lsl r3
14543
+	str	r3, [r1, r0, lsl #2]
14544
+.L2326:
14545
+	add	r10, r10, #1
14546
+	uxth	r10, r10
14547
+	b	.L2325
14548
+.L2330:
14549
+	mov	r0, fp
14550
+	bl	FlashTestBlk
14551
+	cmp	r0, #0
14552
+	beq	.L2329
14553
+	mov	r1, fp
14554
+	mov	r0, r9
14555
+	bl	printk
14556
+	ldr	r1, [r5, #1696]
14557
+	lsr	r0, fp, #5
14558
+	and	r3, fp, #31
14559
+	ldr	r2, [r1, r0, lsl #2]
14560
+	orr	r3, r2, r10, lsl r3
14561
+	str	r3, [r1, r0, lsl #2]
14562
+.L2329:
14563
+	sub	fp, fp, #1
14564
+	uxth	fp, fp
14565
+	b	.L2328
14566
+.L2334:
14567
+	sub	r6, r6, #1
14568
+	uxth	r6, r6
14569
+	b	.L2333
14570
+.L2309:
14571
+	ldr	r3, [sp, #12]
14572
+	add	r3, r3, #1
14573
+	str	r3, [sp, #12]
14574
+	b	.L2308
14575
+.L2358:
14113
14576
 	.align	2
14114
-.L2403:
14577
+.L2357:
14115
14578
 	.word	.LANCHOR2
14116
14579
 	.word	.LANCHOR0
14117
14580
 	.word	.LC121
14118
-	.word	.LANCHOR2+1736
14119
-	.word	.LC122
14581
+	.word	.LANCHOR2+1742
14120
14582
 	.word	.LC123
14121
14583
 	.word	.LC124
14122
14584
 	.word	.LC125
14123
14585
 	.word	-3872
14586
+	.word	.LC122
14124
14587
 	.fnend
14125
14588
 	.size	FlashMakeFactorBbt, .-FlashMakeFactorBbt
14126
14589
 	.align	2
14127
14590
 	.global	FtlLowFormatEraseBlock
14591
+	.syntax unified
14592
+	.arm
14593
+	.fpu softvfp
14128
14594
 	.type	FtlLowFormatEraseBlock, %function
14129
14595
 FtlLowFormatEraseBlock:
14130
14596
 	.fnstart
14131
14597
 	@ args = 0, pretend = 0, frame = 24
14132
14598
 	@ frame_needed = 0, uses_anonymous_args = 0
14133
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14599
+	ldr	r3, .L2404
14600
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
14134
14601
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14135
14602
 	.pad #28
14136
14603
 	sub	sp, sp, #28
14137
-	ldr	r9, .L2455
14138
-	ldr	fp, .L2455+4
14139
-	ldr	r5, [r9, #-3616]
14140
-	ldrb	r3, [fp, #2240]	@ zero_extendqisi2
14141
-	cmp	r5, #0
14142
-	str	r3, [sp, #16]
14143
-	movne	r0, #0
14144
-	bne	.L2406
14145
-	ldrb	r3, [fp, #144]	@ zero_extendqisi2
14146
-	mov	r6, fp
14147
-	add	fp, fp, #2400
14148
-	mov	r10, r9
14149
-	mov	r4, r5
14150
-	mov	r9, r5
14604
+	ldr	r2, [r3, #-3612]
14605
+	cmp	r2, #0
14606
+	movne	r4, #0
14607
+	bne	.L2359
14608
+	ldr	r5, .L2404+4
14609
+	mov	r10, r3
14610
+	ldr	fp, .L2404+8
14611
+	mov	r9, r2
14612
+	mov	r6, r2
14613
+	mov	r4, r2
14614
+	ldrb	r3, [r5, #2244]	@ zero_extendqisi2
14151
14615
 	mov	r8, #36
14152
-	str	r1, [sp]
14153
-	str	r0, [sp, #4]
14154
-	str	r3, [sp, #8]
14616
+	str	r1, [sp, #4]
14617
+	str	r0, [sp, #8]
14618
+	str	r3, [sp, #20]
14619
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
14155
14620
 	str	r0, [r10, #-548]
14156
-.L2407:
14157
-	ldr	ip, .L2455+4
14158
-	add	r1, ip, #2320
14159
-	ldrh	r0, [r1]
14621
+	str	r3, [sp, #12]
14622
+.L2361:
14623
+	ldrh	r0, [fp]
14160
14624
 	uxth	r1, r9
14161
14625
 	cmp	r0, r1
14162
-	bls	.L2450
14163
-	mul	r0, r8, r1
14164
-	ldr	ip, [r10, #-3612]
14626
+	bhi	.L2365
14627
+	cmp	r6, #0
14628
+	beq	.L2359
14629
+	ldr	r3, [sp, #12]
14630
+	mov	r8, #0
14631
+	mov	r2, r6
14632
+	ldr	r0, [r10, #-3608]
14633
+	strb	r8, [r5, #2244]
14634
+	mov	r9, #36
14635
+	adds	r7, r3, #0
14636
+	movne	r7, #1
14637
+	mov	r1, r7
14638
+	bl	FlashEraseBlocks
14639
+	ldrb	r3, [sp, #20]	@ zero_extendqisi2
14640
+	strb	r3, [r5, #2244]
14641
+.L2367:
14642
+	uxth	r2, r8
14643
+	cmp	r6, r2
14644
+	bhi	.L2369
14645
+	ldr	r3, [sp, #4]
14646
+	cmp	r3, #0
14647
+	bne	.L2370
14648
+	uxth	r7, r7
14649
+	mov	r3, #6
14650
+	str	r3, [sp, #16]
14651
+	mov	r3, #1
14652
+	str	r3, [sp, #12]
14653
+.L2371:
14654
+	ldr	r6, .L2404
14655
+	mov	r9, #0
14656
+.L2380:
14657
+	ldr	fp, .L2404+4
14658
+	mov	r10, #0
14659
+	mov	r5, r10
14660
+.L2372:
14661
+	ldr	r3, .L2404+8
14662
+	ldrh	r1, [r3]
14663
+	uxth	r3, r10
14664
+	cmp	r1, r3
14665
+	bhi	.L2375
14666
+	cmp	r5, #0
14667
+	beq	.L2359
14668
+	mov	r3, #1
14669
+	mov	r8, #0
14670
+	mov	r2, r7
14671
+	mov	r1, r5
14672
+	ldr	r0, [r6, #-3608]
14673
+	strb	r8, [fp, #2244]
14674
+	bl	FlashProgPages
14675
+	ldrb	r3, [sp, #20]	@ zero_extendqisi2
14676
+	strb	r3, [fp, #2244]
14677
+	mov	fp, #36
14678
+.L2377:
14679
+	uxth	r3, r8
14680
+	cmp	r5, r3
14681
+	bhi	.L2379
14682
+	ldr	r3, [sp, #16]
14683
+	add	r9, r9, r3
14684
+	ldr	r3, [sp, #12]
14685
+	uxth	r9, r9
14686
+	cmp	r3, r9
14687
+	bhi	.L2380
14688
+	mov	r8, #0
14689
+	mov	r9, #36
14690
+.L2381:
14691
+	uxth	r3, r8
14692
+	cmp	r5, r3
14693
+	ldr	r3, [sp, #4]
14694
+	bhi	.L2383
14695
+	adds	r0, r3, #0
14696
+	ldr	r3, [sp, #8]
14697
+	movne	r0, #1
14698
+	cmp	r3, #63
14699
+	orrls	r0, r0, #1
14700
+	cmp	r0, #0
14701
+	beq	.L2359
14702
+	mov	r2, r5
14703
+	mov	r1, r7
14704
+	ldr	r0, [r6, #-3608]
14705
+	bl	FlashEraseBlocks
14706
+.L2359:
14707
+	mov	r0, r4
14708
+	add	sp, sp, #28
14709
+	@ sp needed
14710
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
14711
+.L2365:
14712
+	uxth	r1, r9
14713
+	ldr	ip, [r10, #-3608]
14165
14714
 	mov	r3, #0
14715
+	mul	r0, r8, r1
14166
14716
 	str	r3, [ip, r0]
14167
-	ldr	r3, .L2455+4
14168
-	add	r1, r3, r1
14169
-	ldrb	r0, [r1, #2348]	@ zero_extendqisi2
14170
-	ldr	r1, [sp, #4]
14717
+	add	r0, r5, r1
14718
+	ldrb	r0, [r0, #2350]	@ zero_extendqisi2
14719
+	ldr	r1, [sp, #8]
14171
14720
 	bl	V2P_block
14172
-	ldr	r3, [sp]
14721
+	ldr	r3, [sp, #4]
14173
14722
 	mov	r7, r0
14174
14723
 	cmp	r3, #0
14175
-	beq	.L2408
14724
+	beq	.L2362
14176
14725
 	bl	IsBlkInVendorPart
14177
14726
 	cmp	r0, #0
14178
-	bne	.L2409
14179
-.L2408:
14727
+	bne	.L2363
14728
+.L2362:
14180
14729
 	mov	r0, r7
14181
14730
 	bl	FtlBbmIsBadBlock
14182
14731
 	cmp	r0, #0
14183
14732
 	addne	r4, r4, #1
14184
14733
 	uxthne	r4, r4
14185
-	bne	.L2409
14186
-	ldr	ip, [r10, #-3612]
14187
-	mov	r7, r7, asl #10
14188
-	ldrh	r1, [fp]
14189
-	mla	ip, r8, r5, ip
14190
-	mul	r1, r1, r5
14191
-	add	r5, r5, #1
14192
-	uxth	r5, r5
14193
-	cmp	r1, #0
14734
+	bne	.L2363
14735
+	ldr	r3, .L2404+12
14736
+	lsl	r7, r7, #10
14737
+	ldr	ip, [r10, #-3608]
14738
+	ldrh	r1, [r3]
14739
+	mla	ip, r8, r6, ip
14740
+	mul	r1, r6, r1
14741
+	add	r6, r6, #1
14742
+	uxth	r6, r6
14194
14743
 	str	r0, [ip, #8]
14195
-	add	r0, r1, #3
14196
14744
 	str	r7, [ip, #4]
14745
+	add	r0, r1, #3
14746
+	cmp	r1, #0
14197
14747
 	movlt	r1, r0
14198
14748
 	ldr	r0, [r10, #-496]
14199
14749
 	bic	r1, r1, #3
14200
14750
 	add	r1, r0, r1
14201
14751
 	str	r1, [ip, #12]
14202
-.L2409:
14752
+.L2363:
14203
14753
 	add	r9, r9, #1
14204
-	b	.L2407
14205
-.L2450:
14206
-	cmp	r5, #0
14207
-	beq	.L2430
14208
-	ldr	r3, [sp, #8]
14209
-	mov	r2, r5
14210
-	ldr	r0, [r10, #-3612]
14211
-	mov	r8, #0
14212
-	adds	r7, r3, #0
14213
-	strb	r8, [ip, #2240]
14214
-	str	ip, [sp, #8]
14215
-	mov	r9, #36
14216
-	movne	r7, #1
14217
-	mov	r1, r7
14218
-	bl	FlashEraseBlocks
14219
-	ldrb	r3, [sp, #16]	@ zero_extendqisi2
14220
-	ldr	ip, [sp, #8]
14221
-	strb	r3, [ip, #2240]
14222
-.L2413:
14223
-	uxth	r2, r8
14224
-	cmp	r2, r5
14225
-	bcs	.L2451
14754
+	b	.L2361
14755
+.L2369:
14226
14756
 	mul	r2, r9, r8
14227
-	ldr	r1, [r10, #-3612]
14228
-	add	r0, r1, r2
14757
+	ldr	r1, [r10, #-3608]
14758
+	add	ip, r1, r2
14229
14759
 	ldr	r2, [r1, r2]
14230
14760
 	cmn	r2, #1
14231
-	bne	.L2414
14232
-	ldr	r0, [r0, #4]
14761
+	bne	.L2368
14762
+	ldr	r0, [ip, #4]
14233
14763
 	add	r4, r4, #1
14234
-	ubfx	r0, r0, #10, #16
14235
14764
 	uxth	r4, r4
14765
+	ubfx	r0, r0, #10, #16
14236
14766
 	bl	FtlBbmMapBadBlock
14237
-.L2414:
14767
+.L2368:
14238
14768
 	add	r8, r8, #1
14239
-	b	.L2413
14240
-.L2451:
14241
-	ldr	r3, [sp]
14242
-	cmp	r3, #0
14243
-	bne	.L2416
14244
-	mov	r3, #6
14245
-	uxth	r7, r7
14769
+	b	.L2367
14770
+.L2370:
14771
+	movw	r3, #2392
14772
+	ldrh	r3, [r5, r3]
14246
14773
 	str	r3, [sp, #12]
14247
-	mov	r3, #1
14248
-	str	r3, [sp, #8]
14249
-	b	.L2417
14250
-.L2416:
14251
-	movw	r3, #2390
14252
-	ldrh	r3, [r6, r3]
14253
-	str	r3, [sp, #8]
14254
-	ldrb	r3, [r6, #144]	@ zero_extendqisi2
14774
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
14255
14775
 	cmp	r3, #0
14256
-	ldreq	r3, [sp, #8]
14257
-	moveq	r7, #1
14776
+	ldreq	r3, [sp, #12]
14258
14777
 	movne	r7, #1
14259
-	strne	r7, [sp, #12]
14260
-	moveq	r3, r3, lsr #2
14261
-	streq	r3, [sp, #12]
14262
-.L2417:
14263
-	ldr	r10, .L2455
14264
-	mov	r5, #0
14265
-	mov	r8, r10
14266
-.L2426:
14267
-	mov	fp, #0
14268
-	mov	r6, fp
14269
-.L2418:
14270
-	ldr	r9, .L2455+4
14271
-	add	r3, r9, #2320
14272
-	ldrh	r1, [r3]
14273
-	uxth	r3, fp
14274
-	cmp	r1, r3
14275
-	bls	.L2452
14778
+	moveq	r7, #1
14779
+	strne	r7, [sp, #16]
14780
+	lsreq	r3, r3, #2
14781
+	streq	r3, [sp, #16]
14782
+	b	.L2371
14783
+.L2375:
14784
+	uxth	r3, r10
14276
14785
 	mov	r2, #36
14277
-	ldr	r0, [r10, #-3612]
14786
+	ldr	r0, [r6, #-3608]
14278
14787
 	mul	r1, r2, r3
14788
+	add	r3, fp, r3
14279
14789
 	mov	r2, #0
14280
14790
 	str	r2, [r0, r1]
14281
-	ldr	r2, .L2455+4
14282
-	ldr	r1, [sp, #4]
14283
-	add	r3, r2, r3
14284
-	ldrb	r0, [r3, #2348]	@ zero_extendqisi2
14791
+	ldr	r1, [sp, #8]
14792
+	ldrb	r0, [r3, #2350]	@ zero_extendqisi2
14285
14793
 	bl	V2P_block
14286
-	ldr	r3, [sp]
14287
-	mov	r9, r0
14794
+	ldr	r3, [sp, #4]
14795
+	mov	r8, r0
14288
14796
 	cmp	r3, #0
14289
-	beq	.L2419
14797
+	beq	.L2373
14290
14798
 	bl	IsBlkInVendorPart
14291
14799
 	cmp	r0, #0
14292
-	bne	.L2420
14293
-.L2419:
14294
-	mov	r0, r9
14800
+	bne	.L2374
14801
+.L2373:
14802
+	mov	r0, r8
14295
14803
 	bl	FtlBbmIsBadBlock
14296
14804
 	cmp	r0, #0
14297
-	bne	.L2420
14298
-	ldr	r1, [r8, #-3612]
14805
+	bne	.L2374
14806
+	ldr	r1, [r6, #-3608]
14299
14807
 	mov	r3, #36
14300
-	add	r9, r5, r9, asl #10
14301
-	mla	r1, r3, r6, r1
14302
-	ldr	r3, [r8, #-508]
14808
+	add	r8, r9, r8, lsl #10
14809
+	mla	r1, r3, r5, r1
14810
+	ldr	r3, [r6, #-508]
14303
14811
 	str	r3, [r1, #8]
14304
-	ldr	r3, .L2455+8
14305
-	str	r9, [r1, #4]
14812
+	ldr	r3, .L2404+12
14813
+	str	r8, [r1, #4]
14306
14814
 	ldrh	r3, [r3]
14307
-	mul	r3, r3, r6
14308
-	add	r6, r6, #1
14309
-	uxth	r6, r6
14815
+	mul	r3, r5, r3
14816
+	add	r5, r5, #1
14817
+	uxth	r5, r5
14310
14818
 	add	r0, r3, #3
14311
14819
 	cmp	r3, #0
14312
14820
 	movlt	r3, r0
14313
-	ldr	r0, [r8, #-504]
14821
+	ldr	r0, [r6, #-504]
14314
14822
 	bic	r3, r3, #3
14315
14823
 	add	r3, r0, r3
14316
14824
 	str	r3, [r1, #12]
14317
-.L2420:
14318
-	add	fp, fp, #1
14319
-	b	.L2418
14320
-.L2452:
14321
-	cmp	r6, #0
14322
-	beq	.L2430
14323
-	mov	r2, r7
14324
-	mov	r3, #1
14325
-	ldr	r0, [r10, #-3612]
14326
-	mov	r1, r6
14327
-	mov	fp, #0
14328
-	strb	fp, [r9, #2240]
14329
-	bl	FlashProgPages
14330
-	mov	r2, #36
14331
-	ldrb	r3, [sp, #16]	@ zero_extendqisi2
14332
-	strb	r3, [r9, #2240]
14333
-	ldr	r9, .L2455
14334
-.L2423:
14335
-	uxth	r3, fp
14336
-	cmp	r3, r6
14337
-	bcs	.L2453
14338
-	mul	r3, r2, fp
14339
-	ldr	r1, [r8, #-3612]
14340
-	add	r0, r1, r3
14341
-	ldr	r3, [r1, r3]
14342
-	cmp	r3, #0
14343
-	beq	.L2424
14344
-	ldr	r0, [r0, #4]
14345
-	add	r4, r4, #1
14346
-	str	r2, [sp, #20]
14347
-	ubfx	r0, r0, #10, #16
14348
-	uxth	r4, r4
14349
-	bl	FtlBbmMapBadBlock
14350
-	ldr	r2, [sp, #20]
14351
-.L2424:
14352
-	add	fp, fp, #1
14353
-	b	.L2423
14354
-.L2453:
14355
-	ldr	r3, [sp, #12]
14356
-	add	r5, r5, r3
14357
-	ldr	r3, [sp, #8]
14358
-	uxth	r5, r5
14359
-	cmp	r5, r3
14360
-	bcc	.L2426
14361
-	mov	r5, #0
14362
-	mov	r8, #36
14363
-.L2427:
14364
-	uxth	r3, r5
14365
-	cmp	r3, r6
14366
-	ldr	r3, [sp]
14367
-	bcs	.L2454
14368
-	cmp	r3, #0
14369
-	beq	.L2428
14370
-	mul	r3, r8, r5
14371
-	ldr	r2, [r9, #-3612]
14825
+.L2374:
14826
+	add	r10, r10, #1
14827
+	b	.L2372
14828
+.L2379:
14829
+	mul	r3, fp, r8
14830
+	ldr	r2, [r6, #-3608]
14372
14831
 	add	r1, r2, r3
14373
14832
 	ldr	r3, [r2, r3]
14374
14833
 	cmp	r3, #0
14375
-	bne	.L2428
14834
+	beq	.L2378
14835
+	ldr	r0, [r1, #4]
14836
+	add	r4, r4, #1
14837
+	uxth	r4, r4
14838
+	ubfx	r0, r0, #10, #16
14839
+	bl	FtlBbmMapBadBlock
14840
+.L2378:
14841
+	add	r8, r8, #1
14842
+	b	.L2377
14843
+.L2383:
14844
+	cmp	r3, #0
14845
+	beq	.L2382
14846
+	mul	r3, r9, r8
14847
+	ldr	r2, [r6, #-3608]
14848
+	add	r1, r2, r3
14849
+	ldr	r3, [r2, r3]
14850
+	cmp	r3, #0
14851
+	bne	.L2382
14376
14852
 	ldr	r0, [r1, #4]
14377
14853
 	mov	r1, #1
14378
14854
 	ubfx	r0, r0, #10, #16
14379
14855
 	bl	FtlFreeSysBlkQueueIn
14380
-.L2428:
14381
-	add	r5, r5, #1
14382
-	b	.L2427
14383
-.L2454:
14384
-	adds	r1, r3, #0
14385
-	ldr	r3, [sp, #4]
14386
-	movne	r1, #1
14387
-	cmp	r3, #63
14388
-	orrls	r1, r1, #1
14389
-	cmp	r1, #0
14390
-	beq	.L2430
14391
-	ldr	r0, [r9, #-3612]
14392
-	mov	r1, r7
14393
-	mov	r2, r6
14394
-	bl	FlashEraseBlocks
14395
-.L2430:
14396
-	mov	r0, r4
14397
-.L2406:
14398
-	add	sp, sp, #28
14399
-	@ sp needed
14400
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
14401
-.L2456:
14856
+.L2382:
14857
+	add	r8, r8, #1
14858
+	b	.L2381
14859
+.L2405:
14402
14860
 	.align	2
14403
-.L2455:
14861
+.L2404:
14404
14862
 	.word	.LANCHOR2
14405
14863
 	.word	.LANCHOR0
14406
-	.word	.LANCHOR0+2400
14864
+	.word	.LANCHOR0+2324
14865
+	.word	.LANCHOR0+2402
14407
14866
 	.fnend
14408
14867
 	.size	FtlLowFormatEraseBlock, .-FtlLowFormatEraseBlock
14409
14868
 	.align	2
14410
14869
 	.global	FtlBbmTblFlush
14870
+	.syntax unified
14871
+	.arm
14872
+	.fpu softvfp
14411
14873
 	.type	FtlBbmTblFlush, %function
14412
14874
 FtlBbmTblFlush:
14413
14875
 	.fnstart
14414
-	@ args = 0, pretend = 0, frame = 8
14876
+	@ args = 0, pretend = 0, frame = 0
14415
14877
 	@ frame_needed = 0, uses_anonymous_args = 0
14416
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14878
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
14417
14879
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14418
-	.pad #20
14419
-	sub	sp, sp, #20
14420
-	ldr	r4, .L2475
14421
-	ldr	r5, [r4, #-3616]
14880
+	.pad #12
14881
+	ldr	r4, .L2421
14882
+	ldr	r5, [r4, #-3612]
14422
14883
 	cmp	r5, #0
14423
-	bne	.L2459
14424
-	ldr	r3, [r4, #-500]
14884
+	bne	.L2408
14885
+	ldr	r7, .L2421+4
14886
+	sub	r10, r4, #436
14887
+	ldr	r8, .L2421+8
14425
14888
 	mov	r1, r5
14426
-	ldr	r2, .L2475+4
14427
-	sub	r9, r4, #436
14428
14889
 	ldr	r0, [r4, #-524]
14429
-	str	r3, [r4, #1764]
14430
-	movw	r3, #2398
14431
-	ldrh	r2, [r2, r3]
14432
-	str	r0, [r4, #1760]
14433
-	bl	ftl_memset
14434
-	ldr	r6, .L2475+8
14435
-	sub	r8, r6, #134
14436
-.L2460:
14437
-	ldrh	r3, [r8]
14438
-	ldr	r7, .L2475+4
14439
-	cmp	r5, r3
14440
-	bge	.L2474
14441
-	ldrh	r2, [r9]
14442
-	ldr	r3, [r4, #1760]
14443
-	ldr	r1, [r6, #4]!
14444
-	mul	r0, r2, r5
14445
-	mov	r2, r2, asl #2
14446
-	add	r5, r5, #1
14447
-	add	r0, r3, r0, asl #2
14448
-	bl	ftl_memcpy
14449
-	b	.L2460
14450
-.L2474:
14451
-	ldr	r9, [r4, #1764]
14452
-	mov	r1, #255
14453
-	mov	r2, #16
14454
-	ldr	r5, .L2475+12
14455
-	ldr	r10, .L2475
14456
-	mov	r6, #0
14457
-	mov	r0, r9
14458
-	bl	ftl_memset
14459
-	ldr	r3, .L2475+16
14460
-	mov	r8, r5
14461
-	strh	r3, [r9]	@ movhi
14462
-	ldr	r3, [r7, #2460]
14463
-	str	r3, [r9, #4]
14464
-	movw	r3, #2452
14465
-	ldrh	r3, [r7, r3]
14466
-	strh	r3, [r9, #2]	@ movhi
14467
-	ldrh	r3, [r5, #4]
14468
-	strh	r3, [r9, #8]	@ movhi
14469
-	ldrh	r3, [r5, #6]
14470
-	strh	r3, [r9, #10]	@ movhi
14471
-	ldr	r3, [r7, #2316]
14472
-	strh	r3, [r9, #12]	@ movhi
14473
-	str	r6, [sp, #12]
14474
-.L2462:
14475
-	ldr	r3, [r4, #-524]
14476
-	mov	fp, #0
14477
-	ldrh	r1, [r5]
14478
-	ldrh	r2, [r5, #2]
14479
-	str	r3, [r4, #1760]
14480
14890
 	ldr	r3, [r4, #-500]
14481
-	str	fp, [r4, #1752]
14891
+	mov	r6, r7
14892
+	sub	r7, r7, #2400
14893
+	ldrh	r2, [r6], #80
14894
+	mov	r9, r7
14895
+	str	r0, [r4, #1768]
14896
+	str	r3, [r4, #1772]
14897
+	bl	ftl_memset
14898
+.L2409:
14899
+	ldrh	r3, [r8]
14900
+	cmp	r5, r3
14901
+	blt	.L2410
14902
+	ldr	r6, [r4, #1772]
14903
+	mov	r2, #16
14904
+	mov	r1, #255
14905
+	ldr	r5, .L2421+12
14906
+	ldr	fp, .L2421+16
14907
+	mov	r0, r6
14908
+	bl	ftl_memset
14909
+	ldr	r3, .L2421+20
14910
+	strh	r3, [r6]	@ movhi
14911
+	ldr	r3, [r7, #2464]
14912
+	str	r3, [r6, #4]
14913
+	movw	r3, #2456
14914
+	ldrh	r3, [r7, r3]
14915
+	strh	r3, [r6, #2]	@ movhi
14916
+	ldrh	r3, [r5, #4]
14917
+	strh	r3, [r6, #8]	@ movhi
14918
+	ldrh	r3, [r5, #6]
14919
+	strh	r3, [r6, #10]	@ movhi
14920
+	ldr	r3, [r7, #2320]
14921
+	mov	r7, #0
14922
+	mov	r8, r7
14923
+	strh	r3, [r6, #12]	@ movhi
14924
+.L2411:
14925
+	ldr	r3, [r4, #-524]
14926
+	mov	r10, #0
14927
+	ldrh	r2, [r5, #2]
14928
+	ldrh	r1, [r5]
14929
+	str	r3, [r4, #1768]
14930
+	ldr	r3, [r4, #-500]
14931
+	str	r10, [r4, #1760]
14932
+	str	r3, [r4, #1772]
14933
+	orr	r3, r2, r1, lsl #10
14934
+	ldrh	r0, [r6, #10]
14482
14935
 	str	r3, [r4, #1764]
14483
-	orr	r3, r2, r1, asl #10
14484
-	ldrh	r0, [r9, #10]
14485
-	str	r3, [r4, #1756]
14486
14936
 	ldrh	r3, [r5, #4]
14487
14937
 	str	r0, [sp]
14488
-	ldr	r0, .L2475+20
14938
+	mov	r0, fp
14489
14939
 	bl	printk
14490
-	ldr	r3, .L2475+24
14940
+	ldr	r3, .L2421+24
14491
14941
 	ldrh	r2, [r5, #2]
14492
14942
 	ldrh	r3, [r3]
14493
14943
 	sub	r3, r3, #1
14494
14944
 	cmp	r2, r3
14495
-	blt	.L2463
14496
-	ldr	r3, [r7, #2460]
14497
-	mov	r1, #1
14498
-	ldrh	r2, [r8]
14945
+	blt	.L2412
14946
+	ldr	r3, [r9, #2464]
14947
+	ldrh	r2, [r5]
14948
+	ldr	r0, [r4, #-3608]
14499
14949
 	add	r3, r3, #1
14500
-	ldr	r0, [r10, #-3612]
14501
-	str	r3, [r7, #2460]
14502
-	str	r3, [r9, #4]
14503
-	ldrh	r3, [r8, #4]
14504
-	strh	r2, [r9, #8]	@ movhi
14505
-	strh	r2, [r8, #4]	@ movhi
14506
-	mov	r2, r1
14507
-	strh	r3, [r8]	@ movhi
14508
-	mov	r3, r3, asl #10
14509
-	str	r3, [r10, #1756]
14950
+	strh	r10, [r5, #2]	@ movhi
14951
+	str	r3, [r9, #2464]
14952
+	str	r3, [r6, #4]
14953
+	ldrh	r3, [r5, #4]
14954
+	strh	r2, [r6, #8]	@ movhi
14955
+	strh	r2, [r5, #4]	@ movhi
14956
+	mov	r2, #1
14957
+	strh	r3, [r5]	@ movhi
14958
+	mov	r1, r2
14959
+	lsl	r3, r3, #10
14960
+	str	r3, [r4, #1764]
14510
14961
 	str	r3, [r0, #4]
14511
-	strh	fp, [r8, #2]	@ movhi
14512
14962
 	bl	FlashEraseBlocks
14513
-.L2463:
14514
-	mov	r1, #1
14515
-	ldr	r0, .L2475+28
14516
-	mov	r3, r1
14517
-	mov	r2, r1
14963
+.L2412:
14964
+	mov	r3, #1
14965
+	ldr	r0, .L2421+28
14966
+	mov	r2, r3
14967
+	mov	r1, r3
14518
14968
 	bl	FlashProgPages
14519
14969
 	ldrh	r3, [r5, #2]
14520
-	ldr	fp, .L2475
14521
14970
 	add	r3, r3, #1
14522
14971
 	strh	r3, [r5, #2]	@ movhi
14523
-	ldr	r3, [r4, #1752]
14972
+	ldr	r3, [r4, #1760]
14524
14973
 	cmn	r3, #1
14525
-	bne	.L2464
14526
-	add	r6, r6, #1
14527
-	ldr	r0, .L2475+32
14528
-	ldr	r1, [r10, #1756]
14529
-	uxth	r6, r6
14974
+	bne	.L2413
14975
+	add	r7, r7, #1
14976
+	ldr	r1, [r4, #1764]
14977
+	uxth	r7, r7
14978
+	ldr	r0, .L2421+32
14530
14979
 	bl	printk
14531
-	cmp	r6, #3
14532
-	bls	.L2462
14533
-	ldr	r0, .L2475+36
14534
-	mov	r2, r6
14535
-	ldr	r1, [fp, #1756]
14980
+	cmp	r7, #3
14981
+	bls	.L2411
14982
+	mov	r2, r7
14983
+	ldr	r1, [r4, #1764]
14984
+	ldr	r0, .L2421+36
14536
14985
 	bl	printk
14537
14986
 	mov	r3, #1
14538
-	str	r3, [fp, #-3616]
14539
-	b	.L2459
14540
-.L2464:
14541
-	ldr	r2, [sp, #12]
14542
-	add	r2, r2, #1
14543
-	str	r2, [sp, #12]
14544
-	cmp	r2, #1
14545
-	beq	.L2462
14546
-	cmp	r3, #256
14547
-	beq	.L2462
14548
-.L2459:
14987
+	str	r3, [r4, #-3612]
14988
+.L2408:
14549
14989
 	mov	r0, #0
14550
-	add	sp, sp, #20
14990
+	add	sp, sp, #12
14551
14991
 	@ sp needed
14552
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
14553
-.L2476:
14992
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
14993
+.L2410:
14994
+	ldrh	r2, [r10]
14995
+	ldr	r3, [r4, #1768]
14996
+	ldr	r1, [r6, #4]!
14997
+	mul	r0, r5, r2
14998
+	lsl	r2, r2, #2
14999
+	add	r5, r5, #1
15000
+	add	r0, r3, r0, lsl #2
15001
+	bl	ftl_memcpy
15002
+	b	.L2409
15003
+.L2416:
15004
+	mov	r8, #1
15005
+	b	.L2411
15006
+.L2413:
15007
+	add	r8, r8, #1
15008
+	cmp	r8, #1
15009
+	ble	.L2416
15010
+	cmp	r3, #256
15011
+	bne	.L2408
15012
+	b	.L2411
15013
+.L2422:
14554
15014
 	.align	2
14555
-.L2475:
15015
+.L2421:
14556
15016
 	.word	.LANCHOR2
14557
-	.word	.LANCHOR0
14558
-	.word	.LANCHOR0+2476
14559
-	.word	.LANCHOR0+2452
14560
-	.word	-3887
15017
+	.word	.LANCHOR0+2400
15018
+	.word	.LANCHOR0+2346
15019
+	.word	.LANCHOR0+2456
14561
15020
 	.word	.LC126
14562
-	.word	.LANCHOR0+2390
14563
-	.word	.LANCHOR2+1752
15021
+	.word	-3887
15022
+	.word	.LANCHOR0+2392
15023
+	.word	.LANCHOR2+1760
14564
15024
 	.word	.LC127
14565
15025
 	.word	.LC128
14566
15026
 	.fnend
14567
15027
 	.size	FtlBbmTblFlush, .-FtlBbmTblFlush
14568
15028
 	.align	2
14569
15029
 	.global	allocate_data_superblock
15030
+	.syntax unified
15031
+	.arm
15032
+	.fpu softvfp
14570
15033
 	.type	allocate_data_superblock, %function
14571
15034
 allocate_data_superblock:
14572
15035
 	.fnstart
14573
-	@ args = 0, pretend = 0, frame = 16
15036
+	@ args = 0, pretend = 0, frame = 24
14574
15037
 	@ frame_needed = 0, uses_anonymous_args = 0
14575
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
15038
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
14576
15039
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14577
-	.pad #20
14578
-	sub	sp, sp, #20
14579
-	ldr	r4, .L2532
14580
-	ldr	r3, [r4, #-3616]
15040
+	.pad #28
15041
+	sub	sp, sp, #28
15042
+	ldr	r4, .L2473
15043
+	ldr	r3, [r4, #-3612]
14581
15044
 	cmp	r3, #0
14582
-	bne	.L2478
14583
-	mov	r5, r0
14584
-	mov	r8, r4
14585
-.L2479:
14586
-	ldr	r3, .L2532+4
14587
-	ldr	r10, .L2532+8
14588
-	cmp	r5, r3
14589
-	ldrb	r2, [r5, #8]	@ zero_extendqisi2
14590
-	bne	.L2480
14591
-	ldrh	r3, [r5, #-100]
14592
-	ldr	ip, [r8, #-2708]
14593
-	mov	r0, r3, lsr #1
14594
-	mul	lr, ip, r3
14595
-	add	r1, r0, #1
14596
-	add	r1, r1, lr, lsr #2
14597
-	ldr	lr, [r10, #2244]
14598
-	cmp	lr, #0
15045
+	bne	.L2424
15046
+	sub	r9, r4, #3520
15047
+	mov	r7, r0
15048
+	sub	r3, r9, #8
15049
+	str	r3, [sp, #12]
15050
+.L2425:
15051
+	ldr	r3, .L2473+4
15052
+	ldr	r8, .L2473+8
15053
+	ldrb	r2, [r7, #8]	@ zero_extendqisi2
15054
+	cmp	r7, r3
15055
+	bne	.L2426
15056
+	ldrh	r0, [r9, #-4]
15057
+	ldr	lr, [r4, #-2708]
15058
+	lsr	ip, r0, #1
15059
+	mul	r5, lr, r0
15060
+	add	r1, ip, #1
15061
+	add	r1, r1, r5, lsr #2
15062
+	ldr	r5, [r8, #2248]
14599
15063
 	uxth	r1, r1
14600
-	beq	.L2481
14601
-	ldr	lr, [r8, #-3308]
14602
-	cmp	lr, #39
14603
-	bhi	.L2481
14604
-	cmp	lr, #2
14605
-	bls	.L2506
14606
-	cmp	ip, #0
14607
-	movne	r3, #0
14608
-	andeq	r3, r3, #1
14609
-	cmp	r3, #0
14610
-	moveq	r1, r0
14611
-	beq	.L2481
14612
-	b	.L2506
14613
-.L2480:
15064
+	cmp	r5, #0
15065
+	beq	.L2427
15066
+	ldr	r5, [r4, #-3308]
15067
+	cmp	r5, #39
15068
+	bhi	.L2427
15069
+	cmp	r5, #2
15070
+	bls	.L2453
15071
+	cmp	lr, #0
15072
+	movne	r0, #0
15073
+	andeq	r0, r0, #1
15074
+	cmp	r0, #0
15075
+	moveq	r1, ip
15076
+	beq	.L2427
15077
+.L2453:
15078
+	mov	r1, #0
15079
+	b	.L2428
15080
+.L2426:
14614
15081
 	cmp	r2, #1
14615
-	bne	.L2506
14616
-	ldr	r1, .L2532+12
15082
+	bne	.L2453
15083
+	ldr	r1, .L2473+12
14617
15084
 	ldrh	r1, [r1]
14618
15085
 	cmp	r1, #1
14619
-	beq	.L2506
14620
-	ldrb	r1, [r10, #144]	@ zero_extendqisi2
15086
+	beq	.L2453
15087
+	ldrb	r1, [r8, #152]	@ zero_extendqisi2
14621
15088
 	cmp	r1, #0
14622
-	bne	.L2506
14623
-	ldr	r0, [r10, #2244]
14624
-	ldrh	r3, [r3, #-100]
14625
-	cmp	r0, #0
14626
-	mov	r1, r3, lsr #3
14627
-	beq	.L2481
14628
-	ldr	r0, [r8, #-3308]
14629
-	cmp	r0, #1
14630
-	rsbls	r3, r3, r3, asl #3
14631
-	ubfxls	r1, r3, #3, #16
14632
-.L2481:
15089
+	bne	.L2453
15090
+	ldr	ip, [r8, #2248]
15091
+	ldrh	r0, [r9, #-4]
15092
+	cmp	ip, #0
15093
+	lsr	r1, r0, #3
15094
+	beq	.L2427
15095
+	ldr	ip, [r4, #-3308]
15096
+	cmp	ip, #1
15097
+	rsbls	r0, r0, r0, lsl #3
15098
+	ubfxls	r1, r0, #3, #16
15099
+.L2427:
14633
15100
 	cmp	r1, #0
14634
15101
 	subne	r1, r1, #1
14635
15102
 	uxthne	r1, r1
14636
-	b	.L2482
14637
-.L2506:
14638
-	mov	r1, #0
14639
-.L2482:
14640
-	ldr	r0, .L2532+16
15103
+.L2428:
15104
+	ldr	r0, [sp, #12]
14641
15105
 	bl	List_pop_index_node
14642
-	ldr	r2, .L2532+20
14643
-	ldrh	r3, [r2]
14644
-	sub	r3, r3, #1
14645
-	strh	r3, [r2]	@ movhi
14646
-	ldr	r3, .L2532+24
14647
-	ldrh	r3, [r3]
14648
-	uxth	r9, r0
14649
-	cmp	r3, r9
14650
-	bls	.L2479
14651
-	ldr	r3, [r8, #-3544]
14652
-	mov	r7, r9, asl #1
14653
-	ldrh	r6, [r3, r7]
14654
-	cmp	r6, #0
14655
-	bne	.L2479
14656
-	strh	r9, [r5]	@ movhi
14657
-	mov	r0, r5
14658
-	bl	make_superblock
14659
-	ldrb	r3, [r5, #7]	@ zero_extendqisi2
14660
-	cmp	r3, #0
14661
-	beq	.L2484
14662
-	ldr	r2, .L2532+28
14663
-	add	ip, r5, #14
14664
-	ldr	r0, [r8, #-3612]
14665
-	ldrh	lr, [r2]
14666
-	mov	r2, #36
14667
-	mov	r3, r0
14668
-	mla	r1, r2, lr, r0
14669
-	mov	lr, r6
14670
-	str	r1, [sp]
14671
-	b	.L2485
14672
-.L2484:
14673
-	ldr	r3, [r8, #-3544]
14674
-	b	.L2527
14675
-.L2485:
14676
-	ldr	r1, [sp]
14677
-	cmp	r3, r1
14678
-	beq	.L2529
14679
-	str	lr, [r3, #8]
14680
-	movw	fp, #65535
14681
-	str	lr, [r3, #12]
14682
-	add	r3, r3, #36
14683
-	ldrh	r1, [ip, #2]!
14684
-	cmp	r1, fp
14685
-	movne	r1, r1, asl #10
14686
-	mlane	fp, r2, r6, r0
14687
-	addne	r6, r6, #1
14688
-	uxthne	r6, r6
14689
-	strne	r1, [fp, #4]
14690
-	b	.L2485
14691
-.L2529:
14692
-	ldr	r3, .L2532+32
14693
-	ldr	r2, [r10, #2244]
14694
-	rsb	r3, r3, r5
14695
-	clz	r3, r3
14696
-	cmp	r2, #0
14697
-	mov	r3, r3, lsr #5
14698
-	moveq	r3, #0
14699
-	cmp	r3, #0
14700
-	beq	.L2488
14701
-	ldr	r3, [r8, #-3608]
14702
-	ldrh	r3, [r3, r7]
14703
-	cmp	r3, #40
14704
-	movhi	r3, #0
14705
-	strhib	r3, [r8, #-3516]
14706
-.L2488:
14707
-	ldrb	r3, [r5, #8]	@ zero_extendqisi2
14708
-	ldr	r2, [r4, #-3608]
14709
-	cmp	r3, #0
14710
-	ldr	fp, .L2532+36
14711
-	ldrh	r3, [r2, r7]
14712
-	bne	.L2489
14713
-	cmp	r3, #0
14714
-	mov	r0, r9
14715
-	ldrneh	r1, [fp]
14716
-	moveq	r3, #2
14717
-	addne	r3, r3, r1
14718
-	mov	r1, #0
14719
-	uxthne	r3, r3
14720
-	strh	r3, [r2, r7]	@ movhi
14721
-	ldr	r3, [r4, #-3324]
14722
-	add	r3, r3, #1
14723
-	str	r3, [r4, #-3324]
14724
-	bl	ftl_set_blk_mode
14725
-	b	.L2491
14726
-.L2489:
14727
-	add	r3, r3, #1
14728
-	strh	r3, [r2, r7]	@ movhi
14729
-	ldr	r2, [r4, #-3368]
14730
-	mov	r1, r9, lsr #5
14731
-	ldr	r3, [r4, #-3320]
14732
-	mov	r0, #1
14733
-	add	r3, r3, #1
14734
-	str	r3, [r4, #-3320]
14735
-	ldr	ip, [r2, r1, asl #2]
14736
-	and	r3, r9, #31
14737
-	orr	r3, ip, r0, asl r3
14738
-	str	r3, [r2, r1, asl #2]
14739
-.L2491:
14740
-	ldr	r3, [r4, #-3608]
14741
-	ldr	r2, [r4, #-3312]
14742
-	ldr	r0, [r4, #-3324]
14743
-	ldrh	r3, [r3, r7]
14744
-	cmp	r3, r2
14745
-	ldrh	r2, [fp]
14746
-	strhi	r3, [r8, #-3312]
14747
-	ldr	r3, [r4, #-3320]
14748
-	mla	r0, r0, r2, r3
14749
-	ldr	r3, .L2532+24
14750
-	ldrh	r1, [r3]
14751
-	bl	__aeabi_uidiv
14752
-	ldr	r2, [r4, #-480]
14753
-	ldr	r1, [r4, #-3612]
14754
-	ldr	r3, [r2, #16]
14755
-	add	r3, r3, #1
14756
-	str	r3, [r2, #16]
14757
-	mov	r3, #36
14758
-	add	r2, r1, #4
14759
-	mla	r3, r3, r6, r1
14760
-	add	r3, r3, #40
14761
-	str	r0, [r4, #-3316]
14762
-.L2493:
14763
-	add	r2, r2, #36
15106
+	ldrh	r2, [r9, #-4]
15107
+	uxth	r3, r0
15108
+	ldr	r10, .L2473+16
15109
+	str	r3, [sp, #4]
15110
+	sub	r2, r2, #1
15111
+	strh	r2, [r9, #-4]	@ movhi
15112
+	ldrh	r2, [r10]
14764
15113
 	cmp	r2, r3
14765
-	ldrne	r1, [r2, #-36]
14766
-	bicne	r1, r1, #1020
14767
-	bicne	r1, r1, #3
14768
-	strne	r1, [r2, #-36]
14769
-	bne	.L2493
14770
-.L2530:
14771
-	ldrb	r3, [r10, #144]	@ zero_extendqisi2
14772
-	cmp	r3, #0
14773
-	beq	.L2495
14774
-	ldrb	r3, [r5, #8]	@ zero_extendqisi2
15114
+	bls	.L2425
15115
+	ldr	r2, [r4, #-3540]
15116
+	lsl	r5, r3, #1
15117
+	ldrh	r6, [r2, r5]
15118
+	cmp	r6, #0
15119
+	bne	.L2425
15120
+	ldrh	r3, [sp, #4]
15121
+	mov	r0, r7
15122
+	strh	r3, [r7]	@ movhi
15123
+	bl	make_superblock
15124
+	ldrb	r2, [r7, #7]	@ zero_extendqisi2
15125
+	cmp	r2, #0
15126
+	beq	.L2470
15127
+	ldr	r0, [r4, #-3608]
15128
+	add	r3, r7, #16
15129
+	ldrh	ip, [r10, #-8]
15130
+	mov	r1, #36
15131
+	str	r3, [sp, #8]
15132
+	add	fp, r7, #16
15133
+	mov	r2, r0
15134
+	str	r1, [sp, #16]
15135
+	mla	r3, r1, ip, r0
15136
+	mov	ip, r6
15137
+.L2431:
15138
+	cmp	r3, r2
15139
+	bne	.L2433
15140
+	ldr	r2, [r8, #2248]
15141
+	adds	r2, r2, #0
15142
+	movne	r2, #1
15143
+	cmp	r7, r9
15144
+	movne	r2, #0
15145
+	cmp	r2, #0
15146
+	beq	.L2434
15147
+	ldr	r2, [r4, #-3604]
15148
+	ldrh	r2, [r2, r5]
15149
+	cmp	r2, #40
15150
+	movhi	r2, #0
15151
+	strbhi	r2, [r4, #-3512]
15152
+.L2434:
15153
+	ldrb	r2, [r7, #8]	@ zero_extendqisi2
15154
+	ldr	r1, [r4, #-3604]
15155
+	ldr	fp, .L2473+20
15156
+	cmp	r2, #0
15157
+	ldrh	r2, [r1, r5]
15158
+	bne	.L2435
15159
+	cmp	r2, #0
15160
+	ldrhne	r0, [fp]
15161
+	moveq	r2, #2
15162
+	addne	r2, r2, r0
15163
+	ldr	r0, [sp, #4]
15164
+	strh	r2, [r1, r5]	@ movhi
15165
+	mov	r1, #0
15166
+	ldr	r2, [r4, #-3324]
15167
+	add	r2, r2, #1
15168
+	str	r2, [r4, #-3324]
15169
+	bl	ftl_set_blk_mode
15170
+.L2438:
15171
+	ldr	r2, [r4, #-3604]
15172
+	ldr	r1, [r4, #-3312]
15173
+	ldr	ip, [r4, #-3324]
15174
+	ldrh	r2, [r2, r5]
15175
+	ldrh	r0, [fp]
15176
+	cmp	r2, r1
15177
+	ldrh	r1, [r10]
15178
+	strhi	r2, [r4, #-3312]
15179
+	ldr	r2, [r4, #-3320]
15180
+	mla	r0, ip, r0, r2
15181
+	bl	__aeabi_uidiv
15182
+	ldr	r1, [r4, #-480]
15183
+	str	r0, [r4, #-3316]
15184
+	ldr	r0, [r4, #-3608]
15185
+	ldr	r2, [r1, #16]
15186
+	ldr	ip, .L2473+24
15187
+	add	r2, r2, #1
15188
+	str	r2, [r1, #16]
15189
+	mov	r1, #36
15190
+	mla	r1, r1, r6, r0
15191
+	add	r2, r0, #4
15192
+	add	r1, r1, #40
15193
+.L2440:
15194
+	add	r2, r2, #36
15195
+	cmp	r1, r2
15196
+	bne	.L2441
15197
+	ldrb	r2, [r8, #152]	@ zero_extendqisi2
15198
+	cmp	r2, #0
15199
+	beq	.L2442
15200
+	ldrb	r2, [r7, #8]	@ zero_extendqisi2
15201
+	ldr	r0, [r4, #-3608]
15202
+	cmp	r2, #1
14775
15203
 	mov	r2, r6
14776
-	ldr	r0, [r4, #-3612]
14777
-	cmp	r3, #1
14778
15204
 	moveq	r1, #0
14779
15205
 	movne	r1, #1
14780
15206
 	bl	FlashEraseBlocks
14781
-.L2495:
14782
-	ldrb	r1, [r5, #8]	@ zero_extendqisi2
15207
+.L2442:
15208
+	ldrb	r1, [r7, #8]	@ zero_extendqisi2
14783
15209
 	mov	r2, r6
14784
-	ldr	r0, [r4, #-3612]
14785
-	mov	fp, #0
15210
+	ldr	r0, [r4, #-3608]
15211
+	mov	r10, #0
14786
15212
 	bl	FlashEraseBlocks
14787
-	add	r1, r5, #16
14788
-	mov	r2, fp
14789
-	mov	ip, #36
14790
-.L2497:
14791
-	uxth	r3, fp
14792
-	cmp	r3, r6
14793
-	bcs	.L2531
14794
-	mul	r3, ip, fp
14795
-	ldr	lr, [r4, #-3612]
14796
-	add	r0, lr, r3
14797
-	ldr	r3, [lr, r3]
14798
-	cmn	r3, #1
14799
-	bne	.L2498
14800
-	ldr	r0, [r0, #4]
14801
-	add	r2, r2, #1
14802
-	stmib	sp, {r1, r3, ip}
14803
-	ubfx	r0, r0, #10, #16
14804
-	str	r2, [sp]
14805
-	bl	FtlBbmMapBadBlock
14806
-	ldmib	sp, {r1, r3}
14807
-	ldr	ip, [sp, #12]
14808
-	ldr	r2, [sp]
14809
-	strh	r3, [r1]	@ movhi
14810
-	ldrb	r3, [r5, #7]	@ zero_extendqisi2
14811
-	sub	r3, r3, #1
14812
-	strb	r3, [r5, #7]
14813
-.L2498:
14814
-	add	fp, fp, #1
14815
-	add	r1, r1, #2
14816
-	b	.L2497
14817
-.L2531:
14818
-	cmp	r2, #0
14819
-	beq	.L2500
14820
-	mov	r0, r9
15213
+	mov	fp, r10
15214
+	mov	r1, #36
15215
+.L2444:
15216
+	uxth	r2, r10
15217
+	cmp	r6, r2
15218
+	bhi	.L2446
15219
+	cmp	fp, #0
15220
+	ble	.L2447
15221
+	ldr	r0, [sp, #4]
14821
15222
 	bl	update_multiplier_value
14822
15223
 	bl	FtlBbmTblFlush
14823
-.L2500:
14824
-	ldrb	r3, [r5, #7]	@ zero_extendqisi2
14825
-	cmp	r3, #0
14826
-	bne	.L2501
14827
-	ldr	r3, [r4, #-3544]
14828
-.L2527:
14829
-	mvn	r2, #0
14830
-	strh	r2, [r3, r7]	@ movhi
14831
-	b	.L2479
14832
-.L2501:
14833
-	movw	r2, #2388
14834
-	ldrh	r2, [r10, r2]
14835
-	strh	r9, [r5]	@ movhi
14836
-	smulbb	r3, r2, r3
14837
-	mov	r2, #0
14838
-	strh	r2, [r5, #2]	@ movhi
14839
-	strb	r2, [r5, #6]
14840
-	ldr	r2, [r4, #-3332]
14841
-	ldr	r1, [r4, #-3544]
14842
-	uxth	r3, r3
14843
-	strh	r3, [r5, #4]	@ movhi
14844
-	str	r2, [r5, #12]
15224
+.L2447:
15225
+	ldrb	r1, [r7, #7]	@ zero_extendqisi2
15226
+	cmp	r1, #0
15227
+	bne	.L2448
15228
+.L2470:
15229
+	ldr	r2, [r4, #-3540]
15230
+	mvn	r1, #0
15231
+	strh	r1, [r2, r5]	@ movhi
15232
+	b	.L2425
15233
+.L2433:
15234
+	str	ip, [r2, #8]
15235
+	movw	lr, #65535
15236
+	str	ip, [r2, #12]
15237
+	add	r2, r2, #36
15238
+	ldrh	r1, [fp], #2
15239
+	cmp	r1, lr
15240
+	ldrne	lr, [sp, #16]
15241
+	lslne	r1, r1, #10
15242
+	mlane	lr, lr, r6, r0
15243
+	addne	r6, r6, #1
15244
+	uxthne	r6, r6
15245
+	strne	r1, [lr, #4]
15246
+	b	.L2431
15247
+.L2435:
14845
15248
 	add	r2, r2, #1
14846
-	str	r2, [r4, #-3332]
14847
-	ldrh	r2, [r5]
14848
-	mov	r2, r2, asl #1
14849
-	strh	r3, [r1, r2]	@ movhi
14850
-.L2478:
15249
+	ldr	r0, [sp, #4]
15250
+	strh	r2, [r1, r5]	@ movhi
15251
+	ldr	r2, [r4, #-3320]
15252
+	add	r2, r2, #1
15253
+	str	r2, [r4, #-3320]
15254
+	bl	ftl_set_blk_mode.part.9
15255
+	b	.L2438
15256
+.L2441:
15257
+	ldr	r0, [r2, #-36]
15258
+	and	r0, r0, ip
15259
+	str	r0, [r2, #-36]
15260
+	b	.L2440
15261
+.L2446:
15262
+	mul	r2, r1, r10
15263
+	ldr	r0, [r4, #-3608]
15264
+	add	ip, r0, r2
15265
+	ldr	r2, [r0, r2]
15266
+	cmn	r2, #1
15267
+	bne	.L2445
15268
+	ldr	r0, [ip, #4]
15269
+	add	fp, fp, #1
15270
+	str	r1, [sp, #20]
15271
+	str	r2, [sp, #16]
15272
+	ubfx	r0, r0, #10, #16
15273
+	bl	FtlBbmMapBadBlock
15274
+	ldr	r2, [sp, #16]
15275
+	ldr	r3, [sp, #8]
15276
+	ldr	r1, [sp, #20]
15277
+	strh	r2, [r3]	@ movhi
15278
+	ldrb	r2, [r7, #7]	@ zero_extendqisi2
15279
+	sub	r2, r2, #1
15280
+	strb	r2, [r7, #7]
15281
+.L2445:
15282
+	ldr	r3, [sp, #8]
15283
+	add	r10, r10, #1
15284
+	add	r3, r3, #2
15285
+	str	r3, [sp, #8]
15286
+	b	.L2444
15287
+.L2448:
15288
+	movw	r2, #2390
15289
+	ldrh	r3, [sp, #4]
15290
+	ldrh	r2, [r8, r2]
15291
+	strh	r3, [r7]	@ movhi
15292
+	smulbb	r2, r2, r1
15293
+	mov	r1, #0
15294
+	strh	r1, [r7, #2]	@ movhi
15295
+	strb	r1, [r7, #6]
15296
+	ldr	r1, [r4, #-3332]
15297
+	uxth	r2, r2
15298
+	strh	r2, [r7, #4]	@ movhi
15299
+	str	r1, [r7, #12]
15300
+	add	r1, r1, #1
15301
+	str	r1, [r4, #-3332]
15302
+	ldrh	r3, [r7]
15303
+	ldr	r1, [r4, #-3540]
15304
+	lsl	r3, r3, #1
15305
+	strh	r2, [r1, r3]	@ movhi
15306
+.L2424:
14851
15307
 	mov	r0, #0
14852
-	add	sp, sp, #20
15308
+	add	sp, sp, #28
14853
15309
 	@ sp needed
14854
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
14855
-.L2533:
15310
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
15311
+.L2474:
14856
15312
 	.align	2
14857
-.L2532:
15313
+.L2473:
14858
15314
 	.word	.LANCHOR2
14859
-	.word	.LANCHOR2-3428
15315
+	.word	.LANCHOR2-3424
14860
15316
 	.word	.LANCHOR0
14861
-	.word	.LANCHOR0+2340
14862
-	.word	.LANCHOR2-3532
14863
-	.word	.LANCHOR2-3528
14864
-	.word	.LANCHOR0+2328
14865
-	.word	.LANCHOR0+2320
14866
-	.word	.LANCHOR2-3524
14867
-	.word	.LANCHOR0+2380
15317
+	.word	.LANCHOR0+2344
15318
+	.word	.LANCHOR0+2332
15319
+	.word	.LANCHOR0+2382
15320
+	.word	-1024
14868
15321
 	.fnend
14869
15322
 	.size	allocate_data_superblock, .-allocate_data_superblock
14870
15323
 	.align	2
14871
15324
 	.global	FtlGcFreeBadSuperBlk
15325
+	.syntax unified
15326
+	.arm
15327
+	.fpu softvfp
14872
15328
 	.type	FtlGcFreeBadSuperBlk, %function
14873
15329
 FtlGcFreeBadSuperBlk:
14874
15330
 	.fnstart
14875
15331
 	@ args = 0, pretend = 0, frame = 8
14876
15332
 	@ frame_needed = 0, uses_anonymous_args = 0
14877
-	ldr	r3, .L2548
14878
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
15333
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
14879
15334
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14880
15335
 	.pad #12
14881
-	ldrh	r2, [r3, #-2]
14882
-	cmp	r2, #0
14883
-	beq	.L2536
14884
-	sub	r10, r3, #2
14885
-	mov	r7, r0
14886
-	mov	r9, #0
14887
-	mov	r5, r3
14888
-	mov	r8, r10
14889
-.L2535:
14890
-	ldr	r3, .L2548+4
14891
-	add	r2, r3, #2320
14892
-	ldrh	r1, [r2]
14893
-	uxth	r2, r9
14894
-	cmp	r1, r2
14895
-	bls	.L2545
14896
-	add	r3, r3, r2
14897
-	mov	r1, r7
14898
-	mov	fp, #0
14899
-	ldrb	r0, [r3, #2348]	@ zero_extendqisi2
14900
-	bl	V2P_block
14901
-	mov	r6, r0
14902
-.L2537:
14903
-	ldrh	r3, [r10]
14904
-	uxth	r4, fp
14905
-	cmp	r3, r4
14906
-	bls	.L2546
14907
-	mov	r3, r4, asl #1
14908
-	add	ip, r5, r3
14909
-	ldrh	r3, [r5, r3]
14910
-	cmp	r3, r6
14911
-	bne	.L2538
14912
-	mov	r1, r6
14913
-	ldr	r0, .L2548+8
14914
-	str	ip, [sp, #4]
14915
-	bl	printk
14916
-	mov	r0, r6
14917
-	bl	FtlBbmMapBadBlock
14918
-	bl	FtlBbmTblFlush
14919
-	ldrh	r2, [r10]
14920
-	ldr	ip, [sp, #4]
14921
-	mov	r3, ip
14922
-.L2539:
14923
-	cmp	r4, r2
14924
-	ldrcch	r1, [r3, #2]
14925
-	addcc	r4, r4, #1
14926
-	uxthcc	r4, r4
14927
-	strcch	r1, [r3], #2	@ movhi
14928
-	bcc	.L2539
14929
-.L2547:
14930
-	sub	r2, r2, #1
14931
-	strh	r2, [r8]	@ movhi
14932
-.L2538:
14933
-	add	fp, fp, #1
14934
-	b	.L2537
14935
-.L2546:
14936
-	add	r9, r9, #1
14937
-	b	.L2535
14938
-.L2545:
15336
+	ldr	r4, .L2488
15337
+	ldrh	r3, [r4, #-2]
15338
+	cmp	r3, #0
15339
+	beq	.L2476
15340
+	ldr	r9, .L2488+4
15341
+	mov	r6, #0
15342
+	ldr	r8, .L2488+8
15343
+	ldr	r10, .L2488+12
15344
+	str	r0, [sp]
15345
+.L2477:
15346
+	ldrh	r2, [r8]
15347
+	uxth	r3, r6
15348
+	cmp	r2, r3
15349
+	bhi	.L2483
14939
15350
 	bl	FtlGcReFreshBadBlk
14940
-.L2536:
15351
+.L2476:
14941
15352
 	mov	r0, #0
14942
15353
 	add	sp, sp, #12
14943
15354
 	@ sp needed
14944
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
14945
-.L2549:
15355
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
15356
+.L2483:
15357
+	uxtah	r3, r9, r6
15358
+	ldr	r1, [sp]
15359
+	mov	fp, #0
15360
+	ldrb	r0, [r3, #2350]	@ zero_extendqisi2
15361
+	bl	V2P_block
15362
+	mov	r7, r0
15363
+.L2478:
15364
+	ldrh	r3, [r4, #-2]
15365
+	uxth	r5, fp
15366
+	cmp	r3, r5
15367
+	addls	r6, r6, #1
15368
+	bls	.L2477
15369
+.L2482:
15370
+	uxth	r3, fp
15371
+	lsl	r1, r3, #1
15372
+	ldrh	r1, [r4, r1]
15373
+	cmp	r1, r7
15374
+	bne	.L2479
15375
+	mov	r1, r7
15376
+	mov	r0, r10
15377
+	str	r3, [sp, #4]
15378
+	bl	printk
15379
+	mov	r0, r7
15380
+	bl	FtlBbmMapBadBlock
15381
+	bl	FtlBbmTblFlush
15382
+	ldr	r3, [sp, #4]
15383
+	ldrh	r1, [r4, #-2]
15384
+	add	r3, r4, r3, lsl #1
15385
+.L2480:
15386
+	cmp	r5, r1
15387
+	bcc	.L2481
15388
+	sub	r1, r1, #1
15389
+	strh	r1, [r4, #-2]	@ movhi
15390
+.L2479:
15391
+	add	fp, fp, #1
15392
+	b	.L2478
15393
+.L2481:
15394
+	ldrh	r0, [r3, #2]!
15395
+	add	r5, r5, #1
15396
+	uxth	r5, r5
15397
+	strh	r0, [r3, #-2]	@ movhi
15398
+	b	.L2480
15399
+.L2489:
14946
15400
 	.align	2
14947
-.L2548:
15401
+.L2488:
14948
15402
 	.word	.LANCHOR2-2656
14949
15403
 	.word	.LANCHOR0
15404
+	.word	.LANCHOR0+2324
14950
15405
 	.word	.LC129
14951
15406
 	.fnend
14952
15407
 	.size	FtlGcFreeBadSuperBlk, .-FtlGcFreeBadSuperBlk
14953
15408
 	.align	2
14954
15409
 	.global	update_vpc_list
15410
+	.syntax unified
15411
+	.arm
15412
+	.fpu softvfp
14955
15413
 	.type	update_vpc_list, %function
14956
15414
 update_vpc_list:
14957
15415
 	.fnstart
14958
15416
 	@ args = 0, pretend = 0, frame = 0
14959
15417
 	@ frame_needed = 0, uses_anonymous_args = 0
14960
-	ldr	r2, .L2560
14961
-	stmfd	sp!, {r3, r4, r5, lr}
14962
-	.save {r3, r4, r5, lr}
14963
-	mov	r3, r0, asl #1
14964
-	ldr	r1, [r2, #-3544]
14965
-	mov	r4, r0
15418
+	ldr	r2, .L2499
15419
+	lsl	r3, r0, #1
15420
+	push	{r4, r5, r6, lr}
15421
+	.save {r4, r5, r6, lr}
15422
+	ldr	r1, [r2, #-3540]
14966
15423
 	ldrh	r3, [r1, r3]
14967
15424
 	cmp	r3, #0
14968
-	bne	.L2551
15425
+	bne	.L2491
14969
15426
 	sub	r1, r2, #3280
15427
+	mov	r4, r0
14970
15428
 	ldrh	r0, [r1, #-4]
15429
+	sub	r5, r2, #3520
14971
15430
 	cmp	r0, r4
14972
15431
 	mvneq	r3, #0
14973
-	streqh	r3, [r1, #-4]	@ movhi
14974
-	beq	.L2553
14975
-	sub	r1, r2, #3520
14976
-	ldrh	r1, [r1, #-4]
15432
+	strheq	r3, [r1, #-4]	@ movhi
15433
+	beq	.L2493
15434
+	ldrh	r1, [r5]
14977
15435
 	cmp	r1, r4
14978
-	beq	.L2559
15436
+	beq	.L2490
14979
15437
 	sub	r1, r2, #3472
14980
-	ldrh	r1, [r1, #-4]
15438
+	ldrh	r1, [r1]
14981
15439
 	cmp	r1, r4
14982
-	beq	.L2559
15440
+	beq	.L2490
14983
15441
 	sub	r2, r2, #3424
14984
-	ldrh	r2, [r2, #-4]
15442
+	ldrh	r2, [r2]
14985
15443
 	cmp	r2, r4
14986
-	beq	.L2559
14987
-.L2553:
14988
-	ldr	r5, .L2560+4
15444
+	beq	.L2490
15445
+.L2493:
14989
15446
 	mov	r1, r4
14990
-	sub	r0, r5, #12
15447
+	ldr	r0, .L2499+4
14991
15448
 	bl	List_remove_node
14992
-	ldrh	r3, [r5]
15449
+	ldrh	r3, [r5, #-12]
14993
15450
 	mov	r0, r4
14994
15451
 	sub	r3, r3, #1
14995
-	strh	r3, [r5]	@ movhi
15452
+	strh	r3, [r5, #-12]	@ movhi
14996
15453
 	bl	free_data_superblock
14997
15454
 	mov	r0, r4
14998
15455
 	bl	FtlGcFreeBadSuperBlk
14999
-	mov	r0, #1
15000
-	ldmfd	sp!, {r3, r4, r5, pc}
15001
-.L2551:
15456
+	mov	r3, #1
15457
+.L2490:
15458
+	mov	r0, r3
15459
+	pop	{r4, r5, r6, pc}
15460
+.L2491:
15002
15461
 	bl	List_update_data_list
15003
-.L2559:
15004
-	mov	r0, #0
15005
-	ldmfd	sp!, {r3, r4, r5, pc}
15006
-.L2561:
15462
+	mov	r3, #0
15463
+	b	.L2490
15464
+.L2500:
15007
15465
 	.align	2
15008
-.L2560:
15466
+.L2499:
15009
15467
 	.word	.LANCHOR2
15010
-	.word	.LANCHOR2-3536
15468
+	.word	.LANCHOR2-3544
15011
15469
 	.fnend
15012
15470
 	.size	update_vpc_list, .-update_vpc_list
15013
15471
 	.align	2
15014
15472
 	.global	decrement_vpc_count
15473
+	.syntax unified
15474
+	.arm
15475
+	.fpu softvfp
15015
15476
 	.type	decrement_vpc_count, %function
15016
15477
 decrement_vpc_count:
15017
15478
 	.fnstart
15018
15479
 	@ args = 0, pretend = 0, frame = 0
15019
15480
 	@ frame_needed = 0, uses_anonymous_args = 0
15020
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
15021
-	.save {r3, r4, r5, r6, r7, lr}
15022
15481
 	movw	r3, #65535
15482
+	push	{r4, r5, r6, r7, r8, lr}
15483
+	.save {r4, r5, r6, r7, r8, lr}
15023
15484
 	cmp	r0, r3
15024
15485
 	mov	r4, r0
15025
-	beq	.L2563
15026
-	ldr	r6, .L2573
15027
-	mov	r5, r0, asl #1
15028
-	ldr	r3, [r6, #-3544]
15486
+	beq	.L2502
15487
+	ldr	r6, .L2512
15488
+	lsl	r5, r0, #1
15489
+	ldr	r3, [r6, #-3540]
15029
15490
 	ldrh	r2, [r3, r5]
15030
15491
 	cmp	r2, #0
15031
15492
 	subne	r2, r2, #1
15032
-	strneh	r2, [r3, r5]	@ movhi
15033
-	bne	.L2563
15034
-	mov	r1, r4
15035
-	ldr	r0, .L2573+4
15493
+	strhne	r2, [r3, r5]	@ movhi
15494
+	bne	.L2502
15495
+	mov	r1, r0
15496
+	ldr	r0, .L2512+4
15036
15497
 	bl	printk
15037
-	ldr	r3, [r6, #-3544]
15498
+	ldr	r3, [r6, #-3540]
15038
15499
 	sub	r7, r6, #3520
15039
15500
 	mov	r2, #32
15040
-	sub	r0, r7, #12
15501
+	sub	r8, r7, #8
15041
15502
 	mov	r1, r4
15503
+	mov	r0, r8
15042
15504
 	strh	r2, [r3, r5]	@ movhi
15043
15505
 	bl	test_node_in_list
15044
15506
 	cmp	r0, #0
15045
-	beq	.L2565
15507
+	beq	.L2504
15046
15508
 	mov	r1, r4
15047
-	sub	r0, r7, #12
15509
+	mov	r0, r8
15048
15510
 	bl	List_remove_node
15049
-	ldrh	r3, [r7, #-8]
15511
+	ldrh	r3, [r7, #-4]
15050
15512
 	mov	r0, r4
15051
15513
 	sub	r3, r3, #1
15052
-	strh	r3, [r7, #-8]	@ movhi
15514
+	strh	r3, [r7, #-4]	@ movhi
15053
15515
 	bl	INSERT_DATA_LIST
15054
-	ldr	r3, [r6, #-3544]
15055
-	ldr	r0, .L2573+8
15516
+	ldr	r3, [r6, #-3540]
15056
15517
 	mov	r1, r4
15518
+	ldr	r0, .L2512+8
15057
15519
 	ldrh	r2, [r3, r5]
15058
15520
 	bl	printk
15059
-.L2565:
15521
+.L2504:
15060
15522
 	mov	r0, r4
15061
15523
 	bl	FtlGcRefreshBlock
15062
-	b	.L2568
15063
-.L2563:
15064
-	ldr	r5, .L2573+12
15524
+.L2507:
15525
+	mov	r0, #0
15526
+	pop	{r4, r5, r6, r7, r8, pc}
15527
+.L2502:
15528
+	ldr	r5, .L2512+12
15065
15529
 	movw	r3, #65535
15066
15530
 	ldrh	r0, [r5]
15067
15531
 	cmp	r0, r3
15068
-	streqh	r4, [r5]	@ movhi
15069
-	beq	.L2568
15070
-	cmp	r0, r4
15071
-	beq	.L2568
15532
+	strheq	r4, [r5]	@ movhi
15533
+	beq	.L2507
15534
+	cmp	r4, r0
15535
+	beq	.L2507
15072
15536
 	bl	update_vpc_list
15073
-	strh	r4, [r5]	@ movhi
15074
15537
 	adds	r0, r0, #0
15538
+	strh	r4, [r5]	@ movhi
15075
15539
 	movne	r0, #1
15076
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
15077
-.L2568:
15078
-	mov	r0, #0
15079
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
15080
-.L2574:
15540
+	pop	{r4, r5, r6, r7, r8, pc}
15541
+.L2513:
15081
15542
 	.align	2
15082
-.L2573:
15543
+.L2512:
15083
15544
 	.word	.LANCHOR2
15084
15545
 	.word	.LC130
15085
15546
 	.word	.LC131
..
..
@@ -15088,59 +15549,44 @@
15088
15549
 	.size	decrement_vpc_count, .-decrement_vpc_count
15089
15550
 	.align	2
15090
15551
 	.global	FtlSlcSuperblockCheck
15552
+	.syntax unified
15553
+	.arm
15554
+	.fpu softvfp
15091
15555
 	.type	FtlSlcSuperblockCheck, %function
15092
15556
 FtlSlcSuperblockCheck:
15093
15557
 	.fnstart
15094
15558
 	@ args = 0, pretend = 0, frame = 0
15095
15559
 	@ frame_needed = 0, uses_anonymous_args = 0
15096
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
15097
-	.save {r3, r4, r5, r6, r7, lr}
15098
15560
 	ldrh	r3, [r0, #4]
15099
15561
 	cmp	r3, #0
15100
-	ldmeqfd	sp!, {r3, r4, r5, r6, r7, pc}
15562
+	bxeq	lr
15101
15563
 	ldrh	r2, [r0]
15102
15564
 	movw	r3, #65535
15103
15565
 	cmp	r2, r3
15104
-	ldmeqfd	sp!, {r3, r4, r5, r6, r7, pc}
15105
-	ldrb	r3, [r0, #6]	@ zero_extendqisi2
15566
+	bxeq	lr
15567
+	push	{r4, r5, r6, lr}
15568
+	.save {r4, r5, r6, lr}
15106
15569
 	mov	r4, r0
15107
-	ldr	r5, .L2588
15108
-	ldr	r6, .L2588+4
15109
-	add	r3, r0, r3, asl #1
15110
-	add	r7, r5, #2320
15570
+	ldrb	r3, [r0, #6]	@ zero_extendqisi2
15571
+	ldr	r5, .L2529
15572
+	ldr	r6, .L2529+4
15573
+	add	r3, r0, r3, lsl #1
15111
15574
 	ldrh	r3, [r3, #16]
15112
-.L2579:
15575
+.L2518:
15113
15576
 	movw	r1, #65535
15114
15577
 	cmp	r3, r1
15115
-	bne	.L2587
15116
-.L2581:
15117
-	ldrb	r3, [r4, #6]	@ zero_extendqisi2
15118
-	ldrh	r2, [r7]
15119
-	add	r3, r3, #1
15120
-	uxtb	r3, r3
15121
-	strb	r3, [r4, #6]
15122
-	cmp	r2, r3
15123
-	ldreqh	r3, [r4, #2]
15124
-	addeq	r3, r3, #1
15125
-	streqh	r3, [r4, #2]	@ movhi
15126
-	moveq	r3, #0
15127
-	streqb	r3, [r4, #6]
15128
-	ldrb	r3, [r4, #6]	@ zero_extendqisi2
15129
-	add	r3, r4, r3, asl #1
15130
-	ldrh	r3, [r3, #16]
15131
-	b	.L2579
15132
-.L2587:
15578
+	beq	.L2520
15133
15579
 	ldrb	r2, [r4, #8]	@ zero_extendqisi2
15134
15580
 	cmp	r2, #1
15135
-	bne	.L2582
15136
-	ldrb	r3, [r5, #144]	@ zero_extendqisi2
15581
+	bne	.L2521
15582
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
15137
15583
 	cmp	r3, #0
15138
-	bne	.L2582
15584
+	bne	.L2521
15139
15585
 	ldrh	r3, [r4, #2]
15140
-	mov	r3, r3, asl #1
15586
+	lsl	r3, r3, #1
15141
15587
 	ldrh	r3, [r6, r3]
15142
15588
 	cmp	r3, r1
15143
-	bne	.L2582
15589
+	bne	.L2521
15144
15590
 	ldrh	r3, [r4, #4]
15145
15591
 	ldrh	r0, [r4]
15146
15592
 	sub	r3, r3, #1
..
..
@@ -15148,178 +15594,191 @@
15148
15594
 	bl	decrement_vpc_count
15149
15595
 	ldrh	r2, [r4, #4]
15150
15596
 	cmp	r2, #0
15151
-	bne	.L2581
15597
+	bne	.L2520
15152
15598
 	ldrh	r3, [r4, #2]
15153
15599
 	strb	r2, [r4, #6]
15154
15600
 	add	r3, r3, #1
15155
15601
 	strh	r3, [r4, #2]	@ movhi
15156
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
15157
-.L2582:
15158
-	ldr	r1, .L2588
15159
-	ldrb	r3, [r1, #144]	@ zero_extendqisi2
15160
-	cmp	r3, #0
15161
-	ldmeqfd	sp!, {r3, r4, r5, r6, r7, pc}
15162
-	cmp	r2, #1
15163
-	ldmnefd	sp!, {r3, r4, r5, r6, r7, pc}
15164
-	movw	r3, #2390
15165
-	ldrh	r2, [r4, #2]
15166
-	ldrh	r3, [r1, r3]
15602
+	pop	{r4, r5, r6, pc}
15603
+.L2520:
15604
+	ldrb	r3, [r4, #6]	@ zero_extendqisi2
15605
+	ldr	r2, .L2529+8
15606
+	add	r3, r3, #1
15607
+	ldrh	r2, [r2]
15608
+	uxtb	r3, r3
15609
+	strb	r3, [r4, #6]
15167
15610
 	cmp	r2, r3
15168
-	ldmccfd	sp!, {r3, r4, r5, r6, r7, pc}
15169
-	ldr	r2, .L2588+8
15611
+	ldrheq	r3, [r4, #2]
15612
+	addeq	r3, r3, #1
15613
+	strheq	r3, [r4, #2]	@ movhi
15614
+	moveq	r3, #0
15615
+	strbeq	r3, [r4, #6]
15616
+	ldrb	r3, [r4, #6]	@ zero_extendqisi2
15617
+	add	r3, r4, r3, lsl #1
15618
+	ldrh	r3, [r3, #16]
15619
+	b	.L2518
15620
+.L2521:
15621
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
15622
+	adds	r3, r3, #0
15623
+	movne	r3, #1
15624
+	cmp	r2, #1
15625
+	movne	r3, #0
15626
+	cmp	r3, #0
15627
+	popeq	{r4, r5, r6, pc}
15628
+	movw	r3, #2392
15629
+	ldrh	r2, [r4, #2]
15630
+	ldrh	r3, [r5, r3]
15631
+	cmp	r2, r3
15632
+	popcc	{r4, r5, r6, pc}
15170
15633
 	ldrh	r3, [r4]
15171
-	ldrh	ip, [r4, #4]
15172
-	ldr	r0, [r2, #-3544]
15173
-	mov	r3, r3, asl #1
15174
-	ldrh	r2, [r0, r3]
15175
-	rsb	r2, ip, r2
15176
-	strh	r2, [r0, r3]	@ movhi
15177
-	movw	r2, #2388
15634
+	ldr	r2, .L2529+12
15635
+	ldrh	r0, [r4, #4]
15636
+	ldr	r1, [r2, #-3540]
15637
+	lsl	r3, r3, #1
15638
+	ldrh	r2, [r1, r3]
15639
+	sub	r2, r2, r0
15640
+	strh	r2, [r1, r3]	@ movhi
15641
+	movw	r2, #2390
15642
+	ldrh	r2, [r5, r2]
15178
15643
 	mov	r3, #0
15179
-	ldrh	r2, [r1, r2]
15180
15644
 	strh	r3, [r4, #4]	@ movhi
15181
15645
 	strb	r3, [r4, #6]
15182
15646
 	strh	r2, [r4, #2]	@ movhi
15183
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
15184
-.L2589:
15647
+	pop	{r4, r5, r6, pc}
15648
+.L2530:
15185
15649
 	.align	2
15186
-.L2588:
15650
+.L2529:
15187
15651
 	.word	.LANCHOR0
15188
15652
 	.word	.LANCHOR2-2620
15653
+	.word	.LANCHOR0+2324
15189
15654
 	.word	.LANCHOR2
15190
15655
 	.fnend
15191
15656
 	.size	FtlSlcSuperblockCheck, .-FtlSlcSuperblockCheck
15192
15657
 	.align	2
15193
15658
 	.global	get_new_active_ppa
15659
+	.syntax unified
15660
+	.arm
15661
+	.fpu softvfp
15194
15662
 	.type	get_new_active_ppa, %function
15195
15663
 get_new_active_ppa:
15196
15664
 	.fnstart
15197
15665
 	@ args = 0, pretend = 0, frame = 0
15198
15666
 	@ frame_needed = 0, uses_anonymous_args = 0
15199
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
15200
-	.save {r3, r4, r5, r6, r7, r8, r9, lr}
15201
15667
 	mov	r3, #0
15668
+	push	{r4, r5, r6, r7, r8, lr}
15669
+	.save {r4, r5, r6, r7, r8, lr}
15202
15670
 	strb	r3, [r0, #10]
15203
15671
 	mov	r4, r0
15204
15672
 	ldrb	r3, [r0, #6]	@ zero_extendqisi2
15205
-	ldr	r7, .L2608
15206
-	ldr	r9, .L2608+4
15207
-	add	r3, r0, r3, asl #1
15208
-	sub	r8, r7, #2320
15673
+	ldr	r5, .L2547
15674
+	ldr	r7, .L2547+4
15675
+	add	r3, r0, r3, lsl #1
15209
15676
 	ldrh	r2, [r3, #16]
15210
-.L2591:
15677
+.L2532:
15211
15678
 	movw	r1, #65535
15212
15679
 	cmp	r2, r1
15213
-	ldr	r6, .L2608
15214
-	bne	.L2607
15215
-.L2592:
15216
-	ldrb	r3, [r4, #6]	@ zero_extendqisi2
15217
-	ldrh	r2, [r7]
15218
-	add	r3, r3, #1
15219
-	uxtb	r3, r3
15220
-	strb	r3, [r4, #6]
15221
-	cmp	r2, r3
15222
-	ldreqh	r3, [r4, #2]
15223
-	addeq	r3, r3, #1
15224
-	streqh	r3, [r4, #2]	@ movhi
15225
-	moveq	r3, #0
15226
-	streqb	r3, [r4, #6]
15227
-	ldrb	r3, [r4, #6]	@ zero_extendqisi2
15228
-	add	r3, r4, r3, asl #1
15229
-	ldrh	r2, [r3, #16]
15230
-	b	.L2591
15231
-.L2607:
15680
+	beq	.L2533
15232
15681
 	ldrb	r3, [r4, #8]	@ zero_extendqisi2
15233
-	ldrh	r5, [r4, #2]
15682
+	ldrh	r6, [r4, #2]
15234
15683
 	cmp	r3, #1
15235
15684
 	ldrh	r3, [r4, #4]
15236
-	bne	.L2594
15237
-	ldrb	r0, [r8, #144]	@ zero_extendqisi2
15685
+	bne	.L2535
15686
+	ldr	r0, .L2547+8
15687
+	ldrb	r0, [r0, #152]	@ zero_extendqisi2
15238
15688
 	cmp	r0, #0
15239
-	bne	.L2594
15240
-	mov	r0, r5, asl #1
15241
-	ldrh	r0, [r9, r0]
15689
+	bne	.L2535
15690
+	lsl	r0, r6, #1
15691
+	ldrh	r0, [r7, r0]
15242
15692
 	cmp	r0, r1
15243
-	bne	.L2594
15693
+	bne	.L2535
15244
15694
 	sub	r3, r3, #1
15245
15695
 	ldrh	r0, [r4]
15246
15696
 	strh	r3, [r4, #4]	@ movhi
15247
15697
 	bl	decrement_vpc_count
15248
-	b	.L2592
15249
-.L2594:
15250
-	ldr	r7, .L2608+8
15251
-	orr	r5, r5, r2, asl #10
15698
+.L2533:
15699
+	ldrb	r3, [r4, #6]	@ zero_extendqisi2
15700
+	ldrh	r2, [r5]
15701
+	add	r3, r3, #1
15702
+	uxtb	r3, r3
15703
+	cmp	r2, r3
15704
+	strb	r3, [r4, #6]
15705
+	ldrheq	r3, [r4, #2]
15706
+	addeq	r3, r3, #1
15707
+	strheq	r3, [r4, #2]	@ movhi
15708
+	moveq	r3, #0
15709
+	strbeq	r3, [r4, #6]
15710
+	ldrb	r3, [r4, #6]	@ zero_extendqisi2
15711
+	add	r3, r4, r3, lsl #1
15712
+	ldrh	r2, [r3, #16]
15713
+	b	.L2532
15714
+.L2535:
15715
+	ldr	r7, .L2547+4
15716
+	orr	r6, r6, r2, lsl #10
15252
15717
 	sub	r3, r3, #1
15253
15718
 	strh	r3, [r4, #4]	@ movhi
15254
-.L2595:
15719
+.L2536:
15255
15720
 	ldrb	r3, [r4, #6]	@ zero_extendqisi2
15256
-	movw	r2, #65535
15257
-	ldrh	r0, [r6]
15258
-.L2597:
15721
+	movw	r1, #65535
15722
+	ldrh	r0, [r5]
15723
+.L2538:
15259
15724
 	add	r3, r3, #1
15260
15725
 	uxtb	r3, r3
15261
15726
 	cmp	r3, r0
15262
-	ldreqh	r3, [r4, #2]
15727
+	ldrheq	r3, [r4, #2]
15263
15728
 	addeq	r3, r3, #1
15264
-	streqh	r3, [r4, #2]	@ movhi
15729
+	strheq	r3, [r4, #2]	@ movhi
15265
15730
 	moveq	r3, #0
15266
-	add	r1, r4, r3, asl #1
15267
-	ldrh	r1, [r1, #16]
15268
-	cmp	r1, r2
15269
-	beq	.L2597
15731
+	add	r2, r4, r3, lsl #1
15732
+	ldrh	r2, [r2, #16]
15733
+	cmp	r2, r1
15734
+	beq	.L2538
15270
15735
 	strb	r3, [r4, #6]
15271
15736
 	ldrb	r3, [r4, #8]	@ zero_extendqisi2
15272
15737
 	cmp	r3, #1
15273
-	bne	.L2602
15274
-	ldrb	r3, [r7, #144]	@ zero_extendqisi2
15738
+	bne	.L2531
15739
+	ldr	r2, .L2547+8
15740
+	ldrb	r3, [r2, #152]	@ zero_extendqisi2
15275
15741
 	cmp	r3, #0
15276
-	bne	.L2599
15277
15742
 	ldrh	r3, [r4, #2]
15278
-	ldr	r2, .L2608+4
15279
-	mov	r3, r3, asl #1
15280
-	ldrh	r2, [r2, r3]
15281
-	movw	r3, #65535
15282
-	cmp	r2, r3
15283
-	bne	.L2599
15743
+	bne	.L2540
15744
+	lsl	r3, r3, #1
15745
+	ldrh	r3, [r7, r3]
15746
+	cmp	r3, r1
15747
+	bne	.L2531
15284
15748
 	ldrh	r3, [r4, #4]
15285
15749
 	cmp	r3, #0
15286
-	beq	.L2599
15750
+	beq	.L2531
15287
15751
 	sub	r3, r3, #1
15288
15752
 	ldrh	r0, [r4]
15289
15753
 	strh	r3, [r4, #4]	@ movhi
15290
15754
 	bl	decrement_vpc_count
15291
-	b	.L2595
15292
-.L2599:
15293
-	ldr	r1, .L2608+8
15294
-	ldrb	r3, [r1, #144]	@ zero_extendqisi2
15295
-	cmp	r3, #0
15296
-	beq	.L2602
15297
-	movw	r3, #2390
15298
-	ldrh	r2, [r4, #2]
15299
-	ldrh	r3, [r1, r3]
15300
-	cmp	r2, r3
15301
-	bcc	.L2602
15302
-	ldr	r2, .L2608+12
15755
+	b	.L2536
15756
+.L2540:
15757
+	movw	r1, #2392
15758
+	ldrh	r1, [r2, r1]
15759
+	cmp	r3, r1
15760
+	bcc	.L2531
15303
15761
 	ldrh	r3, [r4]
15762
+	ldr	r1, .L2547+12
15304
15763
 	ldrh	ip, [r4, #4]
15305
-	ldr	r0, [r2, #-3544]
15306
-	mov	r3, r3, asl #1
15307
-	ldrh	r2, [r0, r3]
15308
-	rsb	r2, ip, r2
15309
-	strh	r2, [r0, r3]	@ movhi
15310
-	movw	r2, #2388
15764
+	ldr	r0, [r1, #-3540]
15765
+	lsl	r3, r3, #1
15766
+	ldrh	r1, [r0, r3]
15767
+	sub	r1, r1, ip
15768
+	strh	r1, [r0, r3]	@ movhi
15769
+	movw	r1, #2390
15770
+	ldrh	r2, [r2, r1]
15311
15771
 	mov	r3, #0
15312
-	ldrh	r2, [r1, r2]
15313
15772
 	strh	r3, [r4, #4]	@ movhi
15314
15773
 	strb	r3, [r4, #6]
15315
15774
 	strh	r2, [r4, #2]	@ movhi
15316
-.L2602:
15317
-	mov	r0, r5
15318
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
15319
-.L2609:
15775
+.L2531:
15776
+	mov	r0, r6
15777
+	pop	{r4, r5, r6, r7, r8, pc}
15778
+.L2548:
15320
15779
 	.align	2
15321
-.L2608:
15322
-	.word	.LANCHOR0+2320
15780
+.L2547:
15781
+	.word	.LANCHOR0+2324
15323
15782
 	.word	.LANCHOR2-2620
15324
15783
 	.word	.LANCHOR0
15325
15784
 	.word	.LANCHOR2
..
..
@@ -15327,320 +15786,323 @@
15327
15786
 	.size	get_new_active_ppa, .-get_new_active_ppa
15328
15787
 	.align	2
15329
15788
 	.global	FtlVpcTblFlush
15789
+	.syntax unified
15790
+	.arm
15791
+	.fpu softvfp
15330
15792
 	.type	FtlVpcTblFlush, %function
15331
15793
 FtlVpcTblFlush:
15332
15794
 	.fnstart
15333
-	@ args = 0, pretend = 0, frame = 0
15795
+	@ args = 0, pretend = 0, frame = 8
15334
15796
 	@ frame_needed = 0, uses_anonymous_args = 0
15335
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
15336
-	.save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
15337
-	ldr	r4, .L2628
15338
-	ldr	r3, [r4, #-3616]
15797
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
15798
+	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
15799
+	.pad #12
15800
+	ldr	r4, .L2567
15801
+	ldr	r3, [r4, #-3612]
15339
15802
 	cmp	r3, #0
15340
-	bne	.L2612
15803
+	bne	.L2551
15341
15804
 	ldr	r2, [r4, #-524]
15342
-	sub	r6, r4, #3600
15805
+	sub	r5, r4, #3296
15343
15806
 	ldr	r7, [r4, #-500]
15807
+	sub	r8, r5, #300
15808
+	ldr	r6, .L2567+4
15344
15809
 	mov	r1, #255
15345
-	ldr	r5, .L2628+4
15346
-	str	r2, [r4, #1760]
15347
-	sub	r2, r4, #3296
15348
-	str	r7, [r4, #1764]
15349
-	ldrh	r2, [r2, #-4]
15810
+	str	r2, [r4, #1768]
15811
+	ldrh	r2, [r5, #-4]
15812
+	str	r7, [r4, #1772]
15813
+	add	r9, r6, #2400
15350
15814
 	str	r3, [r7, #12]
15351
15815
 	strh	r2, [r7, #2]	@ movhi
15352
-	ldr	r2, .L2628+8
15816
+	ldr	r2, .L2567+8
15353
15817
 	strh	r2, [r7]	@ movhi
15354
15818
 	ldr	r2, [r4, #-3292]
15355
15819
 	stmib	r7, {r2, r3}
15356
-	ldr	r3, .L2628+12
15357
-	ldrh	r2, [r6, #78]
15358
-	str	r3, [r4, #-3600]
15359
-	ldr	r3, .L2628+16
15820
+	ldr	r3, .L2567+12
15360
15821
 	str	r3, [r4, #-3596]
15361
-	add	r3, r6, #300
15362
-	ldrh	r3, [r3, #6]
15363
-	strh	r3, [r6, #8]	@ movhi
15364
-	movw	r3, #2342
15365
-	ldrh	r3, [r5, r3]
15366
-	strb	r3, [r4, #-3590]
15822
+	ldr	r3, .L2567+16
15823
+	str	r3, [r4, #-3592]
15824
+	ldrh	r3, [r5, #2]
15825
+	strh	r3, [r8, #8]	@ movhi
15826
+	movw	r3, #2346
15827
+	ldrh	r3, [r6, r3]
15828
+	strb	r3, [r4, #-3586]
15367
15829
 	sub	r3, r4, #3520
15368
-	ldrh	r3, [r3, #-4]
15369
-	strh	r3, [r6, #14]	@ movhi
15370
-	ldrb	r3, [r4, #-3518]	@ zero_extendqisi2
15371
-	orr	r3, r3, r2, asl #6
15372
-	strh	r3, [r6, #16]	@ movhi
15373
-	ldrb	r3, [r4, #-3516]	@ zero_extendqisi2
15374
-	ldrh	r2, [r6, #126]
15375
-	strb	r3, [r4, #-3589]
15830
+	ldrh	r2, [r3]
15831
+	strh	r2, [r8, #14]	@ movhi
15832
+	ldrh	r2, [r3, #2]
15833
+	ldrb	r3, [r4, #-3514]	@ zero_extendqisi2
15834
+	orr	r3, r3, r2, lsl #6
15835
+	strh	r3, [r8, #16]	@ movhi
15836
+	ldrb	r3, [r4, #-3512]	@ zero_extendqisi2
15837
+	strb	r3, [r4, #-3585]
15376
15838
 	sub	r3, r4, #3472
15377
-	ldrh	r3, [r3, #-4]
15378
-	strh	r3, [r6, #18]	@ movhi
15379
-	ldrb	r3, [r4, #-3470]	@ zero_extendqisi2
15380
-	orr	r3, r3, r2, asl #6
15381
-	strh	r3, [r6, #20]	@ movhi
15382
-	ldrb	r3, [r4, #-3468]	@ zero_extendqisi2
15383
-	strb	r3, [r4, #-3588]
15839
+	ldrh	r2, [r3]
15840
+	strh	r2, [r8, #18]	@ movhi
15841
+	ldrh	r2, [r3, #2]
15842
+	ldrb	r3, [r4, #-3466]	@ zero_extendqisi2
15843
+	orr	r3, r3, r2, lsl #6
15844
+	strh	r3, [r8, #20]	@ movhi
15845
+	ldrb	r3, [r4, #-3464]	@ zero_extendqisi2
15846
+	strb	r3, [r4, #-3584]
15384
15847
 	sub	r3, r4, #3424
15385
-	ldrh	r3, [r3, #-4]
15386
-	strh	r3, [r6, #22]	@ movhi
15387
-	ldrh	r2, [r6, #174]
15388
-	ldrb	r3, [r4, #-3422]	@ zero_extendqisi2
15389
-	ldr	r0, [r4, #1760]
15390
-	orr	r3, r3, r2, asl #6
15391
-	strh	r3, [r6, #24]	@ movhi
15392
-	ldrb	r3, [r4, #-3420]	@ zero_extendqisi2
15393
-	strb	r3, [r4, #-3587]
15848
+	ldrh	r2, [r3]
15849
+	strh	r2, [r8, #22]	@ movhi
15850
+	ldrh	r2, [r3, #2]
15851
+	ldrb	r3, [r4, #-3418]	@ zero_extendqisi2
15852
+	ldr	r0, [r4, #1768]
15853
+	orr	r3, r3, r2, lsl #6
15854
+	strh	r3, [r8, #24]	@ movhi
15855
+	ldrb	r3, [r4, #-3416]	@ zero_extendqisi2
15856
+	strb	r3, [r4, #-3583]
15394
15857
 	ldr	r3, [r4, #-3324]
15395
-	str	r3, [r4, #-3568]
15396
-	ldr	r3, [r4, #-3332]
15397
-	str	r3, [r4, #-3560]
15398
-	ldr	r3, [r4, #-3328]
15399
15858
 	str	r3, [r4, #-3564]
15859
+	ldr	r3, [r4, #-3332]
15860
+	str	r3, [r4, #-3556]
15861
+	ldr	r3, [r4, #-3328]
15862
+	str	r3, [r4, #-3560]
15400
15863
 	sub	r3, r4, #2656
15401
15864
 	ldrh	r2, [r3, #-10]
15402
15865
 	ldrh	r3, [r3, #-8]
15403
-	strh	r2, [r6, #44]	@ movhi
15404
-	strh	r3, [r6, #46]	@ movhi
15405
-	movw	r3, #2398
15406
-	ldrh	r2, [r5, r3]
15866
+	strh	r2, [r8, #44]	@ movhi
15867
+	ldrh	r2, [r9]
15868
+	strh	r3, [r5, #-254]	@ movhi
15407
15869
 	bl	ftl_memset
15408
-	mov	r1, r6
15870
+	mov	r1, r8
15409
15871
 	mov	r2, #48
15410
-	movw	r6, #2328
15411
-	ldr	r0, [r4, #1760]
15872
+	movw	r8, #2332
15873
+	ldr	r0, [r4, #1768]
15412
15874
 	bl	ftl_memcpy
15413
-	ldrh	r2, [r5, r6]
15414
-	ldr	r0, [r4, #1760]
15415
-	ldr	r1, [r4, #-3544]
15416
-	mov	r2, r2, asl #1
15875
+	ldrh	r2, [r6, r8]
15876
+	ldr	r0, [r4, #1768]
15877
+	ldr	r1, [r4, #-3540]
15878
+	lsl	r2, r2, #1
15417
15879
 	add	r0, r0, #48
15418
15880
 	bl	ftl_memcpy
15419
-	ldrh	r2, [r5, r6]
15420
-	ldr	r0, [r4, #1760]
15421
-	ldr	r1, [r4, #-3368]
15422
-	mov	r3, r2, asl #1
15423
-	mov	r2, r2, lsr #3
15424
-	add	r3, r3, #51
15881
+	ldrh	r0, [r6, r8]
15882
+	ldr	r3, [r4, #1768]
15883
+	ldr	r1, [r6, #32]
15884
+	lsr	r2, r0, #3
15885
+	lsl	r0, r0, #1
15886
+	add	r0, r0, #51
15425
15887
 	add	r2, r2, #4
15426
-	bic	r3, r3, #3
15427
-	add	r0, r0, r3
15888
+	bic	r0, r0, #3
15889
+	add	r0, r3, r0
15428
15890
 	bl	ftl_memcpy
15429
-	add	r3, r5, #2432
15430
-	ldrh	r3, [r3]
15891
+	movw	r3, #2436
15892
+	str	r9, [sp, #4]
15893
+	ldrh	r3, [r6, r3]
15431
15894
 	cmp	r3, #0
15432
-	beq	.L2613
15433
-	ldrh	r2, [r5, r6]
15434
-	ldr	r0, [r4, #1760]
15895
+	beq	.L2552
15896
+	ldrh	r0, [r6, r8]
15897
+	movw	r3, #2428
15898
+	ldrh	r2, [r6, r3]
15435
15899
 	ldr	r1, [r4, #-452]
15436
-	mov	r3, r2, lsr #3
15437
-	add	r3, r3, r2, asl #1
15438
-	movw	r2, #2424
15900
+	lsr	r3, r0, #3
15901
+	lsl	r2, r2, #2
15902
+	add	r3, r3, r0, lsl #1
15903
+	ldr	r0, [r4, #1768]
15439
15904
 	add	r3, r3, #52
15440
-	ldrh	r2, [r5, r2]
15441
15905
 	ubfx	r3, r3, #2, #14
15442
-	mov	r2, r2, asl #2
15443
-	add	r0, r0, r3, asl #2
15906
+	add	r0, r0, r3, lsl #2
15444
15907
 	bl	ftl_memcpy
15445
-.L2613:
15446
-	mov	r0, #0
15447
-	ldr	r8, .L2628
15448
-	bl	FtlUpdateVaildLpn
15449
-	ldr	r10, .L2628+20
15450
-	mov	r6, #0
15908
+.L2552:
15909
+	ldr	r10, .L2567+20
15910
+	mov	r8, #0
15451
15911
 	movw	r9, #65535
15452
-.L2614:
15912
+	sub	r5, r5, #4
15913
+	mov	r0, #0
15914
+	mov	fp, r10
15915
+	bl	FtlUpdateVaildLpn
15916
+.L2553:
15453
15917
 	ldr	r3, [r4, #-524]
15454
-	ldrh	r2, [r10]
15455
-	ldr	fp, .L2628+24
15456
-	str	r3, [r4, #1760]
15918
+	ldrh	r1, [r5, #2]
15919
+	ldrh	r2, [r5]
15920
+	str	r3, [r4, #1768]
15457
15921
 	ldr	r3, [r4, #-500]
15458
-	ldrh	r1, [r10, #2]
15922
+	str	r3, [r4, #1772]
15923
+	orr	r3, r1, r2, lsl #10
15459
15924
 	str	r3, [r4, #1764]
15460
-	orr	r3, r1, r2, asl #10
15461
-	str	r3, [r4, #1756]
15462
-	ldrh	r3, [fp]
15925
+	ldrh	r3, [r10]
15463
15926
 	sub	r3, r3, #1
15464
15927
 	cmp	r1, r3
15465
-	blt	.L2615
15928
+	blt	.L2554
15466
15929
 	mov	r3, #0
15467
-	ldrh	r9, [r10, #4]
15468
-	strh	r3, [r10, #2]	@ movhi
15469
-	strh	r2, [r10, #4]	@ movhi
15930
+	ldrh	r9, [r5, #4]
15931
+	strh	r3, [r5, #2]	@ movhi
15932
+	strh	r2, [r5, #4]	@ movhi
15470
15933
 	bl	FtlFreeSysBlkQueueOut
15471
-	ldr	r3, [r8, #-3332]
15934
+	ldr	r3, [r4, #-3332]
15935
+	strh	r0, [r5]	@ movhi
15472
15936
 	add	r2, r3, #1
15473
-	str	r2, [r8, #-3332]
15474
-	str	r3, [r8, #-3292]
15475
-	mov	r2, r0, asl #10
15476
-	strh	r0, [r10]	@ movhi
15477
-	str	r2, [r8, #1756]
15937
+	str	r3, [r4, #-3292]
15938
+	str	r2, [r4, #-3332]
15939
+	lsl	r2, r0, #10
15940
+	str	r2, [r4, #1764]
15478
15941
 	str	r3, [r7, #4]
15479
15942
 	strh	r0, [r7, #2]	@ movhi
15480
-.L2615:
15481
-	ldrb	r3, [r5]	@ zero_extendqisi2
15943
+.L2554:
15944
+	ldrb	r3, [r6, #36]	@ zero_extendqisi2
15482
15945
 	cmp	r3, #0
15483
-	beq	.L2616
15484
-	ldr	r3, .L2628+28
15946
+	beq	.L2555
15947
+	ldr	r3, [sp, #4]
15485
15948
 	ldr	r0, [r4, #-524]
15486
15949
 	ldrh	r1, [r3]
15487
15950
 	bl	js_hash
15488
15951
 	str	r0, [r7, #12]
15489
-.L2616:
15490
-	mov	r1, #1
15491
-	ldr	r0, .L2628+32
15492
-	mov	r2, r1
15493
-	mov	r3, r1
15952
+.L2555:
15953
+	mov	r3, #1
15954
+	ldr	r0, .L2567+24
15955
+	mov	r2, r3
15956
+	mov	r1, r3
15494
15957
 	bl	FlashProgPages
15495
-	ldr	r3, .L2628+20
15496
-	ldr	r2, .L2628+20
15497
-	ldrh	r3, [r3, #2]
15958
+	ldrh	r3, [r5, #2]
15959
+	ldr	r2, [r4, #1760]
15498
15960
 	add	r3, r3, #1
15499
15961
 	uxth	r3, r3
15500
-	strh	r3, [r2, #2]	@ movhi
15501
-	ldr	r2, [r4, #1752]
15502
15962
 	cmn	r2, #1
15503
-	bne	.L2617
15963
+	strh	r3, [r5, #2]	@ movhi
15964
+	bne	.L2556
15504
15965
 	cmp	r3, #1
15505
-	add	r6, r6, #1
15506
-	ldreqh	r3, [fp]
15507
-	uxth	r6, r6
15966
+	add	r8, r8, #1
15967
+	ldrheq	r3, [fp]
15968
+	uxth	r8, r8
15508
15969
 	subeq	r3, r3, #1
15509
-	streqh	r3, [r10, #2]	@ movhi
15510
-	cmp	r6, #3
15511
-	bls	.L2614
15512
-	ldr	r0, .L2628+36
15513
-	mov	r2, r6
15514
-	ldr	r1, [r4, #1756]
15970
+	strheq	r3, [r5, #2]	@ movhi
15971
+	cmp	r8, #3
15972
+	bls	.L2553
15973
+	mov	r2, r8
15974
+	ldr	r1, [r4, #1764]
15975
+	ldr	r0, .L2567+28
15515
15976
 	bl	printk
15516
15977
 	mov	r3, #1
15517
-	str	r3, [r4, #-3616]
15518
-	b	.L2612
15519
-.L2617:
15520
-	cmp	r2, #256
15521
-	cmpne	r3, #1
15522
-	beq	.L2614
15978
+	str	r3, [r4, #-3612]
15979
+.L2551:
15980
+	mov	r0, #0
15981
+	add	sp, sp, #12
15982
+	@ sp needed
15983
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
15984
+.L2556:
15985
+	cmp	r3, #1
15986
+	cmpne	r2, #256
15987
+	beq	.L2553
15523
15988
 	movw	r3, #65535
15524
15989
 	cmp	r9, r3
15525
-	beq	.L2612
15526
-	mov	r0, r9
15990
+	beq	.L2551
15527
15991
 	mov	r1, #1
15992
+	mov	r0, r9
15528
15993
 	bl	FtlFreeSysBlkQueueIn
15529
-.L2612:
15530
-	mov	r0, #0
15531
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
15532
-.L2629:
15994
+	b	.L2551
15995
+.L2568:
15533
15996
 	.align	2
15534
-.L2628:
15997
+.L2567:
15535
15998
 	.word	.LANCHOR2
15536
15999
 	.word	.LANCHOR0
15537
16000
 	.word	-3932
15538
16001
 	.word	1179929683
15539
16002
 	.word	1342177379
15540
-	.word	.LANCHOR2-3300
15541
-	.word	.LANCHOR0+2390
15542
-	.word	.LANCHOR0+2398
15543
-	.word	.LANCHOR2+1752
16003
+	.word	.LANCHOR0+2392
16004
+	.word	.LANCHOR2+1760
15544
16005
 	.word	.LC132
15545
16006
 	.fnend
15546
16007
 	.size	FtlVpcTblFlush, .-FtlVpcTblFlush
15547
16008
 	.align	2
15548
16009
 	.global	FtlSuperblockPowerLostFix
16010
+	.syntax unified
16011
+	.arm
16012
+	.fpu softvfp
15549
16013
 	.type	FtlSuperblockPowerLostFix, %function
15550
16014
 FtlSuperblockPowerLostFix:
15551
16015
 	.fnstart
15552
16016
 	@ args = 0, pretend = 0, frame = 40
15553
16017
 	@ frame_needed = 0, uses_anonymous_args = 0
15554
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
15555
-	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
15556
-	.pad #44
15557
-	sub	sp, sp, #44
15558
-	ldr	r5, .L2647
15559
-	ldr	r3, [r5, #-3616]
16018
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
16019
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
16020
+	.pad #40
16021
+	sub	sp, sp, #40
16022
+	ldr	r5, .L2585
16023
+	ldr	r10, [r5, #-3612]
16024
+	cmp	r10, #0
16025
+	bne	.L2569
16026
+	ldr	r8, .L2585+4
16027
+	ldrb	r3, [r8, #152]	@ zero_extendqisi2
15560
16028
 	cmp	r3, #0
15561
-	bne	.L2630
15562
-	ldr	r8, .L2647+4
15563
-	ldrb	r6, [r8, #144]	@ zero_extendqisi2
15564
-	cmp	r6, #0
15565
-	beq	.L2646
15566
-	ldrb	r6, [r0, #8]	@ zero_extendqisi2
15567
-	cmp	r6, #1
15568
-	ldreqh	fp, [r0, #4]
15569
-	beq	.L2632
15570
-	mov	r6, r3
15571
-.L2646:
15572
-	mov	fp, #12
15573
-.L2632:
15574
-	ldr	r7, [r5, #-500]
16029
+	beq	.L2580
16030
+	ldrb	r3, [r0, #8]	@ zero_extendqisi2
16031
+	cmp	r3, #1
16032
+	ldrheq	r7, [r0, #4]
16033
+	moveq	r10, r3
16034
+	beq	.L2571
16035
+.L2580:
16036
+	mov	r7, #12
16037
+.L2571:
15575
16038
 	mvn	r3, #0
16039
+	ldr	r6, [r5, #-500]
15576
16040
 	str	r3, [sp, #20]
15577
16041
 	mov	r9, #0
15578
16042
 	ldr	r3, [r5, #-524]
15579
16043
 	movw	r2, #61589
15580
-	str	r7, [sp, #16]
16044
+	str	r6, [sp, #16]
15581
16045
 	mov	r4, r0
15582
-	ldr	r10, .L2647
15583
16046
 	str	r3, [sp, #12]
15584
16047
 	mvn	r3, #2
15585
-	str	r3, [r7, #8]
16048
+	str	r3, [r6, #8]
15586
16049
 	mvn	r3, #1
15587
-	str	r3, [r7, #12]
16050
+	str	r3, [r6, #12]
15588
16051
 	ldrh	r3, [r0]
15589
-	strh	r9, [r7]	@ movhi
15590
-	strh	r3, [r7, #2]	@ movhi
16052
+	strh	r9, [r6]	@ movhi
16053
+	strh	r3, [r6, #2]	@ movhi
15591
16054
 	ldr	r3, [r5, #-524]
15592
16055
 	str	r2, [r3]
15593
-	ldr	r2, .L2647+8
16056
+	ldr	r2, .L2585+8
15594
16057
 	ldr	r3, [r5, #-524]
15595
16058
 	str	r2, [r3, #4]
15596
-.L2633:
15597
-	subs	fp, fp, #1
15598
-	bcc	.L2636
16059
+.L2572:
16060
+	subs	r7, r7, #1
16061
+	bcc	.L2575
15599
16062
 	ldrh	r3, [r4, #4]
15600
16063
 	cmp	r3, #0
15601
-	bne	.L2634
15602
-.L2636:
16064
+	bne	.L2573
16065
+.L2575:
15603
16066
 	ldrh	r3, [r4]
15604
-	ldr	r1, [r5, #-3544]
16067
+	ldr	r1, [r5, #-3540]
15605
16068
 	ldrh	r0, [r4, #4]
15606
-	mov	r3, r3, asl #1
16069
+	lsl	r3, r3, #1
15607
16070
 	ldrh	r2, [r1, r3]
15608
-	rsb	r2, r0, r2
16071
+	sub	r2, r2, r0
15609
16072
 	strh	r2, [r1, r3]	@ movhi
15610
-	movw	r3, #2388
16073
+	movw	r3, #2390
15611
16074
 	ldrh	r3, [r8, r3]
15612
16075
 	strh	r3, [r4, #2]	@ movhi
15613
16076
 	mov	r3, #0
15614
16077
 	strb	r3, [r4, #6]
15615
16078
 	strh	r3, [r4, #4]	@ movhi
15616
-	b	.L2630
15617
-.L2634:
16079
+.L2569:
16080
+	add	sp, sp, #40
16081
+	@ sp needed
16082
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
16083
+.L2573:
15618
16084
 	mov	r0, r4
15619
16085
 	bl	get_new_active_ppa
15620
16086
 	cmn	r0, #1
15621
16087
 	str	r0, [sp, #8]
15622
-	beq	.L2636
16088
+	beq	.L2575
15623
16089
 	ldr	r3, [r5, #-3328]
16090
+	mov	r2, r10
15624
16091
 	mov	r1, #1
15625
-	mov	r2, r6
15626
16092
 	add	r0, sp, #4
15627
-	str	r3, [r7, #4]
16093
+	str	r3, [r6, #4]
15628
16094
 	add	r3, r3, #1
15629
16095
 	cmn	r3, #1
15630
16096
 	moveq	r3, r9
15631
-	str	r3, [r10, #-3328]
16097
+	str	r3, [r5, #-3328]
15632
16098
 	mov	r3, #0
15633
16099
 	bl	FlashProgPages
15634
16100
 	ldrh	r0, [r4]
15635
16101
 	bl	decrement_vpc_count
15636
-	b	.L2633
15637
-.L2630:
15638
-	add	sp, sp, #44
15639
-	@ sp needed
15640
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
15641
-.L2648:
16102
+	b	.L2572
16103
+.L2586:
15642
16104
 	.align	2
15643
-.L2647:
16105
+.L2585:
15644
16106
 	.word	.LANCHOR2
15645
16107
 	.word	.LANCHOR0
15646
16108
 	.word	305419896
..
..
@@ -15648,32 +16110,35 @@
15648
16110
 	.size	FtlSuperblockPowerLostFix, .-FtlSuperblockPowerLostFix
15649
16111
 	.align	2
15650
16112
 	.global	ftl_map_blk_gc
16113
+	.syntax unified
16114
+	.arm
16115
+	.fpu softvfp
15651
16116
 	.type	ftl_map_blk_gc, %function
15652
16117
 ftl_map_blk_gc:
15653
16118
 	.fnstart
15654
16119
 	@ args = 0, pretend = 0, frame = 8
15655
16120
 	@ frame_needed = 0, uses_anonymous_args = 0
15656
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
16121
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
15657
16122
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
15658
16123
 	.pad #12
15659
16124
 	mov	r4, r0
15660
16125
 	ldr	r5, [r0, #12]
15661
-	ldr	r7, [r0, #24]
16126
+	ldr	r10, [r0, #24]
15662
16127
 	bl	ftl_free_no_use_map_blk
15663
16128
 	ldrh	r3, [r4, #10]
15664
16129
 	ldrh	r2, [r4, #8]
16130
+	ldr	fp, .L2600
15665
16131
 	sub	r3, r3, #4
15666
-	ldr	r8, .L2663
15667
16132
 	cmp	r2, r3
15668
-	blt	.L2650
16133
+	blt	.L2588
15669
16134
 	uxth	r0, r0
15670
-	mov	r0, r0, asl #1
15671
-	ldrh	r10, [r5, r0]
15672
-	cmp	r10, #0
15673
-	beq	.L2650
16135
+	lsl	r0, r0, #1
16136
+	ldrh	r9, [r5, r0]
16137
+	cmp	r9, #0
16138
+	beq	.L2588
15674
16139
 	ldr	r3, [r4, #32]
15675
16140
 	cmp	r3, #0
15676
-	bne	.L2650
16141
+	bne	.L2588
15677
16142
 	mov	r2, #1
15678
16143
 	str	r2, [r4, #32]
15679
16144
 	strh	r3, [r5, r0]	@ movhi
..
..
@@ -15681,114 +16146,117 @@
15681
16146
 	ldrh	r2, [r4, #2]
15682
16147
 	sub	r3, r3, #1
15683
16148
 	strh	r3, [r4, #8]	@ movhi
15684
-	movw	r3, #2390
15685
-	ldrh	r3, [r8, r3]
16149
+	movw	r3, #2392
16150
+	ldrh	r3, [fp, r3]
15686
16151
 	cmp	r2, r3
15687
-	bcc	.L2651
16152
+	bcc	.L2589
15688
16153
 	mov	r0, r4
15689
16154
 	bl	ftl_map_blk_alloc_new_blk
15690
-.L2651:
15691
-	ldr	r5, .L2663+4
15692
-	mov	fp, #0
15693
-.L2652:
15694
-	ldrh	r3, [r4, #6]
15695
-	uxth	r6, fp
15696
-	cmp	r3, r6
15697
-	bls	.L2662
15698
-	ldr	r3, [r7, r6, asl #2]
15699
-	add	ip, r7, r6, asl #2
15700
-	cmp	r10, r3, lsr #10
15701
-	bne	.L2653
15702
-	ldr	r3, [r5, #-520]
16155
+.L2589:
16156
+	ldr	r5, .L2600+4
16157
+	mov	r6, #0
16158
+.L2590:
16159
+	ldrh	r2, [r4, #6]
16160
+	uxth	r3, r6
16161
+	cmp	r2, r3
16162
+	bhi	.L2595
15703
16163
 	mov	r1, #1
15704
-	ldr	r9, [r5, #-500]
15705
-	mov	r2, r1
15706
-	ldr	r0, .L2663+8
15707
-	str	r3, [r5, #1760]
15708
-	str	r9, [r5, #1764]
15709
-	ldr	r3, [r7, r6, asl #2]
15710
-	str	ip, [sp, #4]
15711
-	str	r3, [r5, #1756]
15712
-	bl	FlashReadPages
15713
-	ldr	r3, [r5, #1752]
15714
-	cmn	r3, #1
15715
-	ldr	r3, .L2663+4
15716
-	ldr	ip, [sp, #4]
15717
-	bne	.L2654
15718
-.L2656:
15719
-	mov	r2, #0
15720
-	ldr	r0, .L2663+12
15721
-	str	r2, [ip]
15722
-	ldr	r1, [r3, #1756]
15723
-	ldrh	r2, [r9, #8]
15724
-	str	r3, [sp, #4]
15725
-	bl	printk
15726
-	mov	r2, #1
15727
-	ldr	r3, [sp, #4]
15728
-	str	r2, [r3, #-3616]
15729
-	b	.L2655
15730
-.L2654:
15731
-	ldrh	r1, [r9, #8]
15732
-	cmp	r1, r6
15733
-	bne	.L2656
15734
-	ldrh	r0, [r9]
15735
-	ldrh	r2, [r4, #4]
15736
-	cmp	r0, r2
15737
-	bne	.L2656
15738
-	mov	r0, r4
15739
-	ldr	r2, [r5, #1760]
15740
-	bl	FtlMapWritePage
15741
-.L2653:
15742
-	add	fp, fp, #1
15743
-	b	.L2652
15744
-.L2662:
15745
-	mov	r0, r10
15746
-	mov	r1, #1
16164
+	mov	r0, r9
15747
16165
 	bl	FtlFreeSysBlkQueueIn
15748
16166
 	mov	r3, #0
15749
16167
 	str	r3, [r4, #32]
15750
-.L2650:
15751
-	movw	r3, #2390
16168
+.L2588:
16169
+	movw	r3, #2392
15752
16170
 	ldrh	r2, [r4, #2]
15753
-	ldrh	r3, [r8, r3]
16171
+	ldrh	r3, [fp, r3]
15754
16172
 	cmp	r2, r3
15755
-	bcc	.L2655
16173
+	bcc	.L2593
15756
16174
 	mov	r0, r4
15757
16175
 	bl	ftl_map_blk_alloc_new_blk
15758
-.L2655:
16176
+	b	.L2593
16177
+.L2595:
16178
+	uxth	r7, r6
16179
+	add	r2, r10, r7, lsl #2
16180
+	str	r2, [sp]
16181
+	ldr	r2, [r10, r7, lsl #2]
16182
+	cmp	r9, r2, lsr #10
16183
+	bne	.L2591
16184
+	ldr	r2, [r5, #-520]
16185
+	ldr	r8, [r5, #-500]
16186
+	ldr	r0, .L2600+8
16187
+	str	r2, [r5, #1768]
16188
+	str	r8, [r5, #1772]
16189
+	ldr	r2, [r10, r7, lsl #2]
16190
+	str	r3, [sp, #4]
16191
+	str	r2, [r5, #1764]
16192
+	mov	r2, #1
16193
+	mov	r1, r2
16194
+	bl	FlashReadPages
16195
+	ldr	r2, [r5, #1760]
16196
+	ldr	r3, [sp, #4]
16197
+	cmn	r2, #1
16198
+	bne	.L2592
16199
+.L2594:
16200
+	ldr	r2, [sp]
16201
+	mov	r3, #0
16202
+	ldr	r0, .L2600+12
16203
+	str	r3, [r2]
16204
+	ldrh	r2, [r8, #8]
16205
+	ldr	r1, [r5, #1764]
16206
+	bl	printk
16207
+	mov	r3, #1
16208
+	str	r3, [r5, #-3612]
16209
+.L2593:
15759
16210
 	mov	r0, #0
15760
16211
 	add	sp, sp, #12
15761
16212
 	@ sp needed
15762
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
15763
-.L2664:
16213
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
16214
+.L2592:
16215
+	ldrh	r2, [r8, #8]
16216
+	cmp	r2, r3
16217
+	bne	.L2594
16218
+	ldrh	r2, [r8]
16219
+	ldrh	r3, [r4, #4]
16220
+	cmp	r2, r3
16221
+	bne	.L2594
16222
+	ldr	r2, [r5, #1768]
16223
+	mov	r1, r7
16224
+	mov	r0, r4
16225
+	bl	FtlMapWritePage
16226
+.L2591:
16227
+	add	r6, r6, #1
16228
+	b	.L2590
16229
+.L2601:
15764
16230
 	.align	2
15765
-.L2663:
16231
+.L2600:
15766
16232
 	.word	.LANCHOR0
15767
16233
 	.word	.LANCHOR2
15768
-	.word	.LANCHOR2+1752
16234
+	.word	.LANCHOR2+1760
15769
16235
 	.word	.LC133
15770
16236
 	.fnend
15771
16237
 	.size	ftl_map_blk_gc, .-ftl_map_blk_gc
15772
16238
 	.align	2
15773
16239
 	.global	Ftl_write_map_blk_to_last_page
16240
+	.syntax unified
16241
+	.arm
16242
+	.fpu softvfp
15774
16243
 	.type	Ftl_write_map_blk_to_last_page, %function
15775
16244
 Ftl_write_map_blk_to_last_page:
15776
16245
 	.fnstart
15777
16246
 	@ args = 0, pretend = 0, frame = 0
15778
16247
 	@ frame_needed = 0, uses_anonymous_args = 0
15779
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
16248
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
15780
16249
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
15781
-	ldr	r5, .L2677
15782
-	ldr	r7, [r0, #12]
15783
-	ldr	r9, [r0, #24]
15784
-	ldr	r6, [r5, #-3616]
16250
+	ldr	r5, .L2613
16251
+	ldr	r6, [r5, #-3612]
15785
16252
 	cmp	r6, #0
15786
-	bne	.L2666
16253
+	bne	.L2603
15787
16254
 	ldrh	r3, [r0]
15788
16255
 	movw	r2, #65535
15789
16256
 	mov	r4, r0
16257
+	ldr	r7, [r0, #12]
15790
16258
 	cmp	r3, r2
15791
-	bne	.L2667
16259
+	bne	.L2604
15792
16260
 	ldrh	r3, [r0, #8]
15793
16261
 	add	r3, r3, #1
15794
16262
 	strh	r3, [r0, #8]	@ movhi
..
..
@@ -15796,479 +16264,346 @@
15796
16264
 	strh	r0, [r7]	@ movhi
15797
16265
 	ldr	r3, [r4, #28]
15798
16266
 	strh	r6, [r4, #2]	@ movhi
15799
-	add	r3, r3, #1
15800
16267
 	strh	r6, [r4]	@ movhi
16268
+	add	r3, r3, #1
15801
16269
 	str	r3, [r4, #28]
15802
-	b	.L2666
15803
-.L2667:
15804
-	mov	r3, r3, asl #1
15805
-	ldr	r10, .L2677+4
16270
+.L2603:
16271
+	mov	r0, #0
16272
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
16273
+.L2604:
16274
+	lsl	r3, r3, #1
16275
+	ldr	r8, [r0, #24]
16276
+	ldr	r10, .L2613+4
15806
16277
 	mov	r1, #255
15807
-	ldrh	r8, [r7, r3]
16278
+	ldrh	r9, [r7, r3]
15808
16279
 	ldrh	r3, [r0, #2]
15809
16280
 	ldr	r7, [r5, #-500]
15810
-	orr	r3, r3, r8, asl #10
15811
-	str	r3, [r5, #1756]
16281
+	orr	r3, r3, r9, lsl #10
16282
+	str	r7, [r5, #1772]
16283
+	str	r3, [r5, #1764]
15812
16284
 	ldr	r3, [r5, #-524]
15813
-	str	r7, [r5, #1764]
15814
-	str	r3, [r5, #1760]
16285
+	str	r3, [r5, #1768]
15815
16286
 	ldr	r3, [r0, #28]
15816
16287
 	str	r3, [r7, #4]
15817
-	ldr	r3, .L2677+8
16288
+	ldr	r3, .L2613+8
15818
16289
 	strh	r3, [r7, #8]	@ movhi
15819
16290
 	ldrh	r3, [r0, #4]
15820
-	strh	r8, [r7, #2]	@ movhi
16291
+	strh	r9, [r7, #2]	@ movhi
15821
16292
 	strh	r3, [r7]	@ movhi
15822
-	movw	r3, #2390
16293
+	movw	r3, #2392
15823
16294
 	ldrh	r2, [r10, r3]
15824
16295
 	ldr	r0, [r5, #-524]
15825
-	mov	r2, r2, asl #3
16296
+	lsl	r2, r2, #3
15826
16297
 	bl	ftl_memset
15827
16298
 	mov	r2, r6
15828
-.L2668:
15829
-	ldrh	r1, [r4, #6]
15830
-	uxth	r3, r2
15831
-	cmp	r1, r3
15832
-	bls	.L2676
15833
-	ldr	r1, [r9, r3, asl #2]
15834
-	cmp	r8, r1, lsr #10
15835
-	bne	.L2669
15836
-	add	r6, r6, #1
15837
-	ldr	r1, [r5, #-524]
15838
-	uxth	r6, r6
15839
-	str	r3, [r1, r6, asl #3]
15840
-	ldr	r1, [r9, r3, asl #2]
15841
-	ldr	r3, [r5, #-524]
15842
-	add	r3, r3, r6, asl #3
15843
-	str	r1, [r3, #4]
15844
-.L2669:
15845
-	add	r2, r2, #1
15846
-	b	.L2668
15847
-.L2676:
15848
-	ldrb	r3, [r10]	@ zero_extendqisi2
16299
+	mov	r3, r6
16300
+.L2605:
16301
+	ldrh	r0, [r4, #6]
16302
+	uxth	r1, r2
16303
+	cmp	r0, r1
16304
+	bhi	.L2607
16305
+	ldrb	r3, [r10, #36]	@ zero_extendqisi2
15849
16306
 	cmp	r3, #0
15850
-	beq	.L2671
15851
-	ldr	r2, .L2677+4
15852
-	movw	r3, #2398
15853
-	ldr	r0, [r5, #1760]
15854
-	ldrh	r1, [r2, r3]
16307
+	beq	.L2608
16308
+	ldr	r3, .L2613+12
16309
+	ldr	r0, [r5, #1768]
16310
+	ldrh	r1, [r3]
15855
16311
 	bl	js_hash
15856
16312
 	str	r0, [r7, #12]
15857
-.L2671:
15858
-	mov	r1, #1
16313
+.L2608:
16314
+	mov	r2, #1
15859
16315
 	mov	r3, #0
15860
-	ldr	r0, .L2677+12
15861
-	mov	r2, r1
16316
+	mov	r1, r2
16317
+	ldr	r0, .L2613+16
15862
16318
 	bl	FlashProgPages
15863
16319
 	ldrh	r3, [r4, #2]
15864
16320
 	mov	r0, r4
15865
16321
 	add	r3, r3, #1
15866
16322
 	strh	r3, [r4, #2]	@ movhi
15867
16323
 	bl	ftl_map_blk_gc
15868
-.L2666:
15869
-	mov	r0, #0
15870
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
15871
-.L2678:
16324
+	b	.L2603
16325
+.L2607:
16326
+	uxth	r1, r2
16327
+	ldr	r0, [r8, r1, lsl #2]
16328
+	cmp	r9, r0, lsr #10
16329
+	bne	.L2606
16330
+	ldr	r0, [r5, #-524]
16331
+	add	r3, r3, #1
16332
+	uxth	r3, r3
16333
+	str	r1, [r0, r3, lsl #3]
16334
+	ldr	r0, [r8, r1, lsl #2]
16335
+	ldr	r1, [r5, #-524]
16336
+	add	r1, r1, r3, lsl #3
16337
+	str	r0, [r1, #4]
16338
+.L2606:
16339
+	add	r2, r2, #1
16340
+	b	.L2605
16341
+.L2614:
15872
16342
 	.align	2
15873
-.L2677:
16343
+.L2613:
15874
16344
 	.word	.LANCHOR2
15875
16345
 	.word	.LANCHOR0
15876
16346
 	.word	-1291
15877
-	.word	.LANCHOR2+1752
16347
+	.word	.LANCHOR0+2400
16348
+	.word	.LANCHOR2+1760
15878
16349
 	.fnend
15879
16350
 	.size	Ftl_write_map_blk_to_last_page, .-Ftl_write_map_blk_to_last_page
15880
16351
 	.align	2
15881
16352
 	.global	FtlMapWritePage
16353
+	.syntax unified
16354
+	.arm
16355
+	.fpu softvfp
15882
16356
 	.type	FtlMapWritePage, %function
15883
16357
 FtlMapWritePage:
15884
16358
 	.fnstart
15885
16359
 	@ args = 0, pretend = 0, frame = 8
15886
16360
 	@ frame_needed = 0, uses_anonymous_args = 0
15887
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
16361
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
15888
16362
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
15889
16363
 	.pad #12
15890
16364
 	mov	r4, r0
15891
-	ldr	r10, .L2698
15892
-	mov	r8, r1
15893
-	ldr	fp, .L2698+4
15894
-	mov	r5, #0
15895
-	str	r2, [sp]
15896
-	mov	r9, r10
15897
-.L2680:
15898
-	ldr	r3, [r10, #-3348]
15899
-	ldr	r6, .L2698
16365
+	ldr	r7, .L2634
16366
+	mov	r9, r1
16367
+	mov	fp, r2
16368
+	mov	r6, #0
16369
+	ldr	r10, .L2634+4
16370
+	mov	r5, r7
16371
+.L2616:
16372
+	ldr	r3, [r7, #-3348]
15900
16373
 	add	r3, r3, #1
15901
-	str	r3, [r10, #-3348]
15902
-	ldrh	r3, [fp]
16374
+	str	r3, [r7, #-3348]
16375
+	ldrh	r3, [r10]
15903
16376
 	ldrh	r2, [r4, #2]
15904
16377
 	sub	r3, r3, #1
15905
16378
 	cmp	r2, r3
15906
-	bge	.L2681
16379
+	bge	.L2617
15907
16380
 	ldrh	r2, [r4]
15908
16381
 	movw	r3, #65535
15909
16382
 	cmp	r2, r3
15910
-	bne	.L2682
15911
-.L2681:
16383
+	bne	.L2618
16384
+.L2617:
15912
16385
 	mov	r0, r4
15913
16386
 	bl	Ftl_write_map_blk_to_last_page
15914
-.L2682:
15915
-	ldr	r1, [r9, #-3616]
16387
+.L2618:
16388
+	ldr	r1, [r5, #-3612]
15916
16389
 	cmp	r1, #0
15917
-	bne	.L2683
16390
+	bne	.L2619
15918
16391
 	ldrh	r3, [r4]
15919
16392
 	ldr	r2, [r4, #12]
15920
-	ldr	r0, [r10, #-500]
15921
-	mov	r3, r3, asl #1
15922
-	ldrh	r7, [r2, r3]
16393
+	ldr	r0, [r5, #-500]
16394
+	lsl	r3, r3, #1
16395
+	ldrh	r8, [r2, r3]
15923
16396
 	mov	r2, #16
15924
16397
 	ldrh	r3, [r4, #2]
15925
-	str	r0, [r10, #1764]
15926
-	orr	r3, r3, r7, asl #10
15927
-	str	r3, [r10, #1756]
15928
-	ldr	r3, [sp]
15929
-	str	r3, [r10, #1760]
16398
+	str	fp, [r5, #1768]
16399
+	str	r0, [r5, #1772]
16400
+	orr	r3, r3, r8, lsl #10
16401
+	str	r3, [r5, #1764]
15930
16402
 	bl	ftl_memset
16403
+	ldr	r3, [r5, #1772]
15931
16404
 	ldr	r2, [r4, #28]
15932
-	ldr	r3, [r10, #1764]
16405
+	strh	r9, [r3, #8]	@ movhi
15933
16406
 	str	r2, [r3, #4]
15934
-	strh	r8, [r3, #8]	@ movhi
15935
16407
 	ldrh	r2, [r4, #4]
15936
-	strh	r7, [r3, #2]	@ movhi
15937
-	strh	r2, [r3]	@ movhi
15938
-	ldr	r2, .L2698+8
15939
-	ldrb	r2, [r2]	@ zero_extendqisi2
15940
-	cmp	r2, #0
15941
-	beq	.L2684
15942
-	ldr	r2, .L2698+12
15943
-	ldr	r0, [r10, #1760]
15944
16408
 	str	r3, [sp, #4]
16409
+	strh	r8, [r3, #2]	@ movhi
16410
+	strh	r2, [r3]	@ movhi
16411
+	ldr	r2, .L2634+8
16412
+	ldrb	r1, [r2, #36]	@ zero_extendqisi2
16413
+	cmp	r1, #0
16414
+	beq	.L2620
16415
+	add	r2, r2, #2400
16416
+	ldr	r0, [r5, #1768]
15945
16417
 	ldrh	r1, [r2]
15946
16418
 	bl	js_hash
15947
16419
 	ldr	r3, [sp, #4]
15948
16420
 	str	r0, [r3, #12]
15949
-.L2684:
15950
-	mov	r1, #1
15951
-	ldr	r0, .L2698+16
15952
-	mov	r2, r1
15953
-	mov	r3, r1
16421
+.L2620:
16422
+	mov	r3, #1
16423
+	ldr	r0, .L2634+12
16424
+	mov	r2, r3
16425
+	mov	r1, r3
15954
16426
 	bl	FlashProgPages
15955
16427
 	ldrh	r3, [r4, #2]
15956
16428
 	add	r3, r3, #1
15957
16429
 	uxth	r3, r3
15958
16430
 	strh	r3, [r4, #2]	@ movhi
15959
-	ldr	r2, [r9, #1752]
16431
+	ldr	r2, [r5, #1760]
15960
16432
 	cmn	r2, #1
15961
-	bne	.L2685
15962
-	ldr	r0, .L2698+20
15963
-	add	r5, r5, #1
15964
-	ldr	r1, [r10, #1756]
16433
+	bne	.L2621
16434
+	ldr	r1, [r5, #1764]
16435
+	add	r6, r6, #1
16436
+	ldr	r0, .L2634+16
16437
+	uxth	r6, r6
15965
16438
 	bl	printk
15966
16439
 	ldrh	r3, [r4, #2]
15967
-	uxth	r5, r5
15968
16440
 	cmp	r3, #2
15969
-	ldrls	r3, .L2698+4
15970
-	ldrlsh	r3, [r3]
16441
+	ldrhls	r3, [r10]
15971
16442
 	subls	r3, r3, #1
15972
-	strlsh	r3, [r4, #2]	@ movhi
15973
-	cmp	r5, #3
15974
-	bls	.L2680
15975
-	ldr	r0, .L2698+24
15976
-	mov	r2, r5
15977
-	ldr	r1, [r6, #1756]
16443
+	strhls	r3, [r4, #2]	@ movhi
16444
+	cmp	r6, #3
16445
+	bls	.L2616
16446
+	mov	r2, r6
16447
+	ldr	r1, [r5, #1764]
16448
+	ldr	r0, .L2634+20
15978
16449
 	bl	printk
15979
16450
 	mov	r3, #1
15980
-	str	r3, [r6, #-3616]
15981
-	b	.L2683
15982
-.L2685:
15983
-	cmp	r2, #0
15984
-	strneh	r7, [r4, #40]	@ movhi
15985
-	cmp	r2, #256
15986
-	cmpne	r3, #1
15987
-	beq	.L2689
15988
-	ldr	r3, [r4, #36]
15989
-	cmp	r3, #0
15990
-	beq	.L2690
15991
-.L2689:
15992
-	mov	r3, #0
15993
-	str	r3, [r4, #36]
15994
-	b	.L2680
15995
-.L2690:
15996
-	ldr	r2, [r6, #1756]
15997
-	ldr	r3, [r4, #24]
15998
-	str	r2, [r3, r8, asl #2]
15999
-.L2683:
16451
+	str	r3, [r5, #-3612]
16452
+.L2619:
16000
16453
 	mov	r0, #0
16001
16454
 	add	sp, sp, #12
16002
16455
 	@ sp needed
16003
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
16004
-.L2699:
16456
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
16457
+.L2621:
16458
+	cmp	r2, #0
16459
+	strhne	r8, [r4, #40]	@ movhi
16460
+	cmp	r3, #1
16461
+	cmpne	r2, #256
16462
+	beq	.L2625
16463
+	ldr	r3, [r4, #36]
16464
+	cmp	r3, #0
16465
+	beq	.L2626
16466
+.L2625:
16467
+	mov	r3, #0
16468
+	str	r3, [r4, #36]
16469
+	b	.L2616
16470
+.L2626:
16471
+	ldr	r2, [r5, #1764]
16472
+	ldr	r3, [r4, #24]
16473
+	str	r2, [r3, r9, lsl #2]
16474
+	b	.L2619
16475
+.L2635:
16005
16476
 	.align	2
16006
-.L2698:
16477
+.L2634:
16007
16478
 	.word	.LANCHOR2
16008
-	.word	.LANCHOR0+2390
16479
+	.word	.LANCHOR0+2392
16009
16480
 	.word	.LANCHOR0
16010
-	.word	.LANCHOR0+2398
16011
-	.word	.LANCHOR2+1752
16481
+	.word	.LANCHOR2+1760
16012
16482
 	.word	.LC134
16013
16483
 	.word	.LC135
16014
16484
 	.fnend
16015
16485
 	.size	FtlMapWritePage, .-FtlMapWritePage
16016
16486
 	.align	2
16017
16487
 	.global	flush_l2p_region
16488
+	.syntax unified
16489
+	.arm
16490
+	.fpu softvfp
16018
16491
 	.type	flush_l2p_region, %function
16019
16492
 flush_l2p_region:
16020
16493
 	.fnstart
16021
16494
 	@ args = 0, pretend = 0, frame = 0
16022
16495
 	@ frame_needed = 0, uses_anonymous_args = 0
16023
-	stmfd	sp!, {r3, r4, r5, lr}
16024
-	.save {r3, r4, r5, lr}
16496
+	push	{r4, r5, r6, lr}
16497
+	.save {r4, r5, r6, lr}
16025
16498
 	mov	r4, #12
16026
-	ldr	r5, .L2702
16499
+	ldr	r5, .L2638
16027
16500
 	mul	r4, r4, r0
16501
+	ldr	r3, [r5, #-3376]
16028
16502
 	sub	r0, r5, #432
16029
-	ldr	r3, [r5, #-3380]
16030
16503
 	add	r2, r3, r4
16031
16504
 	ldrh	r1, [r3, r4]
16032
16505
 	ldr	r2, [r2, #8]
16033
16506
 	bl	FtlMapWritePage
16034
-	ldr	r3, [r5, #-3380]
16507
+	ldr	r3, [r5, #-3376]
16035
16508
 	mov	r0, #0
16036
16509
 	add	r4, r3, r4
16037
16510
 	ldr	r3, [r4, #4]
16038
16511
 	bic	r3, r3, #-2147483648
16039
16512
 	str	r3, [r4, #4]
16040
-	ldmfd	sp!, {r3, r4, r5, pc}
16041
-.L2703:
16513
+	pop	{r4, r5, r6, pc}
16514
+.L2639:
16042
16515
 	.align	2
16043
-.L2702:
16516
+.L2638:
16044
16517
 	.word	.LANCHOR2
16045
16518
 	.fnend
16046
16519
 	.size	flush_l2p_region, .-flush_l2p_region
16047
16520
 	.align	2
16048
16521
 	.global	FtlMapTblRecovery
16522
+	.syntax unified
16523
+	.arm
16524
+	.fpu softvfp
16049
16525
 	.type	FtlMapTblRecovery, %function
16050
16526
 FtlMapTblRecovery:
16051
16527
 	.fnstart
16052
16528
 	@ args = 0, pretend = 0, frame = 24
16053
16529
 	@ frame_needed = 0, uses_anonymous_args = 0
16054
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16530
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
16055
16531
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16056
16532
 	.pad #28
16057
16533
 	sub	sp, sp, #28
16058
-	ldr	r3, [r0, #16]
16534
+	ldr	r3, [r0, #24]
16059
16535
 	mov	r4, r0
16060
-	ldrh	r10, [r0, #6]
16061
16536
 	mov	r1, #0
16062
-	ldr	r8, [r0, #24]
16537
+	mov	r7, #0
16538
+	ldr	r5, .L2682
16539
+	str	r3, [sp]
16540
+	ldr	r3, [r0, #16]
16541
+	ldr	r8, [r0, #12]
16542
+	ldr	fp, .L2682+4
16063
16543
 	str	r3, [sp, #12]
16544
+	ldrh	r3, [r0, #6]
16545
+	str	r3, [sp, #4]
16064
16546
 	ldrh	r3, [r0, #8]
16065
-	mov	r2, r10, asl #2
16066
-	ldr	r9, [r0, #12]
16067
-	mov	r0, r8
16547
+	ldr	r0, [sp]
16068
16548
 	str	r3, [sp, #8]
16549
+	ldr	r3, [sp, #4]
16550
+	lsl	r2, r3, #2
16069
16551
 	bl	ftl_memset
16070
-	ldr	r1, .L2747
16071
-	mov	r2, #1
16072
-	str	r2, [r4, #36]
16073
-	ldr	r3, [r1, #-524]
16074
-	mov	r5, r1
16075
-	ldr	r6, [r1, #-500]
16076
-	mov	r7, r1
16077
-	str	r3, [r1, #1760]
16552
+	ldr	r3, [r5, #-524]
16553
+	ldr	r6, [r5, #-500]
16554
+	str	r7, [r4, #32]
16555
+	str	r3, [r5, #1768]
16078
16556
 	mvn	r3, #0
16079
-	str	r6, [r1, #1764]
16557
+	str	r6, [r5, #1772]
16080
16558
 	strh	r3, [r4]	@ movhi
16081
16559
 	strh	r3, [r4, #2]	@ movhi
16082
-	mov	r3, #0
16083
-	str	r3, [r4, #32]
16084
-	str	r3, [r4, #28]
16085
-	str	r3, [sp, #4]
16086
-.L2705:
16087
-	ldrh	r3, [sp, #4]
16088
-	ldr	r2, [sp, #8]
16089
-	sxth	fp, r3
16090
-	cmp	fp, r2
16091
-	bge	.L2723
16092
-	ldr	r2, [sp, #8]
16093
-	sub	r2, r2, #1
16094
-	cmp	fp, r2
16095
-	mov	r2, fp, asl #1
16096
-	bne	.L2706
16097
-	ldrh	r0, [r9, r2]
16560
+	mov	r3, #1
16561
+	str	r7, [r4, #28]
16562
+	str	r3, [r4, #36]
16563
+.L2641:
16564
+	ldr	r3, [sp, #8]
16565
+	sxth	r10, r7
16566
+	cmp	r10, r3
16567
+	bge	.L2660
16568
+	ldr	r3, [sp, #8]
16569
+	sub	r3, r3, #1
16570
+	cmp	r10, r3
16571
+	lsl	r3, r10, #1
16572
+	bne	.L2642
16573
+	ldrh	r0, [r8, r3]
16098
16574
 	mov	r1, #1
16099
-	str	r3, [sp, #8]
16100
-	add	r3, r9, r2
16101
-	str	r3, [sp, #4]
16575
+	add	r9, r8, r3
16576
+	mov	r8, #0
16102
16577
 	bl	FtlGetLastWrittenPage
16103
-	mov	r7, #0
16104
-	ldr	r3, [sp, #8]
16105
-	add	r2, r0, #1
16106
-	strh	r2, [r4, #2]	@ movhi
16107
-	sxth	r0, r0
16108
-	add	r9, r0, #1
16109
-	strh	r3, [r4]	@ movhi
16110
-	ldr	r3, [sp, #12]
16111
-	ldr	r3, [r3, fp, asl #2]
16112
-	ldr	fp, .L2747
16113
-	str	r3, [r4, #28]
16114
-.L2707:
16115
-	sxth	r3, r7
16116
-	cmp	r3, r9
16117
-	bge	.L2723
16118
-	ldr	r2, [sp, #4]
16119
-	mov	r1, #1
16120
-	ldr	r0, .L2747+4
16121
-	ldrh	r2, [r2]
16122
-	orr	r3, r3, r2, asl #10
16123
-	mov	r2, r1
16124
-	str	r3, [r5, #1756]
16125
-	bl	FlashReadPages
16126
-	ldr	r3, .L2747+8
16127
-	ldrb	r3, [r3]	@ zero_extendqisi2
16128
-	cmp	r3, #0
16129
-	beq	.L2708
16130
-	ldr	r3, [fp, #1764]
16131
-	ldr	r3, [r3, #12]
16132
-	cmp	r3, #0
16133
-	beq	.L2708
16134
-	ldr	r2, .L2747+12
16135
-	ldr	r0, [fp, #1760]
16578
+	sxth	r3, r0
16579
+	strh	r7, [r4]	@ movhi
16580
+	add	r0, r0, #1
16581
+	ldr	r7, .L2682+8
16136
16582
 	str	r3, [sp, #8]
16137
-	ldrh	r1, [r2]
16138
-	bl	js_hash
16583
+	ldr	r3, [sp, #12]
16584
+	strh	r0, [r4, #2]	@ movhi
16585
+	add	fp, r7, #2400
16586
+	ldr	r3, [r3, r10, lsl #2]
16587
+	ldr	r10, .L2682+12
16588
+	str	r3, [r4, #28]
16589
+.L2643:
16139
16590
 	ldr	r3, [sp, #8]
16140
-	cmp	r3, r0
16141
-	mvnne	r3, #0
16142
-	strne	r3, [fp, #1752]
16143
-.L2708:
16144
-	ldr	r3, [fp, #1752]
16145
-	cmn	r3, #1
16146
-	beq	.L2709
16147
-	ldrh	r3, [r6, #8]
16148
-	cmp	r3, r10
16149
-	bcs	.L2709
16150
-	ldrh	r2, [r4, #4]
16151
-	ldrh	r1, [r6]
16152
-	cmp	r1, r2
16153
-	ldreq	r2, [fp, #1756]
16154
-	streq	r2, [r8, r3, asl #2]
16155
-.L2709:
16156
-	add	r7, r7, #1
16157
-	b	.L2707
16158
-.L2723:
16591
+	sxth	r2, r8
16592
+	add	r1, r3, #1
16593
+	cmp	r2, r1
16594
+	blt	.L2646
16595
+.L2660:
16159
16596
 	mov	r0, r4
16160
16597
 	bl	ftl_free_no_use_map_blk
16161
-	ldr	r1, .L2747+8
16162
-	movw	r3, #2390
16598
+	ldr	r1, .L2682+8
16599
+	movw	r3, #2392
16163
16600
 	ldrh	r2, [r4, #2]
16164
16601
 	ldrh	r3, [r1, r3]
16165
16602
 	cmp	r2, r3
16166
-	bne	.L2712
16603
+	bne	.L2648
16167
16604
 	mov	r0, r4
16168
16605
 	bl	ftl_map_blk_alloc_new_blk
16169
-	b	.L2712
16170
-.L2706:
16171
-	ldr	r3, [r5, #-524]
16172
-	mov	r1, #1
16173
-	ldr	fp, .L2747+16
16174
-	ldr	r0, .L2747+4
16175
-	str	r3, [r5, #1760]
16176
-	add	r3, r9, r2
16177
-	ldrh	r2, [r9, r2]
16178
-	str	r3, [sp, #16]
16179
-	ldrh	r3, [fp]
16180
-	sub	r3, r3, #1
16181
-	orr	r3, r3, r2, asl #10
16182
-	mov	r2, r1
16183
-	str	r3, [r5, #1756]
16184
-	bl	FlashReadPages
16185
-	ldr	r3, [r5, #1752]
16186
-	cmn	r3, #1
16187
-	mov	r3, fp
16188
-	beq	.L2725
16189
-	ldrh	r1, [r6]
16190
-	ldrh	r2, [r4, #4]
16191
-	cmp	r1, r2
16192
-	bne	.L2725
16193
-	ldrh	r1, [r6, #8]
16194
-	movw	r2, #64245
16195
-	cmp	r1, r2
16196
-	bne	.L2725
16197
-	mov	r0, #0
16198
-	mov	lr, #8
16199
-	mov	fp, #4
16200
-.L2714:
16201
-	uxth	r2, r0
16202
-	ldrh	ip, [r3]
16203
-	sxth	r1, r2
16204
-	sub	ip, ip, #1
16205
-	cmp	r1, ip
16206
-	bge	.L2717
16207
-	ldr	ip, [r5, #-524]
16208
-	add	r0, r0, #1
16209
-	ldr	r1, [ip, r1, asl #3]
16210
-	uxth	r1, r1
16211
-	cmp	r1, r10
16212
-	smlabbcc	r2, r2, lr, fp
16213
-	ldrcc	r2, [ip, r2]
16214
-	strcc	r2, [r8, r1, asl #2]
16215
-	b	.L2714
16216
-.L2725:
16217
-	mov	fp, #0
16218
-.L2745:
16219
-	ldr	r3, .L2747+16
16220
-	sxth	r2, fp
16221
-	ldrh	r1, [r3]
16222
-	cmp	r2, r1
16223
-	bge	.L2717
16224
-	str	r3, [sp, #20]
16225
-	ldr	r3, [sp, #16]
16226
-	ldr	r0, .L2747+4
16227
-	ldrh	r1, [r3]
16228
-	orr	r2, r2, r1, asl #10
16229
-	mov	r1, #1
16230
-	str	r2, [r7, #1756]
16231
-	mov	r2, r1
16232
-	bl	FlashReadPages
16233
-	ldr	r3, .L2747+8
16234
-	ldrb	r2, [r3]	@ zero_extendqisi2
16235
-	cmp	r2, #0
16236
-	ldr	r3, [sp, #20]
16237
-	beq	.L2718
16238
-	ldr	r2, [r7, #1764]
16239
-	ldr	r2, [r2, #12]
16240
-	cmp	r2, #0
16241
-	beq	.L2718
16242
-	ldrh	r1, [r3, #8]
16243
-	ldr	r0, [r7, #1760]
16244
-	str	r2, [sp, #20]
16245
-	bl	js_hash
16246
-	ldr	r2, [sp, #20]
16247
-	cmp	r2, r0
16248
-	mvnne	r3, #0
16249
-	strne	r3, [r7, #1752]
16250
-.L2718:
16251
-	ldr	r3, .L2747
16252
-	ldr	r3, [r3, #1752]
16253
-	cmn	r3, #1
16254
-	beq	.L2719
16255
-	ldrh	r3, [r6, #8]
16256
-	cmp	r3, r10
16257
-	bcs	.L2719
16258
-	ldrh	r2, [r4, #4]
16259
-	ldrh	r1, [r6]
16260
-	cmp	r1, r2
16261
-	ldreq	r2, [r7, #1756]
16262
-	streq	r2, [r8, r3, asl #2]
16263
-.L2719:
16264
-	add	fp, fp, #1
16265
-	b	.L2745
16266
-.L2717:
16267
-	ldr	r3, [sp, #4]
16268
-	add	r3, r3, #1
16269
-	str	r3, [sp, #4]
16270
-	b	.L2705
16271
-.L2712:
16606
+.L2648:
16272
16607
 	mov	r0, r4
16273
16608
 	bl	ftl_map_blk_gc
16274
16609
 	mov	r0, r4
..
..
@@ -16276,54 +16611,199 @@
16276
16611
 	mov	r0, #0
16277
16612
 	add	sp, sp, #28
16278
16613
 	@ sp needed
16279
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
16280
-.L2748:
16614
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
16615
+.L2646:
16616
+	ldrh	r1, [r9]
16617
+	mov	r0, r10
16618
+	orr	r2, r2, r1, lsl #10
16619
+	str	r2, [r5, #1764]
16620
+	mov	r2, #1
16621
+	mov	r1, r2
16622
+	bl	FlashReadPages
16623
+	ldrb	r2, [r7, #36]	@ zero_extendqisi2
16624
+	cmp	r2, #0
16625
+	beq	.L2644
16626
+	ldr	r2, [r5, #1772]
16627
+	ldr	r2, [r2, #12]
16628
+	cmp	r2, #0
16629
+	str	r2, [sp, #12]
16630
+	beq	.L2644
16631
+	ldrh	r1, [fp]
16632
+	ldr	r0, [r5, #1768]
16633
+	bl	js_hash
16634
+	ldr	r2, [sp, #12]
16635
+	cmp	r2, r0
16636
+	mvnne	r2, #0
16637
+	strne	r2, [r5, #1760]
16638
+.L2644:
16639
+	ldr	r1, .L2682
16640
+	ldr	r2, [r1, #1760]
16641
+	cmn	r2, #1
16642
+	beq	.L2645
16643
+	ldrh	r2, [r6, #8]
16644
+	ldr	r3, [sp, #4]
16645
+	cmp	r3, r2
16646
+	bls	.L2645
16647
+	ldrh	ip, [r6]
16648
+	ldrh	r0, [r4, #4]
16649
+	cmp	ip, r0
16650
+	ldreq	r1, [r1, #1764]
16651
+	ldreq	r3, [sp]
16652
+	streq	r1, [r3, r2, lsl #2]
16653
+.L2645:
16654
+	add	r8, r8, #1
16655
+	b	.L2643
16656
+.L2642:
16657
+	ldr	r2, [r5, #-524]
16658
+	ldr	r0, .L2682+12
16659
+	str	r2, [r5, #1768]
16660
+	add	r2, r8, r3
16661
+	str	r2, [sp, #16]
16662
+	ldrh	r2, [r8, r3]
16663
+	ldrh	r3, [fp]
16664
+	sub	r3, r3, #1
16665
+	orr	r3, r3, r2, lsl #10
16666
+	mov	r2, #1
16667
+	mov	r1, r2
16668
+	str	r3, [r5, #1764]
16669
+	bl	FlashReadPages
16670
+	ldr	r3, [r5, #1760]
16671
+	cmn	r3, #1
16672
+	beq	.L2662
16673
+	ldrh	r2, [r6]
16674
+	ldrh	r3, [r4, #4]
16675
+	cmp	r2, r3
16676
+	bne	.L2662
16677
+	ldrh	r2, [r6, #8]
16678
+	movw	r3, #64245
16679
+	cmp	r2, r3
16680
+	beq	.L2650
16681
+.L2662:
16682
+	ldr	r9, .L2682
16683
+	mov	r10, #0
16684
+.L2651:
16685
+	ldrh	r2, [fp]
16686
+	sxth	r3, r10
16687
+	cmp	r3, r2
16688
+	bge	.L2658
16689
+	ldr	r2, [sp, #16]
16690
+	ldr	r0, .L2682+12
16691
+	ldrh	r2, [r2]
16692
+	orr	r3, r3, r2, lsl #10
16693
+	mov	r2, #1
16694
+	mov	r1, r2
16695
+	str	r3, [r9, #1764]
16696
+	bl	FlashReadPages
16697
+	ldr	r3, .L2682+8
16698
+	ldrb	r3, [r3, #36]	@ zero_extendqisi2
16699
+	cmp	r3, #0
16700
+	beq	.L2655
16701
+	ldr	r3, [r9, #1772]
16702
+	ldr	r3, [r3, #12]
16703
+	cmp	r3, #0
16704
+	str	r3, [sp, #20]
16705
+	beq	.L2655
16706
+	ldr	r2, .L2682+16
16707
+	ldr	r0, [r9, #1768]
16708
+	ldrh	r1, [r2]
16709
+	bl	js_hash
16710
+	ldr	r3, [sp, #20]
16711
+	cmp	r3, r0
16712
+	mvnne	r3, #0
16713
+	strne	r3, [r9, #1760]
16714
+.L2655:
16715
+	ldr	r3, [r9, #1760]
16716
+	cmn	r3, #1
16717
+	beq	.L2656
16718
+	ldrh	r3, [r6, #8]
16719
+	ldr	r2, [sp, #4]
16720
+	cmp	r2, r3
16721
+	bls	.L2656
16722
+	ldrh	r1, [r6]
16723
+	ldrh	r2, [r4, #4]
16724
+	cmp	r1, r2
16725
+	ldreq	r2, [r9, #1764]
16726
+	ldreq	r1, [sp]
16727
+	streq	r2, [r1, r3, lsl #2]
16728
+.L2656:
16729
+	add	r10, r10, #1
16730
+	b	.L2651
16731
+.L2650:
16732
+	mov	r1, #0
16733
+	mov	ip, #4
16734
+.L2652:
16735
+	ldrh	r2, [fp]
16736
+	sxth	r3, r1
16737
+	sub	r2, r2, #1
16738
+	cmp	r3, r2
16739
+	blt	.L2654
16740
+.L2658:
16741
+	add	r7, r7, #1
16742
+	b	.L2641
16743
+.L2654:
16744
+	ldr	r0, [r5, #-524]
16745
+	add	r1, r1, #1
16746
+	ldr	r9, [sp, #4]
16747
+	ldr	r2, [r0, r3, lsl #3]
16748
+	uxth	lr, r2
16749
+	cmp	r9, lr
16750
+	addhi	r3, ip, r3, lsl #3
16751
+	movhi	r2, lr
16752
+	ldrhi	r3, [r0, r3]
16753
+	ldrhi	r0, [sp]
16754
+	strhi	r3, [r0, r2, lsl #2]
16755
+	b	.L2652
16756
+.L2683:
16281
16757
 	.align	2
16282
-.L2747:
16758
+.L2682:
16283
16759
 	.word	.LANCHOR2
16284
-	.word	.LANCHOR2+1752
16760
+	.word	.LANCHOR0+2392
16285
16761
 	.word	.LANCHOR0
16286
-	.word	.LANCHOR0+2398
16287
-	.word	.LANCHOR0+2390
16762
+	.word	.LANCHOR2+1760
16763
+	.word	.LANCHOR0+2400
16288
16764
 	.fnend
16289
16765
 	.size	FtlMapTblRecovery, .-FtlMapTblRecovery
16290
16766
 	.align	2
16291
16767
 	.global	FtlLoadVonderInfo
16768
+	.syntax unified
16769
+	.arm
16770
+	.fpu softvfp
16292
16771
 	.type	FtlLoadVonderInfo, %function
16293
16772
 FtlLoadVonderInfo:
16294
16773
 	.fnstart
16295
16774
 	@ args = 0, pretend = 0, frame = 0
16296
16775
 	@ frame_needed = 0, uses_anonymous_args = 0
16297
-	ldr	r2, .L2751
16298
-	movw	r1, #2408
16299
-	stmfd	sp!, {r3, lr}
16300
-	.save {r3, lr}
16301
-	ldr	r3, .L2751+4
16776
+	ldr	r2, .L2686
16777
+	movw	r1, #2412
16778
+	ldr	r3, .L2686+4
16779
+	push	{r4, lr}
16780
+	.save {r4, lr}
16302
16781
 	ldrh	r1, [r2, r1]
16303
16782
 	add	r0, r3, #1792
16783
+	add	r0, r0, #8
16304
16784
 	strh	r1, [r0, #10]	@ movhi
16305
-	ldr	r1, .L2751+8
16785
+	ldr	r1, .L2686+8
16306
16786
 	strh	r1, [r0, #4]	@ movhi
16307
-	movw	r1, #2434
16787
+	movw	r1, #2438
16308
16788
 	ldrh	r1, [r2, r1]
16309
16789
 	strh	r1, [r0, #8]	@ movhi
16310
-	movw	r1, #2410
16790
+	movw	r1, #2414
16311
16791
 	ldrh	r1, [r2, r1]
16312
-	ldr	r2, [r2, #2436]
16792
+	ldr	r2, [r2, #2440]
16313
16793
 	strh	r1, [r0, #6]	@ movhi
16314
-	str	r2, [r3, #1804]
16315
-	ldr	r2, [r3, #-460]
16316
-	str	r2, [r3, #1808]
16317
-	ldr	r2, [r3, #-464]
16318
16794
 	str	r2, [r3, #1812]
16319
-	ldr	r2, [r3, #-456]
16795
+	ldr	r2, [r3, #-460]
16320
16796
 	str	r2, [r3, #1816]
16797
+	ldr	r2, [r3, #-464]
16798
+	str	r2, [r3, #1820]
16799
+	ldr	r2, [r3, #-456]
16800
+	str	r2, [r3, #1824]
16321
16801
 	bl	FtlMapTblRecovery
16322
16802
 	mov	r0, #0
16323
-	ldmfd	sp!, {r3, pc}
16324
-.L2752:
16803
+	pop	{r4, pc}
16804
+.L2687:
16325
16805
 	.align	2
16326
-.L2751:
16806
+.L2686:
16327
16807
 	.word	.LANCHOR0
16328
16808
 	.word	.LANCHOR2
16329
16809
 	.word	-3962
..
..
@@ -16331,237 +16811,241 @@
16331
16811
 	.size	FtlLoadVonderInfo, .-FtlLoadVonderInfo
16332
16812
 	.align	2
16333
16813
 	.global	FtlLoadMapInfo
16814
+	.syntax unified
16815
+	.arm
16816
+	.fpu softvfp
16334
16817
 	.type	FtlLoadMapInfo, %function
16335
16818
 FtlLoadMapInfo:
16336
16819
 	.fnstart
16337
16820
 	@ args = 0, pretend = 0, frame = 0
16338
16821
 	@ frame_needed = 0, uses_anonymous_args = 0
16339
-	stmfd	sp!, {r3, lr}
16340
-	.save {r3, lr}
16822
+	push	{r4, lr}
16823
+	.save {r4, lr}
16341
16824
 	bl	FtlL2PDataInit
16342
-	ldr	r0, .L2755
16825
+	ldr	r0, .L2690
16343
16826
 	bl	FtlMapTblRecovery
16344
16827
 	mov	r0, #0
16345
-	ldmfd	sp!, {r3, pc}
16346
-.L2756:
16828
+	pop	{r4, pc}
16829
+.L2691:
16347
16830
 	.align	2
16348
-.L2755:
16831
+.L2690:
16349
16832
 	.word	.LANCHOR2-432
16350
16833
 	.fnend
16351
16834
 	.size	FtlLoadMapInfo, .-FtlLoadMapInfo
16352
16835
 	.align	2
16353
16836
 	.global	FtlVendorPartWrite
16837
+	.syntax unified
16838
+	.arm
16839
+	.fpu softvfp
16354
16840
 	.type	FtlVendorPartWrite, %function
16355
16841
 FtlVendorPartWrite:
16356
16842
 	.fnstart
16357
16843
 	@ args = 0, pretend = 0, frame = 56
16358
16844
 	@ frame_needed = 0, uses_anonymous_args = 0
16359
-	ldr	r3, .L2768
16360
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16845
+	ldr	r3, .L2702
16846
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
16361
16847
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16362
16848
 	mov	r10, r2
16363
-	movw	r2, #2396
16364
-	mov	r6, r0
16365
-	ldrh	r5, [r3, r2]
16366
-	add	r3, r3, #2384
16367
-	add	r2, r0, r1
16849
+	movw	r2, #2386
16850
+	mov	r5, r1
16851
+	add	r1, r0, r1
16368
16852
 	.pad #60
16369
16853
 	sub	sp, sp, #60
16370
-	ldrh	r3, [r3]
16371
-	mov	r4, r1
16372
-	cmp	r2, r3
16373
-	mvnhi	r0, #0
16374
-	bhi	.L2758
16375
-	ldr	fp, .L2768+4
16376
-	mov	r5, r6, lsr r5
16377
-	mov	r3, r5, asl #2
16378
-	str	r3, [sp, #4]
16379
-	mov	r7, fp
16380
-	mov	r3, #0
16381
-	str	r3, [sp]
16382
-.L2759:
16383
-	cmp	r4, #0
16384
-	beq	.L2767
16385
-	ldr	r2, [sp, #4]
16386
-	mov	r0, r6
16387
-	ldr	r3, [fp, #-456]
16388
-	ldr	ip, [r3, r2]
16389
-	ldr	r3, .L2768+8
16390
-	str	ip, [sp, #12]
16391
-	ldrh	r2, [r3]
16392
-	mov	r1, r2
16393
-	str	r2, [sp, #8]
16394
-	bl	__aeabi_uidivmod
16395
-	ldr	r2, [sp, #8]
16396
-	mov	r8, r1
16397
-	ldr	ip, [sp, #12]
16398
-	rsb	r3, r1, r2
16399
-	uxth	r9, r3
16400
-	cmp	r9, r4
16401
-	uxthhi	r9, r4
16402
-	cmp	r9, r2
16403
-	cmpne	ip, #0
16404
-	movne	r1, #1
16405
-	moveq	r1, #0
16406
-	beq	.L2761
16407
-	ldr	r2, [r7, #-516]
16408
-	mov	r1, #1
16409
-	add	r0, sp, #20
16410
-	str	ip, [sp, #24]
16411
-	str	r2, [sp, #28]
16412
-	mov	r2, #0
16413
-	str	r2, [sp, #32]
16414
-	mov	r2, r1
16415
-	bl	FlashReadPages
16416
-	b	.L2762
16417
-.L2761:
16418
-	ldr	r2, .L2768+12
16419
-	ldr	r0, [r7, #-516]
16420
-	ldrh	r2, [r2]
16421
-	bl	ftl_memset
16422
-.L2762:
16423
-	mov	ip, r9, asl #9
16424
-	ldr	r0, [r7, #-516]
16425
-	uxth	r8, r8
16426
-	mov	r1, r10
16427
-	mov	r2, ip
16428
-	str	ip, [sp, #8]
16429
-	add	r0, r0, r8, asl #9
16430
-	rsb	r4, r9, r4
16431
-	bl	ftl_memcpy
16432
-	mov	r1, r5
16433
-	ldr	r0, .L2768+16
16434
-	add	r5, r5, #1
16435
-	ldr	r2, [r7, #-516]
16436
-	add	r6, r6, r9
16437
-	bl	FtlMapWritePage
16438
-	ldr	r3, [sp]
16439
-	cmn	r0, #1
16440
-	ldr	ip, [sp, #8]
16441
-	mvneq	r3, #0
16442
-	str	r3, [sp]
16443
-	add	r10, r10, ip
16444
-	ldr	r3, [sp, #4]
16445
-	add	r3, r3, #4
16446
-	str	r3, [sp, #4]
16447
-	b	.L2759
16448
-.L2767:
16449
-	ldr	r0, [sp]
16450
-.L2758:
16854
+	ldrh	r2, [r3, r2]
16855
+	cmp	r1, r2
16856
+	mvnhi	r9, #0
16857
+	bhi	.L2692
16858
+	movw	r2, #2398
16859
+	ldr	r8, .L2702+4
16860
+	ldrh	r6, [r3, r2]
16861
+	mov	r7, r0
16862
+	mov	r9, #0
16863
+	lsr	r6, r0, r6
16864
+	lsl	fp, r6, #2
16865
+.L2694:
16866
+	cmp	r5, #0
16867
+	bne	.L2699
16868
+.L2692:
16869
+	mov	r0, r9
16451
16870
 	add	sp, sp, #60
16452
16871
 	@ sp needed
16453
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
16454
-.L2769:
16872
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
16873
+.L2699:
16874
+	ldr	r3, [r8, #-456]
16875
+	mov	r0, r7
16876
+	ldr	r2, [r3, fp]
16877
+	ldr	r3, .L2702+8
16878
+	str	r2, [sp, #12]
16879
+	ldrh	r3, [r3]
16880
+	mov	r1, r3
16881
+	str	r3, [sp, #8]
16882
+	bl	__aeabi_uidivmod
16883
+	ldr	r3, [sp, #8]
16884
+	ldr	r2, [sp, #12]
16885
+	str	r1, [sp, #4]
16886
+	sub	r4, r3, r1
16887
+	uxth	r4, r4
16888
+	cmp	r5, r4
16889
+	uxthcc	r4, r5
16890
+	cmp	r2, #0
16891
+	cmpne	r4, r3
16892
+	movne	r1, #1
16893
+	moveq	r1, #0
16894
+	beq	.L2696
16895
+	ldr	r3, [r8, #-516]
16896
+	add	r0, sp, #20
16897
+	str	r2, [sp, #24]
16898
+	mov	r2, #1
16899
+	mov	r1, r2
16900
+	str	r3, [sp, #28]
16901
+	mov	r3, #0
16902
+	str	r3, [sp, #32]
16903
+	bl	FlashReadPages
16904
+.L2697:
16905
+	lsl	r3, r4, #9
16906
+	ldr	r0, [r8, #-516]
16907
+	mov	r1, r10
16908
+	mov	r2, r3
16909
+	str	r3, [sp, #8]
16910
+	ldr	r3, [sp, #4]
16911
+	sub	r5, r5, r4
16912
+	add	r7, r7, r4
16913
+	add	fp, fp, #4
16914
+	add	r0, r0, r3, lsl #9
16915
+	bl	ftl_memcpy
16916
+	mov	r1, r6
16917
+	ldr	r2, [r8, #-516]
16918
+	ldr	r0, .L2702+12
16919
+	add	r6, r6, #1
16920
+	bl	FtlMapWritePage
16921
+	ldr	r3, [sp, #8]
16922
+	cmn	r0, #1
16923
+	mvneq	r9, #0
16924
+	add	r10, r10, r3
16925
+	b	.L2694
16926
+.L2696:
16927
+	ldr	r3, .L2702+16
16928
+	ldr	r0, [r8, #-516]
16929
+	ldrh	r2, [r3]
16930
+	bl	ftl_memset
16931
+	b	.L2697
16932
+.L2703:
16455
16933
 	.align	2
16456
-.L2768:
16934
+.L2702:
16457
16935
 	.word	.LANCHOR0
16458
16936
 	.word	.LANCHOR2
16459
-	.word	.LANCHOR0+2394
16460
-	.word	.LANCHOR0+2398
16461
-	.word	.LANCHOR2+1792
16937
+	.word	.LANCHOR0+2396
16938
+	.word	.LANCHOR2+1800
16939
+	.word	.LANCHOR0+2400
16462
16940
 	.fnend
16463
16941
 	.size	FtlVendorPartWrite, .-FtlVendorPartWrite
16464
16942
 	.align	2
16465
16943
 	.global	Ftl_save_ext_data
16944
+	.syntax unified
16945
+	.arm
16946
+	.fpu softvfp
16466
16947
 	.type	Ftl_save_ext_data, %function
16467
16948
 Ftl_save_ext_data:
16468
16949
 	.fnstart
16469
16950
 	@ args = 0, pretend = 0, frame = 0
16470
16951
 	@ frame_needed = 0, uses_anonymous_args = 0
16471
16952
 	@ link register save eliminated.
16472
-	ldr	r2, .L2772
16473
-	ldr	r3, .L2772+4
16474
-	ldr	r1, [r2, #-3232]
16475
-	cmp	r1, r3
16953
+	ldr	r3, .L2706
16954
+	ldr	r2, .L2706+4
16955
+	ldr	r1, [r3, #-3236]
16956
+	cmp	r1, r2
16476
16957
 	bxne	lr
16477
-	ldr	r3, .L2772+8
16478
-	mov	r0, #0
16958
+	ldr	r2, .L2706+8
16479
16959
 	mov	r1, #1
16480
-	sub	r2, r2, #3232
16481
-	str	r3, [r2, #4]
16482
-	ldr	r3, [r2, #-108]
16483
-	str	r3, [r2, #88]
16484
-	ldr	r3, [r2, #-104]
16485
-	str	r3, [r2, #92]
16486
-	ldr	r3, [r2, #-112]
16487
-	str	r3, [r2, #8]
16488
-	ldr	r3, [r2, #-124]
16489
-	str	r3, [r2, #12]
16490
-	ldr	r3, [r2, #-132]
16491
-	str	r3, [r2, #16]
16492
-	ldr	r3, [r2, #-116]
16493
-	str	r3, [r2, #20]
16494
-	ldr	r3, [r2, #-88]
16495
-	str	r3, [r2, #28]
16496
-	ldr	r3, [r2, #-372]
16497
-	str	r3, [r2, #32]
16498
-	ldr	r3, [r2, #-128]
16499
-	str	r3, [r2, #36]
16500
-	ldr	r3, [r2, #-120]
16501
-	str	r3, [r2, #40]
16502
-	ldr	r3, [r2, #-80]
16503
-	str	r3, [r2, #44]
16504
-	ldr	r3, [r2, #-76]
16505
-	str	r3, [r2, #48]
16506
-	ldr	r3, [r2, #-4]
16507
-	str	r3, [r2, #60]
16508
-	ldr	r3, [r2, #2668]
16509
-	str	r3, [r2, #64]
16960
+	mov	r0, #0
16961
+	str	r2, [r3, #-3232]
16962
+	ldr	r2, [r3, #-3340]
16963
+	str	r2, [r3, #-3148]
16964
+	ldr	r2, [r3, #-3336]
16965
+	str	r2, [r3, #-3144]
16966
+	ldr	r2, [r3, #-3344]
16967
+	str	r2, [r3, #-3228]
16968
+	ldr	r2, [r3, #-3356]
16969
+	str	r2, [r3, #-3224]
16970
+	ldr	r2, [r3, #-3364]
16971
+	str	r2, [r3, #-3220]
16972
+	ldr	r2, [r3, #-3348]
16973
+	str	r2, [r3, #-3216]
16974
+	ldr	r2, [r3, #-3320]
16975
+	str	r2, [r3, #-3208]
16976
+	ldr	r2, [r3, #-3600]
16977
+	str	r2, [r3, #-3204]
16978
+	ldr	r2, [r3, #-3360]
16979
+	str	r2, [r3, #-3200]
16980
+	ldr	r2, [r3, #-3352]
16981
+	str	r2, [r3, #-3196]
16982
+	ldr	r2, [r3, #-3312]
16983
+	str	r2, [r3, #-3192]
16984
+	ldr	r2, [r3, #-3308]
16985
+	str	r2, [r3, #-3188]
16986
+	ldr	r2, [r3, #-2724]
16987
+	str	r2, [r3, #-3176]
16988
+	ldr	r2, [r3, #-564]
16989
+	str	r2, [r3, #-3172]
16990
+	ldr	r2, .L2706+12
16510
16991
 	b	FtlVendorPartWrite
16511
-.L2773:
16992
+.L2707:
16512
16993
 	.align	2
16513
-.L2772:
16994
+.L2706:
16514
16995
 	.word	.LANCHOR2
16515
16996
 	.word	1179929683
16516
16997
 	.word	1342177379
16998
+	.word	.LANCHOR2-3236
16517
16999
 	.fnend
16518
17000
 	.size	Ftl_save_ext_data, .-Ftl_save_ext_data
16519
17001
 	.align	2
16520
17002
 	.global	FtlEctTblFlush
17003
+	.syntax unified
17004
+	.arm
17005
+	.fpu softvfp
16521
17006
 	.type	FtlEctTblFlush, %function
16522
17007
 FtlEctTblFlush:
16523
17008
 	.fnstart
16524
17009
 	@ args = 0, pretend = 0, frame = 0
16525
17010
 	@ frame_needed = 0, uses_anonymous_args = 0
16526
-	stmfd	sp!, {r3, lr}
16527
-	.save {r3, lr}
16528
-	ldr	r3, .L2782
16529
-	ldr	r3, [r3, #2244]
17011
+	ldr	r3, .L2718
17012
+	ldr	r3, [r3, #2248]
16530
17013
 	cmp	r3, #0
16531
-	ldr	r3, .L2782+4
17014
+	ldr	r3, .L2718+4
16532
17015
 	moveq	r2, #32
16533
-	beq	.L2775
17016
+	beq	.L2709
16534
17017
 	ldr	r2, [r3, #-3308]
16535
17018
 	cmp	r2, #39
16536
17019
 	movhi	r2, #32
16537
17020
 	movls	r2, #4
16538
-.L2775:
16539
-	movw	ip, #1836
17021
+.L2709:
17022
+	movw	ip, #1844
16540
17023
 	ldrh	r1, [r3, ip]
16541
17024
 	cmp	r1, #31
16542
17025
 	addls	r1, r1, #1
16543
-	ldrls	r2, .L2782+4
16544
-	strlsh	r1, [r2, ip]	@ movhi
16545
17026
 	movls	r2, #1
17027
+	strhls	r1, [r3, ip]	@ movhi
16546
17028
 	cmp	r0, #0
16547
-	bne	.L2777
17029
+	bne	.L2711
16548
17030
 	ldr	r1, [r3, #-480]
16549
17031
 	ldr	r0, [r1, #20]
16550
17032
 	ldr	r1, [r1, #16]
16551
17033
 	add	r2, r2, r0
16552
17034
 	cmp	r1, r2
16553
-	bcc	.L2778
16554
-.L2777:
16555
-	ldr	r2, [r3, #-480]
17035
+	bcc	.L2716
17036
+.L2711:
17037
+	push	{r4, lr}
17038
+	.save {r4, lr}
16556
17039
 	mov	r0, #64
17040
+	ldr	r2, [r3, #-480]
16557
17041
 	ldr	r1, [r2, #16]
16558
17042
 	str	r1, [r2, #20]
16559
-	ldr	r1, .L2782+8
17043
+	ldr	r1, .L2718+8
16560
17044
 	str	r1, [r2]
16561
17045
 	ldr	r2, [r3, #-480]
16562
-	ldr	r3, .L2782+12
17046
+	ldr	r3, .L2718+12
16563
17047
 	ldrh	r1, [r3]
16564
-	mov	r3, r1, asl #9
17048
+	lsl	r3, r1, #9
16565
17049
 	str	r3, [r2, #12]
16566
17050
 	ldr	r3, [r2, #8]
16567
17051
 	add	r3, r3, #1
..
..
@@ -16570,12 +17054,14 @@
16570
17054
 	str	r3, [r2, #4]
16571
17055
 	bl	FtlVendorPartWrite
16572
17056
 	bl	Ftl_save_ext_data
16573
-.L2778:
16574
17057
 	mov	r0, #0
16575
-	ldmfd	sp!, {r3, pc}
16576
-.L2783:
17058
+	pop	{r4, pc}
17059
+.L2716:
17060
+	mov	r0, #0
17061
+	bx	lr
17062
+.L2719:
16577
17063
 	.align	2
16578
-.L2782:
17064
+.L2718:
16579
17065
 	.word	.LANCHOR0
16580
17066
 	.word	.LANCHOR2
16581
17067
 	.word	1112818501
..
..
@@ -16584,404 +17070,411 @@
16584
17070
 	.size	FtlEctTblFlush, .-FtlEctTblFlush
16585
17071
 	.align	2
16586
17072
 	.global	FtlVendorPartRead
17073
+	.syntax unified
17074
+	.arm
17075
+	.fpu softvfp
16587
17076
 	.type	FtlVendorPartRead, %function
16588
17077
 FtlVendorPartRead:
16589
17078
 	.fnstart
16590
17079
 	@ args = 0, pretend = 0, frame = 56
16591
17080
 	@ frame_needed = 0, uses_anonymous_args = 0
16592
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
17081
+	ldr	r3, .L2731
17082
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
16593
17083
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16594
-	movw	r3, #2396
16595
-	ldr	r4, .L2796
16596
-	mov	r8, r2
16597
-	add	r2, r0, r1
16598
-	mov	r7, r0
17084
+	mov	r10, r2
17085
+	movw	r2, #2386
17086
+	mov	r6, r1
17087
+	add	r1, r0, r1
16599
17088
 	.pad #60
16600
17089
 	sub	sp, sp, #60
16601
-	mov	r6, r1
16602
-	ldrh	r5, [r4, r3]
16603
-	add	r4, r4, #2384
16604
-	ldrh	r3, [r4]
16605
-	cmp	r2, r3
16606
-	mvnhi	r0, #0
16607
-	bhi	.L2785
16608
-	ldr	r9, .L2796+4
16609
-	mov	r5, r7, lsr r5
16610
-	mov	r3, r5, asl #2
16611
-	str	r3, [sp, #4]
16612
-	mov	r10, r9
16613
-	mov	r3, #0
16614
-	str	r3, [sp]
16615
-.L2786:
17090
+	ldrh	r2, [r3, r2]
17091
+	cmp	r1, r2
17092
+	mvnhi	r9, #0
17093
+	bhi	.L2720
17094
+	movw	r2, #2398
17095
+	ldr	r8, .L2731+4
17096
+	ldrh	r5, [r3, r2]
17097
+	mov	r7, r0
17098
+	mov	r9, #0
17099
+	lsr	r5, r0, r5
17100
+	lsl	fp, r5, #2
17101
+.L2722:
16616
17102
 	cmp	r6, #0
16617
-	beq	.L2795
16618
-	ldr	r2, [sp, #4]
17103
+	bne	.L2728
17104
+.L2720:
17105
+	mov	r0, r9
17106
+	add	sp, sp, #60
17107
+	@ sp needed
17108
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
17109
+.L2728:
17110
+	ldr	r3, [r8, #-456]
16619
17111
 	mov	r0, r7
16620
-	ldr	r3, [r9, #-456]
16621
-	ldr	r3, [r3, r2]
16622
-	str	r3, [sp, #12]
16623
-	ldr	r3, .L2796+8
17112
+	ldr	r3, [r3, fp]
17113
+	str	r3, [sp, #8]
17114
+	ldr	r3, .L2731+8
16624
17115
 	ldrh	r4, [r3]
16625
17116
 	mov	r1, r4
16626
17117
 	bl	__aeabi_uidivmod
16627
-	rsb	r4, r1, r4
16628
-	ldr	r3, [sp, #12]
16629
-	str	r1, [sp, #8]
17118
+	sub	r4, r4, r1
17119
+	ldr	r3, [sp, #8]
16630
17120
 	uxth	r4, r4
16631
-	cmp	r4, r6
16632
-	uxthhi	r4, r6
17121
+	str	r1, [sp, #4]
17122
+	cmp	r6, r4
17123
+	uxthcc	r4, r6
16633
17124
 	cmp	r3, #0
16634
-	mov	fp, r4, asl #9
16635
-	beq	.L2788
16636
-	ldr	r2, [r10, #-516]
16637
-	mov	r1, #1
17125
+	lsl	r2, r4, #9
17126
+	str	r2, [sp, #8]
17127
+	beq	.L2724
17128
+	ldr	r2, [r8, #-516]
16638
17129
 	add	r0, sp, #20
16639
17130
 	str	r3, [sp, #24]
16640
17131
 	str	r3, [sp, #12]
16641
17132
 	str	r2, [sp, #28]
16642
17133
 	mov	r2, #0
16643
17134
 	str	r2, [sp, #32]
16644
-	mov	r2, r1
17135
+	mov	r2, #1
17136
+	mov	r1, r2
16645
17137
 	bl	FlashReadPages
16646
17138
 	ldr	r2, [sp, #20]
16647
-	ldr	r3, [sp]
16648
-	cmn	r2, #1
16649
-	ldr	r2, [r10, #1752]
16650
-	mvneq	r3, #0
16651
-	cmp	r2, #256
16652
-	str	r3, [sp]
16653
17139
 	ldr	r3, [sp, #12]
16654
-	bne	.L2790
16655
-	mov	r1, r5
17140
+	cmn	r2, #1
17141
+	ldr	r2, [r8, #1760]
17142
+	mvneq	r9, #0
17143
+	cmp	r2, #256
17144
+	bne	.L2726
16656
17145
 	mov	r2, r3
16657
-	ldr	r0, .L2796+12
16658
-	bl	printk
16659
-	ldr	r0, .L2796+16
16660
17146
 	mov	r1, r5
16661
-	ldr	r2, [r9, #-516]
17147
+	ldr	r0, .L2731+12
17148
+	bl	printk
17149
+	ldr	r2, [r8, #-516]
17150
+	mov	r1, r5
17151
+	ldr	r0, .L2731+16
16662
17152
 	bl	FtlMapWritePage
16663
-.L2790:
16664
-	ldrh	r3, [sp, #8]
16665
-	mov	r0, r8
16666
-	ldr	r1, [r10, #-516]
16667
-	mov	r2, fp
16668
-	add	r1, r1, r3, asl #9
16669
-	bl	ftl_memcpy
16670
-	b	.L2791
16671
-.L2788:
16672
-	mov	r0, r8
16673
-	mov	r1, r3
16674
-	mov	r2, fp
16675
-	bl	ftl_memset
16676
-.L2791:
17153
+.L2726:
17154
+	ldr	r1, [r8, #-516]
17155
+	lsl	r2, r4, #9
16677
17156
 	ldr	r3, [sp, #4]
17157
+	mov	r0, r10
17158
+	add	r1, r1, r3, lsl #9
17159
+	bl	ftl_memcpy
17160
+.L2727:
17161
+	ldr	r3, [sp, #8]
16678
17162
 	add	r5, r5, #1
16679
-	rsb	r6, r4, r6
17163
+	sub	r6, r6, r4
16680
17164
 	add	r7, r7, r4
16681
-	add	r3, r3, #4
16682
-	add	r8, r8, fp
16683
-	str	r3, [sp, #4]
16684
-	b	.L2786
16685
-.L2795:
16686
-	ldr	r0, [sp]
16687
-.L2785:
16688
-	add	sp, sp, #60
16689
-	@ sp needed
16690
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
16691
-.L2797:
17165
+	add	fp, fp, #4
17166
+	add	r10, r10, r3
17167
+	b	.L2722
17168
+.L2724:
17169
+	lsl	r2, r4, #9
17170
+	mov	r1, r3
17171
+	mov	r0, r10
17172
+	bl	ftl_memset
17173
+	b	.L2727
17174
+.L2732:
16692
17175
 	.align	2
16693
-.L2796:
17176
+.L2731:
16694
17177
 	.word	.LANCHOR0
16695
17178
 	.word	.LANCHOR2
16696
-	.word	.LANCHOR0+2394
17179
+	.word	.LANCHOR0+2396
16697
17180
 	.word	.LC136
16698
-	.word	.LANCHOR2+1792
17181
+	.word	.LANCHOR2+1800
16699
17182
 	.fnend
16700
17183
 	.size	FtlVendorPartRead, .-FtlVendorPartRead
16701
17184
 	.align	2
16702
17185
 	.global	FtlLoadEctTbl
17186
+	.syntax unified
17187
+	.arm
17188
+	.fpu softvfp
16703
17189
 	.type	FtlLoadEctTbl, %function
16704
17190
 FtlLoadEctTbl:
16705
17191
 	.fnstart
16706
17192
 	@ args = 0, pretend = 0, frame = 0
16707
17193
 	@ frame_needed = 0, uses_anonymous_args = 0
16708
-	stmfd	sp!, {r3, r4, r5, lr}
16709
-	.save {r3, r4, r5, lr}
17194
+	push	{r4, r5, r6, lr}
17195
+	.save {r4, r5, r6, lr}
16710
17196
 	mov	r0, #64
16711
-	ldr	r4, .L2801
17197
+	ldr	r4, .L2736
16712
17198
 	sub	r5, r4, #488
16713
17199
 	ldr	r2, [r4, #-480]
16714
17200
 	ldrh	r1, [r5]
16715
17201
 	bl	FtlVendorPartRead
16716
17202
 	ldr	r3, [r4, #-480]
16717
17203
 	ldr	r2, [r3]
16718
-	ldr	r3, .L2801+4
17204
+	ldr	r3, .L2736+4
16719
17205
 	cmp	r2, r3
16720
-	beq	.L2799
16721
-	ldr	r1, .L2801+8
16722
-	ldr	r0, .L2801+12
17206
+	beq	.L2734
17207
+	ldr	r1, .L2736+8
17208
+	ldr	r0, .L2736+12
16723
17209
 	bl	printk
16724
17210
 	ldrh	r2, [r5]
16725
-	ldr	r0, [r4, #-480]
16726
17211
 	mov	r1, #0
16727
-	mov	r2, r2, asl #9
17212
+	ldr	r0, [r4, #-480]
17213
+	lsl	r2, r2, #9
16728
17214
 	bl	ftl_memset
16729
-.L2799:
17215
+.L2734:
16730
17216
 	mov	r0, #0
16731
-	ldmfd	sp!, {r3, r4, r5, pc}
16732
-.L2802:
17217
+	pop	{r4, r5, r6, pc}
17218
+.L2737:
16733
17219
 	.align	2
16734
-.L2801:
17220
+.L2736:
16735
17221
 	.word	.LANCHOR2
16736
17222
 	.word	1112818501
16737
17223
 	.word	.LC137
16738
-	.word	.LC76
17224
+	.word	.LC77
16739
17225
 	.fnend
16740
17226
 	.size	FtlLoadEctTbl, .-FtlLoadEctTbl
16741
17227
 	.align	2
16742
17228
 	.global	Ftl_load_ext_data
17229
+	.syntax unified
17230
+	.arm
17231
+	.fpu softvfp
16743
17232
 	.type	Ftl_load_ext_data, %function
16744
17233
 Ftl_load_ext_data:
16745
17234
 	.fnstart
16746
17235
 	@ args = 0, pretend = 0, frame = 0
16747
17236
 	@ frame_needed = 0, uses_anonymous_args = 0
16748
-	stmfd	sp!, {r3, r4, r5, lr}
16749
-	.save {r3, r4, r5, lr}
16750
-	mov	r0, #0
16751
-	ldr	r4, .L2809
17237
+	push	{r4, r5, r6, lr}
17238
+	.save {r4, r5, r6, lr}
16752
17239
 	mov	r1, #1
16753
-	ldr	r5, .L2809+4
16754
-	sub	r2, r4, #3232
17240
+	ldr	r4, .L2744
17241
+	mov	r0, #0
17242
+	ldr	r5, .L2744+4
17243
+	sub	r6, r4, #3232
17244
+	sub	r6, r6, #4
17245
+	mov	r2, r6
16755
17246
 	bl	FtlVendorPartRead
16756
-	ldr	r3, [r4, #-3232]
17247
+	ldr	r3, [r4, #-3236]
16757
17248
 	cmp	r3, r5
16758
-	beq	.L2804
16759
-	sub	r0, r4, #3232
16760
-	mov	r1, #0
17249
+	beq	.L2739
16761
17250
 	mov	r2, #512
17251
+	mov	r1, #0
17252
+	mov	r0, r6
16762
17253
 	bl	ftl_memset
16763
-	str	r5, [r4, #-3232]
16764
-.L2804:
16765
-	ldr	r2, [r4, #-3232]
16766
-	ldr	r3, .L2809
16767
-	cmp	r2, r5
16768
-	bne	.L2805
16769
-	ldr	r2, [r3, #-3144]
16770
-	str	r2, [r3, #-3340]
16771
-	ldr	r2, [r3, #-3140]
16772
-	str	r2, [r3, #-3336]
16773
-	ldr	r2, [r3, #-3224]
16774
-	str	r2, [r3, #-3344]
16775
-	ldr	r2, [r3, #-3220]
16776
-	str	r2, [r3, #-3356]
16777
-	ldr	r2, [r3, #-3216]
16778
-	str	r2, [r3, #-3364]
16779
-	ldr	r2, [r3, #-3212]
16780
-	str	r2, [r3, #-3348]
16781
-	ldr	r2, [r3, #-3204]
16782
-	str	r2, [r3, #-3320]
16783
-	ldr	r2, [r3, #-3200]
16784
-	str	r2, [r3, #-3604]
16785
-	ldr	r2, [r3, #-3196]
16786
-	str	r2, [r3, #-3360]
16787
-	ldr	r2, [r3, #-3192]
16788
-	str	r2, [r3, #-3352]
16789
-	ldr	r2, [r3, #-3188]
16790
-	str	r2, [r3, #-3312]
16791
-	ldr	r2, [r3, #-3184]
16792
-	str	r2, [r3, #-3308]
16793
-	ldr	r2, [r3, #-3172]
16794
-	str	r2, [r3, #-3236]
16795
-.L2805:
16796
-	ldr	r1, [r4, #-3164]
17254
+	str	r5, [r4, #-3236]
17255
+.L2739:
17256
+	ldr	r3, [r4, #-3236]
17257
+	cmp	r3, r5
17258
+	bne	.L2740
17259
+	ldr	r3, [r4, #-3148]
17260
+	str	r3, [r4, #-3340]
17261
+	ldr	r3, [r4, #-3144]
17262
+	str	r3, [r4, #-3336]
17263
+	ldr	r3, [r4, #-3228]
17264
+	str	r3, [r4, #-3344]
17265
+	ldr	r3, [r4, #-3224]
17266
+	str	r3, [r4, #-3356]
17267
+	ldr	r3, [r4, #-3220]
17268
+	str	r3, [r4, #-3364]
17269
+	ldr	r3, [r4, #-3216]
17270
+	str	r3, [r4, #-3348]
17271
+	ldr	r3, [r4, #-3208]
17272
+	str	r3, [r4, #-3320]
17273
+	ldr	r3, [r4, #-3204]
17274
+	str	r3, [r4, #-3600]
17275
+	ldr	r3, [r4, #-3200]
17276
+	str	r3, [r4, #-3360]
17277
+	ldr	r3, [r4, #-3196]
17278
+	str	r3, [r4, #-3352]
17279
+	ldr	r3, [r4, #-3192]
17280
+	str	r3, [r4, #-3312]
17281
+	ldr	r3, [r4, #-3188]
17282
+	str	r3, [r4, #-3308]
17283
+	ldr	r3, [r4, #-3176]
17284
+	str	r3, [r4, #-2724]
17285
+.L2740:
17286
+	ldr	r1, [r4, #-3168]
16797
17287
 	mov	r3, #0
16798
-	ldr	r2, .L2809+8
17288
+	ldr	r2, .L2744+8
16799
17289
 	str	r3, [r4, #-564]
17290
+	ldr	r5, .L2744+12
16800
17291
 	cmp	r1, r2
16801
-	ldr	r5, .L2809+12
16802
-	bne	.L2806
16803
-	ldrb	r2, [r5, #144]	@ zero_extendqisi2
17292
+	bne	.L2741
17293
+	ldrb	r2, [r5, #152]	@ zero_extendqisi2
16804
17294
 	cmp	r2, r3
16805
-	beq	.L2807
16806
-	ldr	r2, .L2809
16807
-	str	r3, [r2, #-3164]
17295
+	beq	.L2742
17296
+	str	r3, [r4, #-3168]
16808
17297
 	bl	Ftl_save_ext_data
16809
-	b	.L2806
16810
-.L2807:
16811
-	ldr	r0, .L2809+16
16812
-	mov	r3, #1
16813
-	ldr	r1, .L2809+20
16814
-	str	r3, [r5, #2244]
16815
-	bl	printk
16816
-.L2806:
16817
-	movw	r3, #2380
17298
+.L2741:
17299
+	movw	r3, #2382
16818
17300
 	ldr	r0, [r4, #-3324]
16819
17301
 	ldrh	r2, [r5, r3]
17302
+	movw	r1, #2332
16820
17303
 	ldr	r3, [r4, #-3320]
17304
+	ldrh	r1, [r5, r1]
16821
17305
 	mla	r0, r0, r2, r3
16822
-	movw	r3, #2328
16823
-	ldrh	r1, [r5, r3]
16824
17306
 	bl	__aeabi_uidiv
16825
17307
 	str	r0, [r4, #-3316]
16826
-	ldmfd	sp!, {r3, r4, r5, pc}
16827
-.L2810:
17308
+	pop	{r4, r5, r6, pc}
17309
+.L2742:
17310
+	mov	r3, #1
17311
+	ldr	r1, .L2744+16
17312
+	ldr	r0, .L2744+20
17313
+	str	r3, [r5, #2248]
17314
+	bl	printk
17315
+	b	.L2741
17316
+.L2745:
16828
17317
 	.align	2
16829
-.L2809:
17318
+.L2744:
16830
17319
 	.word	.LANCHOR2
16831
17320
 	.word	1179929683
16832
17321
 	.word	305432421
16833
17322
 	.word	.LANCHOR0
16834
-	.word	.LC76
16835
17323
 	.word	.LC138
17324
+	.word	.LC77
16836
17325
 	.fnend
16837
17326
 	.size	Ftl_load_ext_data, .-Ftl_load_ext_data
16838
17327
 	.align	2
16839
17328
 	.global	FtlMapBlkWriteDumpData
17329
+	.syntax unified
17330
+	.arm
17331
+	.fpu softvfp
16840
17332
 	.type	FtlMapBlkWriteDumpData, %function
16841
17333
 FtlMapBlkWriteDumpData:
16842
17334
 	.fnstart
16843
17335
 	@ args = 0, pretend = 0, frame = 0
16844
17336
 	@ frame_needed = 0, uses_anonymous_args = 0
16845
-	stmfd	sp!, {r4, r5, r6, lr}
17337
+	ldr	r3, [r0, #36]
17338
+	cmp	r3, #0
17339
+	bxeq	lr
17340
+	push	{r4, r5, r6, lr}
16846
17341
 	.save {r4, r5, r6, lr}
16847
-	ldr	r2, [r0, #36]
16848
-	ldrh	r5, [r0, #6]
16849
-	cmp	r2, #0
16850
-	ldr	r3, [r0, #24]
16851
-	ldmeqfd	sp!, {r4, r5, r6, pc}
16852
-	ldr	r4, .L2818
16853
17342
 	mov	r2, #0
17343
+	ldr	r4, .L2756
16854
17344
 	str	r2, [r0, #36]
16855
-	ldr	r2, [r4, #-3616]
17345
+	ldr	r2, [r4, #-3612]
17346
+	ldrh	r5, [r0, #6]
17347
+	ldr	r3, [r0, #24]
16856
17348
 	cmp	r2, #0
16857
-	ldmnefd	sp!, {r4, r5, r6, pc}
16858
-	sub	r5, r5, #1
17349
+	popne	{r4, r5, r6, pc}
16859
17350
 	mov	r6, r0
16860
17351
 	ldr	r2, [r4, #-500]
16861
17352
 	ldr	r0, [r4, #-520]
17353
+	sub	r5, r5, #1
16862
17354
 	uxth	r5, r5
16863
-	str	r2, [r4, #1764]
16864
-	str	r0, [r4, #1760]
16865
-	ldr	r3, [r3, r5, asl #2]
17355
+	str	r2, [r4, #1772]
17356
+	str	r0, [r4, #1768]
17357
+	ldr	r3, [r3, r5, lsl #2]
16866
17358
 	cmp	r3, #0
16867
-	str	r3, [r4, #1756]
16868
-	beq	.L2815
16869
-	mov	r1, #1
16870
-	ldr	r0, .L2818+4
16871
-	mov	r2, r1
17359
+	str	r3, [r4, #1764]
17360
+	beq	.L2750
17361
+	mov	r2, #1
17362
+	add	r0, r4, #1760
17363
+	mov	r1, r2
16872
17364
 	bl	FlashReadPages
16873
-	b	.L2816
16874
-.L2815:
16875
-	ldr	r2, .L2818+8
16876
-	movw	r3, #2398
16877
-	mov	r1, #255
16878
-	ldrh	r2, [r2, r3]
16879
-	bl	ftl_memset
16880
-.L2816:
16881
-	mov	r0, r6
17365
+.L2751:
17366
+	ldr	r2, [r4, #1768]
16882
17367
 	mov	r1, r5
16883
-	ldr	r2, [r4, #1760]
16884
-	ldmfd	sp!, {r4, r5, r6, lr}
17368
+	mov	r0, r6
17369
+	pop	{r4, r5, r6, lr}
16885
17370
 	b	FtlMapWritePage
16886
-.L2819:
17371
+.L2750:
17372
+	ldr	r3, .L2756+4
17373
+	mov	r1, #255
17374
+	ldrh	r2, [r3]
17375
+	bl	ftl_memset
17376
+	b	.L2751
17377
+.L2757:
16887
17378
 	.align	2
16888
-.L2818:
17379
+.L2756:
16889
17380
 	.word	.LANCHOR2
16890
-	.word	.LANCHOR2+1752
16891
-	.word	.LANCHOR0
17381
+	.word	.LANCHOR0+2400
16892
17382
 	.fnend
16893
17383
 	.size	FtlMapBlkWriteDumpData, .-FtlMapBlkWriteDumpData
16894
17384
 	.align	2
16895
17385
 	.global	FlashReadFacBbtData
17386
+	.syntax unified
17387
+	.arm
17388
+	.fpu softvfp
16896
17389
 	.type	FlashReadFacBbtData, %function
16897
17390
 FlashReadFacBbtData:
16898
17391
 	.fnstart
16899
17392
 	@ args = 0, pretend = 0, frame = 40
16900
17393
 	@ frame_needed = 0, uses_anonymous_args = 0
16901
-	ldr	r3, .L2835
16902
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
17394
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
16903
17395
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
16904
17396
 	mov	r8, r2
16905
-	ldrh	r2, [r3, #128]
17397
+	ldr	r2, .L2771
16906
17398
 	.pad #40
16907
17399
 	sub	sp, sp, #40
16908
-	ldrh	r3, [r3, #130]
16909
17400
 	mov	r5, r0
16910
-	ldr	r9, .L2835+4
16911
17401
 	mov	r7, r1
16912
-	smulbb	r3, r2, r3
16913
-	ldr	r2, [r9, #1688]
16914
-	str	r2, [sp, #12]
16915
-	ldr	r2, [r9, #1720]
17402
+	ldr	r9, .L2771+4
17403
+	ldrh	r3, [r2, #138]
17404
+	ldrh	r2, [r2, #136]
17405
+	smulbb	r3, r3, r2
17406
+	ldr	r2, [r9, #1696]
16916
17407
 	uxth	r3, r3
17408
+	str	r2, [sp, #12]
17409
+	ldr	r2, [r9, #1728]
16917
17410
 	sub	r6, r3, #1
16918
-	sub	r4, r3, #16
16919
-	mul	r10, r3, r1
17411
+	mul	r10, r1, r3
16920
17412
 	uxth	r6, r6
17413
+	sub	r4, r3, #16
16921
17414
 	str	r2, [sp, #16]
16922
-.L2821:
17415
+.L2759:
16923
17416
 	cmp	r6, r4
16924
-	ble	.L2834
16925
-	mov	r1, #1
17417
+	mvnle	r0, #0
17418
+	ble	.L2758
17419
+.L2765:
16926
17420
 	add	r3, r6, r10
17421
+	mov	r2, #1
17422
+	lsl	r3, r3, #10
17423
+	mov	r1, r2
16927
17424
 	add	r0, sp, #4
16928
-	mov	r2, r1
16929
-	mov	r3, r3, asl #10
16930
17425
 	str	r3, [sp, #8]
16931
17426
 	bl	FlashReadPages
16932
17427
 	ldr	r3, [sp, #4]
16933
17428
 	cmn	r3, #1
16934
-	beq	.L2822
16935
-	ldr	r3, [r9, #1720]
17429
+	beq	.L2760
17430
+	ldr	r3, [r9, #1728]
16936
17431
 	ldrh	r2, [r3]
16937
17432
 	movw	r3, #61664
16938
17433
 	cmp	r2, r3
16939
-	bne	.L2822
17434
+	bne	.L2760
16940
17435
 	cmp	r5, #0
16941
17436
 	moveq	r0, r5
16942
-	beq	.L2823
17437
+	beq	.L2758
16943
17438
 	cmp	r7, #0
16944
-	ldreq	ip, .L2835+4
17439
+	moveq	r1, r7
16945
17440
 	moveq	lr, #1
16946
-	beq	.L2824
16947
-.L2826:
16948
-	ldr	r1, [r9, #1688]
17441
+	beq	.L2763
17442
+.L2762:
16949
17443
 	mov	r2, r8
17444
+	ldr	r1, [r9, #1696]
16950
17445
 	mov	r0, r5
16951
17446
 	bl	ftl_memcpy
16952
-	mov	r2, #4
16953
-	ldr	r0, .L2835+8
17447
+	mov	r3, #4
17448
+	ldr	r0, .L2771+8
17449
+	mov	r2, r3
16954
17450
 	mov	r1, r5
16955
-	mov	r3, r2
16956
17451
 	bl	rknand_print_hex
16957
17452
 	mov	r0, #0
16958
-	b	.L2823
16959
-.L2824:
16960
-	ldr	r2, [r9, #1708]
16961
-	uxth	r3, r7
16962
-	add	r7, r7, #1
16963
-	cmp	r3, r2
16964
-	bcs	.L2826
16965
-	ldr	r1, [ip, #1688]
16966
-	mov	r0, r3, lsr #5
16967
-	and	r4, r3, #31
16968
-	ldr	r2, [r1, r0, asl #2]
16969
-	orr	r4, r2, lr, asl r4
16970
-	str	r4, [r1, r0, asl #2]
16971
-	b	.L2824
16972
-.L2822:
16973
-	sub	r6, r6, #1
16974
-	uxth	r6, r6
16975
-	b	.L2821
16976
-.L2834:
16977
-	mvn	r0, #0
16978
-.L2823:
17453
+.L2758:
16979
17454
 	add	sp, sp, #40
16980
17455
 	@ sp needed
16981
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
16982
-.L2836:
17456
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
17457
+.L2764:
17458
+	ldr	r0, [r9, #1696]
17459
+	lsr	ip, r3, #5
17460
+	and	r3, r3, #31
17461
+	ldr	r2, [r0, ip, lsl #2]
17462
+	orr	r3, r2, lr, lsl r3
17463
+	str	r3, [r0, ip, lsl #2]
17464
+.L2763:
17465
+	ldr	r0, [r9, #1716]
17466
+	uxth	r3, r1
17467
+	add	r1, r1, #1
17468
+	cmp	r3, r0
17469
+	bcc	.L2764
17470
+	b	.L2762
17471
+.L2760:
17472
+	sub	r6, r6, #1
17473
+	uxth	r6, r6
17474
+	b	.L2759
17475
+.L2772:
16983
17476
 	.align	2
16984
-.L2835:
17477
+.L2771:
16985
17478
 	.word	.LANCHOR0
16986
17479
 	.word	.LANCHOR2
16987
17480
 	.word	.LC139
..
..
@@ -16989,378 +17482,371 @@
16989
17482
 	.size	FlashReadFacBbtData, .-FlashReadFacBbtData
16990
17483
 	.align	2
16991
17484
 	.global	FlashGetBadBlockList
17485
+	.syntax unified
17486
+	.arm
17487
+	.fpu softvfp
16992
17488
 	.type	FlashGetBadBlockList, %function
16993
17489
 FlashGetBadBlockList:
16994
17490
 	.fnstart
16995
17491
 	@ args = 0, pretend = 0, frame = 0
16996
17492
 	@ frame_needed = 0, uses_anonymous_args = 0
16997
-	ldr	r3, .L2848
16998
-	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
17493
+	ldr	r3, .L2784
17494
+	push	{r4, r5, r6, r7, r8, lr}
16999
17495
 	.save {r4, r5, r6, r7, r8, lr}
17000
17496
 	mov	r5, r0
17001
-	ldr	r3, [r3, #44]
17002
-	ldr	r6, .L2848+4
17497
+	ldr	r6, .L2784+4
17498
+	ldr	r3, [r3, #48]
17499
+	ldr	r0, [r6, #1724]
17003
17500
 	ldrb	r4, [r3, #13]	@ zero_extendqisi2
17004
17501
 	ldrh	r3, [r3, #14]
17005
-	ldr	r0, [r6, #1716]
17006
17502
 	smulbb	r4, r4, r3
17007
17503
 	uxth	r4, r4
17008
17504
 	add	r2, r4, #7
17009
-	mov	r2, r2, asr #3
17505
+	asr	r2, r2, #3
17010
17506
 	bl	FlashReadFacBbtData
17011
17507
 	cmn	r0, #1
17012
-	bne	.L2838
17013
-.L2842:
17508
+	bne	.L2774
17509
+.L2778:
17014
17510
 	mov	r3, #0
17015
-	b	.L2839
17016
-.L2838:
17017
-	mov	lr, r4, lsr #4
17018
-	mov	ip, #0
17019
-	sub	r4, r4, #1
17020
-	mov	r3, ip
17021
-	mov	r7, #1
17022
-.L2840:
17023
-	uxth	r0, ip
17024
-	cmp	r0, r4
17025
-	bge	.L2839
17026
-	ldr	r8, [r6, #1716]
17027
-	mov	r1, r0, lsr #5
17028
-	and	r2, r0, #31
17029
-	add	ip, ip, #1
17030
-	ldr	r1, [r8, r1, asl #2]
17031
-	ands	r2, r1, r7, asl r2
17032
-	addne	r2, r3, #1
17033
-	movne	r3, r3, asl #1
17034
-	strneh	r0, [r5, r3]	@ movhi
17035
-	uxthne	r3, r2
17036
-	cmp	r3, lr
17037
-	bcc	.L2840
17038
-	b	.L2842
17039
-.L2839:
17040
-	mov	r3, r3, asl #1
17511
+.L2775:
17512
+	lsl	r3, r3, #1
17041
17513
 	mvn	r2, #0
17042
17514
 	mov	r0, #0
17043
17515
 	strh	r2, [r5, r3]	@ movhi
17044
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
17045
-.L2849:
17516
+	pop	{r4, r5, r6, r7, r8, pc}
17517
+.L2774:
17518
+	mov	r2, #0
17519
+	lsr	lr, r4, #4
17520
+	mov	r3, r2
17521
+	sub	r4, r4, #1
17522
+	mov	r7, #1
17523
+.L2776:
17524
+	uxth	r1, r2
17525
+	cmp	r1, r4
17526
+	bge	.L2775
17527
+	ldr	r8, [r6, #1724]
17528
+	lsr	ip, r1, #5
17529
+	and	r0, r1, #31
17530
+	add	r2, r2, #1
17531
+	ldr	ip, [r8, ip, lsl #2]
17532
+	ands	r0, ip, r7, lsl r0
17533
+	addne	r0, r3, #1
17534
+	lslne	r3, r3, #1
17535
+	strhne	r1, [r5, r3]	@ movhi
17536
+	uxthne	r3, r0
17537
+	cmp	r3, lr
17538
+	bcc	.L2776
17539
+	b	.L2778
17540
+.L2785:
17046
17541
 	.align	2
17047
-.L2848:
17542
+.L2784:
17048
17543
 	.word	.LANCHOR0
17049
17544
 	.word	.LANCHOR2
17050
17545
 	.fnend
17051
17546
 	.size	FlashGetBadBlockList, .-FlashGetBadBlockList
17052
17547
 	.align	2
17053
17548
 	.global	FtlMakeBbt
17549
+	.syntax unified
17550
+	.arm
17551
+	.fpu softvfp
17054
17552
 	.type	FtlMakeBbt, %function
17055
17553
 FtlMakeBbt:
17056
17554
 	.fnstart
17057
17555
 	@ args = 0, pretend = 0, frame = 8
17058
17556
 	@ frame_needed = 0, uses_anonymous_args = 0
17059
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
17557
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
17060
17558
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
17061
17559
 	.pad #12
17062
-	ldr	r4, .L2874
17063
-	ldr	r5, [r4, #-3616]
17064
-	cmp	r5, #0
17065
-	bne	.L2851
17560
+	ldr	r4, .L2807
17561
+	ldr	r8, [r4, #-3612]
17562
+	cmp	r8, #0
17563
+	bne	.L2787
17564
+	ldr	r9, .L2807+4
17066
17565
 	bl	FtlBbtMemInit
17067
-	ldr	r7, .L2874+4
17068
17566
 	bl	FtlLoadFactoryBbt
17069
-	sub	r9, r7, #18
17070
-	sub	r10, r7, #94
17071
-.L2852:
17072
-	ldr	r3, .L2874+8
17073
-	ldr	r6, .L2874+12
17567
+	sub	r10, r9, #18
17568
+	sub	r5, r9, #28
17569
+.L2788:
17570
+	ldr	r3, .L2807+8
17571
+	ldr	r6, .L2807+12
17074
17572
 	ldrh	r3, [r3]
17075
-	cmp	r5, r3
17076
-	bcs	.L2871
17077
-	ldrh	r3, [r9, #2]!
17573
+	cmp	r8, r3
17574
+	bcc	.L2794
17575
+	ldr	r8, .L2807+16
17576
+	mov	r7, #0
17577
+.L2795:
17578
+	ldrh	r3, [r8]
17579
+	uxth	r0, r7
17580
+	add	r7, r7, #1
17581
+	cmp	r3, r0
17582
+	bhi	.L2796
17583
+	ldrh	r7, [r5, #12]
17584
+	movw	r8, #65535
17585
+	sub	r7, r7, #1
17586
+	uxth	r7, r7
17587
+.L2797:
17588
+	ldrh	r3, [r5, #12]
17589
+	sub	r3, r3, #48
17590
+	cmp	r7, r3
17591
+	ble	.L2801
17592
+	mov	r0, r7
17593
+	bl	FtlBbmIsBadBlock
17594
+	cmp	r0, #1
17595
+	beq	.L2798
17596
+	mov	r0, r7
17597
+	bl	FlashTestBlk
17598
+	cmp	r0, #0
17599
+	beq	.L2799
17600
+	mov	r0, r7
17601
+	bl	FtlBbmMapBadBlock
17602
+.L2798:
17603
+	sub	r7, r7, #1
17604
+	uxth	r7, r7
17605
+	b	.L2797
17606
+.L2794:
17607
+	ldr	r3, [r4, #-500]
17078
17608
 	movw	r2, #65535
17079
17609
 	ldr	r0, [r4, #-524]
17080
-	ldr	fp, [r4, #-500]
17610
+	ldr	fp, .L2807+20
17611
+	str	r3, [sp, #4]
17612
+	str	r3, [r4, #1772]
17613
+	ldrh	r3, [r10, #2]!
17614
+	str	r0, [r4, #1768]
17081
17615
 	cmp	r3, r2
17082
-	ldr	r8, .L2874
17083
-	str	r0, [r4, #1760]
17084
-	str	fp, [r4, #1764]
17085
-	beq	.L2853
17086
-	ldrh	ip, [r10]
17087
-	mov	r1, #1
17088
-	mov	r2, r1
17089
-	ldr	r0, .L2874+16
17090
-	mla	ip, ip, r5, r3
17091
-	mov	r3, ip, asl #10
17092
-	str	ip, [sp, #4]
17093
-	str	r3, [r8, #1756]
17616
+	beq	.L2789
17617
+	ldrh	r7, [fp]
17618
+	mov	r2, #1
17619
+	mov	r1, r2
17620
+	ldr	r0, .L2807+24
17621
+	mla	r7, r8, r7, r3
17622
+	lsl	r3, r7, #10
17623
+	str	r3, [r4, #1764]
17094
17624
 	bl	FlashReadPages
17095
-	ldrh	r2, [r10]
17096
-	ldr	r0, [r7]
17625
+	ldrh	r2, [fp]
17626
+	ldr	r1, [r4, #1768]
17627
+	ldr	r0, [r9]
17097
17628
 	add	r2, r2, #7
17098
-	ldr	r1, [r8, #1760]
17099
-	mov	r2, r2, asr #3
17629
+	asr	r2, r2, #3
17100
17630
 	bl	ftl_memcpy
17101
-	ldr	ip, [sp, #4]
17102
-	b	.L2854
17103
-.L2853:
17104
-	mov	r1, r5
17105
-	sub	r8, r8, #436
17631
+.L2790:
17632
+	uxth	r0, r7
17633
+	add	r8, r8, #1
17634
+	add	r9, r9, #4
17635
+	bl	FtlBbmMapBadBlock
17636
+	b	.L2788
17637
+.L2789:
17638
+	mov	r1, r8
17106
17639
 	bl	FlashGetBadBlockList
17107
-	ldr	r0, [r8, #2196]
17108
-	ldr	r1, [r7]
17640
+	ldr	r1, [r9]
17641
+	ldr	r0, [r4, #1768]
17109
17642
 	bl	FtlBbt2Bitmap
17110
-	ldrh	r6, [r10]
17643
+	ldrh	r6, [fp]
17644
+.L2792:
17111
17645
 	sub	r6, r6, #1
17112
17646
 	uxth	r6, r6
17113
-.L2855:
17114
-	ldrh	r0, [r10]
17115
-	smlabb	r0, r0, r5, r6
17647
+.L2791:
17648
+	ldrh	r0, [fp]
17649
+	smlabb	r0, r0, r8, r6
17116
17650
 	uxth	r0, r0
17117
17651
 	bl	FtlBbmIsBadBlock
17118
17652
 	cmp	r0, #1
17119
-	subeq	r6, r6, #1
17120
-	uxtheq	r6, r6
17121
-	beq	.L2855
17122
-.L2872:
17123
-	mov	r1, #0
17653
+	beq	.L2792
17124
17654
 	mov	r2, #16
17125
-	strh	r6, [r9]	@ movhi
17655
+	mov	r1, #0
17656
+	strh	r6, [r10]	@ movhi
17126
17657
 	ldr	r0, [r4, #-500]
17127
17658
 	bl	ftl_memset
17128
-	ldr	r3, .L2874+20
17129
-	strh	r3, [fp]	@ movhi
17659
+	ldr	r3, [sp, #4]
17660
+	movw	r2, 61664	@ movhi
17661
+	strh	r2, [r3]	@ movhi
17130
17662
 	mov	r3, #0
17131
-	str	r3, [fp, #4]
17132
-	ldrh	r3, [r9]
17133
-	ldrh	ip, [r10]
17134
-	ldrh	r2, [r8]
17135
-	strh	r3, [fp, #2]	@ movhi
17136
-	ldrh	r3, [r9]
17137
-	ldr	r1, [r7]
17138
-	mov	r2, r2, asl #2
17139
-	ldr	r0, [r4, #1760]
17140
-	mla	ip, ip, r5, r3
17141
-	mov	r3, ip, asl #10
17142
-	str	r3, [r4, #1756]
17143
-	str	ip, [sp, #4]
17663
+	ldr	r2, [sp, #4]
17664
+	ldrh	r7, [fp]
17665
+	str	r3, [r2, #4]
17666
+	ldrh	r3, [r10]
17667
+	strh	r3, [r2, #2]	@ movhi
17668
+	ldrh	r3, [r10]
17669
+	ldr	r1, [r9]
17670
+	ldr	r0, [r4, #1768]
17671
+	mla	r7, r8, r7, r3
17672
+	lsl	r3, r7, #10
17673
+	str	r3, [r4, #1764]
17674
+	ldr	r3, .L2807+28
17675
+	ldrh	r2, [r3]
17676
+	lsl	r2, r2, #2
17144
17677
 	bl	ftl_memcpy
17145
-	mov	r1, #1
17146
-	ldr	r0, .L2874+16
17147
-	mov	r2, r1
17678
+	mov	r2, #1
17679
+	ldr	r0, .L2807+24
17680
+	mov	r1, r2
17148
17681
 	bl	FlashEraseBlocks
17149
-	mov	r1, #1
17150
-	mov	r3, r1
17151
-	ldr	r0, .L2874+16
17152
-	mov	r2, r1
17682
+	mov	r3, #1
17683
+	ldr	r0, .L2807+24
17684
+	mov	r2, r3
17685
+	mov	r1, r3
17153
17686
 	bl	FlashProgPages
17154
-	ldr	r3, [r4, #1752]
17687
+	ldr	r3, [r4, #1760]
17155
17688
 	cmn	r3, #1
17156
-	ldr	ip, [sp, #4]
17157
-	bne	.L2854
17158
-	uxth	r0, ip
17689
+	bne	.L2790
17690
+	uxth	r0, r7
17159
17691
 	bl	FtlBbmMapBadBlock
17160
-	b	.L2855
17161
-.L2854:
17162
-	uxth	r0, ip
17163
-	add	r5, r5, #1
17692
+	b	.L2791
17693
+.L2796:
17164
17694
 	bl	FtlBbmMapBadBlock
17165
-	add	r7, r7, #4
17166
-	b	.L2852
17167
-.L2871:
17168
-	ldr	r7, .L2874+24
17169
-	mov	r5, #0
17170
-.L2859:
17171
-	ldrh	r3, [r7]
17172
-	uxth	r0, r5
17173
-	add	r5, r5, #1
17174
-	cmp	r3, r0
17175
-	bls	.L2873
17176
-	bl	FtlBbmMapBadBlock
17177
-	b	.L2859
17178
-.L2873:
17179
-	ldr	r7, .L2874+28
17180
-	movw	r9, #65535
17181
-	ldrh	r5, [r7, #12]
17182
-	mov	r8, r7
17183
-	sub	r5, r5, #1
17184
-	uxth	r5, r5
17185
-.L2861:
17186
-	ldrh	r3, [r7, #12]
17187
-	sub	r3, r3, #48
17188
-	cmp	r5, r3
17189
-	ble	.L2865
17190
-	mov	r0, r5
17191
-	bl	FtlBbmIsBadBlock
17192
-	cmp	r0, #1
17193
-	beq	.L2862
17194
-	mov	r0, r5
17195
-	bl	FlashTestBlk
17196
-	cmp	r0, #0
17197
-	beq	.L2863
17198
-	mov	r0, r5
17199
-	bl	FtlBbmMapBadBlock
17200
-	b	.L2862
17201
-.L2863:
17202
-	ldrh	r3, [r8]
17203
-	cmp	r3, r9
17204
-	streqh	r5, [r8]	@ movhi
17205
-.L2864:
17206
-	ldrne	r3, .L2874+28
17207
-	strneh	r5, [r3, #4]	@ movhi
17208
-	bne	.L2865
17209
-.L2862:
17210
-	sub	r5, r5, #1
17211
-	uxth	r5, r5
17212
-	b	.L2861
17213
-.L2865:
17214
-	movw	r5, #2452
17215
-	ldr	r0, [r4, #-3612]
17216
-	ldrh	r3, [r6, r5]
17695
+	b	.L2795
17696
+.L2799:
17697
+	ldrh	r3, [r5]
17698
+	cmp	r3, r8
17699
+	strheq	r7, [r5]	@ movhi
17700
+	beq	.L2798
17701
+.L2800:
17702
+	strh	r7, [r5, #4]	@ movhi
17703
+.L2801:
17704
+	movw	r7, #2456
17705
+	ldr	r0, [r4, #-3608]
17706
+	ldrh	r3, [r6, r7]
17217
17707
 	mov	r8, #0
17218
-	str	r8, [r6, #2460]
17708
+	str	r8, [r6, #2464]
17219
17709
 	mov	r2, #2
17220
17710
 	mov	r1, #1
17221
-	strh	r8, [r7, #2]	@ movhi
17222
-	mov	r3, r3, asl #10
17711
+	strh	r8, [r5, #2]	@ movhi
17712
+	lsl	r3, r3, #10
17223
17713
 	str	r3, [r0, #4]
17224
-	ldrh	r3, [r7, #4]
17225
-	mov	r3, r3, asl #10
17714
+	ldrh	r3, [r5, #4]
17715
+	lsl	r3, r3, #10
17226
17716
 	str	r3, [r0, #40]
17227
17717
 	bl	FlashEraseBlocks
17228
-	ldrh	r0, [r6, r5]
17718
+	ldrh	r0, [r6, r7]
17229
17719
 	bl	FtlBbmMapBadBlock
17230
-	ldrh	r0, [r7, #4]
17720
+	ldrh	r0, [r5, #4]
17231
17721
 	bl	FtlBbmMapBadBlock
17232
17722
 	bl	FtlBbmTblFlush
17233
-	ldr	r3, [r6, #2460]
17234
-	ldrh	r2, [r7, #4]
17723
+	ldr	r3, [r6, #2464]
17724
+	ldrh	r2, [r5, #4]
17725
+	strh	r8, [r5, #2]	@ movhi
17235
17726
 	add	r3, r3, #1
17236
-	str	r3, [r6, #2460]
17237
-	ldrh	r3, [r6, r5]
17238
-	strh	r8, [r7, #2]	@ movhi
17239
-	strh	r2, [r6, r5]	@ movhi
17240
-	strh	r3, [r7, #4]	@ movhi
17727
+	str	r3, [r6, #2464]
17728
+	ldrh	r3, [r6, r7]
17729
+	strh	r2, [r6, r7]	@ movhi
17730
+	strh	r3, [r5, #4]	@ movhi
17241
17731
 	bl	FtlBbmTblFlush
17242
-.L2851:
17732
+.L2787:
17243
17733
 	mov	r0, #0
17244
17734
 	add	sp, sp, #12
17245
17735
 	@ sp needed
17246
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
17247
-.L2875:
17736
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
17737
+.L2808:
17248
17738
 	.align	2
17249
-.L2874:
17739
+.L2807:
17250
17740
 	.word	.LANCHOR2
17251
-	.word	.LANCHOR0+2480
17252
-	.word	.LANCHOR0+2342
17741
+	.word	.LANCHOR0+2484
17742
+	.word	.LANCHOR0+2346
17253
17743
 	.word	.LANCHOR0
17254
-	.word	.LANCHOR2+1752
17255
-	.word	-3872
17256
-	.word	.LANCHOR0+2402
17257
-	.word	.LANCHOR0+2452
17744
+	.word	.LANCHOR0+2404
17745
+	.word	.LANCHOR0+2388
17746
+	.word	.LANCHOR2+1760
17747
+	.word	.LANCHOR2-436
17258
17748
 	.fnend
17259
17749
 	.size	FtlMakeBbt, .-FtlMakeBbt
17260
17750
 	.align	2
17261
17751
 	.global	log2phys
17752
+	.syntax unified
17753
+	.arm
17754
+	.fpu softvfp
17262
17755
 	.type	log2phys, %function
17263
17756
 log2phys:
17264
17757
 	.fnstart
17265
-	@ args = 0, pretend = 0, frame = 8
17758
+	@ args = 0, pretend = 0, frame = 16
17266
17759
 	@ frame_needed = 0, uses_anonymous_args = 0
17267
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
17760
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
17268
17761
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
17269
-	.pad #12
17270
-	movw	r3, #2396
17271
-	ldr	r7, .L2893
17272
-	ldrh	r10, [r7, r3]
17273
-	ldr	r3, [r7, #2448]
17762
+	.pad #20
17763
+	sub	sp, sp, #20
17764
+	ldr	r8, .L2825
17765
+	ldr	r3, [r8, #2452]
17274
17766
 	cmp	r0, r3
17275
-	bcs	.L2877
17276
-	add	r10, r10, #7
17277
-	ldr	fp, .L2893+4
17278
-	mov	r5, r0, lsr r10
17279
-	movw	r3, #2426
17280
-	str	r2, [sp, #4]
17281
-	mov	r9, r1
17282
-	mov	r6, r7
17283
-	str	r0, [sp]
17284
-	uxth	r5, r5
17285
-	ldrh	r2, [r7, r3]
17286
-	ldr	r8, [fp, #-3380]
17287
-	mov	r4, #0
17288
-	mov	r1, #12
17289
-	b	.L2878
17290
-.L2877:
17767
+	bcs	.L2810
17768
+	movw	r3, #2398
17769
+	mov	r10, r0
17770
+	ldrh	r0, [r8, r3]
17771
+	mov	r5, #12
17772
+	ldr	r4, .L2825+4
17773
+	str	r1, [sp, #8]
17774
+	add	r3, r0, #7
17775
+	str	r2, [sp, #12]
17776
+	lsr	r6, r10, r3
17777
+	ldr	fp, [r4, #-3376]
17778
+	str	r3, [sp, #4]
17779
+	movw	r3, #2430
17780
+	uxth	r9, r6
17781
+	ldrh	r1, [r8, r3]
17782
+	mov	r3, #0
17783
+.L2811:
17784
+	uxth	r7, r3
17785
+	cmp	r7, r1
17786
+	bcc	.L2816
17787
+	bl	select_l2p_ram_region
17788
+	mul	r5, r5, r0
17789
+	movw	r2, #65535
17790
+	mov	r7, r0
17791
+	ldrh	r1, [fp, r5]
17792
+	add	r3, fp, r5
17793
+	cmp	r1, r2
17794
+	beq	.L2817
17795
+	ldr	r3, [r3, #4]
17796
+	cmp	r3, #0
17797
+	bge	.L2817
17798
+	bl	flush_l2p_region
17799
+.L2817:
17800
+	ldr	r3, [r4, #-452]
17801
+	uxth	r6, r6
17802
+	ldr	fp, [r3, r6, lsl #2]
17803
+	cmp	fp, #0
17804
+	bne	.L2818
17805
+	ldr	r0, [r4, #-3376]
17806
+	mov	r1, #255
17807
+	ldr	r2, .L2825+8
17808
+	add	r0, r0, r5
17809
+	ldrh	r2, [r2]
17810
+	ldr	r0, [r0, #8]
17811
+	bl	ftl_memset
17812
+	ldr	r2, [r4, #-3376]
17813
+	strh	r9, [r2, r5]	@ movhi
17814
+	ldr	r2, [r4, #-3376]
17815
+	add	r5, r2, r5
17816
+	str	fp, [r5, #4]
17817
+	b	.L2813
17818
+.L2810:
17291
17819
 	cmp	r2, #0
17292
17820
 	mvn	r0, #0
17293
17821
 	streq	r0, [r1]
17294
-	b	.L2879
17295
-.L2883:
17296
-	add	r4, r4, #1
17297
-	mla	r0, r1, r4, r8
17822
+.L2809:
17823
+	add	sp, sp, #20
17824
+	@ sp needed
17825
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
17826
+.L2816:
17827
+	add	r3, r3, #1
17828
+	mla	r0, r5, r3, fp
17298
17829
 	ldrh	r0, [r0, #-12]
17299
-	cmp	r0, r5
17300
-	beq	.L2880
17301
-.L2878:
17302
-	uxth	r7, r4
17303
-	cmp	r7, r2
17304
-	bcc	.L2883
17305
-	bl	select_l2p_ram_region
17306
-	mov	r4, #12
17307
-	movw	r3, #65535
17308
-	mul	r4, r4, r0
17309
-	mov	r7, r0
17310
-	add	r2, r8, r4
17311
-	ldrh	r1, [r8, r4]
17312
-	cmp	r1, r3
17313
-	bne	.L2892
17314
-.L2884:
17315
-	ldr	r3, [fp, #-452]
17316
-	ldr	r8, .L2893+4
17317
-	ldr	fp, [r3, r5, asl #2]
17318
-	cmp	fp, #0
17319
-	bne	.L2885
17320
-	ldr	r3, [r8, #-3380]
17321
-	mov	r1, #255
17322
-	add	r3, r3, r4
17323
-	ldr	r0, [r3, #8]
17324
-	movw	r3, #2398
17325
-	ldrh	r2, [r6, r3]
17326
-	bl	ftl_memset
17327
-	ldr	r3, [r8, #-3380]
17328
-	strh	r5, [r3, r4]	@ movhi
17329
-	ldr	r3, [r8, #-3380]
17330
-	add	r4, r3, r4
17331
-	str	fp, [r4, #4]
17332
-.L2880:
17333
-	ldr	r2, [sp]
17334
-	mvn	r3, #0
17335
-	mov	r6, #12
17336
-	bic	r10, r2, r3, asl r10
17830
+	cmp	r0, r9
17831
+	bne	.L2811
17832
+.L2813:
17337
17833
 	ldr	r3, [sp, #4]
17338
-	ldr	r2, .L2893+4
17339
-	cmp	r3, #0
17834
+	mvn	r0, #0
17835
+	ldr	r1, .L2825+4
17836
+	bic	r10, r10, r0, lsl r3
17837
+	ldr	r3, [sp, #12]
17340
17838
 	uxth	r10, r10
17341
-	bne	.L2881
17342
-	ldr	r3, [r2, #-3380]
17343
-	mla	r6, r6, r7, r3
17344
-	ldr	r3, [r6, #8]
17345
-	ldr	r3, [r3, r10, asl #2]
17346
-	str	r3, [r9]
17347
-	b	.L2882
17348
-.L2881:
17349
-	mul	r6, r6, r7
17350
-	ldr	r3, [r2, #-3380]
17351
-	ldr	r1, [r9]
17352
-	add	r3, r3, r6
17839
+	cmp	r3, #0
17840
+	mov	r3, #12
17841
+	bne	.L2814
17842
+	ldr	r2, [r1, #-3376]
17843
+	mla	r3, r3, r7, r2
17844
+	ldr	r2, [sp, #8]
17353
17845
 	ldr	r3, [r3, #8]
17354
-	str	r1, [r3, r10, asl #2]
17355
-	ldr	r3, [r2, #-3380]
17356
-	add	r6, r3, r6
17357
-	ldr	r3, [r6, #4]
17358
-	orr	r3, r3, #-2147483648
17359
-	str	r3, [r6, #4]
17360
-	sub	r3, r2, #3376
17361
-	strh	r5, [r3]	@ movhi
17362
-.L2882:
17363
-	ldr	r2, [r2, #-3380]
17846
+	ldr	r3, [r3, r10, lsl #2]
17847
+	str	r3, [r2]
17848
+.L2815:
17849
+	ldr	r2, [r1, #-3376]
17364
17850
 	mov	r3, #12
17365
17851
 	mov	r0, #0
17366
17852
 	mla	r7, r3, r7, r2
..
..
@@ -17368,1841 +17854,1868 @@
17368
17854
 	cmn	r3, #1
17369
17855
 	addne	r3, r3, #1
17370
17856
 	strne	r3, [r7, #4]
17371
-	b	.L2879
17372
-.L2892:
17373
-	ldr	r3, [r2, #4]
17374
-	cmp	r3, #0
17375
-	bge	.L2884
17376
-	bl	flush_l2p_region
17377
-	b	.L2884
17378
-.L2885:
17379
-	ldr	r3, [r8, #-3380]
17380
-	mov	r1, #1
17381
-	ldr	r0, .L2893+8
17382
-	mov	r2, r1
17383
-	add	r3, r3, r4
17384
-	str	fp, [r8, #1756]
17385
-	ldr	r3, [r3, #8]
17386
-	str	r3, [r8, #1760]
17387
-	ldr	r3, [r8, #-500]
17388
-	str	r3, [r8, #1764]
17857
+	b	.L2809
17858
+.L2814:
17859
+	ldr	r2, [sp, #8]
17860
+	mul	r3, r3, r7
17861
+	ldr	r0, [r2]
17862
+	ldr	r2, [r4, #-3376]
17863
+	add	r2, r2, r3
17864
+	ldr	r2, [r2, #8]
17865
+	str	r0, [r2, r10, lsl #2]
17866
+	ldr	r2, [r4, #-3376]
17867
+	add	r3, r2, r3
17868
+	ldr	r2, [r3, #4]
17869
+	orr	r2, r2, #-2147483648
17870
+	str	r2, [r3, #4]
17871
+	sub	r3, r1, #3360
17872
+	strh	r9, [r3, #-12]	@ movhi
17873
+	b	.L2815
17874
+.L2818:
17875
+	ldr	r2, [r4, #-3376]
17876
+	ldr	r0, .L2825+12
17877
+	str	fp, [r4, #1764]
17878
+	add	r2, r2, r5
17879
+	ldr	r2, [r2, #8]
17880
+	str	r2, [r4, #1768]
17881
+	ldr	r2, [r4, #-500]
17882
+	str	r2, [r4, #1772]
17883
+	mov	r2, #1
17884
+	mov	r1, r2
17389
17885
 	bl	FlashReadPages
17390
-	ldr	r3, [r8, #1764]
17391
-	ldrh	r3, [r3, #8]
17392
-	cmp	r3, r5
17393
-	beq	.L2886
17394
-	mov	r1, r5
17886
+	ldr	r2, [r4, #1772]
17887
+	ldrh	r2, [r2, #8]
17888
+	cmp	r2, r9
17889
+	beq	.L2819
17395
17890
 	mov	r2, fp
17396
-	ldr	r0, .L2893+12
17891
+	mov	r1, r6
17892
+	ldr	r0, .L2825+16
17397
17893
 	bl	printk
17398
-	mov	r2, #4
17399
-	mov	r3, r2
17400
-	ldr	r0, .L2893+16
17401
-	ldr	r1, [r8, #1764]
17894
+	mov	r3, #4
17895
+	ldr	r1, [r4, #1772]
17896
+	mov	r2, r3
17897
+	ldr	r0, .L2825+20
17402
17898
 	bl	rknand_print_hex
17403
-	movw	r3, #2424
17404
-	ldrh	r3, [r6, r3]
17899
+	movw	r3, #2428
17405
17900
 	mov	r2, #4
17406
-	ldr	r0, .L2893+20
17407
-	ldr	r1, [r8, #-452]
17901
+	ldrh	r3, [r8, r3]
17902
+	ldr	r1, [r4, #-452]
17903
+	ldr	r0, .L2825+24
17408
17904
 	bl	rknand_print_hex
17409
17905
 	mov	r3, #1
17410
-	str	r3, [r8, #-3616]
17411
-	b	.L2887
17412
-.L2886:
17413
-	ldr	r3, [r8, #1752]
17414
-	cmp	r3, #256
17415
-	bne	.L2887
17416
-	mov	r1, r5
17906
+	str	r3, [r4, #-3612]
17907
+.L2820:
17908
+	ldr	r3, .L2825+4
17909
+	mov	r1, #0
17910
+	ldr	r3, [r3, #-3376]
17911
+	add	r2, r3, r5
17912
+	str	r1, [r2, #4]
17913
+	strh	r9, [r3, r5]	@ movhi
17914
+	b	.L2813
17915
+.L2819:
17916
+	ldr	r2, [r4, #1760]
17917
+	cmp	r2, #256
17918
+	bne	.L2820
17417
17919
 	mov	r2, fp
17418
-	ldr	r0, .L2893+24
17920
+	mov	r1, r6
17921
+	ldr	r0, .L2825+28
17419
17922
 	bl	printk
17420
-	ldr	r3, [r8, #-3380]
17421
-	sub	r0, r8, #432
17422
-	mov	r1, r5
17423
-	add	r3, r3, r4
17923
+	ldr	r3, [r4, #-3376]
17924
+	mov	r1, r6
17925
+	ldr	r0, .L2825+32
17926
+	add	r3, r3, r5
17424
17927
 	ldr	r2, [r3, #8]
17425
17928
 	bl	FtlMapWritePage
17426
-.L2887:
17427
-	ldr	r3, .L2893+4
17428
-	mov	r1, #0
17429
-	ldr	r3, [r3, #-3380]
17430
-	add	r2, r3, r4
17431
-	str	r1, [r2, #4]
17432
-	strh	r5, [r3, r4]	@ movhi
17433
-	b	.L2880
17434
-.L2879:
17435
-	add	sp, sp, #12
17436
-	@ sp needed
17437
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
17438
-.L2894:
17929
+	b	.L2820
17930
+.L2826:
17439
17931
 	.align	2
17440
-.L2893:
17932
+.L2825:
17441
17933
 	.word	.LANCHOR0
17442
17934
 	.word	.LANCHOR2
17443
-	.word	.LANCHOR2+1752
17935
+	.word	.LANCHOR0+2400
17936
+	.word	.LANCHOR2+1760
17444
17937
 	.word	.LC140
17445
17938
 	.word	.LC101
17446
17939
 	.word	.LC141
17447
17940
 	.word	.LC142
17941
+	.word	.LANCHOR2-432
17448
17942
 	.fnend
17449
17943
 	.size	log2phys, .-log2phys
17450
17944
 	.align	2
17451
17945
 	.global	FtlWriteDumpData
17946
+	.syntax unified
17947
+	.arm
17948
+	.fpu softvfp
17452
17949
 	.type	FtlWriteDumpData, %function
17453
17950
 FtlWriteDumpData:
17454
17951
 	.fnstart
17455
17952
 	@ args = 0, pretend = 0, frame = 40
17456
17953
 	@ frame_needed = 0, uses_anonymous_args = 0
17457
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
17954
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
17458
17955
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
17459
17956
 	.pad #44
17460
17957
 	sub	sp, sp, #44
17461
-	ldr	r4, .L2915
17462
-	ldr	r3, [r4, #-3616]
17958
+	ldr	r4, .L2846
17959
+	ldr	r3, [r4, #-3612]
17463
17960
 	cmp	r3, #0
17464
-	bne	.L2895
17465
-	ldr	r3, .L2915+4
17466
-	ldrh	r2, [r3, #4]
17961
+	bne	.L2827
17962
+	sub	r6, r4, #3520
17963
+	ldrh	r2, [r6, #4]
17467
17964
 	cmp	r2, #0
17468
-	beq	.L2897
17469
-	ldrb	r3, [r4, #-3516]	@ zero_extendqisi2
17965
+	beq	.L2829
17966
+	ldrb	r3, [r4, #-3512]	@ zero_extendqisi2
17470
17967
 	cmp	r3, #0
17471
-	bne	.L2897
17472
-	ldr	r8, .L2915+8
17473
-	movw	r3, #2388
17474
-	ldrb	r1, [r4, #-3517]	@ zero_extendqisi2
17968
+	bne	.L2829
17969
+	ldr	r8, .L2846+4
17970
+	movw	r3, #2390
17971
+	ldrb	r1, [r4, #-3513]	@ zero_extendqisi2
17475
17972
 	ldrh	r3, [r8, r3]
17476
17973
 	mul	r3, r3, r1
17477
17974
 	cmp	r2, r3
17478
-	beq	.L2897
17479
-	ldrb	r9, [r4, #-3514]	@ zero_extendqisi2
17480
-	add	r3, r8, #2320
17481
-	ldr	r6, [r8, #2448]
17482
-	cmp	r9, #0
17483
-	ldrh	r7, [r3]
17484
-	bne	.L2895
17485
-	sub	r6, r6, #1
17975
+	beq	.L2829
17976
+	ldrb	r10, [r4, #-3510]	@ zero_extendqisi2
17977
+	cmp	r10, #0
17978
+	bne	.L2827
17979
+	ldr	r7, [r8, #2452]
17980
+	movw	r3, #2324
17981
+	mov	r2, r10
17486
17982
 	mov	r1, sp
17487
-	mov	r2, r9
17488
-	mov	r0, r6
17983
+	ldrh	r9, [r8, r3]
17984
+	sub	r7, r7, #1
17985
+	mov	r0, r7
17489
17986
 	bl	log2phys
17987
+	ldr	r3, [sp]
17490
17988
 	ldr	r5, [r4, #-500]
17491
17989
 	ldr	r0, [r4, #-524]
17492
-	ldr	r3, [sp]
17493
-	str	r6, [sp, #20]
17494
17990
 	cmn	r3, #1
17495
-	str	r0, [sp, #12]
17496
17991
 	str	r3, [sp, #8]
17992
+	str	r7, [sp, #20]
17993
+	str	r0, [sp, #12]
17497
17994
 	str	r5, [sp, #16]
17498
-	str	r9, [r5, #4]
17499
-	beq	.L2899
17995
+	str	r10, [r5, #4]
17996
+	beq	.L2831
17997
+	mov	r2, r10
17500
17998
 	mov	r1, #1
17501
-	mov	r2, r9
17502
17999
 	add	r0, sp, #4
17503
18000
 	bl	FlashReadPages
17504
-	b	.L2900
17505
-.L2899:
17506
-	movw	r3, #2398
17507
-	mov	r1, #255
17508
-	ldrh	r2, [r8, r3]
17509
-	bl	ftl_memset
17510
-.L2900:
17511
-	ldr	fp, .L2915+4
17512
-	mov	r7, r7, asl #2
17513
-	ldr	r3, .L2915+12
18001
+.L2832:
18002
+	ldr	r10, .L2846+8
17514
18003
 	mov	r8, #0
17515
-	ldr	r9, .L2915
17516
-	mov	r10, fp
18004
+	ldr	r3, .L2846+12
18005
+	lsl	r9, r9, #2
18006
+	mov	fp, r8
17517
18007
 	strh	r3, [r5]	@ movhi
17518
-.L2901:
17519
-	cmp	r8, r7
17520
-	beq	.L2902
17521
-	ldrh	r3, [fp, #4]
18008
+.L2833:
18009
+	cmp	r9, r8
18010
+	bne	.L2837
18011
+.L2834:
18012
+	mov	r3, #1
18013
+.L2845:
18014
+	strb	r3, [r4, #-3510]
18015
+.L2827:
18016
+	add	sp, sp, #44
18017
+	@ sp needed
18018
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
18019
+.L2831:
18020
+	add	r8, r8, #2400
18021
+	mov	r1, #255
18022
+	ldrh	r2, [r8]
18023
+	bl	ftl_memset
18024
+	b	.L2832
18025
+.L2837:
18026
+	ldrh	r3, [r6, #4]
17522
18027
 	cmp	r3, #0
17523
-	beq	.L2902
18028
+	beq	.L2834
17524
18029
 	ldr	r3, [sp, #8]
18030
+	mov	r0, r10
18031
+	str	r7, [r5, #8]
17525
18032
 	add	r8, r8, #1
17526
-	str	r6, [r5, #8]
17527
-	ldr	r0, .L2915+4
17528
18033
 	str	r3, [r5, #12]
17529
-	ldrh	r3, [fp]
18034
+	ldrh	r3, [r6]
17530
18035
 	strh	r3, [r5, #2]	@ movhi
17531
18036
 	bl	get_new_active_ppa
17532
-	ldr	r3, [r9, #-3328]
17533
-	mov	r2, #0
18037
+	ldr	r3, [r4, #-3328]
17534
18038
 	mov	r1, #1
17535
18039
 	str	r0, [sp, #8]
17536
18040
 	add	r0, sp, #4
17537
18041
 	str	r3, [r5, #4]
17538
18042
 	add	r3, r3, #1
17539
18043
 	cmn	r3, #1
17540
-	moveq	r3, #0
17541
-	str	r3, [r9, #-3328]
17542
-	mov	r3, r2
17543
-	bl	FlashProgPages
17544
-	ldrh	r0, [r10]
17545
-	bl	decrement_vpc_count
17546
-	b	.L2901
17547
-.L2902:
17548
-	mov	r3, #1
17549
-	b	.L2914
17550
-.L2897:
18044
+	moveq	r3, fp
18045
+	str	r3, [r4, #-3328]
17551
18046
 	mov	r3, #0
17552
-.L2914:
17553
-	strb	r3, [r4, #-3514]
17554
-.L2895:
17555
-	add	sp, sp, #44
17556
-	@ sp needed
17557
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
17558
-.L2916:
18047
+	mov	r2, r3
18048
+	bl	FlashProgPages
18049
+	ldrh	r0, [r6]
18050
+	bl	decrement_vpc_count
18051
+	b	.L2833
18052
+.L2829:
18053
+	mov	r3, #0
18054
+	b	.L2845
18055
+.L2847:
17559
18056
 	.align	2
17560
-.L2915:
18057
+.L2846:
17561
18058
 	.word	.LANCHOR2
17562
-	.word	.LANCHOR2-3524
17563
18059
 	.word	.LANCHOR0
18060
+	.word	.LANCHOR2-3520
17564
18061
 	.word	-3947
17565
18062
 	.fnend
17566
18063
 	.size	FtlWriteDumpData, .-FtlWriteDumpData
17567
18064
 	.align	2
17568
18065
 	.global	l2p_flush
18066
+	.syntax unified
18067
+	.arm
18068
+	.fpu softvfp
17569
18069
 	.type	l2p_flush, %function
17570
18070
 l2p_flush:
17571
18071
 	.fnstart
17572
18072
 	@ args = 0, pretend = 0, frame = 0
17573
18073
 	@ frame_needed = 0, uses_anonymous_args = 0
17574
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
17575
-	.save {r3, r4, r5, r6, r7, lr}
17576
-	bl	FtlWriteDumpData
18074
+	push	{r4, r5, r6, r7, r8, lr}
18075
+	.save {r4, r5, r6, r7, r8, lr}
17577
18076
 	mov	r4, #0
17578
-	ldr	r5, .L2923
18077
+	ldr	r5, .L2853
17579
18078
 	mov	r7, #12
17580
-	ldr	r6, .L2923+4
17581
-.L2918:
18079
+	ldr	r6, .L2853+4
18080
+	bl	FtlWriteDumpData
18081
+.L2849:
17582
18082
 	ldrh	r3, [r5]
17583
18083
 	uxth	r0, r4
17584
18084
 	cmp	r3, r0
17585
-	bls	.L2922
17586
-	ldr	r3, [r6, #-3380]
17587
-	mla	r3, r7, r0, r3
18085
+	bhi	.L2851
18086
+	mov	r0, #0
18087
+	pop	{r4, r5, r6, r7, r8, pc}
18088
+.L2851:
18089
+	ldr	r2, [r6, #-3376]
18090
+	uxth	r3, r4
18091
+	mla	r3, r7, r3, r2
17588
18092
 	ldr	r3, [r3, #4]
17589
18093
 	cmp	r3, #0
17590
-	bge	.L2919
18094
+	bge	.L2850
17591
18095
 	bl	flush_l2p_region
17592
-.L2919:
18096
+.L2850:
17593
18097
 	add	r4, r4, #1
17594
-	b	.L2918
17595
-.L2922:
17596
-	mov	r0, #0
17597
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
17598
-.L2924:
18098
+	b	.L2849
18099
+.L2854:
17599
18100
 	.align	2
17600
-.L2923:
17601
-	.word	.LANCHOR0+2426
18101
+.L2853:
18102
+	.word	.LANCHOR0+2430
17602
18103
 	.word	.LANCHOR2
17603
18104
 	.fnend
17604
18105
 	.size	l2p_flush, .-l2p_flush
17605
18106
 	.align	2
17606
18107
 	.global	allocate_new_data_superblock
18108
+	.syntax unified
18109
+	.arm
18110
+	.fpu softvfp
17607
18111
 	.type	allocate_new_data_superblock, %function
17608
18112
 allocate_new_data_superblock:
17609
18113
 	.fnstart
17610
18114
 	@ args = 0, pretend = 0, frame = 0
17611
18115
 	@ frame_needed = 0, uses_anonymous_args = 0
17612
-	stmfd	sp!, {r4, r5, r6, lr}
17613
-	.save {r4, r5, r6, lr}
17614
-	ldr	r5, .L2952
17615
-	ldrh	r6, [r0]
17616
-	ldr	r3, [r5, #-3616]
18116
+	push	{r4, r5, r6, r7, r8, lr}
18117
+	.save {r4, r5, r6, r7, r8, lr}
18118
+	ldr	r4, .L2882
18119
+	ldr	r3, [r4, #-3612]
17617
18120
 	cmp	r3, #0
17618
-	bne	.L2926
18121
+	bne	.L2856
18122
+	ldrh	r5, [r0]
17619
18123
 	movw	r3, #65535
17620
-	cmp	r6, r3
17621
-	mov	r4, r0
17622
-	beq	.L2927
17623
-	ldr	r2, [r5, #-3544]
17624
-	mov	r3, r6, asl #1
17625
-	mov	r0, r6
18124
+	mov	r7, r0
18125
+	cmp	r5, r3
18126
+	beq	.L2857
18127
+	ldr	r2, [r4, #-3540]
18128
+	lsl	r3, r5, #1
18129
+	mov	r0, r5
17626
18130
 	ldrh	r3, [r2, r3]
17627
18131
 	cmp	r3, #0
17628
-	beq	.L2928
18132
+	beq	.L2858
17629
18133
 	bl	INSERT_DATA_LIST
17630
-	b	.L2927
17631
-.L2928:
17632
-	bl	INSERT_FREE_LIST
17633
-.L2927:
18134
+.L2857:
18135
+	ldr	r2, .L2882+4
17634
18136
 	mov	r3, #0
17635
-	strb	r3, [r4, #8]
17636
-	ldr	r3, .L2952+4
17637
-	cmp	r4, r3
17638
-	beq	.L2929
17639
-	ldr	r3, .L2952+8
17640
-	movw	r2, #2340
17641
-	ldrh	r2, [r3, r2]
17642
-	cmp	r2, #1
17643
-	beq	.L2929
17644
-	ldrb	r1, [r3, #144]	@ zero_extendqisi2
17645
-	cmp	r1, #0
17646
-	beq	.L2930
17647
-.L2929:
18137
+	strb	r3, [r7, #8]
18138
+	cmp	r7, r2
18139
+	beq	.L2859
18140
+	ldr	r3, .L2882+8
18141
+	movw	r1, #2344
18142
+	ldrh	r1, [r3, r1]
18143
+	cmp	r1, #1
18144
+	beq	.L2859
18145
+	ldrb	r0, [r3, #152]	@ zero_extendqisi2
18146
+	cmp	r0, #0
18147
+	beq	.L2860
18148
+.L2859:
17648
18149
 	mov	r3, #1
17649
-	strb	r3, [r4, #8]
17650
-	b	.L2931
17651
-.L2930:
17652
-	ldr	r1, .L2952+12
17653
-	cmp	r4, r1
17654
-	bne	.L2931
17655
-	cmp	r2, #3
17656
-	beq	.L2933
17657
-	ldr	r2, .L2952
17658
-	ldr	r2, [r2, #-3236]
17659
-	cmp	r2, #1
17660
-	bne	.L2934
17661
-.L2933:
17662
-	mov	r2, #1
17663
-	strb	r2, [r5, #-3516]
17664
-.L2934:
17665
-	ldr	r3, [r3, #2244]
17666
-	cmp	r3, #0
17667
-	beq	.L2931
17668
-	ldr	r3, [r5, #-3308]
17669
-	cmp	r3, #39
17670
-	ldrls	r3, .L2952
17671
-	movls	r2, #1
17672
-	strlsb	r2, [r3, #-3516]
17673
-.L2931:
17674
-	ldr	r2, .L2952
17675
-	movw	r1, #65535
17676
-	sub	r3, r2, #380
18150
+	strb	r3, [r7, #8]
18151
+.L2861:
18152
+	ldr	r3, .L2882+12
18153
+	movw	r2, #65535
17677
18154
 	ldrh	r0, [r3]
17678
-	mov	r5, r3
17679
-	cmp	r0, r1
17680
-	beq	.L2936
17681
-	cmp	r6, r0
17682
-	bne	.L2937
17683
-	ldr	r2, [r2, #-3544]
17684
-	mov	r3, r0, asl #1
18155
+	mov	r6, r3
18156
+	cmp	r0, r2
18157
+	beq	.L2866
18158
+	cmp	r5, r0
18159
+	bne	.L2867
18160
+	ldr	r2, [r4, #-3540]
18161
+	lsl	r3, r0, #1
17685
18162
 	ldrh	r3, [r2, r3]
17686
18163
 	cmp	r3, #0
17687
-	beq	.L2938
17688
-.L2937:
18164
+	beq	.L2868
18165
+.L2867:
17689
18166
 	bl	update_vpc_list
17690
-.L2938:
18167
+.L2868:
17691
18168
 	mvn	r3, #0
17692
-	strh	r3, [r5]	@ movhi
17693
-.L2936:
17694
-	mov	r0, r4
18169
+	strh	r3, [r6]	@ movhi
18170
+.L2866:
18171
+	mov	r0, r7
17695
18172
 	bl	allocate_data_superblock
17696
18173
 	bl	l2p_flush
17697
18174
 	mov	r0, #0
17698
18175
 	bl	FtlEctTblFlush
17699
18176
 	bl	FtlVpcTblFlush
17700
-.L2926:
18177
+.L2856:
17701
18178
 	mov	r0, #0
17702
-	ldmfd	sp!, {r4, r5, r6, pc}
17703
-.L2953:
18179
+	pop	{r4, r5, r6, r7, r8, pc}
18180
+.L2858:
18181
+	bl	INSERT_FREE_LIST
18182
+	b	.L2857
18183
+.L2860:
18184
+	sub	r2, r2, #48
18185
+	cmp	r7, r2
18186
+	bne	.L2861
18187
+	cmp	r1, #3
18188
+	beq	.L2863
18189
+	ldr	r2, [r4, #-2724]
18190
+	cmp	r2, #1
18191
+	bne	.L2864
18192
+.L2863:
18193
+	mov	r2, #1
18194
+	strb	r2, [r4, #-3512]
18195
+.L2864:
18196
+	ldr	r3, [r3, #2248]
18197
+	cmp	r3, #0
18198
+	beq	.L2861
18199
+	ldr	r3, [r4, #-3308]
18200
+	cmp	r3, #39
18201
+	movls	r3, #1
18202
+	strbls	r3, [r4, #-3512]
18203
+	b	.L2861
18204
+.L2883:
17704
18205
 	.align	2
17705
-.L2952:
18206
+.L2882:
17706
18207
 	.word	.LANCHOR2
17707
-	.word	.LANCHOR2-3476
18208
+	.word	.LANCHOR2-3472
17708
18209
 	.word	.LANCHOR0
17709
-	.word	.LANCHOR2-3524
18210
+	.word	.LANCHOR2-380
17710
18211
 	.fnend
17711
18212
 	.size	allocate_new_data_superblock, .-allocate_new_data_superblock
17712
18213
 	.align	2
17713
18214
 	.global	FtlCheckVpc
18215
+	.syntax unified
18216
+	.arm
18217
+	.fpu softvfp
17714
18218
 	.type	FtlCheckVpc, %function
17715
18219
 FtlCheckVpc:
17716
18220
 	.fnstart
17717
18221
 	@ args = 0, pretend = 0, frame = 8
17718
18222
 	@ frame_needed = 0, uses_anonymous_args = 0
17719
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
17720
-	.save {r4, r5, r6, r7, r8, r9, lr}
18223
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
18224
+	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
17721
18225
 	.pad #12
17722
18226
 	mov	r4, #0
17723
-	ldr	r1, .L2977
17724
-	ldr	r0, .L2977+4
18227
+	ldr	r6, .L2905
18228
+	ldr	r5, .L2905+4
18229
+	ldr	r1, .L2905+8
18230
+	ldr	r0, .L2905+12
17725
18231
 	bl	printk
17726
-	ldr	r0, .L2977+8
17727
-	mov	r1, #0
17728
18232
 	mov	r2, #8192
18233
+	mov	r1, #0
18234
+	ldr	r0, .L2905+4
17729
18235
 	bl	memset
17730
-	ldr	r6, .L2977+12
17731
-	ldr	r5, .L2977+8
17732
-.L2955:
17733
-	ldr	r3, [r6, #2448]
18236
+.L2885:
18237
+	ldr	r3, [r6, #2452]
17734
18238
 	cmp	r4, r3
17735
-	bcs	.L2975
17736
-	mov	r0, r4
17737
-	add	r1, sp, #4
17738
-	mov	r2, #0
17739
-	bl	log2phys
17740
-	ldr	r0, [sp, #4]
17741
-	cmn	r0, #1
17742
-	beq	.L2956
17743
-	ubfx	r0, r0, #10, #16
17744
-	bl	P2V_block_in_plane
17745
-	mov	r0, r0, asl #1
17746
-	ldrh	r3, [r5, r0]
17747
-	add	r3, r3, #1
17748
-	strh	r3, [r5, r0]	@ movhi
17749
-.L2956:
17750
-	add	r4, r4, #1
17751
-	b	.L2955
17752
-.L2975:
17753
-	ldr	r7, .L2977+16
18239
+	bcc	.L2887
18240
+	ldr	r9, .L2905+16
17754
18241
 	mov	r4, #0
17755
-	ldr	r9, .L2977+20
18242
+	ldr	r5, .L2905+20
17756
18243
 	mov	r6, r4
17757
-	add	r8, r7, #1840
17758
-.L2958:
17759
-	ldrh	r3, [r9]
17760
-	uxth	r1, r4
17761
-	ldr	r5, .L2977+16
17762
-	cmp	r3, r1
17763
-	bls	.L2976
17764
-	ldr	r3, [r7, #-3544]
17765
-	mov	r5, r1, asl #1
17766
-	ldrh	r2, [r3, r5]
17767
-	ldrh	r3, [r8, r5]
18244
+	ldr	r8, .L2905+4
18245
+.L2888:
18246
+	ldrh	r2, [r9]
18247
+	uxth	r3, r4
17768
18248
 	cmp	r2, r3
17769
-	beq	.L2959
17770
-	ldr	r0, .L2977+24
17771
-	bl	printk
17772
-	ldr	r3, [r7, #-3544]
17773
-	movw	r2, #65535
17774
-	ldrh	r3, [r3, r5]
17775
-	cmp	r3, r2
17776
-	beq	.L2959
17777
-	ldrh	r2, [r8, r5]
17778
-	cmp	r2, r3
17779
-	movhi	r6, #1
17780
-.L2959:
17781
-	add	r4, r4, #1
17782
-	b	.L2958
17783
-.L2976:
17784
-	ldr	r3, [r5, #-3532]
17785
-	cmp	r3, #0
17786
-	beq	.L2961
17787
-	sub	r2, r5, #3520
17788
-	add	r9, r5, #1840
17789
-	mov	r8, #0
17790
-	ldrh	r7, [r2, #-8]
17791
-	ldr	r2, [r5, #-3552]
17792
-	rsb	r3, r2, r3
17793
-	ldr	r2, .L2977+28
17794
-	mov	r3, r3, asr #1
17795
-	mul	r3, r2, r3
17796
-	uxth	r4, r3
17797
-.L2962:
17798
-	uxth	r3, r8
17799
-	cmp	r3, r7
17800
-	bcs	.L2961
17801
-	ldr	r2, [r5, #-3544]
17802
-	mov	r3, r4, asl #1
18249
+	bhi	.L2890
18250
+	ldr	r4, [r5, #-3528]
18251
+	cmp	r4, #0
18252
+	beq	.L2891
18253
+	ldr	r3, .L2905+24
18254
+	mov	r7, #0
18255
+	ldr	r9, .L2905+4
18256
+	mov	fp, #6
18257
+	ldr	r10, .L2905+28
18258
+	ldrh	r8, [r3, #-4]
18259
+	ldr	r3, [r5, #-3548]
18260
+	sub	r4, r4, r3
18261
+	ldr	r3, .L2905+32
18262
+	asr	r4, r4, #1
18263
+	mul	r4, r3, r4
18264
+	uxth	r4, r4
18265
+.L2892:
18266
+	uxth	r3, r7
18267
+	cmp	r8, r3
18268
+	bls	.L2891
18269
+	ldr	r2, [r5, #-3540]
18270
+	lsl	r3, r4, #1
17803
18271
 	ldrh	r2, [r2, r3]
17804
18272
 	cmp	r2, #0
17805
-	beq	.L2963
17806
-	ldr	r0, .L2977+32
17807
-	mov	r1, r4
17808
-	ldrh	r3, [r9, r3]
18273
+	beq	.L2893
17809
18274
 	mov	r6, #1
18275
+	ldrh	r3, [r9, r3]
18276
+	mov	r1, r4
18277
+	mov	r0, r10
17810
18278
 	bl	printk
17811
-.L2963:
17812
-	mov	r3, #6
17813
-	ldr	r2, [r5, #-3552]
17814
-	mul	r4, r3, r4
18279
+.L2893:
18280
+	mul	r4, fp, r4
18281
+	ldr	r3, [r5, #-3548]
18282
+	add	r7, r7, #1
18283
+	ldrh	r4, [r3, r4]
17815
18284
 	movw	r3, #65535
17816
-	add	r8, r8, #1
17817
-	ldrh	r4, [r2, r4]
17818
18285
 	cmp	r4, r3
17819
-	bne	.L2962
17820
-.L2961:
18286
+	bne	.L2892
18287
+.L2891:
17821
18288
 	mov	r1, r6
17822
-	ldr	r0, .L2977+36
18289
+	ldr	r0, .L2905+36
17823
18290
 	bl	printk
17824
18291
 	add	sp, sp, #12
17825
18292
 	@ sp needed
17826
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, pc}
17827
-.L2978:
18293
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
18294
+.L2887:
18295
+	mov	r2, #0
18296
+	add	r1, sp, #4
18297
+	mov	r0, r4
18298
+	bl	log2phys
18299
+	ldr	r0, [sp, #4]
18300
+	cmn	r0, #1
18301
+	beq	.L2886
18302
+	ubfx	r0, r0, #10, #16
18303
+	bl	P2V_block_in_plane
18304
+	lsl	r0, r0, #1
18305
+	ldrh	r3, [r5, r0]
18306
+	add	r3, r3, #1
18307
+	strh	r3, [r5, r0]	@ movhi
18308
+.L2886:
18309
+	add	r4, r4, #1
18310
+	b	.L2885
18311
+.L2890:
18312
+	uxth	r1, r4
18313
+	ldr	r3, [r5, #-3540]
18314
+	lsl	r7, r1, #1
18315
+	ldrh	r2, [r3, r7]
18316
+	ldrh	r3, [r8, r7]
18317
+	cmp	r2, r3
18318
+	beq	.L2889
18319
+	ldr	r0, .L2905+40
18320
+	bl	printk
18321
+	ldr	r3, [r5, #-3540]
18322
+	movw	r2, #65535
18323
+	ldrh	r3, [r3, r7]
18324
+	cmp	r3, r2
18325
+	beq	.L2889
18326
+	ldrh	r2, [r8, r7]
18327
+	cmp	r2, r3
18328
+	movhi	r6, #1
18329
+.L2889:
18330
+	add	r4, r4, #1
18331
+	b	.L2888
18332
+.L2906:
17828
18333
 	.align	2
17829
-.L2977:
17830
-	.word	.LANCHOR3+204
17831
-	.word	.LC110
17832
-	.word	.LANCHOR2+1840
18334
+.L2905:
17833
18335
 	.word	.LANCHOR0
18336
+	.word	check_valid_page_count_table
18337
+	.word	.LANCHOR3+191
18338
+	.word	.LC110
18339
+	.word	.LANCHOR0+2332
17834
18340
 	.word	.LANCHOR2
17835
-	.word	.LANCHOR0+2328
17836
-	.word	.LC143
17837
-	.word	-1431655765
18341
+	.word	.LANCHOR2-3520
17838
18342
 	.word	.LC144
18343
+	.word	-1431655765
17839
18344
 	.word	.LC145
18345
+	.word	.LC143
17840
18346
 	.fnend
17841
18347
 	.size	FtlCheckVpc, .-FtlCheckVpc
17842
18348
 	.align	2
17843
18349
 	.global	Ftlscanalldata
18350
+	.syntax unified
18351
+	.arm
18352
+	.fpu softvfp
17844
18353
 	.type	Ftlscanalldata, %function
17845
18354
 Ftlscanalldata:
17846
18355
 	.fnstart
17847
18356
 	@ args = 0, pretend = 0, frame = 8
17848
18357
 	@ frame_needed = 0, uses_anonymous_args = 0
17849
-	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
18358
+	push	{r4, r5, r6, r7, r8, lr}
17850
18359
 	.save {r4, r5, r6, r7, r8, lr}
17851
-	mov	r1, #0
18360
+	mov	r5, #0
18361
+	ldr	r4, .L2916
17852
18362
 	.pad #32
17853
18363
 	sub	sp, sp, #32
17854
-	ldr	r0, .L2989
18364
+	mov	r1, #0
18365
+	ldr	r7, .L2916+4
18366
+	add	r8, r4, #1760
18367
+	ldr	r0, .L2916+8
17855
18368
 	bl	printk
17856
-	ldr	r5, .L2989+4
17857
-	ldr	r8, .L2989+8
17858
-	mov	r4, #0
17859
-	mov	r6, r5
17860
-.L2980:
17861
-	ldr	r3, [r8, #2448]
17862
-	cmp	r4, r3
17863
-	bcs	.L2988
17864
-	mov	r0, r4
17865
-	add	r1, sp, #28
17866
-	mov	r2, #0
17867
-	bl	log2phys
17868
-	ubfx	r3, r4, #0, #11
17869
-	cmp	r3, #0
17870
-	bne	.L2981
17871
-	ldr	r0, .L2989+12
17872
-	mov	r1, r4
17873
-	ldr	r2, [sp, #28]
17874
-	bl	printk
17875
-.L2981:
17876
-	ldr	r3, [sp, #28]
17877
-	cmn	r3, #1
17878
-	beq	.L2983
17879
-	str	r3, [r5, #1756]
17880
-	mov	r2, #0
17881
-	ldr	r3, [r5, #-524]
17882
-	mov	r1, #1
17883
-	ldr	r7, [r5, #-500]
17884
-	ldr	r0, .L2989+16
17885
-	str	r3, [r5, #1760]
17886
-	str	r4, [r5, #1768]
17887
-	str	r7, [r5, #1764]
17888
-	str	r2, [r5, #1752]
17889
-	bl	FlashReadPages
17890
-	ldr	r3, [r5, #1752]
17891
-	cmn	r3, #1
17892
-	cmpne	r3, #256
17893
-	beq	.L2984
17894
-	ldr	r3, [r7, #8]
17895
-	cmp	r3, r4
17896
-	beq	.L2983
17897
-.L2984:
17898
-	ldr	r3, [r6, #1764]
17899
-	ldr	r2, [r6, #1760]
17900
-	ldr	r0, .L2989+20
17901
-	ldr	r1, [r3, #4]
17902
-	str	r1, [sp]
17903
-	ldr	r1, [r3, #8]
17904
-	str	r1, [sp, #4]
17905
-	ldr	r1, [r3, #12]
17906
-	str	r1, [sp, #8]
17907
-	ldr	r1, [r2]
17908
-	str	r1, [sp, #12]
17909
-	mov	r1, r4
17910
-	ldr	r2, [r2, #4]
17911
-	str	r2, [sp, #16]
17912
-	ldr	r2, [r6, #1756]
17913
-	ldr	r3, [r3]
17914
-	bl	printk
17915
-.L2983:
17916
-	add	r4, r4, #1
17917
-	b	.L2980
17918
-.L2988:
18369
+.L2908:
18370
+	ldr	r3, [r7, #2452]
18371
+	cmp	r5, r3
18372
+	bcc	.L2914
17919
18373
 	add	sp, sp, #32
17920
18374
 	@ sp needed
17921
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
17922
-.L2990:
18375
+	pop	{r4, r5, r6, r7, r8, pc}
18376
+.L2914:
18377
+	mov	r2, #0
18378
+	add	r1, sp, #28
18379
+	mov	r0, r5
18380
+	bl	log2phys
18381
+	ubfx	r3, r5, #0, #11
18382
+	cmp	r3, #0
18383
+	bne	.L2909
18384
+	ldr	r2, [sp, #28]
18385
+	mov	r1, r5
18386
+	ldr	r0, .L2916+12
18387
+	bl	printk
18388
+.L2909:
18389
+	ldr	r3, [sp, #28]
18390
+	cmn	r3, #1
18391
+	beq	.L2911
18392
+	str	r3, [r4, #1764]
18393
+	mov	r2, #0
18394
+	ldr	r3, [r4, #-524]
18395
+	mov	r1, #1
18396
+	ldr	r6, [r4, #-500]
18397
+	mov	r0, r8
18398
+	str	r5, [r4, #1776]
18399
+	str	r3, [r4, #1768]
18400
+	str	r6, [r4, #1772]
18401
+	str	r2, [r4, #1760]
18402
+	bl	FlashReadPages
18403
+	ldr	r3, [r4, #1760]
18404
+	cmn	r3, #1
18405
+	cmpne	r3, #256
18406
+	beq	.L2912
18407
+	ldr	r3, [r6, #8]
18408
+	cmp	r5, r3
18409
+	beq	.L2911
18410
+.L2912:
18411
+	ldr	r2, [r4, #1768]
18412
+	ldr	r3, [r4, #1772]
18413
+	ldr	r0, .L2916+16
18414
+	ldr	r1, [r2, #4]
18415
+	str	r1, [sp, #16]
18416
+	mov	r1, r5
18417
+	ldr	r2, [r2]
18418
+	str	r2, [sp, #12]
18419
+	ldr	r2, [r3, #12]
18420
+	str	r2, [sp, #8]
18421
+	ldr	r2, [r3, #8]
18422
+	str	r2, [sp, #4]
18423
+	ldr	r2, [r3, #4]
18424
+	str	r2, [sp]
18425
+	ldr	r2, [r4, #1764]
18426
+	ldr	r3, [r3]
18427
+	bl	printk
18428
+.L2911:
18429
+	add	r5, r5, #1
18430
+	b	.L2908
18431
+.L2917:
17923
18432
 	.align	2
17924
-.L2989:
17925
-	.word	.LC146
18433
+.L2916:
17926
18434
 	.word	.LANCHOR2
17927
18435
 	.word	.LANCHOR0
18436
+	.word	.LC146
17928
18437
 	.word	.LC147
17929
-	.word	.LANCHOR2+1752
17930
18438
 	.word	.LC148
17931
18439
 	.fnend
17932
18440
 	.size	Ftlscanalldata, .-Ftlscanalldata
17933
18441
 	.align	2
17934
18442
 	.global	FtlReUsePrevPpa
18443
+	.syntax unified
18444
+	.arm
18445
+	.fpu softvfp
17935
18446
 	.type	FtlReUsePrevPpa, %function
17936
18447
 FtlReUsePrevPpa:
17937
18448
 	.fnstart
17938
18449
 	@ args = 0, pretend = 0, frame = 8
17939
18450
 	@ frame_needed = 0, uses_anonymous_args = 0
17940
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
18451
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
17941
18452
 	.save {r4, r5, r6, r7, r8, r9, lr}
17942
18453
 	.pad #12
17943
18454
 	mov	r5, r0
18455
+	ldr	r6, .L2928
17944
18456
 	ubfx	r0, r1, #10, #16
17945
18457
 	str	r1, [sp, #4]
17946
18458
 	bl	P2V_block_in_plane
17947
-	ldr	r6, .L3001
17948
-	ldr	r4, [r6, #-3544]
17949
-	mov	r7, r0, asl #1
17950
-	ldrh	r3, [r4, r7]
18459
+	ldr	r2, [r6, #-3540]
18460
+	lsl	r7, r0, #1
18461
+	ldrh	r3, [r2, r7]
17951
18462
 	cmp	r3, #0
17952
-	addne	r3, r3, #1
17953
-	strneh	r3, [r4, r7]	@ movhi
17954
-	bne	.L2993
17955
-	ldr	r4, [r6, #-3532]
18463
+	bne	.L2919
18464
+	ldr	r4, [r6, #-3528]
17956
18465
 	cmp	r4, #0
17957
-	beq	.L2993
17958
-	ldr	r1, [r6, #-3552]
17959
-	sub	r2, r6, #3520
17960
-	ldr	lr, .L3001+4
17961
-	movw	r9, #65535
17962
-	rsb	r4, r1, r4
17963
-	ldrh	ip, [r2, #-8]
17964
-	mov	r8, r2
17965
-	mov	r4, r4, asr #1
17966
-	mul	r4, lr, r4
18466
+	beq	.L2920
18467
+	ldr	r2, [r6, #-3548]
18468
+	sub	r8, r6, #3520
18469
+	ldr	ip, .L2928+4
17967
18470
 	mov	lr, #6
18471
+	ldrh	r1, [r8, #-4]
18472
+	movw	r9, #65535
18473
+	sub	r4, r4, r2
18474
+	asr	r4, r4, #1
18475
+	mul	r4, ip, r4
17968
18476
 	uxth	r4, r4
17969
-.L2994:
17970
-	uxth	r2, r3
17971
-	cmp	r2, ip
17972
-	bcs	.L2993
18477
+.L2921:
18478
+	uxth	ip, r3
18479
+	cmp	r1, ip
18480
+	bls	.L2920
17973
18481
 	cmp	r4, r0
17974
-	bne	.L2995
18482
+	bne	.L2922
17975
18483
 	mov	r1, r4
17976
-	ldr	r0, .L3001+8
18484
+	sub	r0, r8, #8
17977
18485
 	bl	List_remove_node
17978
-	ldrh	r3, [r8, #-8]
18486
+	ldrh	r3, [r8, #-4]
17979
18487
 	mov	r0, r4
17980
18488
 	sub	r3, r3, #1
17981
-	strh	r3, [r8, #-8]	@ movhi
18489
+	strh	r3, [r8, #-4]	@ movhi
17982
18490
 	bl	INSERT_DATA_LIST
17983
-	ldr	r2, [r6, #-3544]
18491
+	ldr	r2, [r6, #-3540]
17984
18492
 	ldrh	r3, [r2, r7]
18493
+.L2919:
17985
18494
 	add	r3, r3, #1
17986
18495
 	strh	r3, [r2, r7]	@ movhi
17987
-	b	.L2993
17988
-.L2995:
18496
+	b	.L2920
18497
+.L2922:
17989
18498
 	mul	r4, lr, r4
17990
18499
 	add	r3, r3, #1
17991
-	ldrh	r4, [r1, r4]
18500
+	ldrh	r4, [r2, r4]
17992
18501
 	cmp	r4, r9
17993
-	bne	.L2994
17994
-.L2993:
17995
-	mov	r0, r5
17996
-	add	r1, sp, #4
18502
+	bne	.L2921
18503
+.L2920:
17997
18504
 	mov	r2, #1
18505
+	add	r1, sp, #4
18506
+	mov	r0, r5
17998
18507
 	bl	log2phys
17999
18508
 	add	sp, sp, #12
18000
18509
 	@ sp needed
18001
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, pc}
18002
-.L3002:
18510
+	pop	{r4, r5, r6, r7, r8, r9, pc}
18511
+.L2929:
18003
18512
 	.align	2
18004
-.L3001:
18513
+.L2928:
18005
18514
 	.word	.LANCHOR2
18006
18515
 	.word	-1431655765
18007
-	.word	.LANCHOR2-3532
18008
18516
 	.fnend
18009
18517
 	.size	FtlReUsePrevPpa, .-FtlReUsePrevPpa
18010
18518
 	.align	2
18011
18519
 	.global	FtlRecoverySuperblock
18520
+	.syntax unified
18521
+	.arm
18522
+	.fpu softvfp
18012
18523
 	.type	FtlRecoverySuperblock, %function
18013
18524
 FtlRecoverySuperblock:
18014
18525
 	.fnstart
18015
-	@ args = 0, pretend = 0, frame = 64
18526
+	@ args = 0, pretend = 0, frame = 48
18016
18527
 	@ frame_needed = 0, uses_anonymous_args = 0
18017
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
18528
+	ldrh	r2, [r0]
18529
+	movw	r1, #65535
18530
+	cmp	r2, r1
18531
+	beq	.L3075
18532
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
18018
18533
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
18019
-	movw	r2, #65535
18020
-	ldrh	r3, [r0]
18021
-	.pad #68
18022
-	sub	sp, sp, #68
18023
-	mov	r4, r0
18024
-	cmp	r3, r2
18025
-	beq	.L3144
18534
+	movw	r2, #2390
18535
+	ldr	r6, .L3087
18536
+	.pad #52
18537
+	sub	sp, sp, #52
18538
+	mov	r10, r0
18026
18539
 	ldrh	r3, [r0, #2]
18027
-	ldr	r5, .L3161
18540
+	ldrh	r2, [r6, r2]
18028
18541
 	str	r3, [sp, #8]
18029
-	ldrb	r3, [r0, #6]	@ zero_extendqisi2
18030
-	ldr	r1, [sp, #8]
18031
-	str	r3, [sp, #16]
18032
-	movw	r3, #2388
18033
-	ldrh	r3, [r5, r3]
18034
-	cmp	r3, r1
18035
-	mov	r3, #0
18036
-	streqh	r3, [r0, #4]	@ movhi
18037
-	streqb	r3, [r0, #6]
18038
-	ldrneh	r0, [r0, #16]
18039
-	beq	.L3144
18040
-.L3007:
18041
-	cmp	r0, r2
18042
-	add	r3, r3, #1
18043
-	uxtheq	r1, r3
18044
-	addeq	r1, r4, r1, asl #1
18045
-	ldreqh	r0, [r1, #16]
18046
-	beq	.L3007
18047
-.L3156:
18048
-	ldrb	r1, [r4, #8]	@ zero_extendqisi2
18049
-	mov	r9, r4
18542
+	cmp	r2, r3
18543
+	mov	r2, #0
18544
+	strheq	r2, [r0, #4]	@ movhi
18545
+	strbeq	r2, [r0, #6]
18546
+	ldrhne	r0, [r0, #16]
18547
+	bne	.L2934
18548
+.L3073:
18549
+	mov	r0, #0
18550
+	add	sp, sp, #52
18551
+	@ sp needed
18552
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
18553
+.L2935:
18554
+	uxth	r0, r2
18555
+	add	r0, r10, r0, lsl #1
18556
+	ldrh	r0, [r0, #16]
18557
+.L2934:
18558
+	cmp	r0, r1
18559
+	add	r2, r2, #1
18560
+	beq	.L2935
18561
+	ldrb	r1, [r10, #8]	@ zero_extendqisi2
18562
+	ldrb	r3, [r10, #6]	@ zero_extendqisi2
18050
18563
 	cmp	r1, #1
18051
-	bne	.L3009
18564
+	str	r3, [sp, #12]
18565
+	bne	.L2936
18052
18566
 	bl	FtlGetLastWrittenPage
18053
18567
 	cmn	r0, #1
18054
18568
 	mov	r4, r0
18055
-	beq	.L3010
18056
-	ldrb	r3, [r5, #144]	@ zero_extendqisi2
18569
+	beq	.L2937
18570
+	ldrb	r3, [r6, #152]	@ zero_extendqisi2
18057
18571
 	cmp	r3, #0
18058
-	bne	.L3147
18059
-	ldr	r3, .L3161
18060
-	add	r3, r3, r0, asl #1
18061
-	ldrh	r6, [r3, #148]
18062
-	b	.L3081
18063
-.L3009:
18572
+	addeq	r3, r6, r0, lsl #1
18573
+	ldrheq	r5, [r3, #156]
18574
+	beq	.L2938
18575
+.L3008:
18576
+	mov	r5, r4
18577
+.L2938:
18578
+	movw	r3, #2324
18579
+	mov	r2, #0
18580
+	ldrh	r3, [r6, r3]
18581
+	movw	r8, #65535
18582
+	mov	r9, #36
18583
+	str	r3, [sp]
18584
+	ldr	r3, .L3087+4
18585
+	ldr	r0, [r3, #-536]
18586
+	ldr	lr, [r3, #-2692]
18587
+	movw	r3, #2402
18588
+	ldrh	r7, [r6, r3]
18589
+	add	r3, r10, #16
18590
+	mov	ip, r3
18591
+	mov	r6, r2
18592
+	str	r3, [sp, #20]
18593
+.L2939:
18594
+	ldr	r1, [sp]
18595
+	uxth	r3, r2
18596
+	cmp	r1, r3
18597
+	bhi	.L2941
18598
+	ldrb	r3, [r10, #8]	@ zero_extendqisi2
18599
+	cmp	r3, #1
18600
+	movne	r3, #0
18601
+	bne	.L3078
18602
+	ldr	r3, .L3087
18603
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
18604
+	adds	r3, r3, #0
18605
+	movne	r3, #1
18606
+.L3078:
18607
+	ldr	r7, .L3087+4
18608
+	mov	r1, r6
18609
+	str	r3, [sp, #24]
18610
+	mov	r8, #0
18611
+	ldr	r2, [sp, #24]
18612
+	movw	r9, #65535
18613
+	bl	FlashReadPages
18614
+	ldr	r3, [r7, #-3328]
18615
+	mov	fp, r7
18616
+	str	r3, [sp, #16]
18617
+.L2943:
18618
+	uxth	r3, r8
18619
+	cmp	r6, r3
18620
+	bhi	.L2948
18621
+	bne	.L2946
18622
+	add	r4, r4, #1
18623
+	uxth	r3, r4
18624
+	str	r3, [sp]
18625
+	ldr	r3, [r7, #-536]
18626
+	ldr	r0, [r3, #4]
18627
+.L3079:
18628
+	ubfx	r0, r0, #10, #16
18629
+	bl	P2V_plane
18630
+	ldrb	r2, [r10, #8]	@ zero_extendqisi2
18631
+	str	r0, [sp, #4]
18632
+	ldr	r3, .L3087
18633
+	cmp	r2, #1
18634
+	bne	.L2950
18635
+	ldrb	r1, [r3, #152]	@ zero_extendqisi2
18636
+	cmp	r1, #0
18637
+	ldreq	r1, [sp]
18638
+	addeq	r4, r3, r1, lsl #1
18639
+	ldrheq	r1, [r4, #156]
18640
+	streq	r1, [sp]
18641
+.L2950:
18642
+	movw	r1, #2390
18643
+	ldrh	r3, [r3, r1]
18644
+	ldr	r1, [sp]
18645
+	cmp	r3, r1
18646
+	ldmib	sp, {r0, r1}
18647
+	ldrheq	r3, [sp]
18648
+	strheq	r3, [r10, #2]	@ movhi
18649
+	moveq	r3, #0
18650
+	strbeq	r3, [r10, #6]
18651
+	strheq	r3, [r10, #4]	@ movhi
18652
+	ldrh	r3, [sp, #12]
18653
+	str	r3, [sp, #28]
18654
+	ldr	ip, [sp, #28]
18655
+	ldr	r3, [sp]
18656
+	cmp	r3, r1
18657
+	cmpeq	r0, ip
18658
+	moveq	r2, r0
18659
+	moveq	r1, r3
18660
+	beq	.L3085
18661
+	ldr	r3, [sp, #16]
18662
+	sub	fp, r3, #1
18663
+	movw	r3, #65535
18664
+	subs	r9, r9, r3
18665
+	movne	r9, #1
18666
+	cmp	r2, #0
18667
+	orreq	r9, r9, #1
18668
+	cmp	r9, #0
18669
+	beq	.L2954
18670
+	ldr	r3, [r7, #-368]
18671
+	uxth	r8, r5
18672
+	uxth	r5, r5
18673
+	cmn	r3, #1
18674
+	streq	fp, [r7, #-368]
18675
+	ldr	r3, [r7, #-368]
18676
+	mvn	r7, #0
18677
+	mov	r6, r7
18678
+	str	r3, [sp, #12]
18679
+	ldr	r3, [sp, #8]
18680
+	add	r3, r3, #7
18681
+	cmp	r5, r3
18682
+	subgt	r4, r8, #7
18683
+	ldrle	r4, [sp, #8]
18684
+	uxthgt	r4, r4
18685
+.L2957:
18686
+	cmp	r4, r8
18687
+	ldr	r3, .L3087+4
18688
+	bhi	.L2970
18689
+	ldr	r2, .L3087+8
18690
+	mov	ip, #36
18691
+	ldr	r0, [r3, #-536]
18692
+	mov	r3, #0
18693
+	ldr	r1, [sp, #20]
18694
+	mov	r5, r3
18695
+	ldrh	r9, [r2]
18696
+	b	.L2971
18697
+.L2936:
18064
18698
 	mov	r1, #0
18065
18699
 	bl	FtlGetLastWrittenPage
18066
18700
 	cmn	r0, #1
18067
18701
 	mov	r4, r0
18068
-	beq	.L3010
18069
-.L3147:
18070
-	mov	r6, r4
18071
-.L3081:
18072
-	ldr	r3, .L3161+4
18073
-	movw	r8, #65535
18074
-	ldrh	r2, [r3], #80
18075
-	str	r2, [sp, #4]
18076
-	ldr	r2, .L3161+8
18077
-	ldrh	r7, [r3]
18078
-	add	r3, r9, #14
18079
-	str	r3, [sp, #20]
18080
-	ldr	ip, [r2, #-536]
18081
-	mov	r0, r3
18082
-	ldr	lr, [r2, #-2692]
18083
-	mov	r2, #0
18084
-	mov	r5, r2
18085
-	mov	r10, r2
18086
-	b	.L3012
18087
-.L3010:
18702
+	bne	.L3008
18703
+.L2937:
18088
18704
 	mov	r3, #0
18089
-	strh	r3, [r9, #2]	@ movhi
18090
-	strb	r3, [r9, #6]
18091
-	b	.L3144
18092
-.L3014:
18093
-	ldrh	r3, [r0, #2]!
18705
+	strh	r3, [r10, #2]	@ movhi
18706
+.L3084:
18707
+	strb	r3, [r10, #6]
18708
+	b	.L3073
18709
+.L2941:
18710
+	ldrh	r3, [ip], #2
18094
18711
 	cmp	r3, r8
18095
-	beq	.L3013
18096
-	mov	r1, #36
18097
-	orr	r3, r6, r3, asl #10
18098
-	mla	r1, r1, r5, ip
18099
-	stmib	r1, {r3, r10}
18100
-	mul	r3, r7, r5
18101
-	add	r5, r5, #1
18102
-	uxth	r5, r5
18712
+	beq	.L2940
18713
+	mla	r1, r9, r6, r0
18714
+	orr	r3, r5, r3, lsl #10
18715
+	str	r3, [r1, #4]
18716
+	mov	r3, #0
18717
+	str	r3, [r1, #8]
18718
+	mul	r3, r7, r6
18719
+	add	r6, r6, #1
18720
+	uxth	r6, r6
18103
18721
 	add	fp, r3, #3
18104
18722
 	cmp	r3, #0
18105
18723
 	movlt	r3, fp
18106
18724
 	bic	r3, r3, #3
18107
18725
 	add	r3, lr, r3
18108
18726
 	str	r3, [r1, #12]
18109
-.L3013:
18727
+.L2940:
18110
18728
 	add	r2, r2, #1
18111
-.L3012:
18112
-	ldr	r1, [sp, #4]
18113
-	uxth	r3, r2
18114
-	cmp	r3, r1
18115
-	bcc	.L3014
18116
-	ldrb	r3, [r9, #8]	@ zero_extendqisi2
18117
-	cmp	r3, #1
18118
-	movne	r3, #0
18119
-	bne	.L3148
18120
-	ldr	r3, .L3161
18121
-	ldrb	lr, [r3, #144]	@ zero_extendqisi2
18122
-	adds	r3, lr, #0
18123
-	movne	r3, #1
18124
-.L3148:
18125
-	ldr	r7, .L3161+8
18126
-	mov	r1, r5
18127
-	str	r3, [sp, #24]
18128
-	mov	fp, #0
18129
-	ldr	r2, [sp, #24]
18130
-	movw	r10, #65535
18131
-	ldr	r0, [r7, #-536]
18132
-	bl	FlashReadPages
18133
-	ldr	r3, [r7, #-3328]
18134
-	str	r7, [sp, #12]
18135
-	str	r3, [sp, #28]
18136
-.L3016:
18137
-	uxth	r8, fp
18138
-	cmp	r8, r5
18139
-	bcs	.L3023
18140
-	mov	r1, #36
18141
-	ldr	r0, [r7, #-536]
18142
-	mul	r1, r1, fp
18143
-	add	ip, r0, r1
18144
-	ldr	r1, [r0, r1]
18145
-	cmp	r1, #0
18146
-	bne	.L3017
18147
-	ldr	ip, [ip, #12]
18148
-	ldr	r3, [ip, #4]
18729
+	b	.L2939
18730
+.L2948:
18731
+	mov	r3, #36
18732
+	ldr	r1, [fp, #-536]
18733
+	mul	r3, r3, r8
18734
+	add	r2, r1, r3
18735
+	ldr	r3, [r1, r3]
18736
+	cmp	r3, #0
18737
+	bne	.L2944
18738
+	ldr	r2, [r2, #12]
18739
+	ldr	r3, [r2, #4]
18149
18740
 	cmn	r3, #1
18150
-	beq	.L3018
18741
+	beq	.L2945
18742
+	ldr	r1, [fp, #-3328]
18151
18743
 	mov	r0, r3
18152
-	ldr	r1, [r7, #-3328]
18153
-	str	ip, [sp, #32]
18154
-	str	r3, [sp, #4]
18155
18744
 	bl	ftl_cmp_data_ver
18156
-	ldr	r3, [sp, #4]
18157
18745
 	cmp	r0, #0
18158
-	ldr	ip, [sp, #32]
18159
18746
 	addne	r3, r3, #1
18160
-	strne	r3, [r7, #-3328]
18161
-.L3018:
18162
-	ldr	r1, [ip]
18163
-	cmn	r1, #1
18164
-	bne	.L3019
18165
-.L3023:
18166
-	cmp	r8, r5
18167
-	ldr	r5, .L3161+8
18168
-	bne	.L3145
18169
-	add	fp, r4, #1
18170
-	uxth	r3, fp
18171
-	str	r3, [sp, #4]
18172
-	ldr	r3, [r5, #-536]
18173
-	ldr	r0, [r3, #4]
18174
-	b	.L3149
18175
-.L3017:
18176
-	ldr	r1, [ip, #4]
18177
-	uxth	r10, r6
18178
-	ldr	r0, .L3161+12
18179
-	bl	printk
18180
-	ldrh	r1, [r9]
18181
-	ldr	r3, .L3161+16
18182
-	strh	r1, [r3]	@ movhi
18183
-.L3019:
18184
-	add	fp, fp, #1
18185
-	b	.L3016
18186
-.L3145:
18747
+	strne	r3, [fp, #-3328]
18748
+.L2945:
18749
+	ldr	r3, [r2]
18750
+	cmn	r3, #1
18751
+	bne	.L2947
18752
+.L2946:
18187
18753
 	uxth	r3, r4
18188
-	str	r3, [sp, #4]
18189
-	ldr	r3, [sp, #12]
18754
+	uxth	r8, r8
18755
+	str	r3, [sp]
18190
18756
 	mov	r2, #36
18191
-	ldr	r3, [r3, #-536]
18757
+	ldr	r3, [r7, #-536]
18192
18758
 	mla	r8, r2, r8, r3
18193
18759
 	ldr	r0, [r8, #4]
18194
-.L3149:
18195
-	ubfx	r0, r0, #10, #16
18196
-	bl	P2V_plane
18197
-	ldr	r2, .L3161
18198
-	str	r0, [sp, #12]
18199
-	ldrb	r0, [r9, #8]	@ zero_extendqisi2
18200
-	cmp	r0, #1
18201
-	bne	.L3025
18202
-	ldrb	r3, [r2, #144]	@ zero_extendqisi2
18203
-	cmp	r3, #0
18204
-	ldreq	r3, [sp, #4]
18205
-	addeq	fp, r2, r3, asl #1
18206
-	ldreqh	r3, [fp, #148]
18207
-	streq	r3, [sp, #4]
18208
-.L3025:
18209
-	movw	r3, #2388
18210
-	ldr	r1, [sp, #12]
18211
-	ldrh	r3, [r2, r3]
18212
-	ldr	r2, [sp, #4]
18213
-	cmp	r3, r2
18214
-	ldr	r2, [sp, #8]
18215
-	ldreqh	r3, [sp, #4]
18216
-	streqh	r3, [r9, #2]	@ movhi
18217
-	moveq	r3, #0
18218
-	streqb	r3, [r9, #6]
18219
-	streqh	r3, [r9, #4]	@ movhi
18220
-	ldrh	r3, [sp, #16]
18221
-	str	r3, [sp, #32]
18222
-	ldr	ip, [sp, #32]
18223
-	ldr	r3, [sp, #4]
18224
-	cmp	r3, r2
18225
-	cmpeq	r1, ip
18226
-	moveq	r0, r9
18227
-	moveq	r1, r3
18228
-	beq	.L3154
18229
-	ldr	r3, [sp, #28]
18230
-	movw	r2, #65535
18231
-	sub	fp, r3, #1
18232
-	clz	r3, r0
18233
-	mov	r3, r3, lsr #5
18234
-	cmp	r10, r2
18235
-	orrne	r3, r3, #1
18236
-	cmp	r3, #0
18237
-	beq	.L3029
18238
-	ldr	r3, [r5, #-368]
18239
-	uxth	r10, r6
18240
-	ldr	r7, .L3161+8
18241
-	mvn	r8, #0
18242
-	cmn	r3, #1
18243
-	mov	r6, r8
18244
-	ldreq	r3, .L3161+8
18245
-	streq	fp, [r3, #-368]
18246
-	ldr	r3, [r5, #-368]
18247
-	str	r3, [sp, #16]
18248
-	ldr	r3, [sp, #8]
18249
-	add	r3, r3, #7
18250
-	cmp	r10, r3
18251
-	subgt	r4, r10, #7
18252
-	ldrle	r4, [sp, #8]
18253
-	uxthgt	r4, r4
18254
-.L3032:
18255
-	cmp	r4, r10
18256
-	bhi	.L3045
18257
-	ldr	r3, .L3161+4
18258
-	mov	r0, #36
18259
-	ldr	lr, [r7, #-536]
18260
-	ldr	r1, [sp, #20]
18261
-	ldrh	r3, [r3]
18262
-	str	r3, [sp, #28]
18263
-	mov	r3, #0
18264
-	mov	r5, r3
18265
-.L3046:
18266
-	ldr	ip, [sp, #28]
18267
-	uxth	r2, r3
18268
-	cmp	r2, ip
18269
-	bcs	.L3157
18270
-	ldrh	r2, [r1, #2]!
18271
-	movw	ip, #65535
18760
+	b	.L3079
18761
+.L2944:
18762
+	ldr	r1, [r2, #4]
18763
+	uxth	r9, r5
18764
+	ldr	r0, .L3087+12
18765
+	bl	printk
18766
+	ldrh	r3, [r10]
18767
+	ldr	r2, .L3087+16
18768
+	strh	r3, [r2]	@ movhi
18769
+.L2947:
18770
+	add	r8, r8, #1
18771
+	b	.L2943
18772
+.L2959:
18773
+	ldrh	r2, [r1], #2
18774
+	movw	lr, #65535
18272
18775
 	add	r3, r3, #1
18273
-	cmp	r2, ip
18274
-	orrne	r2, r4, r2, asl #10
18275
-	mlane	ip, r0, r5, lr
18776
+	cmp	r2, lr
18777
+	mlane	lr, ip, r5, r0
18276
18778
 	addne	r5, r5, #1
18779
+	orrne	r2, r4, r2, lsl #10
18277
18780
 	uxthne	r5, r5
18278
-	strne	r2, [ip, #4]
18279
-	b	.L3046
18280
-.L3157:
18781
+	strne	r2, [lr, #4]
18782
+.L2971:
18783
+	uxth	r2, r3
18784
+	cmp	r2, r9
18785
+	bcc	.L2959
18281
18786
 	mov	r1, r5
18282
18787
 	ldr	r2, [sp, #24]
18283
-	ldr	r0, [r7, #-536]
18284
18788
 	bl	FlashReadPages
18285
-	ldr	r3, .L3161
18286
-	mov	r2, #36
18789
+	ldr	r3, .L3087
18790
+	mov	r1, #36
18791
+	ldr	r2, .L3087+4
18792
+	ldr	r0, .L3087+20
18793
+	ldrb	ip, [r3, #152]	@ zero_extendqisi2
18794
+	ldr	r3, [r2, #-536]
18795
+	add	lr, r0, r4, lsl #1
18796
+	mla	r5, r1, r5, r3
18287
18797
 	movw	r1, #65535
18288
-	ldrb	ip, [r3, #144]	@ zero_extendqisi2
18289
-	ldr	r3, [r7, #-536]
18290
-	mla	r5, r2, r5, r3
18291
-	ldr	r2, .L3161+20
18292
-	add	r2, r2, r4, asl #1
18293
-.L3035:
18294
-	cmp	r3, r5
18295
-	beq	.L3158
18798
+.L2960:
18799
+	cmp	r5, r3
18800
+	addeq	r4, r4, #1
18801
+	uxtheq	r4, r4
18802
+	beq	.L2957
18803
+.L2969:
18296
18804
 	ldr	r0, [r3]
18297
18805
 	cmp	r0, #0
18298
-	bne	.L3036
18806
+	bne	.L2961
18299
18807
 	ldr	r0, [r3, #12]
18300
-	ldrh	lr, [r0]
18301
-	cmp	lr, r1
18302
-	beq	.L3037
18808
+	ldrh	r9, [r0]
18809
+	cmp	r9, r1
18810
+	beq	.L2962
18303
18811
 	ldr	r0, [r0, #4]
18304
18812
 	cmn	r0, #1
18305
-	beq	.L3037
18306
-	cmn	r8, #1
18307
-	ldr	r6, [r7, #-368]
18308
-	str	r0, [r7, #-368]
18309
-	bne	.L3037
18310
-	ldrh	r0, [r2]
18813
+	beq	.L2962
18814
+	cmn	r7, #1
18815
+	ldr	r6, [r2, #-368]
18816
+	str	r0, [r2, #-368]
18817
+	bne	.L2962
18818
+	ldrh	r0, [lr]
18311
18819
 	cmp	r0, r1
18312
-	bne	.L3038
18820
+	bne	.L2963
18313
18821
 	cmp	ip, #0
18314
-	beq	.L3037
18315
-.L3038:
18316
-	cmp	r6, fp
18317
-	mvneq	r8, #0
18318
-	movne	r8, r6
18319
-	b	.L3037
18320
-.L3036:
18321
-	ldrh	r1, [r9]
18322
-	movw	r3, #1848
18323
-	ldr	r2, .L3161+24
18324
-	strh	r1, [r2, r3]	@ movhi
18325
-	ldrb	r3, [r9, #8]	@ zero_extendqisi2
18326
-	cmp	r3, #0
18327
-	bne	.L3029
18328
-	ldr	r2, .L3161+20
18329
-	mov	r4, r4, asl #1
18330
-	ldr	r3, .L3161+8
18822
+	beq	.L2962
18823
+.L2963:
18824
+	cmp	fp, r6
18825
+	movne	r7, r6
18826
+.L2962:
18827
+	add	r3, r3, #36
18828
+	b	.L2960
18829
+.L2961:
18830
+	ldrh	r1, [r10]
18831
+	movw	r2, #1846
18832
+	ldr	r3, .L3087+4
18833
+	strh	r1, [r3, r2]	@ movhi
18834
+	ldrb	r2, [r10, #8]	@ zero_extendqisi2
18835
+	cmp	r2, #0
18836
+	bne	.L2954
18837
+	ldr	r2, .L3087+20
18838
+	lsl	r4, r4, #1
18331
18839
 	ldrh	r1, [r2, r4]
18332
18840
 	movw	r2, #65535
18333
18841
 	cmp	r1, r2
18334
-	bne	.L3040
18335
-	cmn	r8, #1
18336
-	strne	r8, [r3, #-368]
18337
-	bne	.L3029
18338
-	ldr	r2, [sp, #16]
18339
-	cmp	r2, fp
18340
-	bne	.L3150
18842
+	bne	.L2965
18843
+	cmn	r7, #1
18844
+	strne	r7, [r3, #-368]
18845
+	bne	.L2954
18846
+	ldr	r2, [sp, #12]
18847
+	cmp	fp, r2
18848
+	beq	.L2967
18849
+.L3080:
18850
+	str	r2, [r3, #-368]
18851
+	b	.L2954
18852
+.L2967:
18341
18853
 	ldr	r2, [r3, #-368]
18342
-	b	.L3155
18343
-.L3040:
18854
+.L3086:
18855
+	sub	r2, r2, #1
18856
+	b	.L3080
18857
+.L2965:
18344
18858
 	cmp	r6, fp
18345
-	beq	.L3043
18859
+	beq	.L2968
18346
18860
 	cmn	r6, #1
18347
18861
 	strne	r6, [r3, #-368]
18348
-	b	.L3029
18349
-.L3043:
18350
-	ldr	r2, [r3, #-368]
18351
-	cmp	r2, fp
18352
-	beq	.L3029
18353
-.L3155:
18354
-	sub	r2, r2, #1
18355
-	b	.L3150
18356
-.L3037:
18357
-	add	r3, r3, #36
18358
-	b	.L3035
18359
-.L3158:
18360
-	add	r4, r4, #1
18361
-	uxth	r4, r4
18362
-	b	.L3032
18363
-.L3045:
18364
-	ldr	r3, .L3161+8
18365
-	mvn	r2, #0
18366
-.L3150:
18367
-	str	r2, [r3, #-368]
18368
-.L3029:
18369
-	ldr	r2, .L3161+24
18370
-	movw	r3, #1850
18371
-	ldr	r10, [sp, #8]
18372
-	mov	r1, #1
18373
-	ldr	r4, .L3161+8
18374
-	strh	r1, [r2, r3]	@ movhi
18375
-.L3047:
18376
-	ldr	r3, .L3161+4
18377
-	movw	r1, #65535
18378
-	ldr	r8, [r4, #-536]
18379
-	mov	r0, #36
18380
-	ldr	r6, [sp, #20]
18381
-	mov	r5, #0
18382
-	ldrh	r7, [r3]
18383
-	ldrb	lr, [r3, #-2176]	@ zero_extendqisi2
18384
-	str	r5, [sp, #16]
18385
-.L3048:
18386
-	uxth	r3, r5
18387
-	cmp	r3, r7
18388
-	bcs	.L3159
18389
-	ldrh	r3, [r6, #2]!
18390
-	cmp	r3, r1
18391
-	beq	.L3049
18392
-	ldr	r2, [sp, #16]
18393
-	orr	r3, r10, r3, asl #10
18394
-	mla	r2, r0, r2, r8
18395
-	str	r3, [r2, #4]
18396
-	ldrb	ip, [r9, #8]	@ zero_extendqisi2
18397
-	cmp	ip, #1
18398
-	bne	.L3050
18399
-	cmp	lr, #0
18400
-	orrne	r3, r3, #-2147483648
18401
-	strne	r3, [r2, #4]
18402
-.L3050:
18403
-	ldr	r3, [sp, #16]
18404
-	add	r3, r3, #1
18405
-	uxth	r3, r3
18406
-	str	r3, [sp, #16]
18407
-.L3049:
18408
-	add	r5, r5, #1
18409
-	b	.L3048
18410
-.L3159:
18862
+.L2954:
18863
+	ldr	r9, [sp, #8]
18864
+	mov	r2, #1
18865
+	ldr	r4, .L3087+4
18866
+	movw	r3, #1848
18867
+	strh	r2, [r4, r3]	@ movhi
18868
+.L2972:
18869
+	ldr	r3, .L3087+8
18870
+	movw	r6, #65535
18411
18871
 	ldr	r0, [r4, #-536]
18412
-	ldr	r1, [sp, #16]
18872
+	mov	r7, #36
18873
+	ldr	r1, [sp, #20]
18874
+	mov	r2, #0
18875
+	ldrh	lr, [r3]
18876
+	ldr	r3, .L3087
18877
+	str	r2, [sp, #12]
18878
+	ldrb	r5, [r3, #152]	@ zero_extendqisi2
18879
+.L2973:
18880
+	uxth	r3, r2
18881
+	cmp	lr, r3
18882
+	bhi	.L2976
18413
18883
 	ldr	r2, [sp, #24]
18884
+	ldr	r1, [sp, #12]
18414
18885
 	bl	FlashReadPages
18415
18886
 	mov	r3, #0
18416
-.L3153:
18417
-	str	r3, [sp, #28]
18418
-	ldr	r2, [sp, #16]
18419
-	ldrh	r3, [sp, #28]
18420
-	cmp	r3, r2
18421
-	bcs	.L3160
18422
-	ldr	r3, [sp, #28]
18423
-	mov	r5, #36
18887
+.L3083:
18888
+	str	r3, [sp, #16]
18889
+	ldr	r2, [sp, #12]
18890
+	ldrh	r3, [sp, #16]
18891
+	cmp	r2, r3
18892
+	bhi	.L3002
18893
+	ldrb	r3, [r10, #8]	@ zero_extendqisi2
18894
+	add	r9, r9, #1
18895
+	uxth	r9, r9
18896
+	cmp	r3, #1
18897
+	bne	.L3003
18898
+	ldr	r3, .L3087
18899
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
18900
+	cmp	r3, #0
18901
+	beq	.L3003
18902
+	ldr	r3, .L3087+24
18903
+	ldr	r2, [sp]
18904
+	ldrh	r3, [r3]
18905
+	cmp	r3, r9
18906
+	cmpeq	r2, r9
18907
+	beq	.L2979
18908
+.L3003:
18909
+	ldr	r3, .L3087+28
18910
+	ldrh	r3, [r3]
18911
+	cmp	r3, r9
18912
+	bne	.L2972
18913
+	ldr	r1, .L3087
18914
+	movw	r2, #2324
18915
+	movw	r0, #65535
18916
+	mov	r3, #0
18917
+	strh	r9, [r10, #2]	@ movhi
18918
+	ldrh	r2, [r1, r2]
18919
+	strh	r3, [r10, #4]	@ movhi
18920
+.L3004:
18921
+	uxth	r1, r3
18922
+	cmp	r1, r2
18923
+	bcs	.L3073
18924
+	ldr	r1, [sp, #20]
18925
+	ldrh	ip, [r1], #2
18926
+	cmp	ip, r0
18927
+	str	r1, [sp, #20]
18928
+	add	r1, r3, #1
18929
+	bne	.L3084
18930
+	mov	r3, r1
18931
+	b	.L3004
18932
+.L2968:
18933
+	ldr	r2, [r3, #-368]
18934
+	cmp	fp, r2
18935
+	bne	.L3086
18936
+	b	.L2954
18937
+.L2970:
18938
+	mvn	r2, #0
18939
+	b	.L3080
18940
+.L2976:
18941
+	ldrh	r3, [r1], #2
18942
+	cmp	r3, r6
18943
+	beq	.L2974
18944
+	ldr	ip, [sp, #12]
18945
+	orr	r3, r9, r3, lsl #10
18946
+	mla	ip, r7, ip, r0
18947
+	str	r3, [ip, #4]
18948
+	ldrb	r8, [r10, #8]	@ zero_extendqisi2
18949
+	cmp	r8, #1
18950
+	bne	.L2975
18951
+	cmp	r5, #0
18952
+	orrne	r3, r3, #-2147483648
18953
+	strne	r3, [ip, #4]
18954
+.L2975:
18955
+	ldr	r3, [sp, #12]
18956
+	add	r3, r3, #1
18957
+	uxth	r3, r3
18958
+	str	r3, [sp, #12]
18959
+.L2974:
18960
+	add	r2, r2, #1
18961
+	b	.L2973
18962
+.L3002:
18963
+	ldr	r3, [sp, #16]
18964
+	mov	r6, #36
18424
18965
 	ldr	r8, [r4, #-536]
18425
-	mul	r5, r5, r3
18426
-	add	r7, r8, r5
18427
-	ldr	r6, [r7, #4]
18428
-	ubfx	r0, r6, #10, #16
18429
-	str	r6, [sp, #60]
18966
+	mul	r6, r6, r3
18967
+	add	r7, r8, r6
18968
+	ldr	r5, [r7, #4]
18969
+	ubfx	r0, r5, #10, #16
18970
+	str	r5, [sp, #44]
18430
18971
 	bl	P2V_plane
18431
18972
 	ldr	r3, [sp, #8]
18432
-	cmp	r10, r3
18433
-	bcc	.L3053
18434
-	ldr	r3, [sp, #32]
18435
-	ldr	r2, [sp, #8]
18436
-	cmp	r0, r3
18437
-	movcs	r3, #0
18438
-	movcc	r3, #1
18439
-	cmp	r10, r2
18973
+	cmp	r9, r3
18974
+	bcc	.L2978
18975
+	ldr	r2, [sp, #28]
18976
+	moveq	r3, #1
18440
18977
 	movne	r3, #0
18978
+	cmp	r2, r0
18979
+	movls	r3, #0
18980
+	andhi	r3, r3, #1
18441
18981
 	cmp	r3, #0
18442
-	bne	.L3053
18443
-	ldr	r3, [sp, #12]
18982
+	bne	.L2978
18983
+	ldr	r3, [sp]
18444
18984
 	ldr	r2, [sp, #4]
18445
-	cmp	r0, r3
18446
-	cmpeq	r10, r2
18447
-	beq	.L3054
18448
-	ldr	r3, [r8, r5]
18985
+	cmp	r9, r3
18986
+	cmpeq	r2, r0
18987
+	beq	.L2979
18988
+	ldr	r3, [r8, r6]
18449
18989
 	cmn	r3, #1
18450
-	beq	.L3055
18451
-	ldr	r7, [r7, #12]
18452
-	movw	r3, #61589
18453
-	ldrh	r2, [r7]
18454
-	cmp	r2, r3
18455
-	ldrneh	r0, [r9]
18456
-	bne	.L3151
18457
-	ldr	fp, [r7, #4]
18990
+	beq	.L2980
18991
+	ldr	r3, [r7, #12]
18992
+	movw	r2, #61589
18993
+	ldrh	r1, [r3]
18994
+	cmp	r1, r2
18995
+	ldrhne	r0, [r10]
18996
+	bne	.L3081
18997
+	ldr	fp, [r3, #4]
18458
18998
 	cmn	fp, #1
18459
-	beq	.L3057
18999
+	beq	.L2982
18460
19000
 	ldr	r1, [r4, #-3328]
18461
19001
 	mov	r0, fp
18462
19002
 	bl	ftl_cmp_data_ver
18463
19003
 	cmp	r0, #0
18464
-	addne	r3, fp, #1
18465
-	strne	r3, [r4, #-3328]
18466
-.L3057:
18467
-	ldr	r6, [r7, #8]
18468
-	add	r1, sp, #56
18469
-	ldr	r3, [r7, #12]
19004
+	addne	r2, fp, #1
19005
+	strne	r2, [r4, #-3328]
19006
+.L2982:
19007
+	ldr	r5, [r3, #8]
19008
+	add	r1, sp, #40
19009
+	ldr	r3, [r3, #12]
18470
19010
 	mov	r2, #0
18471
-	mov	r0, r6
18472
-	str	r3, [sp, #52]
19011
+	mov	r0, r5
19012
+	str	r3, [sp, #36]
18473
19013
 	bl	log2phys
18474
19014
 	ldr	r1, [r4, #-368]
18475
19015
 	cmn	r1, #1
18476
-	beq	.L3058
19016
+	beq	.L2983
18477
19017
 	mov	r0, fp
18478
19018
 	bl	ftl_cmp_data_ver
18479
19019
 	cmp	r0, #0
18480
-	beq	.L3058
18481
-	ldr	r3, [sp, #52]
19020
+	beq	.L2983
19021
+	ldr	r3, [sp, #36]
18482
19022
 	cmn	r3, #1
18483
-	beq	.L3059
19023
+	beq	.L2984
18484
19024
 	ldr	r0, [r4, #-536]
18485
19025
 	mov	r2, #0
18486
19026
 	mov	r1, #1
18487
-	add	r0, r0, r5
19027
+	add	r0, r0, r6
18488
19028
 	str	r3, [r0, #4]
18489
-	ldr	r8, [r0, #12]
18490
-	bl	FlashReadPages
18491
-	ldr	r2, [r4, #-536]
18492
-	ldr	r3, [r8, #4]
18493
-	add	ip, r2, r5
18494
-	str	r3, [sp, #36]
18495
-	ldr	r3, [r2, r5]
18496
-	cmn	r3, #1
18497
-	bne	.L3060
18498
-	b	.L3061
18499
-.L3059:
18500
-	ldr	r3, [sp, #60]
18501
-	ldr	r2, [sp, #56]
18502
-	cmp	r2, r3
18503
-	bne	.L3053
18504
-	mov	r0, r6
18505
-	add	r1, sp, #52
18506
-	mov	r2, #1
18507
-	bl	log2phys
18508
-	b	.L3053
18509
-.L3060:
18510
-	ldr	r7, [r8, #8]
18511
-	cmp	r7, r6
18512
-	bne	.L3061
18513
-	ldr	r0, [r4, #-368]
18514
-	ldr	r1, [sp, #36]
18515
-	str	r2, [sp, #44]
18516
-	str	ip, [sp, #40]
18517
-	bl	ftl_cmp_data_ver
18518
-	cmp	r0, #0
18519
-	ldr	ip, [sp, #40]
18520
-	ldr	r2, [sp, #44]
18521
-	beq	.L3061
18522
-	ldr	r3, [sp, #56]
18523
-	ldr	r1, [sp, #60]
18524
-	cmp	r3, r1
18525
-	beq	.L3066
18526
-	ldr	r1, [sp, #52]
18527
-	cmp	r3, r1
18528
-	beq	.L3061
18529
-	cmn	r3, #1
18530
-	streq	r3, [r2, r5]
18531
-	beq	.L3065
18532
-	str	r3, [ip, #4]
18533
-	mov	r0, ip
18534
-	mov	r1, #1
18535
-	mov	r2, #0
18536
-	ldr	r8, [ip, #12]
18537
-	bl	FlashReadPages
18538
-.L3065:
18539
-	ldr	r3, [r4, #-536]
18540
-	ldr	r3, [r3, r5]
18541
-	cmn	r3, #1
18542
-	beq	.L3066
18543
-	ldr	r5, [r8, #4]
18544
-	ldr	r0, [r4, #-368]
18545
-	mov	r1, r5
18546
-	bl	ftl_cmp_data_ver
18547
-	cmp	r0, #0
18548
-	beq	.L3066
18549
-	ldr	r0, [sp, #36]
18550
-	mov	r1, r5
18551
-	bl	ftl_cmp_data_ver
18552
-	cmp	r0, #0
18553
-	beq	.L3061
18554
-.L3066:
18555
-	mov	r0, r7
18556
-	ldr	r1, [sp, #52]
18557
-	bl	FtlReUsePrevPpa
18558
-.L3061:
18559
-	mvn	r3, #0
18560
-	str	r3, [sp, #52]
18561
-	b	.L3068
18562
-.L3058:
18563
-	ldr	r3, [sp, #60]
18564
-	ldr	r2, [sp, #56]
18565
-	cmp	r2, r3
18566
-	beq	.L3068
18567
-	ldr	r3, [sp, #52]
18568
-	cmn	r3, #1
18569
-	beq	.L3070
18570
-	ldr	r2, .L3161
18571
-	ubfx	r3, r3, #10, #21
18572
-	ldr	r2, [r2, #2336]
18573
-	cmp	r3, r2
18574
-	bcs	.L3053
18575
-.L3070:
18576
-	mov	r0, r6
18577
-	add	r1, sp, #60
18578
-	mov	r2, #1
18579
-	bl	log2phys
18580
-	ldr	r5, [sp, #56]
18581
-	cmn	r5, #1
18582
-	beq	.L3068
18583
-	ldr	r3, [sp, #52]
18584
-	cmp	r5, r3
18585
-	beq	.L3068
18586
-	ubfx	r0, r5, #10, #16
18587
-	bl	P2V_block_in_plane
18588
-	ldr	r3, .L3161+28
18589
-	ldrh	r2, [r3]
18590
-	cmp	r2, r0
18591
-	beq	.L3072
18592
-	ldrh	r2, [r3, #48]
18593
-	cmp	r2, r0
18594
-	beq	.L3072
18595
-	ldrh	r3, [r3, #96]
18596
-	cmp	r3, r0
18597
-	bne	.L3068
18598
-.L3072:
18599
-	ldr	r0, [r4, #-536]
18600
-	mov	r1, #1
18601
-	mov	r2, #0
18602
-	str	r5, [r0, #4]
18603
19029
 	ldr	r7, [r0, #12]
18604
19030
 	bl	FlashReadPages
18605
-	ldr	r3, [r4, #-536]
18606
-	ldr	r1, [r7, #4]
18607
-	ldr	r3, [r3]
18608
-	cmn	r3, #1
18609
-	beq	.L3068
18610
-	mov	r0, fp
18611
-	bl	ftl_cmp_data_ver
18612
-	cmp	r0, #0
18613
-	bne	.L3068
18614
-	mov	r0, r6
18615
-	add	r1, sp, #56
18616
-	mov	r2, #1
18617
-	bl	log2phys
18618
-.L3068:
18619
-	ldr	r0, [sp, #52]
18620
-	cmn	r0, #1
18621
-	beq	.L3053
18622
-	ubfx	r0, r0, #10, #16
19031
+	ldr	r2, [r4, #-536]
19032
+	ldr	r1, [r2, r6]
19033
+	add	r3, r2, r6
19034
+	cmn	r1, #1
19035
+	bne	.L2985
19036
+.L2986:
19037
+	mvn	r3, #0
19038
+	str	r3, [sp, #36]
19039
+.L2993:
19040
+	ldr	r8, [sp, #36]
19041
+	cmn	r8, #1
19042
+	beq	.L2978
19043
+.L3007:
19044
+	ubfx	r0, r8, #10, #16
18623
19045
 	bl	P2V_block_in_plane
18624
-	ldr	r2, [r4, #-3544]
18625
-	mov	r3, r0, asl #1
19046
+	ldr	r2, [r4, #-3540]
19047
+	lsl	r3, r0, #1
18626
19048
 	mov	r1, r0
18627
19049
 	ldrh	r3, [r2, r3]
18628
19050
 	cmp	r3, #0
18629
-	beq	.L3073
18630
-.L3151:
19051
+	beq	.L2999
19052
+.L3081:
18631
19053
 	bl	decrement_vpc_count
18632
-	b	.L3053
18633
-.L3073:
18634
-	ldr	r0, .L3161+32
19054
+	b	.L2978
19055
+.L2984:
19056
+	ldr	r3, [sp, #44]
19057
+	ldr	r2, [sp, #40]
19058
+	cmp	r2, r3
19059
+	bne	.L2978
19060
+	mov	r2, #1
19061
+	add	r1, sp, #36
19062
+	mov	r0, r5
19063
+	bl	log2phys
19064
+.L2978:
19065
+	ldr	r3, [sp, #16]
19066
+	add	r3, r3, #1
19067
+	b	.L3083
19068
+.L2985:
19069
+	ldr	r1, [r7, #8]
19070
+	cmp	r5, r1
19071
+	bne	.L2986
19072
+	ldr	r8, [r7, #4]
19073
+	ldr	r0, [r4, #-368]
19074
+	mov	r1, r8
19075
+	bl	ftl_cmp_data_ver
19076
+	cmp	r0, #0
19077
+	beq	.L2986
19078
+	ldr	r1, [sp, #40]
19079
+	ldr	r0, [sp, #44]
19080
+	cmp	r1, r0
19081
+	bne	.L2988
19082
+.L2991:
19083
+	ldr	r1, [sp, #36]
19084
+	mov	r0, r5
19085
+	bl	FtlReUsePrevPpa
19086
+	b	.L2986
19087
+.L2988:
19088
+	ldr	r0, [sp, #36]
19089
+	cmp	r1, r0
19090
+	beq	.L2986
19091
+	cmn	r1, #1
19092
+	streq	r1, [r2, r6]
19093
+	beq	.L2990
19094
+	str	r1, [r3, #4]
19095
+	mov	r2, #0
19096
+	mov	r1, #1
19097
+	mov	r0, r3
19098
+	ldr	r7, [r3, #12]
19099
+	bl	FlashReadPages
19100
+.L2990:
19101
+	ldr	r3, [r4, #-536]
19102
+	ldr	r3, [r3, r6]
19103
+	cmn	r3, #1
19104
+	beq	.L2991
19105
+	ldr	r3, [r7, #4]
19106
+	ldr	r0, [r4, #-368]
19107
+	mov	r1, r3
19108
+	bl	ftl_cmp_data_ver
19109
+	cmp	r0, #0
19110
+	beq	.L2991
19111
+	mov	r1, r3
19112
+	mov	r0, r8
19113
+	bl	ftl_cmp_data_ver
19114
+	cmp	r0, #0
19115
+	beq	.L2986
19116
+	b	.L2991
19117
+.L2983:
19118
+	ldr	r3, [sp, #44]
19119
+	ldr	r2, [sp, #40]
19120
+	cmp	r2, r3
19121
+	beq	.L2993
19122
+	ldr	r3, [sp, #36]
19123
+	cmn	r3, #1
19124
+	beq	.L2995
19125
+	ldr	r2, .L3087
19126
+	ubfx	r3, r3, #10, #21
19127
+	ldr	r2, [r2, #2340]
19128
+	cmp	r3, r2
19129
+	bcs	.L2978
19130
+.L2995:
19131
+	mov	r2, #1
19132
+	add	r1, sp, #44
19133
+	mov	r0, r5
19134
+	bl	log2phys
19135
+	ldr	r8, [sp, #40]
19136
+	cmn	r8, #1
19137
+	beq	.L2993
19138
+	ldr	r3, [sp, #36]
19139
+	cmp	r8, r3
19140
+	beq	.L3007
19141
+	ldr	r6, .L3087+32
19142
+	ubfx	r0, r8, #10, #16
19143
+	bl	P2V_block_in_plane
19144
+	ldrh	r3, [r6]
19145
+	cmp	r3, r0
19146
+	beq	.L2998
19147
+	add	r2, r6, #48
19148
+	ldrh	r2, [r2]
19149
+	cmp	r2, r0
19150
+	beq	.L2998
19151
+	add	r3, r6, #96
19152
+	ldrh	r3, [r3]
19153
+	cmp	r3, r0
19154
+	bne	.L2993
19155
+.L2998:
19156
+	ldr	r0, [r6, #2984]
19157
+	mov	r2, #0
19158
+	mov	r1, #1
19159
+	str	r8, [r0, #4]
19160
+	ldr	r7, [r0, #12]
19161
+	bl	FlashReadPages
19162
+	ldr	r3, [r6, #2984]
19163
+	ldr	r3, [r3]
19164
+	cmn	r3, #1
19165
+	beq	.L2993
19166
+	ldr	r1, [r7, #4]
19167
+	mov	r0, fp
19168
+	bl	ftl_cmp_data_ver
19169
+	cmp	r0, #0
19170
+	bne	.L2993
19171
+	mov	r2, #1
19172
+	add	r1, sp, #40
19173
+	mov	r0, r5
19174
+	bl	log2phys
19175
+	b	.L2993
19176
+.L2999:
19177
+	ldr	r0, .L3087+36
18635
19178
 	bl	printk
18636
-	b	.L3053
18637
-.L3055:
18638
-	ldrh	r3, [r9]
18639
-	mov	r1, r6
18640
-	ldr	r2, .L3161+16
18641
-	ldr	r0, .L3161+36
19179
+	b	.L2978
19180
+.L2980:
19181
+	ldrh	r3, [r10]
19182
+	mov	r1, r5
19183
+	ldr	r2, .L3087+16
19184
+	ldr	r0, .L3087+40
18642
19185
 	strh	r3, [r2]	@ movhi
18643
19186
 	mov	r2, fp
18644
19187
 	bl	printk
18645
-	ldr	r3, .L3161+24
18646
-	ldr	r3, [r3, #1852]
19188
+	ldr	r3, [r4, #1852]
18647
19189
 	cmp	r3, #31
18648
-	bhi	.L3074
18649
-	ldr	r2, .L3161+24
18650
-	ldr	r1, [sp, #60]
18651
-	add	r2, r2, r3, asl #2
18652
-	add	r3, r3, #1
18653
-	str	r1, [r2, #1856]
18654
-	ldr	r2, .L3161+24
18655
-	str	r3, [r2, #1852]
18656
-.L3074:
18657
-	ldrh	r0, [r9]
19190
+	ldrls	r1, [sp, #44]
19191
+	addls	r2, r4, r3, lsl #2
19192
+	addls	r3, r3, #1
19193
+	strls	r3, [r4, #1852]
19194
+	strls	r1, [r2, #1856]
19195
+	ldrh	r0, [r10]
18658
19196
 	bl	decrement_vpc_count
18659
19197
 	ldr	r3, [r4, #-368]
18660
19198
 	cmn	r3, #1
18661
-	beq	.L3152
18662
-	cmp	r3, fp
18663
-	bls	.L3053
18664
-.L3152:
19199
+	bne	.L3001
19200
+.L3082:
18665
19201
 	str	fp, [r4, #-368]
18666
-.L3053:
18667
-	ldr	r3, [sp, #28]
18668
-	add	r3, r3, #1
18669
-	b	.L3153
18670
-.L3160:
18671
-	ldrb	r3, [r9, #8]	@ zero_extendqisi2
18672
-	add	r10, r10, #1
18673
-	cmp	r3, #1
18674
-	uxth	r10, r10
18675
-	bne	.L3077
18676
-	ldr	r3, .L3161
18677
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
18678
-	cmp	r3, #0
18679
-	beq	.L3077
18680
-	ldr	r3, .L3161+40
18681
-	ldr	r2, [sp, #4]
18682
-	ldrh	r3, [r3]
18683
-	cmp	r2, r10
18684
-	cmpeq	r3, r10
18685
-	beq	.L3054
18686
-.L3077:
18687
-	ldr	r2, .L3161+44
18688
-	ldrh	r3, [r2]
18689
-	cmp	r10, r3
18690
-	bne	.L3047
18691
-	ldrh	r1, [r2, #-68]
18692
-	movw	r0, #65535
18693
-	mov	r3, #0
18694
-	strh	r10, [r9, #2]	@ movhi
18695
-	strh	r3, [r9, #4]	@ movhi
18696
-.L3078:
18697
-	uxth	r2, r3
18698
-	cmp	r2, r1
18699
-	bcs	.L3144
18700
-	ldr	lr, [sp, #20]
18701
-	add	r3, r3, #1
18702
-	ldrh	ip, [lr, #2]!
18703
-	cmp	ip, r0
18704
-	str	lr, [sp, #20]
18705
-	beq	.L3078
18706
-	strb	r2, [r9, #6]
18707
-	b	.L3144
18708
-.L3054:
18709
-	ldrb	r3, [sp, #12]	@ zero_extendqisi2
18710
-	mov	r0, r9
18711
-	ldr	r1, [sp, #4]
18712
-	strb	r3, [r9, #6]
18713
-	ldrh	r3, [sp, #4]
18714
-	strh	r3, [r9, #2]	@ movhi
18715
-.L3154:
18716
-	ldr	r2, [sp, #12]
19202
+	b	.L2978
19203
+.L3001:
19204
+	cmp	fp, r3
19205
+	bcs	.L2978
19206
+	b	.L3082
19207
+.L2979:
19208
+	ldrb	r3, [sp, #4]	@ zero_extendqisi2
19209
+	ldm	sp, {r1, r2}
19210
+	strb	r3, [r10, #6]
19211
+	ldrh	r3, [sp]
19212
+	strh	r3, [r10, #2]	@ movhi
19213
+.L3085:
19214
+	mov	r0, r10
18717
19215
 	bl	ftl_sb_update_avl_pages
18718
-.L3144:
19216
+	b	.L3073
19217
+.L3075:
18719
19218
 	mov	r0, #0
18720
-	add	sp, sp, #68
18721
-	@ sp needed
18722
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
18723
-.L3162:
19219
+	bx	lr
19220
+.L3088:
18724
19221
 	.align	2
18725
-.L3161:
19222
+.L3087:
18726
19223
 	.word	.LANCHOR0
18727
-	.word	.LANCHOR0+2320
18728
19224
 	.word	.LANCHOR2
19225
+	.word	.LANCHOR0+2324
18729
19226
 	.word	.LC149
18730
-	.word	.LANCHOR4+1848
19227
+	.word	.LANCHOR2+1846
18731
19228
 	.word	.LANCHOR2-2620
18732
-	.word	.LANCHOR4
18733
-	.word	.LANCHOR2-3524
19229
+	.word	.LANCHOR0+2392
19230
+	.word	.LANCHOR0+2390
19231
+	.word	.LANCHOR2-3520
18734
19232
 	.word	.LC150
18735
19233
 	.word	.LC151
18736
-	.word	.LANCHOR0+2390
18737
-	.word	.LANCHOR0+2388
18738
19234
 	.fnend
18739
19235
 	.size	FtlRecoverySuperblock, .-FtlRecoverySuperblock
18740
19236
 	.align	2
18741
19237
 	.global	FtlVpcCheckAndModify
19238
+	.syntax unified
19239
+	.arm
19240
+	.fpu softvfp
18742
19241
 	.type	FtlVpcCheckAndModify, %function
18743
19242
 FtlVpcCheckAndModify:
18744
19243
 	.fnstart
18745
19244
 	@ args = 0, pretend = 0, frame = 8
18746
19245
 	@ frame_needed = 0, uses_anonymous_args = 0
18747
-	stmfd	sp!, {r0, r1, r4, r5, r6, r7, r8, r9, r10, lr}
19246
+	push	{r0, r1, r4, r5, r6, r7, r8, r9, r10, lr}
18748
19247
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
18749
19248
 	.pad #8
18750
-	mov	r4, #0
18751
-	ldr	r5, .L3180
18752
-	ldr	r1, .L3180+4
18753
-	ldr	r0, .L3180+8
19249
+	mov	r5, #0
19250
+	ldr	r6, .L3104
19251
+	ldr	r1, .L3104+4
19252
+	ldr	r0, .L3104+8
18754
19253
 	bl	printk
18755
-	movw	r3, #2330
18756
-	ldrh	r2, [r5, r3]
19254
+	movw	r3, #2334
19255
+	ldr	r4, .L3104+12
19256
+	ldrh	r2, [r6, r3]
18757
19257
 	mov	r1, #0
18758
-	ldr	r6, .L3180+12
18759
-	mov	r2, r2, asl #1
18760
-	ldr	r0, [r6, #-476]
19258
+	ldr	r0, [r4, #-476]
19259
+	lsl	r2, r2, #1
18761
19260
 	bl	ftl_memset
18762
-.L3164:
18763
-	ldr	r3, [r5, #2448]
18764
-	cmp	r4, r3
18765
-	bcs	.L3178
18766
-	mov	r0, r4
18767
-	add	r1, sp, #4
18768
-	mov	r2, #0
18769
-	bl	log2phys
18770
-	ldr	r0, [sp, #4]
18771
-	cmn	r0, #1
18772
-	beq	.L3165
18773
-	ubfx	r0, r0, #10, #16
18774
-	bl	P2V_block_in_plane
18775
-	ldr	r2, [r6, #-476]
18776
-	mov	r0, r0, asl #1
18777
-	ldrh	r3, [r2, r0]
18778
-	add	r3, r3, #1
18779
-	strh	r3, [r2, r0]	@ movhi
18780
-.L3165:
18781
-	add	r4, r4, #1
18782
-	b	.L3164
18783
-.L3178:
18784
-	ldr	r8, .L3180+16
19261
+.L3090:
19262
+	ldr	r3, [r6, #2452]
19263
+	cmp	r5, r3
19264
+	bcc	.L3092
19265
+	ldr	r8, .L3104+16
18785
19266
 	mov	r7, #0
18786
-	ldr	r10, .L3180+12
18787
-	ldr	r9, .L3180+20
18788
-.L3167:
18789
-	ldrh	r3, [r8]
18790
-	uxth	r4, r7
18791
-	cmp	r3, r4
18792
-	bls	.L3179
18793
-	ldr	r3, [r6, #-3544]
18794
-	mov	r5, r4, asl #1
18795
-	movw	r1, #65535
18796
-	ldrh	r2, [r3, r5]
18797
-	ldr	r3, [r6, #-476]
18798
-	ldrh	r3, [r3, r5]
18799
-	cmp	r2, r1
18800
-	cmpne	r2, r3
18801
-	beq	.L3168
18802
-	ldrh	r1, [r9]
18803
-	cmp	r1, r4
18804
-	beq	.L3168
18805
-	ldr	r1, .L3180+24
18806
-	ldrh	r0, [r1]
18807
-	cmp	r0, r4
18808
-	beq	.L3168
18809
-	ldrh	r1, [r1, #-48]
18810
-	cmp	r1, r4
18811
-	beq	.L3168
18812
-	ldr	r0, .L3180+28
18813
-	mov	r1, r4
18814
-	bl	printk
18815
-	ldr	r3, [r10, #-3544]
18816
-	ldrh	r2, [r3, r5]
18817
-	cmp	r2, #0
18818
-	ldr	r2, [r10, #-476]
18819
-	ldrh	r2, [r2, r5]
18820
-	strh	r2, [r3, r5]	@ movhi
18821
-	beq	.L3168
18822
-	mov	r0, r4
18823
-	bl	update_vpc_list
18824
-.L3168:
18825
-	add	r7, r7, #1
18826
-	b	.L3167
18827
-.L3179:
19267
+	ldr	r9, .L3104+20
19268
+	add	r10, r8, #96
19269
+.L3093:
19270
+	ldrh	r3, [r9]
19271
+	uxth	r6, r7
19272
+	cmp	r3, r6
19273
+	bhi	.L3096
18828
19274
 	bl	l2p_flush
18829
19275
 	bl	FtlVpcTblFlush
18830
19276
 	add	sp, sp, #8
18831
19277
 	@ sp needed
18832
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
18833
-.L3181:
19278
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
19279
+.L3092:
19280
+	mov	r2, #0
19281
+	add	r1, sp, #4
19282
+	mov	r0, r5
19283
+	bl	log2phys
19284
+	ldr	r0, [sp, #4]
19285
+	cmn	r0, #1
19286
+	beq	.L3091
19287
+	ubfx	r0, r0, #10, #16
19288
+	bl	P2V_block_in_plane
19289
+	ldr	r2, [r4, #-476]
19290
+	lsl	r0, r0, #1
19291
+	ldrh	r3, [r2, r0]
19292
+	add	r3, r3, #1
19293
+	strh	r3, [r2, r0]	@ movhi
19294
+.L3091:
19295
+	add	r5, r5, #1
19296
+	b	.L3090
19297
+.L3096:
19298
+	uxth	r1, r7
19299
+	ldr	r3, [r4, #-3540]
19300
+	movw	r0, #65535
19301
+	lsl	r5, r1, #1
19302
+	ldrh	r2, [r3, r5]
19303
+	ldr	r3, [r4, #-476]
19304
+	ldrh	r3, [r3, r5]
19305
+	cmp	r2, r0
19306
+	cmpne	r2, r3
19307
+	beq	.L3094
19308
+	ldrh	r0, [r8]
19309
+	cmp	r0, r6
19310
+	beq	.L3094
19311
+	ldrh	r0, [r10]
19312
+	cmp	r0, r6
19313
+	beq	.L3094
19314
+	ldr	r0, .L3104+24
19315
+	ldrh	r0, [r0]
19316
+	cmp	r0, r6
19317
+	beq	.L3094
19318
+	ldr	r0, .L3104+28
19319
+	bl	printk
19320
+	ldr	r3, [r4, #-3540]
19321
+	ldrh	r2, [r3, r5]
19322
+	cmp	r2, #0
19323
+	ldr	r2, [r4, #-476]
19324
+	ldrh	r2, [r2, r5]
19325
+	strh	r2, [r3, r5]	@ movhi
19326
+	bne	.L3095
19327
+.L3094:
19328
+	add	r7, r7, #1
19329
+	b	.L3093
19330
+.L3095:
19331
+	mov	r0, r6
19332
+	bl	update_vpc_list
19333
+	b	.L3094
19334
+.L3105:
18834
19335
 	.align	2
18835
-.L3180:
19336
+.L3104:
18836
19337
 	.word	.LANCHOR0
18837
-	.word	.LANCHOR3+216
19338
+	.word	.LANCHOR3+203
18838
19339
 	.word	.LC110
18839
19340
 	.word	.LANCHOR2
18840
-	.word	.LANCHOR0+2328
18841
-	.word	.LANCHOR2-3524
18842
-	.word	.LANCHOR2-3428
19341
+	.word	.LANCHOR2-3520
19342
+	.word	.LANCHOR0+2332
19343
+	.word	.LANCHOR2-3472
18843
19344
 	.word	.LC152
18844
19345
 	.fnend
18845
19346
 	.size	FtlVpcCheckAndModify, .-FtlVpcCheckAndModify
18846
19347
 	.align	2
18847
19348
 	.global	FtlGcScanTempBlk
19349
+	.syntax unified
19350
+	.arm
19351
+	.fpu softvfp
18848
19352
 	.type	FtlGcScanTempBlk, %function
18849
19353
 FtlGcScanTempBlk:
18850
19354
 	.fnstart
18851
19355
 	@ args = 0, pretend = 0, frame = 64
18852
19356
 	@ frame_needed = 0, uses_anonymous_args = 0
18853
-	ldr	r2, .L3235
18854
-	movw	r3, #3448
18855
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
19357
+	ldr	r2, .L3154
19358
+	movw	r3, #3444
19359
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
18856
19360
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
18857
19361
 	.pad #68
18858
19362
 	sub	sp, sp, #68
18859
-	ldrh	r5, [r2, r3]
18860
-	movw	r3, #65535
18861
19363
 	mov	r4, r0
18862
19364
 	str	r1, [sp, #12]
18863
-	cmp	r5, r3
18864
-	beq	.L3216
18865
-	cmp	r5, #0
18866
-	bne	.L3183
18867
-	b	.L3184
18868
-.L3216:
18869
-	mov	r5, #0
18870
-.L3183:
18871
-	ldr	r2, .L3235+4
18872
-	movw	r3, #2388
19365
+	ldrh	r6, [r2, r3]
19366
+	movw	r3, #65535
19367
+	cmp	r6, r3
19368
+	beq	.L3138
19369
+	cmp	r6, #0
19370
+	bne	.L3107
19371
+.L3108:
19372
+	bl	FtlGcPageVarInit
19373
+	b	.L3109
19374
+.L3138:
19375
+	mov	r6, #0
19376
+.L3107:
19377
+	ldr	r2, .L3154+4
19378
+	movw	r3, #2390
18873
19379
 	ldrh	r3, [r2, r3]
18874
19380
 	ldr	r2, [sp, #12]
18875
-	cmp	r2, r3
18876
-	bne	.L3185
18877
-.L3184:
18878
-	bl	FtlGcPageVarInit
18879
-.L3185:
18880
-	ldr	r6, .L3235+8
19381
+	cmp	r3, r2
19382
+	beq	.L3108
19383
+.L3109:
19384
+	ldr	r5, .L3154+8
18881
19385
 	mvn	r3, #0
18882
19386
 	str	r3, [sp, #8]
18883
19387
 	mov	r3, #0
18884
19388
 	str	r3, [sp]
18885
-.L3186:
19389
+.L3110:
18886
19390
 	ldrh	r1, [r4]
18887
19391
 	movw	r3, #65535
18888
19392
 	mov	r2, #0
18889
19393
 	strb	r2, [r4, #8]
18890
19394
 	cmp	r1, r3
18891
-	beq	.L3187
18892
-.L3188:
18893
-.L3213:
18894
-	ldr	r3, .L3235+12
18895
-	mov	r7, #0
18896
-	ldr	ip, [r6, #-2692]
18897
-	add	r1, r4, #14
18898
-	mov	r8, r7
19395
+	beq	.L3111
19396
+.L3135:
19397
+	ldr	r3, .L3154+12
19398
+	add	ip, r4, #16
19399
+	ldr	r0, [r5, #-536]
18899
19400
 	movw	r9, #65535
18900
-	ldrh	r3, [r3]
19401
+	ldr	lr, [r5, #-2692]
18901
19402
 	mov	r10, #36
19403
+	ldrh	r3, [r3]
18902
19404
 	str	r3, [sp, #4]
18903
-	ldr	r3, [r6, #-536]
19405
+	ldr	r3, [r5, #-2696]
18904
19406
 	str	r3, [sp, #16]
18905
-	ldr	r3, [r6, #-2696]
18906
-	str	r3, [sp, #20]
18907
-	ldr	r3, .L3235+16
18908
-	ldrh	r0, [r3]
18909
-	ldrh	lr, [r3, #2]
18910
-.L3189:
18911
-	ldr	r2, [sp, #4]
18912
-	uxth	r3, r7
19407
+	ldr	r3, .L3154+16
19408
+	ldrh	r2, [r3]
19409
+	ldrh	r8, [r3, #2]
19410
+	str	r2, [sp, #20]
19411
+	mov	r2, #0
19412
+	mov	r7, r2
19413
+.L3112:
19414
+	ldr	r1, [sp, #4]
19415
+	uxth	r3, r2
19416
+	cmp	r1, r3
19417
+	bhi	.L3114
19418
+	ldr	r10, .L3154+4
19419
+	mov	fp, #0
19420
+	mov	r2, #0
19421
+	mov	r1, r7
19422
+	bl	FlashReadPages
19423
+.L3115:
19424
+	uxth	r3, fp
19425
+	cmp	r7, r3
19426
+	bhi	.L3133
19427
+	ldr	r3, [sp]
19428
+	add	r6, r6, #1
19429
+	uxth	r6, r6
19430
+	add	r3, r3, #1
19431
+	str	r3, [sp]
19432
+	ldr	r2, [sp]
19433
+	ldr	r3, [sp, #12]
18913
19434
 	cmp	r3, r2
18914
-	bcs	.L3233
18915
-	ldrh	r3, [r1, #2]!
19435
+	ldr	r2, .L3154+20
19436
+	bls	.L3134
19437
+.L3136:
19438
+	ldrh	r3, [r2]
19439
+	cmp	r3, r6
19440
+	bhi	.L3135
19441
+	mov	r2, #0
19442
+	b	.L3111
19443
+.L3114:
19444
+	ldrh	r3, [ip], #2
18916
19445
 	cmp	r3, r9
18917
-	beq	.L3190
18918
-	ldr	r2, [sp, #16]
18919
-	orr	r3, r5, r3, asl #10
18920
-	mla	r2, r10, r8, r2
18921
-	str	r3, [r2, #4]
18922
-	mul	r3, r0, r8
19446
+	beq	.L3113
19447
+	mla	r1, r10, r7, r0
19448
+	orr	r3, r6, r3, lsl #10
19449
+	str	r3, [r1, #4]
19450
+	ldr	r3, [sp, #20]
19451
+	mul	r3, r3, r7
18923
19452
 	add	fp, r3, #3
18924
19453
 	cmp	r3, #0
18925
19454
 	movlt	r3, fp
18926
-	ldr	fp, [sp, #20]
19455
+	ldr	fp, [sp, #16]
18927
19456
 	bic	r3, r3, #3
18928
19457
 	add	r3, fp, r3
18929
-	str	r3, [r2, #8]
18930
-	mul	r3, lr, r8
18931
-	add	r8, r8, #1
18932
-	uxth	r8, r8
19458
+	str	r3, [r1, #8]
19459
+	mul	r3, r8, r7
19460
+	add	r7, r7, #1
19461
+	uxth	r7, r7
18933
19462
 	add	fp, r3, #3
18934
19463
 	cmp	r3, #0
18935
19464
 	movlt	r3, fp
18936
19465
 	bic	r3, r3, #3
18937
-	add	r3, ip, r3
18938
-	str	r3, [r2, #12]
18939
-.L3190:
18940
-	add	r7, r7, #1
18941
-	b	.L3189
18942
-.L3233:
18943
-	ldr	r0, [r6, #-536]
18944
-	mov	r1, r8
18945
-	mov	r2, #0
18946
-	mov	fp, #0
18947
-	bl	FlashReadPages
18948
-.L3192:
18949
-	uxth	r3, fp
18950
-	cmp	r3, r8
18951
-	bcs	.L3234
18952
-	ldr	r3, .L3235+8
19466
+	add	r3, lr, r3
19467
+	str	r3, [r1, #12]
19468
+.L3113:
19469
+	add	r2, r2, #1
19470
+	b	.L3112
19471
+.L3133:
18953
19472
 	mov	r9, #36
19473
+	ldr	r8, [r5, #-536]
18954
19474
 	mul	r9, r9, fp
18955
-	ldr	r7, [r3, #-536]
18956
-	add	r10, r7, r9
18957
-	ldr	r3, [r10, #4]
18958
-	ubfx	r0, r3, #10, #16
18959
-	str	r3, [sp, #4]
19475
+	add	r3, r8, r9
19476
+	ldr	r2, [r3, #4]
19477
+	str	r3, [sp, #16]
19478
+	ubfx	r0, r2, #10, #16
19479
+	str	r2, [sp, #4]
18960
19480
 	bl	P2V_plane
18961
-	ldr	r7, [r7, r9]
18962
-	ldr	r10, [r10, #12]
18963
-	cmp	r7, #0
18964
-	ldr	ip, .L3235+4
18965
-	ldr	r3, .L3235+8
19481
+	ldr	r8, [r8, r9]
18966
19482
 	mov	r2, r0
18967
-	bne	.L3193
18968
-	ldrh	r0, [r10]
19483
+	ldr	r3, [sp, #16]
19484
+	cmp	r8, #0
19485
+	ldr	r3, [r3, #12]
19486
+	bne	.L3116
19487
+	ldrh	r0, [r3]
18969
19488
 	movw	r1, #65535
18970
19489
 	cmp	r0, r1
18971
-	bne	.L3194
18972
-.L3197:
18973
-	ldrb	r1, [ip, #144]	@ zero_extendqisi2
19490
+	bne	.L3117
19491
+.L3120:
19492
+	ldrb	r1, [r10, #152]	@ zero_extendqisi2
18974
19493
 	cmp	r1, #0
18975
-	beq	.L3228
18976
-	mov	r1, #1
18977
-	str	r1, [r3, #-372]
18978
-	b	.L3187
18979
-.L3194:
18980
-	ldr	r1, .L3235+4
18981
-	ldr	r0, [r10, #8]
18982
-	ldr	r1, [r1, #2448]
19494
+	beq	.L3150
19495
+	mov	r3, #1
19496
+	str	r3, [r5, #-372]
19497
+.L3111:
19498
+	ldr	r1, .L3154
19499
+	mvn	r0, #0
19500
+	movw	r3, #3444
19501
+	strh	r6, [r4, #2]	@ movhi
19502
+	strb	r2, [r4, #6]
19503
+	strh	r0, [r1, r3]	@ movhi
19504
+	mov	r1, r6
19505
+	mov	r0, r4
19506
+	bl	ftl_sb_update_avl_pages
19507
+	b	.L3106
19508
+.L3117:
19509
+	ldr	r0, [r3, #8]
19510
+	ldr	r1, [r10, #2452]
18983
19511
 	cmp	r0, r1
18984
-	bls	.L3229
18985
-	b	.L3197
18986
-.L3228:
19512
+	bhi	.L3120
19513
+	ldrb	r2, [r10, #36]	@ zero_extendqisi2
19514
+	cmp	r2, #0
19515
+	bne	.L3123
19516
+.L3124:
19517
+	ldr	r2, [r3, #8]
19518
+	add	fp, fp, #1
19519
+	ldr	r1, [sp, #4]
19520
+	ldr	r0, [r3, #12]
19521
+	bl	FtlGcUpdatePage
19522
+	b	.L3115
19523
+.L3150:
18987
19524
 	ldrh	r3, [r4]
18988
-	ldr	r2, .L3235+8
18989
-	mov	r3, r3, asl #1
18990
-	ldr	r2, [r2, #-3544]
18991
-	b	.L3232
18992
-.L3229:
18993
-	ldr	r3, .L3235+4
18994
-	ldrb	r3, [r3]	@ zero_extendqisi2
18995
-	cmp	r3, #0
18996
-	beq	.L3201
18997
-	add	r1, sp, #24
18998
-	mov	r2, r7
18999
-	bl	log2phys
19000
-	ldr	r3, [r10, #12]
19001
-	ldr	r2, [sp, #24]
19002
-	rsb	r1, r3, r2
19003
-	cmn	r2, #1
19004
-	clz	r1, r1
19005
-	mov	r1, r1, lsr #5
19006
-	moveq	r1, #0
19007
-	cmp	r1, #0
19008
-	beq	.L3201
19009
-	str	r3, [sp, #32]
19010
-	mov	r2, r7
19011
-	ldr	r3, [r6, #-504]
19012
-	add	r0, sp, #28
19013
-	mov	r1, #1
19014
-	str	r3, [sp, #36]
19015
-	ldr	r3, [r6, #-496]
19016
-	str	r3, [sp, #40]
19017
-	bl	FlashReadPages
19018
-	ldr	r3, .L3235+20
19019
-	ldr	r2, [r6, #-536]
19020
-	ldrh	r3, [r3]
19021
-	add	r9, r2, r9
19022
-	mov	r3, r3, asl #7
19023
-	ldr	r2, [sp, #36]
19024
-	b	.L3203
19025
-.L3204:
19026
-	add	r7, r7, #1
19027
-.L3203:
19028
-	cmp	r7, r3
19029
-	beq	.L3201
19030
-	ldr	r1, [r9, #8]
19031
-	ldr	r0, [r1, r7, asl #2]
19032
-	ldr	r1, [r2, r7, asl #2]
19033
-	cmp	r0, r1
19034
-	beq	.L3204
19035
-	ldrh	r1, [r4]
19036
-	ldr	r2, [sp, #32]
19037
-	ldr	r0, .L3235+24
19038
-	bl	printk
19039
-	ldrh	r3, [r4]
19040
-	ldr	r2, [r6, #-3544]
19041
-	mov	r1, #0
19042
-	mov	r3, r3, asl #1
19043
-.L3232:
19525
+	ldr	r2, [r5, #-3540]
19526
+	lsl	r3, r3, #1
19044
19527
 	strh	r1, [r2, r3]	@ movhi
19045
19528
 	ldrh	r0, [r4]
19046
19529
 	bl	INSERT_FREE_LIST
19047
-	ldr	r2, .L3235+28
19530
+	ldr	r2, .L3154+24
19048
19531
 	mvn	r3, #0
19049
19532
 	strh	r3, [r4]	@ movhi
19050
19533
 	strh	r3, [r2]	@ movhi
19051
-	b	.L3231
19052
-.L3201:
19053
-	ldr	r0, [r10, #12]
19054
-	add	fp, fp, #1
19055
-	ldr	r1, [sp, #4]
19056
-	ldr	r2, [r10, #8]
19057
-	bl	FtlGcUpdatePage
19058
-	b	.L3192
19059
-.L3193:
19060
-	ldr	r2, [sp, #4]
19061
-	ldr	r0, .L3235+32
19534
+.L3153:
19535
+	bl	FtlGcPageVarInit
19536
+	mov	r6, #0
19537
+	b	.L3110
19538
+.L3123:
19539
+	mov	r2, r8
19540
+	add	r1, sp, #24
19541
+	str	r3, [sp, #16]
19542
+	bl	log2phys
19543
+	ldr	r3, [sp, #16]
19544
+	ldr	r1, [sp, #24]
19545
+	ldr	r2, [r3, #12]
19546
+	cmn	r1, #1
19547
+	sub	r0, r2, r1
19548
+	clz	r0, r0
19549
+	lsr	r0, r0, #5
19550
+	moveq	r0, #0
19551
+	cmp	r0, #0
19552
+	beq	.L3124
19553
+	str	r2, [sp, #32]
19554
+	mov	r1, #1
19555
+	ldr	r2, [r5, #-504]
19556
+	add	r0, sp, #28
19557
+	str	r2, [sp, #36]
19558
+	ldr	r2, [r5, #-496]
19559
+	str	r2, [sp, #40]
19560
+	mov	r2, r8
19561
+	bl	FlashReadPages
19562
+	ldr	r2, .L3154+28
19563
+	ldr	r1, [r5, #-536]
19564
+	ldr	r3, [sp, #16]
19565
+	ldrh	r2, [r2]
19566
+	add	r9, r1, r9
19567
+	ldr	r1, [sp, #36]
19568
+	lsl	r2, r2, #7
19569
+.L3125:
19570
+	cmp	r8, r2
19571
+	beq	.L3124
19572
+	ldr	r0, [r9, #8]
19573
+	ldr	ip, [r0, r8, lsl #2]
19574
+	ldr	r0, [r1, r8, lsl #2]
19575
+	cmp	ip, r0
19576
+	beq	.L3126
19577
+	ldr	r2, [sp, #32]
19062
19578
 	ldrh	r1, [r4]
19063
-	str	r3, [sp, #20]
19064
-	str	ip, [sp, #16]
19579
+	ldr	r0, .L3154+32
19065
19580
 	bl	printk
19066
-	ldrh	r5, [r4]
19067
-	ldr	ip, [sp, #16]
19068
-	ldr	r3, [sp, #20]
19069
-	ldr	r2, [ip, #2244]
19581
+	ldrh	r3, [r4]
19582
+	mov	r1, #0
19583
+	ldr	r2, [r5, #-3540]
19584
+	lsl	r3, r3, #1
19585
+	strh	r1, [r2, r3]	@ movhi
19586
+	ldrh	r0, [r4]
19587
+	bl	INSERT_FREE_LIST
19588
+	ldr	r2, .L3154+36
19589
+	mvn	r3, #0
19590
+	strh	r3, [r4]	@ movhi
19591
+	strh	r3, [r2, #-4]	@ movhi
19592
+	b	.L3153
19593
+.L3126:
19594
+	add	r8, r8, #1
19595
+	b	.L3125
19596
+.L3116:
19597
+	ldr	r2, [sp, #4]
19598
+	ldrh	r1, [r4]
19599
+	ldr	r0, .L3154+40
19600
+	bl	printk
19601
+	ldr	r3, [r10, #2248]
19602
+	cmp	r3, #0
19603
+	ldrh	r3, [r4]
19604
+	bne	.L3129
19605
+	ldrb	r2, [r10, #152]	@ zero_extendqisi2
19070
19606
 	cmp	r2, #0
19071
-	bne	.L3207
19072
-	ldrb	r2, [ip, #144]	@ zero_extendqisi2
19073
-	cmp	r2, #0
19074
-	beq	.L3208
19075
-.L3207:
19076
-	ldr	r1, [r3, #-3608]
19077
-	mov	r2, r5, asl #1
19607
+	beq	.L3130
19608
+.L3129:
19609
+	ldr	r1, [r5, #-3604]
19610
+	lsl	r2, r3, #1
19078
19611
 	ldrh	r2, [r1, r2]
19079
19612
 	cmp	r2, #159
19080
-	bls	.L3209
19081
-.L3208:
19082
-	ldr	r2, [r3, #-536]
19613
+	bls	.L3131
19614
+.L3130:
19615
+	ldr	r2, [r5, #-536]
19083
19616
 	ldr	r2, [r2, r9]
19084
19617
 	cmn	r2, #1
19085
-	bne	.L3210
19086
-.L3209:
19087
-	ldr	r3, [r3, #-536]
19088
-	add	r9, r3, r9
19089
-	ldr	r3, [r9, #4]
19090
-	str	r3, [sp, #8]
19091
-.L3210:
19092
-	ldr	r3, .L3235+8
19093
-	mov	r5, r5, asl #1
19094
-	mov	r2, #0
19095
-	ldr	r3, [r3, #-3544]
19096
-	strh	r2, [r3, r5]	@ movhi
19618
+	bne	.L3132
19619
+.L3131:
19620
+	ldr	r2, [r5, #-536]
19621
+	add	r9, r2, r9
19622
+	ldr	r2, [r9, #4]
19623
+	str	r2, [sp, #8]
19624
+.L3132:
19625
+	ldr	r2, [r5, #-3540]
19626
+	lsl	r3, r3, #1
19627
+	mov	r1, #0
19628
+	strh	r1, [r2, r3]	@ movhi
19097
19629
 	ldrh	r0, [r4]
19098
19630
 	bl	INSERT_FREE_LIST
19099
19631
 	mvn	r3, #0
19100
19632
 	strh	r3, [r4]	@ movhi
19101
-.L3231:
19102
-	bl	FtlGcPageVarInit
19103
-	mov	r5, #0
19104
-	b	.L3186
19105
-.L3234:
19106
-	ldr	r3, [sp]
19107
-	add	r5, r5, #1
19108
-	ldr	r2, [sp, #12]
19109
-	add	r3, r3, #1
19110
-	uxth	r5, r5
19111
-	cmp	r3, r2
19112
-	str	r3, [sp]
19113
-	ldr	r2, .L3235+36
19114
-	bcs	.L3212
19115
-.L3214:
19116
-	ldrh	r3, [r2]
19117
-	cmp	r3, r5
19118
-	bhi	.L3213
19119
-	mov	r2, #0
19120
-	b	.L3187
19121
-.L3212:
19122
-	ldr	r1, .L3235+40
19633
+	b	.L3153
19634
+.L3134:
19635
+	ldr	r1, .L3154+44
19123
19636
 	movw	r0, #65535
19124
19637
 	ldrh	r3, [r1]
19125
19638
 	cmp	r3, r0
19126
-	beq	.L3214
19639
+	beq	.L3136
19127
19640
 	ldr	r0, [sp]
19128
19641
 	add	r3, r3, r0
19129
19642
 	strh	r3, [r1]	@ movhi
19130
19643
 	ldrh	r3, [r2]
19131
-	cmp	r3, r5
19132
-	bls	.L3214
19133
-	b	.L3215
19134
-.L3187:
19135
-	ldr	r1, .L3235
19136
-	movw	r3, #3448
19137
-	mvn	r0, #0
19138
-	strh	r5, [r4, #2]	@ movhi
19139
-	strb	r2, [r4, #6]
19140
-	strh	r0, [r1, r3]	@ movhi
19141
-	mov	r0, r4
19142
-	mov	r1, r5
19143
-	bl	ftl_sb_update_avl_pages
19144
-.L3215:
19644
+	cmp	r3, r6
19645
+	bls	.L3136
19646
+.L3106:
19145
19647
 	ldr	r0, [sp, #8]
19146
19648
 	add	sp, sp, #68
19147
19649
 	@ sp needed
19148
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
19149
-.L3236:
19650
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
19651
+.L3155:
19150
19652
 	.align	2
19151
-.L3235:
19653
+.L3154:
19152
19654
 	.word	.LANCHOR1
19153
19655
 	.word	.LANCHOR0
19154
19656
 	.word	.LANCHOR2
19155
-	.word	.LANCHOR0+2320
19156
-	.word	.LANCHOR0+2398
19157
-	.word	.LANCHOR0+2394
19158
-	.word	.LC153
19657
+	.word	.LANCHOR0+2324
19658
+	.word	.LANCHOR0+2400
19659
+	.word	.LANCHOR0+2390
19159
19660
 	.word	.LANCHOR2-3284
19661
+	.word	.LANCHOR0+2396
19662
+	.word	.LC153
19663
+	.word	.LANCHOR2-3280
19160
19664
 	.word	.LC154
19161
-	.word	.LANCHOR0+2388
19162
-	.word	.LANCHOR1+3448
19665
+	.word	.LANCHOR1+3444
19163
19666
 	.fnend
19164
19667
 	.size	FtlGcScanTempBlk, .-FtlGcScanTempBlk
19165
19668
 	.align	2
19166
19669
 	.global	FtlReadRefresh
19670
+	.syntax unified
19671
+	.arm
19672
+	.fpu softvfp
19167
19673
 	.type	FtlReadRefresh, %function
19168
19674
 FtlReadRefresh:
19169
19675
 	.fnstart
19170
19676
 	@ args = 0, pretend = 0, frame = 40
19171
19677
 	@ frame_needed = 0, uses_anonymous_args = 0
19172
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
19678
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
19173
19679
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
19174
19680
 	.pad #40
19175
19681
 	sub	sp, sp, #40
19176
-	ldr	r5, .L3254
19177
-	ldr	r4, .L3254+4
19178
-	ldr	r9, [r5, #-3152]
19682
+	ldr	r5, .L3173
19683
+	ldr	r9, [r5, #-3156]
19179
19684
 	mov	r6, r5
19180
19685
 	cmp	r9, #0
19181
-	beq	.L3238
19182
-	ldr	r2, [r5, #-3148]
19183
-	ldr	r3, [r4, #2448]
19184
-	cmp	r2, r3
19185
-	bcs	.L3239
19686
+	beq	.L3157
19687
+	ldr	r3, .L3173+4
19688
+	ldr	r1, [r5, #-3152]
19689
+	ldr	r2, [r3, #2452]
19690
+	mov	r4, r3
19691
+	cmp	r1, r2
19692
+	bcs	.L3158
19186
19693
 	mov	r5, #2048
19187
-	mov	r7, r6
19188
-.L3244:
19189
-	ldr	r0, [r6, #-3148]
19190
-	ldr	r3, [r4, #2448]
19694
+.L3163:
19695
+	ldr	r0, [r6, #-3152]
19696
+	ldr	r3, [r4, #2452]
19191
19697
 	cmp	r0, r3
19192
-	bcs	.L3243
19698
+	bcc	.L3159
19699
+.L3162:
19700
+	mvn	r0, #0
19701
+.L3156:
19702
+	add	sp, sp, #40
19703
+	@ sp needed
19704
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
19705
+.L3159:
19193
19706
 	mov	r2, #0
19194
19707
 	mov	r1, sp
19195
19708
 	bl	log2phys
19196
-	ldr	r3, [r7, #-3148]
19197
-	add	r3, r3, #1
19198
-	str	r3, [r7, #-3148]
19199
19709
 	ldr	r2, [sp]
19710
+	ldr	r3, [r6, #-3152]
19200
19711
 	cmn	r2, #1
19201
-	beq	.L3242
19202
-	add	r0, sp, #40
19712
+	add	r3, r3, #1
19713
+	str	r3, [r6, #-3152]
19714
+	beq	.L3161
19203
19715
 	str	r2, [sp, #8]
19204
-	mov	r1, #1
19716
+	add	r0, sp, #40
19205
19717
 	mov	r2, #0
19718
+	mov	r1, #1
19206
19719
 	str	r2, [r0, #-36]!
19207
19720
 	str	r3, [sp, #20]
19208
19721
 	str	r2, [sp, #12]
..
..
@@ -19210,357 +19723,352 @@
19210
19723
 	bl	FlashReadPages
19211
19724
 	ldr	r3, [sp, #4]
19212
19725
 	cmp	r3, #256
19213
-	bne	.L3243
19726
+	bne	.L3162
19214
19727
 	ldr	r0, [sp]
19215
19728
 	ubfx	r0, r0, #10, #16
19216
19729
 	bl	P2V_block_in_plane
19217
19730
 	bl	FtlGcRefreshBlock
19218
-.L3243:
19219
-	mvn	r0, #0
19220
-	b	.L3246
19221
-.L3242:
19731
+	b	.L3162
19732
+.L3161:
19222
19733
 	subs	r5, r5, #1
19223
-	bne	.L3244
19224
-	b	.L3243
19225
-.L3239:
19734
+	bne	.L3163
19735
+	b	.L3162
19736
+.L3158:
19226
19737
 	ldr	r3, [r5, #-3364]
19227
19738
 	mov	r0, #0
19739
+	str	r0, [r5, #-3156]
19228
19740
 	str	r0, [r5, #-3152]
19229
-	str	r0, [r5, #-3148]
19230
-	str	r3, [r5, #-3156]
19231
-	b	.L3246
19232
-.L3238:
19741
+	str	r3, [r5, #-3160]
19742
+	b	.L3156
19743
+.L3157:
19233
19744
 	ldr	r1, [r5, #-3312]
19234
-	sub	r10, r5, #3600
19235
-	ldr	r8, [r5, #-3364]
19236
-	ldr	r3, [r4, #2448]
19237
19745
 	movw	r4, #10000
19238
-	ldr	r7, [r5, #-3156]
19746
+	ldr	r8, [r5, #-3364]
19747
+	sub	r10, r5, #3584
19748
+	ldr	r7, [r5, #-3160]
19239
19749
 	cmp	r1, r4
19240
-	add	r2, r8, #1048576
19750
+	add	r3, r8, #1048576
19241
19751
 	movhi	r4, #31
19242
19752
 	movls	r4, #63
19243
-	cmp	r7, r2
19244
-	bhi	.L3248
19245
-	mov	r1, r1, lsr #10
19753
+	cmp	r7, r3
19754
+	bhi	.L3167
19755
+	ldr	r3, .L3173+4
19756
+	lsr	r1, r1, #10
19246
19757
 	mov	r0, #1000
19247
-	mul	r0, r0, r3
19248
19758
 	add	r1, r1, #1
19759
+	ldr	r3, [r3, #2452]
19760
+	mul	r0, r0, r3
19249
19761
 	bl	__aeabi_uidiv
19250
19762
 	add	r0, r0, r7
19251
-	cmp	r0, r8
19252
-	bcc	.L3248
19253
-	ldrh	r3, [r10, #28]
19763
+	cmp	r8, r0
19764
+	bhi	.L3167
19765
+	ldrh	r3, [r10, #16]
19254
19766
 	ands	r0, r4, r3
19255
19767
 	movne	r0, r9
19256
-	bne	.L3246
19257
-	ldr	r2, [r5, #-3132]
19258
-	cmp	r2, r3
19259
-	beq	.L3246
19260
-.L3248:
19261
-	ldrh	r3, [r10, #28]
19768
+	bne	.L3156
19769
+	ldr	r2, [r5, #-3136]
19770
+	cmp	r3, r2
19771
+	beq	.L3156
19772
+.L3167:
19773
+	ldrh	r3, [r10, #16]
19262
19774
 	mov	r0, #0
19263
-	str	r8, [r6, #-3156]
19264
-	str	r0, [r6, #-3148]
19265
-	str	r3, [r6, #-3132]
19775
+	str	r0, [r6, #-3152]
19776
+	str	r8, [r6, #-3160]
19777
+	str	r3, [r6, #-3136]
19266
19778
 	mov	r3, #1
19267
-	str	r3, [r6, #-3152]
19268
-.L3246:
19269
-	add	sp, sp, #40
19270
-	@ sp needed
19271
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
19272
-.L3255:
19779
+	str	r3, [r6, #-3156]
19780
+	b	.L3156
19781
+.L3174:
19273
19782
 	.align	2
19274
-.L3254:
19783
+.L3173:
19275
19784
 	.word	.LANCHOR2
19276
19785
 	.word	.LANCHOR0
19277
19786
 	.fnend
19278
19787
 	.size	FtlReadRefresh, .-FtlReadRefresh
19279
19788
 	.align	2
19280
19789
 	.global	FtlGcFreeTempBlock
19790
+	.syntax unified
19791
+	.arm
19792
+	.fpu softvfp
19281
19793
 	.type	FtlGcFreeTempBlock, %function
19282
19794
 FtlGcFreeTempBlock:
19283
19795
 	.fnstart
19284
-	@ args = 0, pretend = 0, frame = 24
19796
+	@ args = 0, pretend = 0, frame = 16
19285
19797
 	@ frame_needed = 0, uses_anonymous_args = 0
19286
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
19798
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
19287
19799
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
19288
-	movw	r3, #2388
19289
-	ldr	r4, .L3295
19290
-	.pad #28
19291
-	sub	sp, sp, #28
19292
-	ldr	r6, .L3295+4
19293
-	ldr	ip, [r4, #-3616]
19800
+	movw	r3, #2390
19801
+	ldr	r4, .L3213
19802
+	.pad #20
19803
+	sub	sp, sp, #20
19804
+	ldr	r6, .L3213+4
19805
+	ldr	ip, [r4, #-3612]
19294
19806
 	ldrh	r1, [r6, r3]
19295
19807
 	cmp	ip, #0
19296
-	bne	.L3293
19297
-	sub	r7, r4, #3424
19808
+	beq	.L3176
19809
+.L3212:
19810
+	mov	r0, #0
19811
+.L3175:
19812
+	add	sp, sp, #20
19813
+	@ sp needed
19814
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
19815
+.L3176:
19816
+	sub	r5, r4, #3424
19298
19817
 	movw	lr, #65535
19299
-	ldrh	r5, [r7, #-4]
19300
-	cmp	r5, lr
19301
-	bne	.L3259
19302
-.L3268:
19303
-	ldrh	r2, [r7, #-4]
19818
+	ldrh	r7, [r5]
19819
+	cmp	r7, lr
19820
+	bne	.L3178
19821
+.L3187:
19822
+	ldrh	r2, [r5]
19304
19823
 	movw	r3, #65535
19305
-	ldr	r5, .L3295
19306
-	mov	r8, #0
19824
+	mov	r7, #0
19825
+	str	r7, [r4, #-372]
19307
19826
 	cmp	r2, r3
19308
-	str	r8, [r4, #-372]
19309
-	sub	r9, r5, #3424
19310
-	beq	.L3293
19827
+	beq	.L3212
19311
19828
 	bl	FtlCacheWriteBack
19312
-	movw	r2, #2388
19313
-	ldrb	r0, [r5, #-3421]	@ zero_extendqisi2
19314
-	ldrh	r2, [r6, r2]
19315
-	ldrh	r3, [r9, #-4]
19316
-	ldr	r1, [r5, #-3544]
19317
-	smulbb	r2, r0, r2
19318
-	mov	r3, r3, asl #1
19829
+	movw	r0, #2390
19830
+	ldrb	r2, [r4, #-3417]	@ zero_extendqisi2
19831
+	ldrh	r0, [r6, r0]
19832
+	mov	fp, #12
19833
+	ldrh	r3, [r5]
19834
+	ldr	r1, [r4, #-3540]
19835
+	ldr	r8, .L3213+8
19836
+	smulbb	r2, r2, r0
19837
+	lsl	r3, r3, #1
19319
19838
 	strh	r2, [r1, r3]	@ movhi
19320
-	sub	r2, r5, #2656
19321
-	ldr	r3, [r5, #-3344]
19322
-	sub	fp, r2, #12
19323
-	ldrh	ip, [r2, #-12]
19324
-	sub	r10, r2, #772
19325
-	add	r3, ip, r3
19326
-	str	r3, [r5, #-3344]
19327
-	stmib	sp, {r2, r5}
19328
-	b	.L3269
19329
-.L3259:
19839
+	ldr	r2, [r4, #-3344]
19840
+	ldrh	r3, [r8, #-12]
19841
+	add	r3, r3, r2
19842
+	str	r3, [r4, #-3344]
19843
+.L3188:
19844
+	ldrh	r2, [r8, #-12]
19845
+	uxth	r3, r7
19846
+	cmp	r2, r3
19847
+	bhi	.L3192
19848
+	movw	r0, #65535
19849
+	bl	decrement_vpc_count
19850
+	ldrb	r3, [r6, #152]	@ zero_extendqisi2
19851
+	cmp	r3, #0
19852
+	beq	.L3193
19853
+	ldrh	r1, [r5]
19854
+	ldr	r0, .L3213+12
19855
+	bl	printk
19856
+.L3193:
19857
+	ldrh	r0, [r5]
19858
+	ldr	r2, [r4, #-3540]
19859
+	lsl	r3, r0, #1
19860
+	ldrh	r3, [r2, r3]
19861
+	cmp	r3, #0
19862
+	beq	.L3194
19863
+	bl	INSERT_DATA_LIST
19864
+.L3195:
19865
+	ldr	r7, .L3213+16
19866
+	mvn	r9, #0
19867
+	strh	r9, [r5]	@ movhi
19868
+	mov	r5, #0
19869
+	strh	r5, [r8, #-12]	@ movhi
19870
+	strh	r5, [r7, #-4]	@ movhi
19871
+	bl	l2p_flush
19872
+	bl	FtlVpcTblFlush
19873
+	sub	r3, r7, #608
19874
+	sub	r2, r7, #848
19875
+	strh	r9, [r3, #-4]	@ movhi
19876
+	ldr	r3, [r6, #2248]
19877
+	ldrh	r2, [r2, #-4]
19878
+	cmp	r3, r5
19879
+	sub	r3, r7, #624
19880
+	ldrh	r3, [r3, #-8]
19881
+	beq	.L3196
19882
+	ldr	r1, [r4, #-3308]
19883
+	cmp	r1, #39
19884
+	bhi	.L3196
19885
+	cmp	r2, r3
19886
+	lslcc	r3, r3, #1
19887
+	strhcc	r3, [r7, #-48]	@ movhi
19888
+	b	.L3212
19889
+.L3178:
19330
19890
 	cmp	r0, #0
19331
-	beq	.L3262
19332
-	ldr	r2, .L3295+8
19333
-	movw	r3, #3448
19891
+	beq	.L3181
19892
+	ldr	r2, .L3213+20
19893
+	movw	r3, #3444
19334
19894
 	ldrh	r0, [r2, r3]
19335
19895
 	cmp	r0, lr
19336
-	beq	.L3263
19337
-.L3264:
19896
+	beq	.L3182
19897
+.L3183:
19338
19898
 	mov	r1, #2
19339
-	b	.L3262
19340
-.L3263:
19341
-	strh	ip, [r2, r3]	@ movhi
19342
-	sub	r3, r4, #3520
19343
-	ldrh	r3, [r3, #-8]
19344
-	cmp	r3, #17
19345
-	bhi	.L3264
19346
-.L3262:
19347
-	ldr	r0, .L3295+12
19899
+.L3181:
19900
+	ldr	r0, .L3213+24
19348
19901
 	bl	FtlGcScanTempBlk
19349
19902
 	cmn	r0, #1
19350
-	str	r0, [sp, #20]
19351
-	beq	.L3265
19352
-	ldr	r3, .L3295
19353
-	mov	r5, r5, asl #1
19354
-	ldr	r2, [r3, #-3608]
19355
-	ldrh	r3, [r2, r5]
19903
+	str	r0, [sp, #12]
19904
+	beq	.L3184
19905
+	ldr	r2, [r4, #-3604]
19906
+	lsl	r7, r7, #1
19907
+	ldrh	r3, [r2, r7]
19356
19908
 	cmp	r3, #4
19357
-	bls	.L3266
19909
+	bls	.L3185
19358
19910
 	sub	r3, r3, #5
19359
19911
 	mov	r0, #1
19360
-	strh	r3, [r2, r5]	@ movhi
19912
+	strh	r3, [r2, r7]	@ movhi
19361
19913
 	bl	FtlEctTblFlush
19362
-.L3266:
19914
+.L3185:
19363
19915
 	ldr	r3, [r4, #-372]
19364
-	ldr	r2, .L3295
19365
19916
 	cmp	r3, #0
19366
-	bne	.L3267
19367
-	ldr	r0, [sp, #20]
19368
-	ldr	r3, [r2, #-3136]
19369
-	ubfx	r0, r0, #10, #16
19917
+	bne	.L3186
19918
+	ldr	r3, [r4, #-3140]
19919
+	ldr	r0, [sp, #12]
19370
19920
 	add	r3, r3, #1
19371
-	str	r3, [r2, #-3136]
19921
+	ubfx	r0, r0, #10, #16
19922
+	str	r3, [r4, #-3140]
19372
19923
 	bl	FtlBbmMapBadBlock
19373
19924
 	bl	FtlBbmTblFlush
19374
-.L3267:
19925
+.L3186:
19375
19926
 	mov	r3, #0
19376
19927
 	str	r3, [r4, #-372]
19377
-	b	.L3279
19378
-.L3265:
19379
-	ldr	r2, .L3295+8
19380
-	movw	r3, #3448
19928
+.L3198:
19929
+	mov	r0, #1
19930
+	b	.L3175
19931
+.L3182:
19932
+	strh	ip, [r2, r3]	@ movhi
19933
+	sub	r3, r4, #3520
19934
+	ldrh	r3, [r3, #-4]
19935
+	cmp	r3, #17
19936
+	bhi	.L3183
19937
+	b	.L3181
19938
+.L3184:
19939
+	ldr	r2, .L3213+20
19940
+	movw	r3, #3444
19381
19941
 	ldrh	r2, [r2, r3]
19382
19942
 	movw	r3, #65535
19383
19943
 	cmp	r2, r3
19384
-	bne	.L3279
19385
-	b	.L3268
19386
-.L3272:
19387
-	ldr	r3, [r5, #4]
19388
-	cmp	r0, r3
19389
-	bne	.L3291
19390
-.L3271:
19391
-	add	r8, r8, #1
19392
-.L3269:
19393
-	ldrh	r2, [fp]
19394
-	uxth	r3, r8
19395
-	cmp	r2, r3
19396
-	bls	.L3294
19397
-	mov	r9, #12
19398
-	ldr	r2, [r6, #2448]
19399
-	mul	r9, r9, r3
19400
-	ldr	r3, [sp, #8]
19401
-	ldr	ip, [r3, #-2672]
19402
-	add	r5, ip, r9
19403
-	ldr	r0, [r5, #8]
19944
+	bne	.L3198
19945
+	b	.L3187
19946
+.L3192:
19947
+	uxth	r10, r7
19948
+	ldr	r3, [r4, #-2672]
19949
+	ldr	r2, [r6, #2452]
19950
+	mul	r10, fp, r10
19951
+	add	r9, r3, r10
19952
+	ldr	r0, [r9, #8]
19404
19953
 	cmp	r0, r2
19405
-	bcs	.L3291
19954
+	bcc	.L3189
19955
+.L3210:
19956
+	ldrh	r0, [r5]
19957
+	b	.L3211
19958
+.L3189:
19406
19959
 	mov	r2, #0
19407
-	add	r1, sp, #20
19408
-	str	ip, [sp, #12]
19960
+	add	r1, sp, #12
19961
+	str	r3, [sp, #4]
19409
19962
 	bl	log2phys
19410
-	ldr	ip, [sp, #12]
19411
-	ldr	r0, [sp, #20]
19412
-	ldr	r2, [ip, r9]
19963
+	ldr	r3, [sp, #4]
19964
+	ldr	r2, [sp, #12]
19965
+	ldr	r0, [r3, r10]
19413
19966
 	cmp	r0, r2
19414
-	bne	.L3272
19967
+	bne	.L3191
19415
19968
 	ubfx	r0, r0, #10, #16
19416
19969
 	bl	P2V_block_in_plane
19417
-	add	r1, r5, #4
19418
19970
 	mov	r2, #1
19419
-	mov	r9, r0
19420
-	ldr	r0, [r5, #8]
19971
+	mov	r10, r0
19972
+	add	r1, r9, #4
19973
+	ldr	r0, [r9, #8]
19421
19974
 	bl	log2phys
19422
-	mov	r0, r9
19423
-	b	.L3292
19424
-.L3291:
19425
-	ldrh	r0, [r10]
19426
-.L3292:
19975
+	mov	r0, r10
19976
+.L3211:
19427
19977
 	bl	decrement_vpc_count
19428
-	b	.L3271
19429
-.L3294:
19430
-	movw	r0, #65535
19431
-	bl	decrement_vpc_count
19432
-	ldrb	r3, [r6, #144]	@ zero_extendqisi2
19433
-	cmp	r3, #0
19434
-	beq	.L3274
19435
-	ldr	r0, .L3295+16
19436
-	ldrh	r1, [r7, #-4]
19437
-	bl	printk
19438
-.L3274:
19439
-	ldrh	r0, [r7, #-4]
19440
-	ldr	r2, [r4, #-3544]
19441
-	mov	r3, r0, asl #1
19442
-	ldrh	r3, [r2, r3]
19443
-	cmp	r3, #0
19444
-	beq	.L3275
19445
-	bl	INSERT_DATA_LIST
19446
-	b	.L3276
19447
-.L3275:
19448
-	bl	INSERT_FREE_LIST
19449
-.L3276:
19450
-	ldr	r3, [sp, #4]
19451
-	mvn	r5, #0
19452
-	ldr	r4, .L3295
19453
-	strh	r5, [r7, #-4]	@ movhi
19454
-	mov	r7, #0
19455
-	strh	r7, [r3, #-12]	@ movhi
19456
-	sub	r3, r4, #2672
19457
-	strh	r7, [r3, #-4]	@ movhi
19458
-	bl	l2p_flush
19459
-	bl	FtlVpcTblFlush
19460
-	sub	r3, r4, #3280
19461
-	sub	r2, r4, #3520
19462
-	strh	r5, [r3, #-4]	@ movhi
19463
-	ldr	r3, [r6, #2244]
19464
-	ldrh	r2, [r2, #-8]
19465
-	cmp	r3, r7
19466
-	sub	r3, r4, #3296
19467
-	ldrh	r3, [r3, #-8]
19468
-	beq	.L3277
19469
-	ldr	r1, [r4, #-3308]
19470
-	cmp	r1, #39
19471
-	bhi	.L3277
19978
+	b	.L3190
19979
+.L3191:
19980
+	ldr	r3, [r9, #4]
19472
19981
 	cmp	r2, r3
19473
-	subcc	r4, r4, #2720
19474
-	movcc	r3, r3, asl #1
19475
-	strcch	r3, [r4]	@ movhi
19476
-	b	.L3293
19477
-.L3277:
19478
-	add	r1, r3, r3, asl #1
19982
+	bne	.L3210
19983
+.L3190:
19984
+	add	r7, r7, #1
19985
+	b	.L3188
19986
+.L3194:
19987
+	bl	INSERT_FREE_LIST
19988
+	b	.L3195
19989
+.L3196:
19990
+	add	r1, r3, r3, lsl #1
19479
19991
 	cmp	r2, r1, asr #2
19480
-	ble	.L3293
19481
-	ldrb	r0, [r6, #144]	@ zero_extendqisi2
19482
-	ldr	r2, .L3295+20
19992
+	ble	.L3212
19993
+	ldrb	r0, [r6, #152]	@ zero_extendqisi2
19994
+	ldr	r2, .L3213+28
19483
19995
 	cmp	r0, #0
19484
19996
 	moveq	r3, #20
19485
-	streqh	r3, [r2]	@ movhi
19486
-	beq	.L3258
19997
+	strheq	r3, [r2]	@ movhi
19998
+	beq	.L3175
19487
19999
 	sub	r3, r3, #2
19488
20000
 	strh	r3, [r2]	@ movhi
19489
-.L3293:
19490
-	mov	r0, #0
19491
-	b	.L3258
19492
-.L3279:
19493
-	mov	r0, #1
19494
-.L3258:
19495
-	add	sp, sp, #28
19496
-	@ sp needed
19497
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
19498
-.L3296:
20001
+	b	.L3212
20002
+.L3214:
19499
20003
 	.align	2
19500
-.L3295:
20004
+.L3213:
19501
20005
 	.word	.LANCHOR2
19502
20006
 	.word	.LANCHOR0
19503
-	.word	.LANCHOR1
19504
-	.word	.LANCHOR2-3428
20007
+	.word	.LANCHOR2-2656
19505
20008
 	.word	.LC155
20009
+	.word	.LANCHOR2-2672
20010
+	.word	.LANCHOR1
20011
+	.word	.LANCHOR2-3424
19506
20012
 	.word	.LANCHOR2-2720
19507
20013
 	.fnend
19508
20014
 	.size	FtlGcFreeTempBlock, .-FtlGcFreeTempBlock
19509
20015
 	.align	2
19510
20016
 	.global	FtlGcPageRecovery
20017
+	.syntax unified
20018
+	.arm
20019
+	.fpu softvfp
19511
20020
 	.type	FtlGcPageRecovery, %function
19512
20021
 FtlGcPageRecovery:
19513
20022
 	.fnstart
19514
20023
 	@ args = 0, pretend = 0, frame = 0
19515
20024
 	@ frame_needed = 0, uses_anonymous_args = 0
19516
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
19517
-	.save {r3, r4, r5, r6, r7, lr}
19518
-	movw	r5, #2388
19519
-	ldr	r7, .L3300
19520
-	ldr	r6, .L3300+4
19521
-	ldr	r4, .L3300+8
20025
+	push	{r4, r5, r6, r7, r8, lr}
20026
+	.save {r4, r5, r6, r7, r8, lr}
20027
+	movw	r5, #2390
20028
+	ldr	r4, .L3218
20029
+	ldr	r6, .L3218+4
20030
+	sub	r7, r4, #3424
19522
20031
 	mov	r0, r7
19523
20032
 	ldrh	r1, [r6, r5]
19524
20033
 	bl	FtlGcScanTempBlk
19525
20034
 	ldrh	r2, [r7, #2]
19526
20035
 	ldrh	r3, [r6, r5]
19527
20036
 	cmp	r2, r3
19528
-	ldmccfd	sp!, {r3, r4, r5, r6, r7, pc}
20037
+	popcc	{r4, r5, r6, r7, r8, pc}
19529
20038
 	sub	r0, r4, #432
19530
20039
 	bl	FtlMapBlkWriteDumpData
19531
20040
 	mov	r0, #0
19532
20041
 	bl	FtlGcFreeTempBlock
19533
20042
 	mov	r3, #0
19534
20043
 	str	r3, [r4, #-372]
19535
-	ldmfd	sp!, {r3, r4, r5, r6, r7, pc}
19536
-.L3301:
20044
+	pop	{r4, r5, r6, r7, r8, pc}
20045
+.L3219:
19537
20046
 	.align	2
19538
-.L3300:
19539
-	.word	.LANCHOR2-3428
19540
-	.word	.LANCHOR0
20047
+.L3218:
19541
20048
 	.word	.LANCHOR2
20049
+	.word	.LANCHOR0
19542
20050
 	.fnend
19543
20051
 	.size	FtlGcPageRecovery, .-FtlGcPageRecovery
19544
20052
 	.align	2
19545
20053
 	.global	FtlPowerLostRecovery
20054
+	.syntax unified
20055
+	.arm
20056
+	.fpu softvfp
19546
20057
 	.type	FtlPowerLostRecovery, %function
19547
20058
 FtlPowerLostRecovery:
19548
20059
 	.fnstart
19549
20060
 	@ args = 0, pretend = 0, frame = 0
19550
20061
 	@ frame_needed = 0, uses_anonymous_args = 0
19551
-	stmfd	sp!, {r4, r5, r6, lr}
20062
+	push	{r4, r5, r6, lr}
19552
20063
 	.save {r4, r5, r6, lr}
19553
-	mov	r6, #0
19554
-	ldr	r4, .L3304
19555
-	ldr	r3, .L3304+4
19556
-	sub	r5, r4, #3520
20064
+	mov	r5, #0
20065
+	ldr	r4, .L3222
20066
+	sub	r6, r4, #3520
20067
+	str	r5, [r4, #1852]
20068
+	mov	r0, r6
19557
20069
 	sub	r4, r4, #3472
19558
-	sub	r5, r5, #4
19559
-	sub	r4, r4, #4
19560
-	str	r6, [r3, #1852]
19561
-	mov	r0, r5
19562
20070
 	bl	FtlRecoverySuperblock
19563
-	mov	r0, r5
20071
+	mov	r0, r6
19564
20072
 	bl	FtlSlcSuperblockCheck
19565
20073
 	mov	r0, r4
19566
20074
 	bl	FtlRecoverySuperblock
..
..
@@ -19569,51 +20077,54 @@
19569
20077
 	bl	FtlGcPageRecovery
19570
20078
 	movw	r0, #65535
19571
20079
 	bl	decrement_vpc_count
19572
-	mov	r0, r6
19573
-	ldmfd	sp!, {r4, r5, r6, pc}
19574
-.L3305:
20080
+	mov	r0, r5
20081
+	pop	{r4, r5, r6, pc}
20082
+.L3223:
19575
20083
 	.align	2
19576
-.L3304:
20084
+.L3222:
19577
20085
 	.word	.LANCHOR2
19578
-	.word	.LANCHOR4
19579
20086
 	.fnend
19580
20087
 	.size	FtlPowerLostRecovery, .-FtlPowerLostRecovery
19581
20088
 	.align	2
19582
20089
 	.global	FtlSysBlkInit
20090
+	.syntax unified
20091
+	.arm
20092
+	.fpu softvfp
19583
20093
 	.type	FtlSysBlkInit, %function
19584
20094
 FtlSysBlkInit:
19585
20095
 	.fnstart
19586
20096
 	@ args = 0, pretend = 0, frame = 0
19587
20097
 	@ frame_needed = 0, uses_anonymous_args = 0
19588
-	stmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
19589
-	.save {r3, r4, r5, r6, r7, r8, r9, lr}
19590
-	movw	r3, #1850
19591
-	ldr	r4, .L3324
20098
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
20099
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
19592
20100
 	mov	r2, #0
19593
-	ldr	r6, .L3324+4
19594
-	ldr	r5, .L3324+8
19595
-	strh	r2, [r4, r3]	@ movhi
20101
+	ldr	r5, .L3242
19596
20102
 	movw	r3, #1848
20103
+	ldr	r6, .L3242+4
20104
+	strh	r2, [r5, r3]	@ movhi
19597
20105
 	mvn	r2, #0
19598
-	strh	r2, [r4, r3]	@ movhi
19599
-	ldr	r3, [r6, #2324]
19600
-	uxth	r0, r3
20106
+	movw	r3, #1846
20107
+	strh	r2, [r5, r3]	@ movhi
20108
+	add	r3, r6, #2320
20109
+	add	r3, r3, #8
20110
+	ldrh	r0, [r3]
19601
20111
 	bl	FtlFreeSysBlkQueueInit
19602
20112
 	bl	FtlScanSysBlk
19603
20113
 	sub	r3, r5, #3296
19604
20114
 	ldrh	r2, [r3, #-4]
19605
20115
 	movw	r3, #65535
19606
20116
 	cmp	r2, r3
19607
-	bne	.L3307
19608
-.L3309:
19609
-	mvn	r8, #0
19610
-	b	.L3308
19611
-.L3307:
20117
+	bne	.L3225
20118
+.L3227:
20119
+	mvn	r7, #0
20120
+.L3224:
20121
+	mov	r0, r7
20122
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
20123
+.L3225:
19612
20124
 	bl	FtlLoadSysInfo
19613
-	subs	r8, r0, #0
19614
-	bne	.L3309
20125
+	subs	r7, r0, #0
20126
+	bne	.L3227
19615
20127
 	bl	FtlLoadMapInfo
19616
-	mov	r7, r4
19617
20128
 	bl	FtlLoadVonderInfo
19618
20129
 	bl	Ftl_load_ext_data
19619
20130
 	bl	FtlLoadEctTbl
..
..
@@ -19622,638 +20133,642 @@
19622
20133
 	bl	FtlPowerLostRecovery
19623
20134
 	mov	r0, #1
19624
20135
 	bl	FtlUpdateVaildLpn
19625
-	ldr	r2, [r5, #-3380]
19626
-	movw	r3, #2426
19627
-	mov	r0, #12
20136
+	ldr	r2, [r5, #-3376]
20137
+	movw	r3, #2430
19628
20138
 	ldrh	r1, [r6, r3]
19629
-	mov	r3, r8
19630
-.L3310:
20139
+	mov	r0, #12
20140
+	mov	r3, r7
20141
+.L3228:
19631
20142
 	cmp	r3, r1
19632
-	bge	.L3315
20143
+	bge	.L3233
19633
20144
 	mla	ip, r0, r3, r2
19634
20145
 	ldr	ip, [ip, #4]
19635
20146
 	cmp	ip, #0
19636
-	bge	.L3311
19637
-.L3315:
19638
-	ldr	r4, .L3324+12
20147
+	bge	.L3229
20148
+.L3233:
20149
+	ldr	r4, .L3242+8
19639
20150
 	cmp	r3, r1
19640
-	add	r9, r4, #80
19641
20151
 	ldrh	r2, [r4, #28]
20152
+	add	r8, r4, #12
20153
+	add	r4, r4, #76
19642
20154
 	add	r2, r2, #1
19643
-	strh	r2, [r4, #28]	@ movhi
19644
-	bge	.L3322
19645
-	b	.L3312
19646
-.L3311:
19647
-	add	r3, r3, #1
19648
-	b	.L3310
19649
-.L3322:
19650
-	movw	r3, #1850
19651
-	ldrh	r3, [r7, r3]
19652
-	cmp	r3, #0
19653
-	beq	.L3316
19654
-.L3312:
19655
-	ldrh	r2, [r9, #-4]
19656
-	ldr	r3, .L3324+16
19657
-	ldr	r0, [r5, #-3544]
19658
-	mov	r2, r2, asl #1
19659
-	ldrh	ip, [r3, #4]
19660
-	ldrh	r1, [r0, r2]
19661
-	rsb	r1, ip, r1
19662
-	movw	ip, #2388
19663
-	strh	r1, [r0, r2]	@ movhi
19664
-	add	r1, r3, #48
19665
-	ldrh	r2, [r6, ip]
19666
-	ldr	lr, [r5, #-3544]
19667
-	ldrh	r7, [r1, #4]
19668
-	strh	r2, [r3, #2]	@ movhi
20155
+	strh	r2, [r4, #-48]	@ movhi
20156
+	bge	.L3240
20157
+.L3230:
20158
+	ldrh	r3, [r4]
20159
+	movw	ip, #2390
20160
+	ldr	r1, [r5, #-3540]
20161
+	ldrh	r0, [r4, #4]
20162
+	lsl	r3, r3, #1
20163
+	ldrh	r2, [r1, r3]
20164
+	sub	r2, r2, r0
20165
+	strh	r2, [r1, r3]	@ movhi
19669
20166
 	mov	r2, #0
19670
-	strh	r2, [r3, #4]	@ movhi
19671
-	ldrh	r3, [r3, #48]
19672
-	strb	r2, [r5, #-3518]
19673
-	mov	r3, r3, asl #1
19674
-	ldrh	r0, [lr, r3]
19675
-	rsb	r0, r7, r0
19676
-	strh	r0, [lr, r3]	@ movhi
19677
20167
 	ldrh	r3, [r6, ip]
19678
-	strb	r2, [r5, #-3470]
19679
-	strh	r2, [r1, #4]	@ movhi
19680
-	strh	r3, [r1, #2]	@ movhi
19681
-	ldrh	r3, [r4, #30]
20168
+	ldr	lr, [r5, #-3540]
20169
+	strb	r2, [r5, #-3514]
20170
+	strh	r3, [r4, #2]	@ movhi
20171
+	ldr	r3, .L3242+12
20172
+	strh	r2, [r4, #4]	@ movhi
20173
+	ldrh	r1, [r3]
20174
+	ldrh	r9, [r3, #4]
20175
+	lsl	r1, r1, #1
20176
+	ldrh	r0, [lr, r1]
20177
+	sub	r0, r0, r9
20178
+	strh	r0, [lr, r1]	@ movhi
20179
+	ldrh	r1, [r6, ip]
20180
+	strh	r2, [r3, #4]	@ movhi
20181
+	strb	r2, [r5, #-3466]
20182
+	strh	r1, [r3, #2]	@ movhi
20183
+	ldrh	r3, [r8, #18]
19682
20184
 	add	r3, r3, #1
19683
-	strh	r3, [r4, #30]	@ movhi
20185
+	strh	r3, [r8, #18]	@ movhi
19684
20186
 	bl	l2p_flush
19685
20187
 	bl	FtlVpcTblFlush
19686
20188
 	bl	FtlVpcTblFlush
19687
-.L3316:
19688
-	ldrh	r0, [r9, #-4]
20189
+	b	.L3234
20190
+.L3229:
20191
+	add	r3, r3, #1
20192
+	b	.L3228
20193
+.L3240:
20194
+	movw	r3, #1848
20195
+	ldrh	r3, [r5, r3]
20196
+	cmp	r3, #0
20197
+	bne	.L3230
20198
+.L3234:
20199
+	ldrh	r0, [r4]
19689
20200
 	movw	r3, #65535
19690
-	ldr	r5, .L3324+16
19691
20201
 	cmp	r0, r3
19692
-	beq	.L3317
19693
-	ldrh	r3, [r5, #4]
20202
+	beq	.L3235
20203
+	ldrh	r3, [r4, #4]
19694
20204
 	cmp	r3, #0
19695
-	bne	.L3317
19696
-	ldrh	r3, [r5, #52]
19697
-	add	r9, r5, #52
19698
-	add	r7, r5, #48
20205
+	bne	.L3235
20206
+	ldr	r4, .L3242+12
20207
+	ldrh	r3, [r4, #4]
19699
20208
 	cmp	r3, #0
19700
-	bne	.L3317
20209
+	bne	.L3235
19701
20210
 	bl	FtlGcRefreshOpenBlock
19702
-	ldrh	r0, [r5, #48]
20211
+	ldrh	r0, [r4]
19703
20212
 	bl	FtlGcRefreshOpenBlock
19704
20213
 	bl	FtlVpcTblFlush
19705
-	mov	r0, r5
20214
+	sub	r0, r4, #48
19706
20215
 	bl	allocate_new_data_superblock
19707
-	mov	r0, r7
20216
+	mov	r0, r4
19708
20217
 	bl	allocate_new_data_superblock
19709
-.L3317:
19710
-	ldrb	r3, [r6]	@ zero_extendqisi2
20218
+.L3235:
20219
+	ldrb	r3, [r6, #36]	@ zero_extendqisi2
19711
20220
 	cmp	r3, #0
19712
-	bne	.L3318
19713
-	ldrh	r3, [r4, #28]
20221
+	bne	.L3236
20222
+	ldrh	r3, [r8, #16]
19714
20223
 	tst	r3, #31
19715
-	bne	.L3308
19716
-.L3318:
20224
+	bne	.L3224
20225
+.L3236:
19717
20226
 	bl	FtlVpcCheckAndModify
19718
-.L3308:
19719
-	mov	r0, r8
19720
-	ldmfd	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
19721
-.L3325:
20227
+	b	.L3224
20228
+.L3243:
19722
20229
 	.align	2
19723
-.L3324:
19724
-	.word	.LANCHOR4
19725
-	.word	.LANCHOR0
20230
+.L3242:
19726
20231
 	.word	.LANCHOR2
19727
-	.word	.LANCHOR2-3600
19728
-	.word	.LANCHOR2-3524
20232
+	.word	.LANCHOR0
20233
+	.word	.LANCHOR2-3596
20234
+	.word	.LANCHOR2-3472
19729
20235
 	.fnend
19730
20236
 	.size	FtlSysBlkInit, .-FtlSysBlkInit
19731
20237
 	.align	2
19732
20238
 	.global	FtlLowFormat
20239
+	.syntax unified
20240
+	.arm
20241
+	.fpu softvfp
19733
20242
 	.type	FtlLowFormat, %function
19734
20243
 FtlLowFormat:
19735
20244
 	.fnstart
19736
20245
 	@ args = 0, pretend = 0, frame = 8
19737
20246
 	@ frame_needed = 0, uses_anonymous_args = 0
19738
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
20247
+	push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
19739
20248
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
19740
20249
 	.pad #12
19741
-	ldr	r4, .L3361
19742
-	ldr	r6, [r4, #-3616]
20250
+	ldr	r4, .L3276
20251
+	ldr	r6, [r4, #-3612]
19743
20252
 	cmp	r6, #0
19744
-	bne	.L3328
19745
-	ldr	r5, .L3361+4
19746
-	movw	r7, #2424
20253
+	bne	.L3246
20254
+	ldr	r5, .L3276+4
20255
+	movw	r7, #2428
19747
20256
 	mov	r1, r6
19748
20257
 	ldr	r0, [r4, #-448]
19749
20258
 	ldrh	r2, [r5, r7]
19750
-	mov	r2, r2, asl #2
20259
+	lsl	r2, r2, #2
19751
20260
 	bl	ftl_memset
19752
20261
 	ldrh	r2, [r5, r7]
19753
20262
 	mov	r1, r6
19754
20263
 	ldr	r0, [r4, #-452]
19755
-	mov	r2, r2, asl #2
20264
+	lsl	r2, r2, #2
19756
20265
 	bl	ftl_memset
19757
-	ldr	r3, [r5, #2324]
20266
+	add	r3, r5, #2320
19758
20267
 	str	r6, [r4, #-3332]
20268
+	add	r3, r3, #8
20269
+	ldrh	r0, [r3]
19759
20270
 	str	r6, [r4, #-3328]
19760
-	uxth	r0, r3
19761
20271
 	bl	FtlFreeSysBlkQueueInit
19762
20272
 	bl	FtlLoadBbt
19763
20273
 	cmp	r0, #0
19764
-	beq	.L3329
20274
+	beq	.L3247
19765
20275
 	bl	FtlMakeBbt
19766
-.L3329:
19767
-	ldr	r0, .L3361+8
20276
+.L3247:
20277
+	ldr	r0, .L3276+8
19768
20278
 	mov	r2, #0
19769
-	ldr	ip, .L3361+12
19770
-.L3330:
20279
+	ldr	ip, .L3276+12
20280
+.L3248:
19771
20281
 	ldrh	r1, [r0]
19772
20282
 	uxth	r3, r2
19773
20283
 	add	r2, r2, #1
19774
-	cmp	r3, r1, asl #7
19775
-	bge	.L3358
19776
-	ldr	lr, [r4, #-508]
19777
-	mvn	r1, r3
19778
-	orr	r1, r3, r1, asl #16
19779
-	str	r1, [lr, r3, asl #2]
19780
-	ldr	r1, [r4, #-504]
19781
-	str	ip, [r1, r3, asl #2]
19782
-	b	.L3330
19783
-.L3358:
19784
-	ldr	r2, .L3361+4
19785
-	movw	r3, #2328
19786
-	ldr	r7, .L3361+16
19787
-	mov	r8, #0
19788
-	ldrh	r6, [r2, r3]
19789
-.L3332:
19790
-	ldrh	r3, [r7]
19791
-	ldr	r10, .L3361+4
19792
-	cmp	r3, r6
19793
-	ldr	r9, .L3361+16
19794
-	bls	.L3359
20284
+	cmp	r3, r1, lsl #7
20285
+	blt	.L3249
20286
+	movw	r3, #2332
20287
+	ldr	r9, .L3276+16
20288
+	ldrh	r7, [r5, r3]
20289
+	mov	r6, #0
20290
+	mov	r8, r9
20291
+.L3250:
20292
+	ldrh	r3, [r9]
20293
+	cmp	r3, r7
20294
+	bhi	.L3251
20295
+	movw	r3, #2324
20296
+	ldrh	r1, [r5, r3]
20297
+	sub	r3, r6, #3
20298
+	cmp	r3, r1, lsl #1
20299
+	blt	.L3252
19795
20300
 	mov	r0, r6
19796
-	mov	r1, #1
19797
-	bl	FtlLowFormatEraseBlock
19798
-	add	r6, r6, #1
19799
-	uxth	r6, r6
19800
-	add	r0, r8, r0
19801
-	uxth	r8, r0
19802
-	b	.L3332
19803
-.L3359:
19804
-	add	r7, r10, #2320
19805
-	sub	r3, r8, #3
19806
-	ldrh	r1, [r7]
19807
-	cmp	r3, r1, asl #1
19808
-	blt	.L3334
19809
-	mov	r0, r8
19810
-	mov	r8, #0
20301
+	mov	r6, #0
19811
20302
 	bl	__aeabi_uidiv
19812
-	ldr	r3, [r10, #2420]
20303
+	ldr	r3, [r5, #2424]
19813
20304
 	add	r0, r0, r3
19814
20305
 	uxth	r0, r0
19815
20306
 	bl	FtlSysBlkNumInit
19816
-	ldr	r3, [r10, #2324]
19817
-	uxth	r0, r3
20307
+	add	r3, r5, #2320
20308
+	add	r3, r3, #8
20309
+	ldrh	r0, [r3]
19818
20310
 	bl	FtlFreeSysBlkQueueInit
19819
-	movw	r3, #2328
19820
-	ldrh	r6, [r10, r3]
19821
-.L3335:
19822
-	ldrh	r3, [r9]
19823
-	cmp	r3, r6
19824
-	bls	.L3334
19825
-	mov	r0, r6
19826
-	mov	r1, #1
19827
-	bl	FtlLowFormatEraseBlock
19828
-	add	r6, r6, #1
19829
-	uxth	r6, r6
19830
-	add	r0, r8, r0
19831
-	uxth	r8, r0
19832
-	b	.L3335
19833
-.L3334:
19834
-	ldr	r10, .L3361+20
19835
-	mov	r9, #0
19836
-	mov	r6, r9
19837
-.L3337:
19838
-	ldrh	r2, [r10]
19839
-	uxth	r0, r9
19840
-	ldr	r3, .L3361+4
19841
-	add	r9, r9, #1
19842
-	cmp	r2, r0
19843
-	bls	.L3360
19844
-	mov	r1, #0
19845
-	bl	FtlLowFormatEraseBlock
19846
-	add	r0, r6, r0
19847
-	uxth	r6, r0
19848
-	b	.L3337
19849
-.L3360:
19850
-	movw	r2, #2330
19851
-	ldrh	r9, [r7]
19852
-	ldrh	r2, [r3, r2]
19853
-	str	r3, [sp, #4]
19854
-	mov	r1, r9
19855
-	ldr	r7, .L3361+24
19856
-	str	r2, [r4, #-548]
19857
-	ldr	r2, [r3, #2332]
20311
+	movw	r3, #2332
20312
+	ldrh	r7, [r5, r3]
20313
+.L3253:
20314
+	ldrh	r3, [r8]
20315
+	cmp	r3, r7
20316
+	bhi	.L3254
20317
+.L3252:
20318
+	ldr	r8, .L3276+20
20319
+	mov	r7, #0
20320
+	mov	r9, r7
20321
+.L3255:
20322
+	ldrh	r3, [r8]
20323
+	uxth	r0, r7
20324
+	add	r7, r7, #1
20325
+	cmp	r3, r0
20326
+	bhi	.L3256
20327
+	movw	r3, #2334
20328
+	ldr	r2, [r5, #2336]
20329
+	ldrh	r3, [r5, r3]
20330
+	ldr	r8, .L3276+24
19858
20331
 	mov	r0, r2
19859
-	str	r2, [sp]
20332
+	str	r2, [sp, #4]
20333
+	str	r3, [r4, #-548]
20334
+	movw	r3, #2324
20335
+	ldrh	r7, [r5, r3]
20336
+	mov	r1, r7
19860
20337
 	bl	__aeabi_uidiv
19861
20338
 	ubfx	r10, r0, #5, #16
19862
-	ldr	r3, [sp, #4]
19863
-	add	r1, r10, #36
19864
-	strh	r1, [r7, #-8]	@ movhi
19865
-	mov	r1, #24
19866
20339
 	mov	fp, r0
19867
-	mul	r1, r1, r9
19868
-	str	r0, [r3, #2448]
19869
-	ldr	r2, [sp]
19870
-	cmp	r6, r1
19871
-	ble	.L3339
19872
-	rsb	r0, r6, r2
19873
-	mov	r1, r9
19874
-	str	r3, [sp]
20340
+	add	r3, r10, #36
20341
+	str	r0, [r5, #2452]
20342
+	strh	r3, [r8, #-8]	@ movhi
20343
+	mov	r3, #24
20344
+	mul	r3, r3, r7
20345
+	cmp	r9, r3
20346
+	ble	.L3257
20347
+	ldr	r2, [sp, #4]
20348
+	mov	r1, r7
20349
+	sub	r0, r2, r9
19875
20350
 	bl	__aeabi_uidiv
19876
-	ldr	r3, [sp]
19877
-	str	r0, [r3, #2448]
19878
-	mov	r0, r0, lsr #5
20351
+	str	r0, [r5, #2452]
20352
+	lsr	r0, r0, #5
19879
20353
 	add	r0, r0, #24
19880
-	strh	r0, [r7, #-8]	@ movhi
19881
-.L3339:
19882
-	ldr	r3, [r5, #2244]
20354
+	strh	r0, [r8, #-8]	@ movhi
20355
+.L3257:
20356
+	ldr	r3, [r5, #2248]
19883
20357
 	cmp	r3, #1
19884
-	bne	.L3340
19885
-	ldrh	r3, [r7, #-8]
19886
-	mov	r0, r6
19887
-	mov	r1, r9
19888
-	str	r3, [sp]
20358
+	bne	.L3258
20359
+	ldrh	r3, [r8, #-8]
20360
+	mov	r1, r7
20361
+	mov	r0, r9
20362
+	str	r3, [sp, #4]
19889
20363
 	bl	__aeabi_uidiv
19890
-	ldr	r3, [sp]
20364
+	ldr	r3, [sp, #4]
19891
20365
 	uxtah	r0, r3, r0
19892
20366
 	add	r3, r3, r0, asr #2
19893
-	strh	r3, [r7, #-8]	@ movhi
19894
-.L3340:
19895
-	ldrb	r3, [r5, #144]	@ zero_extendqisi2
20367
+	strh	r3, [r8, #-8]	@ movhi
20368
+.L3258:
20369
+	ldrb	r3, [r5, #152]	@ zero_extendqisi2
19896
20370
 	cmp	r3, #0
19897
-	beq	.L3341
19898
-	ldrh	r3, [r7, #-8]
19899
-	mov	r0, r6
19900
-	mov	r1, r9
19901
-	str	r3, [sp]
20371
+	beq	.L3259
20372
+	ldrh	r3, [r8, #-8]
20373
+	mov	r1, r7
20374
+	mov	r0, r9
20375
+	str	r3, [sp, #4]
19902
20376
 	bl	__aeabi_uidiv
19903
-	ldr	r3, [sp]
20377
+	ldr	r3, [sp, #4]
19904
20378
 	uxtah	r0, r3, r0
19905
20379
 	add	r3, r3, r0, asr #2
19906
-	strh	r3, [r7, #-8]	@ movhi
19907
-.L3341:
19908
-	movw	r3, #2382
19909
-	ldrh	r3, [r5, r3]
20380
+	strh	r3, [r8, #-8]	@ movhi
20381
+.L3259:
20382
+	ldr	r3, .L3276+28
20383
+	ldrh	r3, [r3]
19910
20384
 	cmp	r3, #0
19911
-	beq	.L3343
19912
-	ldrh	r2, [r7, #-8]
20385
+	beq	.L3261
20386
+	ldrh	r2, [r8, #-8]
19913
20387
 	add	r2, r2, r3, lsr #1
19914
-	strh	r2, [r7, #-8]	@ movhi
19915
-	mul	r2, r9, r3
19916
-	cmp	r2, r6
19917
-	addgt	r3, r3, #32
19918
-	ldrgt	r2, .L3361+4
19919
-	addgt	r3, r10, r3
19920
-	strgt	fp, [r2, #2448]
19921
-	ldrgt	r2, .L3361+24
19922
-	strgth	r3, [r2, #-8]	@ movhi
19923
-.L3343:
19924
-	ldrh	r2, [r7, #-8]
19925
-	ldr	r3, [r5, #2448]
19926
-	rsb	r3, r2, r3
19927
-	mul	r9, r9, r3
19928
-	movw	r3, #2388
20388
+	strh	r2, [r8, #-8]	@ movhi
20389
+	mul	r2, r7, r3
20390
+	cmp	r9, r2
20391
+	addlt	r3, r3, #32
20392
+	strlt	fp, [r5, #2452]
20393
+	addlt	r3, r10, r3
20394
+	strhlt	r3, [r8, #-8]	@ movhi
20395
+.L3261:
20396
+	ldrh	r2, [r8, #-8]
20397
+	ldr	r3, [r5, #2452]
20398
+	sub	r3, r3, r2
20399
+	mul	r7, r7, r3
20400
+	movw	r3, #2390
19929
20401
 	ldrh	r3, [r5, r3]
19930
-	str	r9, [r4, #1788]
19931
-	mul	r9, r3, r9
19932
-	movw	r3, #2394
20402
+	str	r7, [r4, #1796]
20403
+	mul	r7, r7, r3
20404
+	movw	r3, #2396
19933
20405
 	ldrh	r3, [r5, r3]
19934
-	str	r9, [r5, #2448]
19935
-	mul	r9, r3, r9
19936
-	str	r9, [r5, #2428]
20406
+	str	r7, [r5, #2452]
20407
+	mul	r7, r7, r3
20408
+	str	r7, [r5, #2432]
19937
20409
 	bl	FtlBbmTblFlush
19938
-	ldr	r2, [r5, #2336]
19939
-	movw	r3, #2402
20410
+	movw	r3, #2404
20411
+	ldr	r2, [r5, #2340]
19940
20412
 	ldrh	r3, [r5, r3]
19941
-	add	r1, r6, r8
20413
+	add	r1, r6, r9
19942
20414
 	add	r3, r3, r2, lsr #3
19943
20415
 	cmp	r1, r3
19944
-	bls	.L3345
19945
-	ldr	r0, .L3361+28
19946
-	mov	r2, r2, lsr #5
20416
+	bls	.L3263
20417
+	lsr	r2, r2, #5
20418
+	ldr	r0, .L3276+32
19947
20419
 	bl	printk
19948
-.L3345:
19949
-	movw	r3, #2330
19950
-	ldr	r6, .L3361+32
20420
+.L3263:
20421
+	movw	r3, #2334
20422
+	ldr	r6, .L3276+36
19951
20423
 	ldrh	r2, [r5, r3]
19952
20424
 	mov	r1, #0
19953
-	sub	r8, r6, #244
19954
-	ldr	r0, [r4, #-3544]
19955
-	mvn	r9, #0
19956
-	mov	r2, r2, asl #1
19957
-	mov	fp, r8
20425
+	ldr	r0, [r4, #-3540]
20426
+	mvn	r7, #0
20427
+	sub	r6, r6, #240
20428
+	lsl	r2, r2, #1
19958
20429
 	bl	ftl_memset
19959
20430
 	mov	r3, #0
19960
-	strh	r3, [r6, #-2]	@ movhi
20431
+	strh	r7, [r6, #236]	@ movhi
20432
+	strh	r3, [r6, #238]	@ movhi
19961
20433
 	mov	r1, #255
19962
-	strh	r3, [r6, #-244]	@ movhi
19963
-	str	r3, [r4, #-3372]
20434
+	str	r3, [r4, #-3368]
19964
20435
 	strb	r3, [r4, #-3278]
19965
20436
 	strb	r3, [r4, #-3276]
19966
-	strh	r3, [r8, #2]	@ movhi
19967
-	strb	r3, [r4, #-3518]
19968
-	mov	r3, #1
19969
-	strb	r3, [r4, #-3516]
19970
-	movw	r3, #2328
19971
-	ldrh	r2, [r5, r3]
19972
-	ldr	r0, [r4, #-3368]
19973
-	strh	r9, [r6, #-4]	@ movhi
19974
-	add	r6, r6, #3280
19975
-	mov	r2, r2, lsr #3
19976
-	bl	ftl_memset
19977
-.L3346:
19978
-	ldr	r10, .L3361+36
19979
-	ldr	r5, .L3361
19980
-	mov	r0, r10
19981
-	bl	make_superblock
19982
-	ldrb	r3, [r4, #-3517]	@ zero_extendqisi2
19983
-	cmp	r3, #0
19984
-	ldrh	r3, [r8]
19985
-	bne	.L3347
19986
-	ldr	r2, [r6, #-3544]
19987
-	mov	r3, r3, asl #1
19988
-	strh	r9, [r2, r3]	@ movhi
19989
-	ldrh	r3, [fp]
19990
-	add	r3, r3, #1
19991
-	strh	r3, [fp]	@ movhi
19992
-	b	.L3346
19993
-.L3347:
19994
-	ldr	r2, [r5, #-3332]
19995
-	mov	r3, r3, asl #1
19996
-	ldrh	r1, [r10, #4]
19997
-	mov	r9, r5
19998
-	str	r2, [r5, #-3512]
19999
-	add	r2, r2, #1
20000
-	str	r2, [r5, #-3332]
20001
-	ldr	r2, [r5, #-3544]
20002
-	strh	r1, [r2, r3]	@ movhi
20003
-	sub	r2, r5, #3472
20004
-	sub	r6, r2, #4
20005
-	mov	r3, #0
20006
-	strb	r3, [r5, #-3470]
20007
20437
 	strh	r3, [r6, #2]	@ movhi
20008
-	ldrh	r3, [r10]
20009
-	mvn	r10, #0
20010
-	add	r3, r3, #1
20011
-	strh	r3, [r2, #-4]	@ movhi
20012
-	mov	r3, #1
20013
-	strb	r3, [r5, #-3468]
20014
-.L3348:
20015
-	ldr	r8, .L3361+40
20016
-	ldr	r5, .L3361
20017
-	mov	r0, r8
20018
-	bl	make_superblock
20019
-	ldrb	r3, [r4, #-3469]	@ zero_extendqisi2
20020
-	cmp	r3, #0
20021
-	ldrh	r3, [r6]
20022
-	bne	.L3349
20023
-	ldr	r2, [r9, #-3544]
20024
-	mov	r3, r3, asl #1
20025
-	strh	r10, [r2, r3]	@ movhi
20026
-	ldrh	r3, [r6]
20027
-	add	r3, r3, #1
20438
+	strb	r3, [r4, #-3514]
20028
20439
 	strh	r3, [r6]	@ movhi
20029
-	b	.L3348
20030
-.L3349:
20031
-	ldr	r2, [r5, #-3332]
20032
-	mov	r3, r3, asl #1
20033
-	ldrh	r1, [r8, #4]
20034
-	mvn	r4, #0
20035
-	str	r2, [r5, #-3464]
20036
-	add	r2, r2, #1
20037
-	str	r2, [r5, #-3332]
20038
-	ldr	r2, [r5, #-3544]
20039
-	strh	r1, [r2, r3]	@ movhi
20040
-	sub	r3, r5, #3424
20041
-	strh	r4, [r3, #-4]	@ movhi
20042
-	bl	FtlFreeSysBlkQueueOut
20043
-	ldr	r3, .L3361+44
20044
-	mov	r2, #0
20045
-	strh	r2, [r3, #2]	@ movhi
20046
-	ldr	r2, [r5, #1788]
20047
-	strh	r4, [r3, #4]	@ movhi
20048
-	strh	r2, [r3, #6]	@ movhi
20049
-	ldr	r3, [r5, #-3332]
20050
-	str	r3, [r5, #-3292]
20440
+	mov	r3, #1
20441
+	strb	r3, [r4, #-3512]
20442
+	movw	r3, #2332
20443
+	ldrh	r2, [r5, r3]
20444
+	ldr	r0, [r5, #32]
20445
+	mov	r5, r6
20446
+	lsr	r2, r2, #3
20447
+	bl	ftl_memset
20448
+.L3264:
20449
+	mov	r0, r6
20450
+	bl	make_superblock
20451
+	ldrb	r3, [r4, #-3513]	@ zero_extendqisi2
20452
+	cmp	r3, #0
20453
+	ldrh	r3, [r5]
20454
+	bne	.L3265
20455
+	ldr	r2, [r4, #-3540]
20456
+	lsl	r3, r3, #1
20457
+	strh	r7, [r2, r3]	@ movhi
20458
+	ldrh	r3, [r5]
20051
20459
 	add	r3, r3, #1
20052
-	str	r3, [r5, #-3332]
20053
-	strh	r0, [r7, #-4]	@ movhi
20460
+	strh	r3, [r5]	@ movhi
20461
+	b	.L3264
20462
+.L3249:
20463
+	ldr	lr, [r4, #-508]
20464
+	mvn	r1, r3
20465
+	orr	r1, r3, r1, lsl #16
20466
+	str	r1, [lr, r3, lsl #2]
20467
+	ldr	r1, [r4, #-504]
20468
+	str	ip, [r1, r3, lsl #2]
20469
+	b	.L3248
20470
+.L3251:
20471
+	mov	r0, r7
20472
+	mov	r1, #1
20473
+	bl	FtlLowFormatEraseBlock
20474
+	add	r7, r7, #1
20475
+	add	r6, r6, r0
20476
+	uxth	r6, r6
20477
+	uxth	r7, r7
20478
+	b	.L3250
20479
+.L3254:
20480
+	mov	r0, r7
20481
+	mov	r1, #1
20482
+	bl	FtlLowFormatEraseBlock
20483
+	add	r7, r7, #1
20484
+	add	r6, r6, r0
20485
+	uxth	r6, r6
20486
+	uxth	r7, r7
20487
+	b	.L3253
20488
+.L3256:
20489
+	mov	r1, #0
20490
+	bl	FtlLowFormatEraseBlock
20491
+	add	r9, r9, r0
20492
+	uxth	r9, r9
20493
+	b	.L3255
20494
+.L3265:
20495
+	ldr	r2, [r4, #-3332]
20496
+	lsl	r3, r3, #1
20497
+	ldrh	r1, [r5, #4]
20498
+	mvn	r6, #0
20499
+	str	r2, [r4, #-3508]
20500
+	add	r2, r2, #1
20501
+	str	r2, [r4, #-3332]
20502
+	ldr	r2, [r4, #-3540]
20503
+	strh	r1, [r2, r3]	@ movhi
20504
+	mov	r2, #0
20505
+	ldr	r3, .L3276+40
20506
+	strb	r2, [r4, #-3466]
20507
+	strh	r2, [r3, #2]	@ movhi
20508
+	mov	r7, r3
20509
+	ldrh	r2, [r5]
20510
+	mov	r5, r3
20511
+	add	r2, r2, #1
20512
+	strh	r2, [r3]	@ movhi
20513
+	mov	r2, #1
20514
+	strb	r2, [r4, #-3464]
20515
+.L3266:
20516
+	mov	r0, r7
20517
+	bl	make_superblock
20518
+	ldrb	r3, [r4, #-3465]	@ zero_extendqisi2
20519
+	cmp	r3, #0
20520
+	ldrh	r3, [r5]
20521
+	bne	.L3267
20522
+	ldr	r2, [r4, #-3540]
20523
+	lsl	r3, r3, #1
20524
+	strh	r6, [r2, r3]	@ movhi
20525
+	ldrh	r3, [r5]
20526
+	add	r3, r3, #1
20527
+	strh	r3, [r5]	@ movhi
20528
+	b	.L3266
20529
+.L3267:
20530
+	ldr	r2, [r4, #-3332]
20531
+	lsl	r3, r3, #1
20532
+	ldrh	r1, [r5, #4]
20533
+	mvn	r5, #0
20534
+	str	r2, [r4, #-3460]
20535
+	add	r2, r2, #1
20536
+	str	r2, [r4, #-3332]
20537
+	ldr	r2, [r4, #-3540]
20538
+	strh	r1, [r2, r3]	@ movhi
20539
+	ldr	r3, .L3276+44
20540
+	strh	r5, [r3]	@ movhi
20541
+	bl	FtlFreeSysBlkQueueOut
20542
+	sub	r3, r8, #4
20543
+	mov	r2, #0
20544
+	strh	r5, [r3, #4]	@ movhi
20545
+	ldr	r3, [r4, #-3332]
20546
+	strh	r2, [r8, #-2]	@ movhi
20547
+	ldr	r2, [r4, #1796]
20548
+	str	r3, [r4, #-3292]
20549
+	add	r3, r3, #1
20550
+	str	r3, [r4, #-3332]
20551
+	strh	r2, [r8, #2]	@ movhi
20552
+	strh	r0, [r8, #-4]	@ movhi
20054
20553
 	bl	FtlVpcTblFlush
20055
20554
 	bl	FtlSysBlkInit
20056
20555
 	cmp	r0, #0
20057
-	ldreq	r3, .L3361+48
20556
+	ldreq	r3, .L3276+48
20058
20557
 	moveq	r2, #1
20059
-	streq	r2, [r3, #504]
20060
-.L3328:
20558
+	streq	r2, [r3, #500]
20559
+.L3246:
20061
20560
 	mov	r0, #0
20062
20561
 	add	sp, sp, #12
20063
20562
 	@ sp needed
20064
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
20065
-.L3362:
20563
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
20564
+.L3277:
20066
20565
 	.align	2
20067
-.L3361:
20566
+.L3276:
20068
20567
 	.word	.LANCHOR2
20069
20568
 	.word	.LANCHOR0
20070
-	.word	.LANCHOR0+2394
20569
+	.word	.LANCHOR0+2396
20071
20570
 	.word	168778952
20072
-	.word	.LANCHOR0+2330
20073
-	.word	.LANCHOR0+2328
20571
+	.word	.LANCHOR0+2334
20572
+	.word	.LANCHOR0+2332
20074
20573
 	.word	.LANCHOR2-3296
20574
+	.word	.LANCHOR0+2384
20075
20575
 	.word	.LC156
20076
20576
 	.word	.LANCHOR2-3280
20077
-	.word	.LANCHOR2-3524
20078
-	.word	.LANCHOR2-3476
20079
-	.word	.LANCHOR2-3300
20577
+	.word	.LANCHOR2-3472
20578
+	.word	.LANCHOR2-3424
20080
20579
 	.word	.LANCHOR1
20081
20580
 	.fnend
20082
20581
 	.size	FtlLowFormat, .-FtlLowFormat
20083
20582
 	.align	2
20084
20583
 	.global	FtlReInitForSDUpdata
20584
+	.syntax unified
20585
+	.arm
20586
+	.fpu softvfp
20085
20587
 	.type	FtlReInitForSDUpdata, %function
20086
20588
 FtlReInitForSDUpdata:
20087
20589
 	.fnstart
20088
20590
 	@ args = 0, pretend = 0, frame = 16
20089
20591
 	@ frame_needed = 0, uses_anonymous_args = 0
20090
-	stmfd	sp!, {r4, r5, lr}
20091
-	.save {r4, r5, lr}
20092
-	.pad #20
20093
-	sub	sp, sp, #20
20094
-	ldr	r4, .L3392
20095
-	ldrb	r3, [r4, #144]	@ zero_extendqisi2
20592
+	push	{r0, r1, r2, r3, r4, r5, r6, lr}
20593
+	.save {r4, r5, r6, lr}
20594
+	.pad #16
20595
+	ldr	r4, .L3314
20596
+	ldrb	r3, [r4, #152]	@ zero_extendqisi2
20096
20597
 	cmp	r3, #0
20097
-	beq	.L3364
20098
-.L3366:
20099
-	mov	r0, #0
20100
-	b	.L3365
20101
-.L3364:
20102
-	ldr	r5, .L3392+4
20598
+	beq	.L3279
20599
+.L3281:
20600
+	mov	r6, #0
20601
+.L3278:
20602
+	mov	r0, r6
20603
+	add	sp, sp, #16
20604
+	@ sp needed
20605
+	pop	{r4, r5, r6, pc}
20606
+.L3279:
20607
+	ldr	r5, .L3314+4
20103
20608
 	ldr	r0, [r5, #1684]
20104
20609
 	bl	FlashInit
20105
-	cmp	r0, #0
20106
-	bne	.L3366
20610
+	subs	r6, r0, #0
20611
+	bne	.L3281
20107
20612
 	bl	FlashLoadFactorBbt
20108
20613
 	cmp	r0, #0
20109
-	beq	.L3367
20614
+	beq	.L3282
20110
20615
 	bl	FlashMakeFactorBbt
20111
-.L3367:
20112
-	ldr	r0, [r5, #1716]
20616
+.L3282:
20617
+	ldr	r0, [r5, #1724]
20113
20618
 	bl	FlashReadIdbDataRaw
20114
20619
 	cmp	r0, #0
20115
-	beq	.L3368
20116
-	mov	r1, #0
20620
+	beq	.L3283
20117
20621
 	mov	r2, #16
20622
+	mov	r1, #0
20118
20623
 	mov	r0, sp
20119
20624
 	bl	FlashReadFacBbtData
20625
+	ldr	r1, [sp]
20120
20626
 	mov	r3, #0
20121
20627
 	mov	r2, r3
20122
-	mov	ip, #1
20123
-	ldr	r1, [sp]
20124
-.L3369:
20125
-	ands	lr, r1, ip, asl r2
20126
-	add	r0, r3, #1
20628
+	mov	r0, #1
20629
+.L3285:
20630
+	ands	ip, r1, r0, lsl r2
20127
20631
 	add	r2, r2, #1
20128
-	movne	r3, r0
20632
+	addne	r3, r3, #1
20129
20633
 	cmp	r2, #16
20130
-	bne	.L3369
20634
+	bne	.L3285
20131
20635
 	cmp	r3, #6
20132
-	bls	.L3388
20636
+	bhi	.L3286
20637
+.L3311:
20638
+	strb	r2, [r4, #37]
20639
+	b	.L3287
20640
+.L3286:
20133
20641
 	mov	r2, #0
20134
-	mov	ip, #1
20135
-.L3372:
20136
-	ands	lr, r1, ip, asl r2
20137
-	add	r0, r3, #1
20642
+	mov	r0, #1
20643
+.L3289:
20644
+	ands	ip, r1, r0, lsl r2
20138
20645
 	add	r2, r2, #1
20139
-	movne	r3, r0
20646
+	addne	r3, r3, #1
20140
20647
 	cmp	r2, #24
20141
-	bne	.L3372
20648
+	bne	.L3289
20142
20649
 	cmp	r3, #17
20143
20650
 	movhi	r3, #36
20144
-	strhib	r3, [r4, #1]
20145
-	bhi	.L3371
20146
-.L3388:
20147
-	strb	r2, [r4, #1]
20148
-.L3371:
20149
-	ldrb	r3, [r4, #1]	@ zero_extendqisi2
20150
-	strh	r3, [r4, #142]	@ movhi
20151
-.L3368:
20152
-	ldr	r1, .L3392+8
20153
-	ldr	r0, .L3392+12
20651
+	strbhi	r3, [r4, #37]
20652
+	bls	.L3311
20653
+.L3287:
20654
+	ldrb	r3, [r4, #37]	@ zero_extendqisi2
20655
+	strh	r3, [r4, #150]	@ movhi
20656
+.L3283:
20657
+	ldr	r1, .L3314+8
20658
+	ldr	r0, .L3314+12
20154
20659
 	bl	printk
20155
-	ldr	r0, .L3392+16
20660
+	ldr	r0, .L3314+16
20156
20661
 	bl	FtlConstantsInit
20157
20662
 	bl	FtlVariablesInit
20158
-	ldr	r0, [r4, #2324]
20663
+	ldr	r0, [r4, #2328]
20159
20664
 	mov	r4, #1
20160
20665
 	uxth	r0, r0
20161
20666
 	bl	FtlFreeSysBlkQueueInit
20162
-.L3374:
20667
+.L3291:
20163
20668
 	bl	FtlLoadBbt
20164
20669
 	cmp	r0, #0
20165
-	beq	.L3375
20166
-.L3390:
20670
+	beq	.L3292
20671
+.L3313:
20167
20672
 	bl	FtlLowFormat
20168
20673
 	cmp	r4, #3
20169
-	addls	r4, r4, #1
20170
-	bls	.L3374
20171
-.L3391:
20172
-	mvn	r0, #0
20173
-	b	.L3365
20174
-.L3375:
20674
+	mvnhi	r6, #0
20675
+	bhi	.L3278
20676
+.L3293:
20677
+	add	r4, r4, #1
20678
+	b	.L3291
20679
+.L3292:
20175
20680
 	bl	FtlSysBlkInit
20176
20681
 	cmp	r0, #0
20177
-	bne	.L3390
20178
-	ldr	r3, .L3392+20
20682
+	bne	.L3313
20683
+	ldr	r3, .L3314+20
20179
20684
 	mov	r2, #1
20180
-	str	r2, [r3, #504]
20181
-.L3365:
20182
-	add	sp, sp, #20
20183
-	@ sp needed
20184
-	ldmfd	sp!, {r4, r5, pc}
20185
-.L3393:
20685
+	str	r2, [r3, #500]
20686
+	b	.L3278
20687
+.L3315:
20186
20688
 	.align	2
20187
-.L3392:
20689
+.L3314:
20188
20690
 	.word	.LANCHOR0
20189
20691
 	.word	.LANCHOR2
20190
-	.word	.LC77
20191
20692
 	.word	.LC76
20192
-	.word	.LANCHOR0+116
20693
+	.word	.LC77
20694
+	.word	.LANCHOR0+124
20193
20695
 	.word	.LANCHOR1
20194
20696
 	.fnend
20195
20697
 	.size	FtlReInitForSDUpdata, .-FtlReInitForSDUpdata
20196
20698
 	.align	2
20197
20699
 	.global	Ftl_gc_temp_data_write_back
20700
+	.syntax unified
20701
+	.arm
20702
+	.fpu softvfp
20198
20703
 	.type	Ftl_gc_temp_data_write_back, %function
20199
20704
 Ftl_gc_temp_data_write_back:
20200
20705
 	.fnstart
20201
20706
 	@ args = 0, pretend = 0, frame = 0
20202
20707
 	@ frame_needed = 0, uses_anonymous_args = 0
20203
-	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
20204
-	.save {r4, r5, r6, r7, r8, lr}
20205
-	ldr	r5, .L3411
20206
-	ldr	r3, [r5, #-3616]
20708
+	push	{r4, r5, r6, lr}
20709
+	.save {r4, r5, r6, lr}
20710
+	ldr	r4, .L3332
20711
+	ldr	r3, [r4, #-3612]
20207
20712
 	cmp	r3, #0
20208
-	beq	.L3395
20209
-.L3398:
20713
+	beq	.L3317
20714
+.L3320:
20210
20715
 	mov	r0, #0
20211
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
20212
-.L3395:
20213
-	ldr	r3, .L3411+4
20214
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
20716
+	pop	{r4, r5, r6, pc}
20717
+.L3317:
20718
+	ldr	r3, .L3332+4
20719
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
20215
20720
 	cmp	r3, #0
20216
-	beq	.L3397
20217
-	ldr	r3, [r5, #-2704]
20721
+	beq	.L3319
20722
+	ldr	r3, [r4, #-2704]
20218
20723
 	tst	r3, #1
20219
-	beq	.L3397
20220
-	ldr	r3, .L3411+8
20724
+	beq	.L3319
20725
+	sub	r3, r4, #3424
20221
20726
 	ldrh	r3, [r3, #4]
20222
20727
 	cmp	r3, #0
20223
-	bne	.L3398
20224
-.L3397:
20225
-	mov	r2, #0
20226
-	ldr	r0, [r5, #-532]
20227
-	ldr	r1, [r5, #-2704]
20228
-	mov	r3, r2
20728
+	bne	.L3320
20729
+.L3319:
20730
+	mov	r3, #0
20731
+	mov	r5, #0
20732
+	mov	r6, #36
20733
+	mov	r2, r3
20734
+	ldr	r1, [r4, #-2704]
20735
+	ldr	r0, [r4, #-532]
20229
20736
 	bl	FlashProgPages
20230
-	ldr	r7, .L3411
20231
-	mov	r6, #0
20232
-	mov	r8, #36
20233
-.L3399:
20234
-	ldr	r1, [r5, #-2704]
20235
-	uxth	r3, r6
20236
-	ldr	r4, .L3411
20737
+.L3321:
20738
+	ldr	r1, [r4, #-2704]
20739
+	uxth	r3, r5
20237
20740
 	cmp	r3, r1
20238
-	bcs	.L3410
20239
-	mul	r3, r8, r3
20240
-	ldr	r0, [r7, #-532]
20241
-	add	r6, r6, #1
20242
-	add	r1, r0, r3
20243
-	ldr	r0, [r0, r3]
20244
-	ldr	r2, [r1, #12]
20245
-	cmn	r0, #1
20246
-	bne	.L3400
20247
-	sub	r1, r4, #3424
20248
-	ldr	ip, [r4, #-3544]
20741
+	bcc	.L3323
20742
+	ldr	r0, [r4, #-532]
20743
+	bl	FtlGcBufFree
20744
+	mov	r3, #0
20745
+	str	r3, [r4, #-2704]
20746
+	ldr	r3, .L3332+8
20747
+	ldrh	r3, [r3, #4]
20748
+	cmp	r3, #0
20749
+	bne	.L3320
20750
+	mov	r0, #1
20751
+	bl	FtlGcFreeTempBlock
20752
+	b	.L3331
20753
+.L3323:
20754
+	mul	r3, r6, r3
20755
+	ldr	r2, [r4, #-532]
20756
+	add	r5, r5, #1
20757
+	ldr	ip, [r2, r3]
20758
+	add	r1, r2, r3
20759
+	ldr	r0, [r1, #12]
20760
+	cmn	ip, #1
20761
+	bne	.L3322
20762
+	ldr	r1, .L3332+8
20249
20763
 	mov	lr, #0
20250
-	ldrh	r2, [r1, #-4]
20251
-	mov	r2, r2, asl #1
20252
-	strh	lr, [ip, r2]	@ movhi
20253
-	ldr	r2, [r4, #-3136]
20254
-	strh	r0, [r1, #-4]	@ movhi
20764
+	ldr	r0, [r4, #-3540]
20765
+	ldrh	r2, [r1]
20766
+	lsl	r2, r2, #1
20767
+	strh	lr, [r0, r2]	@ movhi
20768
+	ldr	r2, [r4, #-3140]
20769
+	strh	ip, [r1]	@ movhi
20255
20770
 	add	r2, r2, #1
20256
-	str	r2, [r4, #-3136]
20771
+	str	r2, [r4, #-3140]
20257
20772
 	ldr	r2, [r4, #-532]
20258
20773
 	add	r3, r2, r3
20259
20774
 	ldr	r0, [r3, #4]
..
..
@@ -20261,61 +20776,52 @@
20261
20776
 	bl	FtlBbmMapBadBlock
20262
20777
 	bl	FtlBbmTblFlush
20263
20778
 	bl	FtlGcPageVarInit
20264
-	b	.L3409
20265
-.L3400:
20266
-	ldr	r0, [r2, #12]
20779
+.L3331:
20780
+	mov	r0, #1
20781
+	pop	{r4, r5, r6, pc}
20782
+.L3322:
20783
+	ldr	r2, [r0, #8]
20267
20784
 	ldr	r1, [r1, #4]
20268
-	ldr	r2, [r2, #8]
20785
+	ldr	r0, [r0, #12]
20269
20786
 	bl	FtlGcUpdatePage
20270
-	b	.L3399
20271
-.L3410:
20272
-	ldr	r0, [r4, #-532]
20273
-	bl	FtlGcBufFree
20274
-	mov	r3, #0
20275
-	str	r3, [r4, #-2704]
20276
-	ldr	r3, .L3411+8
20277
-	ldrh	r3, [r3, #4]
20278
-	cmp	r3, #0
20279
-	bne	.L3398
20280
-	mov	r0, #1
20281
-	bl	FtlGcFreeTempBlock
20282
-.L3409:
20283
-	mov	r0, #1
20284
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
20285
-.L3412:
20787
+	b	.L3321
20788
+.L3333:
20286
20789
 	.align	2
20287
-.L3411:
20790
+.L3332:
20288
20791
 	.word	.LANCHOR2
20289
20792
 	.word	.LANCHOR0
20290
-	.word	.LANCHOR2-3428
20793
+	.word	.LANCHOR2-3424
20291
20794
 	.fnend
20292
20795
 	.size	Ftl_gc_temp_data_write_back, .-Ftl_gc_temp_data_write_back
20293
20796
 	.align	2
20294
20797
 	.global	Ftl_get_new_temp_ppa
20798
+	.syntax unified
20799
+	.arm
20800
+	.fpu softvfp
20295
20801
 	.type	Ftl_get_new_temp_ppa, %function
20296
20802
 Ftl_get_new_temp_ppa:
20297
20803
 	.fnstart
20298
20804
 	@ args = 0, pretend = 0, frame = 0
20299
20805
 	@ frame_needed = 0, uses_anonymous_args = 0
20300
-	stmfd	sp!, {r3, r4, r5, lr}
20301
-	.save {r3, r4, r5, lr}
20302
-	ldr	r3, .L3417
20303
-	sub	r2, r3, #4
20304
-	ldrh	r1, [r3, #-4]
20305
-	movw	r3, #65535
20306
-	cmp	r1, r3
20307
-	beq	.L3414
20308
-	ldrh	r3, [r2, #4]
20806
+	ldr	r3, .L3341
20807
+	movw	r2, #65535
20808
+	ldrh	r1, [r3]
20809
+	cmp	r1, r2
20810
+	beq	.L3335
20811
+	ldrh	r3, [r3, #4]
20309
20812
 	cmp	r3, #0
20310
-	bne	.L3415
20311
-.L3414:
20312
-	ldr	r4, .L3417+4
20813
+	ldrne	r0, .L3341
20814
+	bne	.L3340
20815
+.L3335:
20816
+	push	{r4, r5, r6, lr}
20817
+	.save {r4, r5, r6, lr}
20818
+	mov	r5, #0
20819
+	ldr	r4, .L3341+4
20313
20820
 	bl	FtlCacheWriteBack
20314
20821
 	mov	r0, #0
20315
-	mov	r5, #0
20316
20822
 	bl	FtlGcFreeTempBlock
20317
-	ldr	r0, .L3417+8
20318
-	strb	r5, [r4, #-3420]
20823
+	sub	r0, r4, #3424
20824
+	strb	r5, [r4, #-3416]
20319
20825
 	bl	allocate_data_superblock
20320
20826
 	sub	r3, r4, #2672
20321
20827
 	sub	r4, r4, #2656
..
..
@@ -20325,712 +20831,833 @@
20325
20831
 	mov	r0, r5
20326
20832
 	bl	FtlEctTblFlush
20327
20833
 	bl	FtlVpcTblFlush
20328
-.L3415:
20329
-	ldr	r0, .L3417+8
20330
-	ldmfd	sp!, {r3, r4, r5, lr}
20834
+	pop	{r4, r5, r6, lr}
20835
+	ldr	r0, .L3341
20836
+.L3340:
20331
20837
 	b	get_new_active_ppa
20332
-.L3418:
20838
+.L3342:
20333
20839
 	.align	2
20334
-.L3417:
20840
+.L3341:
20335
20841
 	.word	.LANCHOR2-3424
20336
20842
 	.word	.LANCHOR2
20337
-	.word	.LANCHOR2-3428
20338
20843
 	.fnend
20339
20844
 	.size	Ftl_get_new_temp_ppa, .-Ftl_get_new_temp_ppa
20340
20845
 	.align	2
20341
20846
 	.global	ftl_do_gc
20847
+	.syntax unified
20848
+	.arm
20849
+	.fpu softvfp
20342
20850
 	.type	ftl_do_gc, %function
20343
20851
 ftl_do_gc:
20344
20852
 	.fnstart
20345
20853
 	@ args = 0, pretend = 0, frame = 32
20346
20854
 	@ frame_needed = 0, uses_anonymous_args = 0
20347
-	ldr	r3, .L3583
20348
-	ldr	ip, [r3, #-3616]
20349
-	cmp	ip, #0
20350
-	bne	.L3513
20351
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
20855
+	ldr	r3, .L3507
20856
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
20352
20857
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
20858
+	mov	lr, r0
20353
20859
 	.pad #44
20354
20860
 	sub	sp, sp, #44
20355
-	ldr	r4, .L3583+4
20356
-	ldr	r8, [r4, #504]
20357
-	cmp	r8, #1
20358
-	bne	.L3515
20861
+	ldr	r0, [r3, #-3612]
20862
+	cmp	r0, #0
20863
+	bne	.L3439
20864
+	ldr	ip, .L3507+4
20865
+	ldr	r5, [ip, #500]
20866
+	cmp	r5, #1
20867
+	bne	.L3343
20359
20868
 	ldr	r2, [r3, #-560]
20360
20869
 	cmp	r2, #0
20361
-	bne	.L3515
20362
-	mov	r9, r0
20363
-	sub	r0, r3, #3536
20364
-	ldrh	r0, [r0]
20870
+	bne	.L3343
20871
+	sub	r8, r3, #3520
20872
+	ldrh	r0, [r8, #-12]
20365
20873
 	cmp	r0, #47
20366
-	movls	r0, r2
20367
-	bls	.L3572
20368
-	movw	r2, #3448
20369
-	str	r1, [sp, #12]
20370
-	ldrh	r1, [r4, r2]
20874
+	bls	.L3439
20875
+	movw	r2, #3444
20876
+	mov	r7, r1
20877
+	ldrh	r1, [ip, r2]
20371
20878
 	movw	r2, #65535
20372
-	mov	r5, r3
20373
-	str	r9, [sp, #16]
20879
+	mov	r4, r3
20880
+	str	lr, [sp, #16]
20374
20881
 	cmp	r1, r2
20375
-	bne	.L3421
20376
-.L3424:
20377
-	ldr	r4, .L3583+8
20882
+	bne	.L3345
20883
+.L3348:
20884
+	ldr	r6, .L3507+8
20378
20885
 	movw	r2, #65535
20379
-	ldrh	r0, [r4, #-8]
20886
+	ldrh	r0, [r6, #-8]
20380
20887
 	cmp	r0, r2
20381
-	bne	.L3422
20382
-	b	.L3423
20383
-.L3421:
20384
-	sub	r3, r3, #3424
20385
-	ldrh	r3, [r3, #-4]
20386
-	cmp	r3, r2
20387
-	beq	.L3424
20388
-	mov	r0, r8
20389
-	bl	FtlGcFreeTempBlock
20390
-	cmp	r0, #0
20391
-	beq	.L3424
20392
-	mov	r0, r8
20393
-	b	.L3572
20394
-.L3422:
20395
-	ldrh	r3, [r4, #-10]
20396
-	cmp	r3, r2
20397
-	bne	.L3423
20398
-	ldrh	r1, [r4, #-6]
20399
-	cmp	r1, r3
20400
-	beq	.L3423
20401
-	ldrh	r2, [r4, #-4]
20402
-	cmp	r2, r3
20403
-	strneh	r0, [r4, #-10]	@ movhi
20404
-	strneh	r1, [r4, #-8]	@ movhi
20405
-	mvnne	r3, #0
20406
-	strneh	r2, [r4, #-6]	@ movhi
20407
-	strneh	r3, [r4, #-4]	@ movhi
20408
-.L3423:
20409
-	ldr	r3, [sp, #16]
20410
-	ldr	r8, [r5, #-2716]
20411
-	ldr	r6, .L3583+12
20412
-	cmp	r3, #1
20413
-	add	r8, r8, #1
20414
-	add	r8, r8, r3, asl #7
20415
-	sub	r7, r6, #240
20416
-	str	r8, [r5, #-2716]
20417
-	bne	.L3435
20418
-	ldr	r9, .L3583+16
20419
-	ldr	r3, [r9, #2244]
20420
-	cmp	r3, #0
20421
-	bne	.L3426
20422
-	ldrb	r3, [r9, #144]	@ zero_extendqisi2
20423
-	cmp	r3, #0
20424
-	beq	.L3435
20425
-.L3426:
20426
-	ldr	r3, [r5, #-3308]
20427
-	ldr	fp, .L3583
20428
-	cmp	r3, #39
20429
-	bhi	.L3435
20430
-	ldr	r10, .L3583+20
20431
-	ldrh	r3, [r10]
20432
-	add	r8, r8, r3
20433
-	str	r8, [fp, #-2716]
20434
-	bl	FtlGcReFreshBadBlk
20435
-	ldrh	r8, [r6, #-4]
20436
-	movw	r3, #65535
20437
-	cmp	r8, r3
20438
-	bne	.L3435
20439
-	ldrh	r3, [r4, #-10]
20440
-	cmp	r3, r8
20441
-	bne	.L3435
20442
-	ldr	r3, [fp, #-2716]
20443
-	cmp	r3, #1024
20444
-	bhi	.L3427
20445
-	ldrh	r3, [r7, #-8]
20446
-	cmp	r3, #63
20447
-	bhi	.L3435
20448
-.L3427:
20449
-	ldr	r1, .L3583
20450
-	mov	r3, #0
20451
-	strh	r3, [r10]	@ movhi
20452
-	sub	r8, r1, #2704
20453
-	ldrh	r0, [r7, #-8]
20454
-	ldr	r2, .L3583+20
20455
-	ldrh	r10, [r8, #-14]
20456
-	add	ip, r10, #64
20457
-	cmp	r0, ip
20458
-	bgt	.L3435
20459
-	str	r3, [r1, #-2716]
20460
-	ldr	r3, [r1, #-3308]
20461
-	cmp	r3, #0
20462
-	moveq	r3, #6
20463
-	beq	.L3574
20464
-	cmp	r3, #5
20465
-	bhi	.L3429
20466
-	mov	r3, #18
20467
-.L3574:
20468
-	strh	r3, [r2]	@ movhi
20469
-.L3429:
20470
-	mov	r0, #32
20471
-	bl	List_get_gc_head_node
20472
-	movw	ip, #65535
20473
-	uxth	r3, r0
20474
-	cmp	r3, ip
20475
-	beq	.L3434
20476
-	ldrh	r0, [r8, #-8]
20477
-	ldr	r2, .L3583
20478
-	cmp	r0, #0
20479
-	sub	r10, r2, #2704
20480
-	beq	.L3431
20481
-	mov	r8, r3, asl #1
20482
-	movw	r3, #2390
20483
-	ldrh	lr, [r9, r3]
20484
-	ldr	r3, .L3583+24
20485
-	ldr	r2, [r2, #-3544]
20486
-	ldrh	r3, [r3]
20487
-	ldrh	r1, [r2, r8]
20488
-	mul	r3, r3, lr
20888
+	bne	.L3346
20889
+.L3347:
20890
+	ldr	r3, [r4, #-2716]
20891
+	ldr	r2, [sp, #16]
20489
20892
 	add	r3, r3, #1
20893
+	cmp	r2, #1
20894
+	add	r3, r3, r2, lsl #7
20895
+	str	r3, [r4, #-2716]
20896
+	bne	.L3349
20897
+	ldr	r9, .L3507+12
20898
+	ldr	r2, [r9, #2248]
20899
+	cmp	r2, #0
20900
+	bne	.L3350
20901
+	ldrb	r2, [r9, #152]	@ zero_extendqisi2
20902
+	cmp	r2, #0
20903
+	beq	.L3349
20904
+.L3350:
20905
+	ldr	r2, [r4, #-3308]
20906
+	cmp	r2, #39
20907
+	bhi	.L3349
20908
+	ldr	r10, .L3507+16
20909
+	movw	r5, #65535
20910
+	ldrh	r2, [r10]
20911
+	add	r3, r2, r3
20912
+	str	r3, [r4, #-2716]
20913
+	bl	FtlGcReFreshBadBlk
20914
+	ldr	r3, .L3507+20
20915
+	mov	r2, r10
20916
+	ldrh	r3, [r3, #-4]
20917
+	cmp	r3, r5
20918
+	bne	.L3351
20919
+	ldrh	r1, [r6, #-10]
20490
20920
 	cmp	r1, r3
20491
-	bgt	.L3434
20492
-	add	r1, r0, #1
20493
-	str	ip, [sp, #28]
20494
-	str	r2, [sp, #24]
20495
-	mov	r9, #0
20496
-	uxth	r1, r1
20497
-	str	r9, [r10, #-4]
20498
-	strh	r1, [r10, #-8]	@ movhi
20499
-	str	r1, [sp, #20]
20921
+	bne	.L3438
20922
+	ldr	r3, [r4, #-2716]
20923
+	cmp	r3, #1024
20924
+	bhi	.L3353
20925
+	ldrh	r3, [r8, #-4]
20926
+	cmp	r3, #63
20927
+	bhi	.L3438
20928
+.L3353:
20929
+	ldr	r6, .L3507+24
20930
+	mov	r1, #0
20931
+	ldrh	r0, [r8, #-4]
20932
+	strh	r1, [r2]	@ movhi
20933
+	ldrh	r3, [r6, #-14]
20934
+	add	r3, r3, #64
20935
+	cmp	r0, r3
20936
+	bgt	.L3438
20937
+	ldr	r3, [r4, #-3308]
20938
+	str	r1, [r4, #-2716]
20939
+	cmp	r3, r1
20940
+	moveq	r3, #6
20941
+	beq	.L3499
20942
+	cmp	r3, #5
20943
+	bhi	.L3355
20944
+	mov	r3, #18
20945
+.L3499:
20946
+	strh	r3, [r2]	@ movhi
20947
+.L3355:
20948
+	mov	r0, #32
20949
+	movw	r10, #65535
20500
20950
 	bl	List_get_gc_head_node
20501
-	ldr	ip, [sp, #28]
20502
-	uxth	fp, r0
20503
-	ldr	r1, [sp, #20]
20504
-	cmp	fp, ip
20505
-	ldr	r2, [sp, #24]
20506
-	beq	.L3434
20507
-	mov	ip, fp, asl #1
20508
-	ldr	r0, .L3583+28
20509
-	str	ip, [sp, #20]
20510
-	ldrh	r3, [r2, ip]
20511
-	ldrh	r2, [r2, r8]
20512
-	str	r2, [sp]
20513
-	mov	r2, fp
20951
+	uxth	r3, r0
20952
+	cmp	r3, r10
20953
+	beq	.L3359
20954
+	ldrh	ip, [r6, #-8]
20955
+	cmp	ip, #0
20956
+	beq	.L3357
20957
+	movw	r2, #2392
20958
+	uxth	r0, r0
20959
+	ldrh	lr, [r9, r2]
20960
+	movw	r2, #2324
20961
+	ldrh	r2, [r9, r2]
20962
+	lsl	r1, r0, #1
20963
+	ldr	r3, [r4, #-3540]
20964
+	str	r1, [sp, #12]
20965
+	mul	r2, r2, lr
20966
+	ldrh	r0, [r3, r1]
20967
+	str	r3, [sp, #8]
20968
+	add	r2, r2, #1
20969
+	cmp	r0, r2
20970
+	bgt	.L3359
20971
+	add	fp, ip, #1
20972
+	mov	r9, #0
20973
+	uxth	fp, fp
20974
+	mov	r0, ip
20975
+	str	r9, [r4, #-2708]
20976
+	strh	fp, [r6, #-8]	@ movhi
20977
+	bl	List_get_gc_head_node
20978
+	uxth	r5, r0
20979
+	ldr	r3, [sp, #8]
20980
+	ldr	r1, [sp, #12]
20981
+	cmp	r5, r10
20982
+	beq	.L3359
20983
+	lsl	r10, r5, #1
20984
+	mov	r2, r5
20985
+	ldrh	r0, [r3, r10]
20986
+	ldrh	r3, [r3, r1]
20987
+	mov	r1, fp
20988
+	str	r3, [sp]
20989
+	mov	r3, r0
20990
+	ldr	r0, .L3507+28
20514
20991
 	bl	printk
20515
-	ldrh	r3, [r10, #-8]
20992
+	ldrh	r3, [r6, #-8]
20516
20993
 	cmp	r3, #40
20517
-	ldr	ip, [sp, #20]
20518
-	bls	.L3432
20519
-	ldr	r3, [r10, #-840]
20520
-	ldrh	r3, [r3, ip]
20994
+	bls	.L3358
20995
+	ldr	r3, [r4, #-3540]
20996
+	ldrh	r3, [r3, r10]
20521
20997
 	cmp	r3, #32
20522
-	strhih	r9, [r10, #-8]	@ movhi
20523
-.L3432:
20524
-	ldr	r3, .L3583+20
20998
+	strhhi	r9, [r6, #-8]	@ movhi
20999
+.L3358:
21000
+	ldr	r3, .L3507+16
20525
21001
 	mov	r2, #6
20526
21002
 	strh	r2, [r3]	@ movhi
20527
-	b	.L3436
20528
-.L3431:
21003
+.L3351:
21004
+	movw	r0, #65535
21005
+	ldr	r3, [sp, #16]
21006
+	sub	r2, r5, r0
21007
+	clz	r2, r2
21008
+	lsr	r2, r2, #5
21009
+	cmp	r3, #0
21010
+	movne	r1, #0
21011
+	andeq	r1, r2, #1
21012
+	cmp	r1, #0
21013
+	beq	.L3373
21014
+	ldrh	r3, [r8, #-4]
21015
+	cmp	r3, #24
21016
+	movhi	r6, #1
21017
+	bhi	.L3374
21018
+	ldr	r1, .L3507+12
21019
+	movw	r2, #2390
21020
+	cmp	r3, #16
21021
+	ldrh	r6, [r1, r2]
21022
+	lsrhi	r6, r6, #5
21023
+	bhi	.L3374
21024
+	cmp	r3, #12
21025
+	lsrhi	r6, r6, #4
21026
+	bhi	.L3374
21027
+	cmp	r3, #8
21028
+	lsrhi	r6, r6, #2
21029
+.L3374:
21030
+	ldr	r1, .L3507+32
21031
+	ldrh	r2, [r1]
21032
+	cmp	r2, r3
21033
+	mov	r2, r1
21034
+	bcs	.L3378
21035
+	sub	r3, r1, #704
21036
+	movw	r0, #65535
21037
+	ldrh	r3, [r3]
21038
+	cmp	r3, r0
21039
+	bne	.L3379
21040
+	ldrh	r0, [r1, #54]
21041
+	cmp	r0, r3
21042
+	bne	.L3379
21043
+	ldr	r3, .L3507+16
21044
+	ldrh	r0, [r3]
21045
+	cmp	r0, #0
21046
+	bne	.L3380
21047
+	ldr	r3, .L3507+12
21048
+	ldr	ip, [r4, #-3368]
21049
+	ldr	r3, [r3, #2452]
21050
+	add	r3, r3, r3, lsl #1
21051
+	cmp	ip, r3, lsr #2
21052
+	movcs	r3, #18
21053
+	strhcs	r3, [r1]	@ movhi
21054
+	bcs	.L3382
21055
+.L3380:
21056
+	ldr	r3, .L3507+36
21057
+	ldrh	r3, [r3, #-8]
21058
+	add	r3, r3, r3, lsl #1
21059
+	asr	r3, r3, #2
21060
+	strh	r3, [r2]	@ movhi
21061
+.L3382:
21062
+	mov	r3, #0
21063
+	str	r3, [r4, #-2708]
21064
+.L3343:
21065
+	add	sp, sp, #44
21066
+	@ sp needed
21067
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
21068
+.L3345:
21069
+	sub	r3, r3, #3424
21070
+	ldrh	r3, [r3]
21071
+	cmp	r3, r2
21072
+	beq	.L3348
21073
+	mov	r0, r5
21074
+	bl	FtlGcFreeTempBlock
21075
+	cmp	r0, #0
21076
+	beq	.L3348
21077
+	mov	r0, r5
21078
+	b	.L3343
21079
+.L3346:
21080
+	ldrh	r3, [r6, #-10]
21081
+	cmp	r3, r2
21082
+	bne	.L3347
21083
+	ldrh	r1, [r6, #-6]
21084
+	cmp	r1, r3
21085
+	beq	.L3347
21086
+	ldrh	r2, [r6, #-4]
21087
+	cmp	r2, r3
21088
+	mvnne	r3, #0
21089
+	strhne	r0, [r6, #-10]	@ movhi
21090
+	strhne	r1, [r6, #-8]	@ movhi
21091
+	strhne	r2, [r6, #-6]	@ movhi
21092
+	strhne	r3, [r6, #-4]	@ movhi
21093
+	b	.L3347
21094
+.L3357:
20529
21095
 	mov	r3, #1
20530
-	strh	r3, [r10, #-8]	@ movhi
20531
-.L3434:
21096
+	strh	r3, [r6, #-8]	@ movhi
21097
+.L3359:
20532
21098
 	bl	GetSwlReplaceBlock
20533
21099
 	movw	r3, #65535
21100
+	mov	r5, r0
20534
21101
 	cmp	r0, r3
20535
-	mov	fp, r0
20536
-	bne	.L3436
20537
-	ldr	r3, .L3583+20
21102
+	bne	.L3351
21103
+	ldr	r3, .L3507+16
20538
21104
 	mov	r2, #0
20539
21105
 	strh	r2, [r3]	@ movhi
20540
-.L3435:
20541
-	ldrh	ip, [r6, #-4]
21106
+.L3349:
21107
+	ldr	r3, .L3507+20
21108
+	movw	r5, #65535
21109
+	ldrh	r3, [r3, #-4]
21110
+	cmp	r3, r5
21111
+	bne	.L3351
21112
+.L3438:
21113
+	ldr	r6, .L3507+40
20542
21114
 	movw	r3, #65535
20543
-	ldr	r8, .L3583
20544
-	cmp	ip, r3
20545
-	bne	.L3577
20546
-	sub	r3, r8, #3424
20547
-	ldrh	r3, [r3, #-4]
20548
-	cmp	r3, ip
20549
-	movne	fp, ip
20550
-	beq	.L3580
20551
-.L3436:
20552
-	movw	r1, #65535
20553
-	rsb	r3, r1, fp
20554
-	clz	r3, r3
20555
-	ldr	r2, [sp, #16]
20556
-	ldr	r8, .L3583+32
20557
-	mov	r3, r3, lsr #5
20558
-	cmp	r2, #0
20559
-	movne	ip, #0
20560
-	andeq	ip, r3, #1
20561
-	cmp	ip, #0
20562
-	beq	.L3449
20563
-	ldrh	r0, [r8, #-8]
20564
-	cmp	r0, #24
20565
-	movhi	r9, #1
20566
-	bhi	.L3450
20567
-	ldr	r2, .L3583+16
20568
-	movw	r3, #2388
20569
-	cmp	r0, #16
20570
-	ldrh	r9, [r2, r3]
20571
-	movhi	r9, r9, lsr #5
20572
-	bhi	.L3450
20573
-	cmp	r0, #12
20574
-	movhi	r9, r9, lsr #4
20575
-	bhi	.L3450
20576
-	cmp	r0, #8
20577
-	movhi	r9, r9, lsr #2
20578
-.L3450:
20579
-	ldr	r1, .L3583
20580
-	sub	r2, r1, #2720
20581
-	ldrh	r3, [r2]
20582
-	cmp	r3, r0
20583
-	bcs	.L3454
20584
-	sub	r3, r1, #3424
20585
-	movw	r0, #65535
20586
-	ldrh	r3, [r3, #-4]
20587
-	cmp	r3, r0
20588
-	bne	.L3455
20589
-	ldrh	r0, [r4, #-10]
20590
-	cmp	r0, r3
20591
-	bne	.L3455
20592
-	ldr	r3, .L3583+20
20593
-	ldrh	r0, [r3]
20594
-	cmp	r0, #0
20595
-	bne	.L3456
20596
-	ldr	r3, .L3583+16
20597
-	ldr	r1, [r1, #-3372]
20598
-	ldr	r3, [r3, #2448]
20599
-	add	r3, r3, r3, asl #1
20600
-	cmp	r1, r3, lsr #2
20601
-	movcs	r3, #18
20602
-	bcs	.L3457
20603
-.L3456:
20604
-	ldr	r3, .L3583+36
20605
-	ldrh	r3, [r3, #-8]
20606
-	add	r3, r3, r3, asl #1
20607
-	ubfx	r3, r3, #2, #16
20608
-.L3457:
20609
-	strh	r3, [r2]	@ movhi
21115
+	ldrh	r5, [r6]
21116
+	cmp	r5, r3
21117
+	movne	r5, r3
21118
+	bne	.L3351
21119
+	add	r3, r6, #768
21120
+	ldrh	r9, [r3, #-10]
21121
+	cmp	r9, r5
21122
+	bne	.L3351
21123
+	ldrh	r3, [r8, #-4]
21124
+	ldr	r2, [r4, #-2716]
21125
+	cmp	r3, #24
21126
+	movcc	r3, #5120
21127
+	movcs	r3, #1024
21128
+	cmp	r2, r3
21129
+	bls	.L3351
21130
+	ldr	r2, .L3507+16
20610
21131
 	mov	r3, #0
20611
-	str	r3, [r5, #-2708]
20612
-	b	.L3572
20613
-.L3455:
20614
-	ldr	r3, .L3583+36
20615
-	ldrh	r3, [r3, #-8]
20616
-	add	r3, r3, r3, asl #1
20617
-	mov	r3, r3, asr #2
21132
+	str	r3, [r4, #-2716]
20618
21133
 	strh	r3, [r2]	@ movhi
20619
-.L3454:
20620
-	ldr	r3, .L3583+16
20621
-	movw	fp, #65535
20622
-	ldr	r2, [r3, #2244]
20623
-	ldr	r3, [sp, #12]
20624
-	cmp	r3, #2
20625
-	movhi	r3, #0
20626
-	movls	r3, #1
21134
+	bl	GetSwlReplaceBlock
21135
+	cmp	r0, r9
21136
+	mov	r5, r0
21137
+	movne	r10, r0
21138
+	bne	.L3361
21139
+	add	r6, r6, #720
21140
+	ldrh	r2, [r8, #-4]
21141
+	ldrh	r3, [r6, #-14]
21142
+	mov	r9, r6
21143
+	cmp	r2, r3
21144
+	movcs	r3, #80
21145
+	strhcs	r3, [r6, #-14]	@ movhi
21146
+	bcs	.L3364
21147
+	mov	r0, #64
21148
+	bl	List_get_gc_head_node
21149
+	uxth	r3, r0
21150
+	cmp	r3, r5
21151
+	beq	.L3364
21152
+	ldr	r3, [r4, #-564]
21153
+	ldr	r6, .L3507+12
21154
+	cmp	r3, #0
21155
+	uxth	r3, r0
21156
+	bne	.L3365
21157
+	movw	r2, #2344
21158
+	ldrh	r2, [r6, r2]
21159
+	cmp	r2, #3
21160
+	beq	.L3365
21161
+	ldr	r2, [r4, #-2724]
20627
21162
 	cmp	r2, #0
20628
-	moveq	r3, #0
20629
-	cmp	r3, #0
20630
-	addne	r9, r9, #1
20631
-	uxthne	r9, r9
20632
-	b	.L3459
20633
-.L3449:
20634
-	ldrh	r0, [r8, #92]
20635
-	add	r2, r8, #3520
20636
-	cmp	r0, r1
20637
-	bne	.L3460
20638
-	ldrh	r1, [r4, #-10]
20639
-	cmp	r1, r0
21163
+	bne	.L3365
21164
+	ldr	r2, [r6, #2248]
21165
+	cmp	r2, #0
21166
+	bne	.L3365
21167
+	ldrb	r0, [r6, #152]	@ zero_extendqisi2
21168
+	cmp	r0, #0
21169
+	beq	.L3366
21170
+.L3365:
21171
+	ldr	r2, [r4, #-3540]
21172
+	lsl	r3, r3, #1
21173
+	movw	r0, #2344
21174
+	ldrh	r0, [r6, r0]
21175
+	ldrh	r1, [r2, r3]
21176
+	movw	r3, #2392
21177
+	movw	r2, #2324
21178
+	ldrh	r3, [r6, r3]
21179
+	ldrh	r2, [r6, r2]
21180
+	cmp	r0, #3
21181
+	mul	r2, r3, r2
21182
+	lsreq	r3, r3, #1
20640
21183
 	movne	r3, #0
20641
-	andeq	r3, r3, #1
20642
-	cmp	r3, #0
20643
-	beq	.L3460
20644
-	ldrh	r3, [r6, #-4]
20645
-	cmp	r3, r0
20646
-	beq	.L3461
20647
-.L3465:
20648
-	movw	fp, #65535
20649
-	b	.L3460
20650
-.L3461:
20651
-	sub	r10, r2, #2720
20652
-	ldrh	r1, [r7, #-8]
20653
-	str	ip, [r2, #-2708]
20654
-	ldrh	r3, [r10]
20655
-	ldr	r9, .L3583+20
21184
+	add	r3, r3, r2
20656
21185
 	cmp	r1, r3
20657
-	bls	.L3462
20658
-	ldrh	r3, [r9]
21186
+	bgt	.L3368
21187
+	mov	r0, #0
21188
+	bl	List_get_gc_head_node
21189
+	ldr	r3, [r6, #2452]
21190
+	uxth	r10, r0
21191
+	ldr	r2, [r4, #-3368]
21192
+	add	r3, r3, r3, lsl #1
21193
+	cmp	r2, r3, lsr #2
21194
+	movls	r3, #160
21195
+	bls	.L3500
21196
+.L3501:
21197
+	mov	r3, #128
21198
+.L3500:
21199
+	strh	r3, [r9, #-14]	@ movhi
21200
+	movw	r3, #65535
21201
+	cmp	r10, r3
21202
+	beq	.L3364
21203
+.L3361:
21204
+	ldr	r0, .L3507+32
21205
+	lsl	r1, r10, #1
21206
+	ldr	r3, [r4, #-3540]
21207
+	mov	r5, r10
21208
+	ldrh	r2, [r8, #-4]
21209
+	ldrh	r0, [r0]
21210
+	ldrh	r3, [r3, r1]
21211
+	str	r0, [sp, #4]
21212
+	ldr	r0, [r4, #-3604]
21213
+	ldrh	r1, [r0, r1]
21214
+	ldr	r0, .L3507+44
21215
+	str	r1, [sp]
21216
+	mov	r1, r10
21217
+	bl	printk
21218
+	b	.L3364
21219
+.L3368:
21220
+	mov	r3, #128
21221
+.L3502:
21222
+	strh	r3, [r9, #-14]	@ movhi
21223
+.L3364:
21224
+	bl	FtlGcReFreshBadBlk
21225
+	b	.L3351
21226
+.L3366:
21227
+	ldr	r2, [r4, #-3540]
21228
+	lsl	r3, r3, #1
21229
+	ldrh	r3, [r2, r3]
21230
+	cmp	r3, #7
21231
+	bhi	.L3371
21232
+	bl	List_get_gc_head_node
21233
+	uxth	r10, r0
21234
+	b	.L3501
21235
+.L3371:
21236
+	mov	r3, #64
21237
+	b	.L3502
21238
+.L3379:
21239
+	ldr	r3, .L3507+36
21240
+	ldrh	r3, [r3, #-8]
21241
+	add	r3, r3, r3, lsl #1
21242
+	asr	r3, r3, #2
21243
+	strh	r3, [r2]	@ movhi
21244
+.L3378:
21245
+	ldr	r3, .L3507+12
21246
+	movw	r5, #65535
21247
+	ldr	r3, [r3, #2248]
21248
+	adds	r3, r3, #0
21249
+	movne	r3, #1
21250
+	cmp	r7, #2
21251
+	movhi	r3, #0
20659
21252
 	cmp	r3, #0
20660
-	bne	.L3463
20661
-	ldr	r3, .L3583+16
20662
-	ldr	r2, [r2, #-3372]
20663
-	ldr	r3, [r3, #2448]
20664
-	add	r3, r3, r3, asl #1
21253
+	addne	r6, r6, #1
21254
+	uxthne	r6, r6
21255
+.L3384:
21256
+	ldr	r7, .L3507+20
21257
+	movw	r2, #65535
21258
+	ldrh	r3, [r7, #-4]
21259
+	cmp	r3, r2
21260
+	bne	.L3394
21261
+	cmp	r5, r3
21262
+	strhne	r5, [r7, #-4]	@ movhi
21263
+	bne	.L3396
21264
+	add	r3, r7, #624
21265
+	ldrh	r2, [r3, #-10]
21266
+	cmp	r2, r5
21267
+	beq	.L3396
21268
+	ldr	r1, [r4, #-3540]
21269
+	lsl	r2, r2, #1
21270
+	ldrh	r2, [r1, r2]
21271
+	cmp	r2, #0
21272
+	mvneq	r2, #0
21273
+	strheq	r2, [r3, #-10]	@ movhi
21274
+	ldrh	r2, [r3, #-10]
21275
+	strh	r2, [r7, #-4]	@ movhi
21276
+	mvn	r2, #0
21277
+	strh	r2, [r3, #-10]	@ movhi
21278
+.L3396:
21279
+	ldrh	r0, [r7, #-4]
21280
+	mov	r3, #0
21281
+	strb	r3, [r4, #-3276]
21282
+	movw	r3, #65535
21283
+	cmp	r0, r3
21284
+	beq	.L3394
21285
+	bl	IsBlkInGcList
21286
+	cmp	r0, #0
21287
+	mvnne	r3, #0
21288
+	strhne	r3, [r7, #-4]	@ movhi
21289
+	ldr	r3, .L3507+12
21290
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
21291
+	cmp	r3, #0
21292
+	beq	.L3400
21293
+	ldrh	r0, [r7, #-4]
21294
+	bl	ftl_get_blk_mode
21295
+	strb	r0, [r4, #-3276]
21296
+.L3400:
21297
+	ldrh	r2, [r7, #-4]
21298
+	movw	r3, #65535
21299
+	sub	r9, r7, #4
21300
+	cmp	r2, r3
21301
+	beq	.L3394
21302
+	mov	r0, r9
21303
+	bl	make_superblock
21304
+	mov	r3, #0
21305
+	movw	r2, #1986
21306
+	strh	r3, [r4, r2]	@ movhi
21307
+	strh	r3, [r7, #-2]	@ movhi
21308
+	strb	r3, [r4, #-3278]
21309
+	ldrh	r3, [r7, #-4]
21310
+	ldr	r2, [r4, #-3540]
21311
+	lsl	r3, r3, #1
21312
+	ldrh	r2, [r2, r3]
21313
+	movw	r3, #1988
21314
+	strh	r2, [r4, r3]	@ movhi
21315
+.L3394:
21316
+	ldrh	r3, [r7, #-4]
21317
+	ldrh	r2, [r8]
21318
+	cmp	r2, r3
21319
+	beq	.L3401
21320
+	ldr	r2, .L3507+48
21321
+	ldrh	r1, [r2]
21322
+	cmp	r1, r3
21323
+	beq	.L3401
21324
+	ldrh	r2, [r2, #48]
21325
+	cmp	r2, r3
21326
+	bne	.L3402
21327
+.L3401:
21328
+	mvn	r3, #0
21329
+	strh	r3, [r7, #-4]	@ movhi
21330
+.L3402:
21331
+	ldr	r4, .L3507
21332
+	sub	r7, r4, #3280
21333
+.L3435:
21334
+	ldrh	r2, [r7, #-4]
21335
+	movw	r3, #65535
21336
+	cmp	r2, r3
21337
+	bne	.L3403
21338
+	ldr	r9, .L3507+24
21339
+	mov	r3, #0
21340
+	ldr	r10, .L3507+52
21341
+	str	r3, [r4, #-2708]
21342
+.L3404:
21343
+	ldr	fp, .L3507+56
21344
+	ldrh	r8, [fp]
21345
+	mov	r0, r8
21346
+	bl	List_get_gc_head_node
21347
+	uxth	r2, r0
21348
+	sub	r1, fp, #568
21349
+	strh	r2, [r1, #-4]	@ movhi
21350
+	movw	r1, #65535
21351
+	cmp	r2, r1
21352
+	bne	.L3405
21353
+	mov	r3, #0
21354
+	mov	r0, #8
21355
+	strh	r3, [fp]	@ movhi
21356
+	b	.L3343
21357
+.L3373:
21358
+	ldr	r3, .L3507+40
21359
+	ldrh	r7, [r3]
21360
+	cmp	r7, r0
21361
+	bne	.L3385
21362
+	add	r0, r3, #768
21363
+	ldrh	r0, [r0, #-10]
21364
+	cmp	r0, r7
21365
+	movne	r2, #0
21366
+	andeq	r2, r2, #1
21367
+	cmp	r2, #0
21368
+	beq	.L3385
21369
+	ldrh	r2, [r3, #140]
21370
+	cmp	r2, r7
21371
+	beq	.L3386
21372
+.L3391:
21373
+	mov	r5, r7
21374
+.L3385:
21375
+	ldr	r3, .L3507+12
21376
+	ldr	r3, [r3, #2248]
21377
+	cmp	r3, #0
21378
+	moveq	r6, #1
21379
+	movne	r6, #2
21380
+	b	.L3384
21381
+.L3386:
21382
+	add	r5, r3, #704
21383
+	ldrh	r2, [r8, #-4]
21384
+	ldrh	r3, [r5]
21385
+	str	r1, [r4, #-2708]
21386
+	ldr	r6, .L3507+16
21387
+	cmp	r2, r3
21388
+	bls	.L3387
21389
+	ldrh	r3, [r6]
21390
+	cmp	r3, #0
21391
+	bne	.L3388
21392
+	ldr	r3, .L3507+12
21393
+	ldr	r2, [r4, #-3368]
21394
+	ldr	r3, [r3, #2452]
21395
+	add	r3, r3, r3, lsl #1
20665
21396
 	cmp	r2, r3, lsr #2
20666
21397
 	movcs	r3, #18
20667
-	bcs	.L3464
20668
-.L3463:
20669
-	ldr	r3, .L3583+36
21398
+	bcs	.L3503
21399
+.L3388:
21400
+	ldr	r3, .L3507+36
20670
21401
 	ldrh	r3, [r3, #-8]
20671
-	add	r3, r3, r3, asl #1
20672
-	ubfx	r3, r3, #2, #16
20673
-.L3464:
20674
-	strh	r3, [r10]	@ movhi
21402
+	add	r3, r3, r3, lsl #1
21403
+	asr	r3, r3, #2
21404
+.L3503:
21405
+	strh	r3, [r5]	@ movhi
20675
21406
 	bl	FtlReadRefresh
20676
21407
 	mov	r0, #0
20677
21408
 	bl	List_get_gc_head_node
20678
-	ldr	r3, [r5, #-3544]
20679
21409
 	uxth	r0, r0
20680
-	mov	r0, r0, asl #1
21410
+	ldr	r3, [r4, #-3540]
21411
+	lsl	r0, r0, #1
20681
21412
 	ldrh	r3, [r3, r0]
20682
21413
 	cmp	r3, #4
20683
-	ldrhih	r0, [r9]
20684
-	bhi	.L3572
20685
-.L3462:
20686
-	ldrh	r0, [r9]
21414
+	bls	.L3387
21415
+.L3504:
21416
+	ldrh	r0, [r6]
21417
+	b	.L3343
21418
+.L3387:
21419
+	ldrh	r0, [r6]
20687
21420
 	cmp	r0, #0
20688
-	bne	.L3465
20689
-	ldr	r3, .L3583+36
21421
+	bne	.L3391
21422
+	ldr	r3, .L3507+36
20690
21423
 	ldrh	r9, [r3, #-8]
20691
-	add	r3, r9, r9, asl #1
20692
-	mov	r3, r3, asr #2
20693
-	strh	r3, [r10]	@ movhi
21424
+	add	r3, r9, r9, lsl #1
21425
+	asr	r3, r3, #2
21426
+	strh	r3, [r5]	@ movhi
20694
21427
 	bl	List_get_gc_head_node
20695
-	ldr	r3, [r5, #-3544]
20696
-	movw	r2, #2390
20697
21428
 	uxth	r0, r0
20698
-	mov	r0, r0, asl #1
21429
+	ldr	r3, [r4, #-3540]
21430
+	ldr	r2, .L3507+12
21431
+	lsl	r0, r0, #1
20699
21432
 	ldrh	r1, [r3, r0]
20700
-	ldr	r3, .L3583+16
20701
-	ldrh	r2, [r3, r2]
20702
-	add	r3, r3, #2320
20703
-	ldrh	r3, [r3]
20704
-	mul	r3, r3, r2
21433
+	movw	r3, #2392
21434
+	ldrh	r0, [r2, r3]
21435
+	movw	r3, #2324
21436
+	ldrh	r3, [r2, r3]
21437
+	mul	r3, r3, r0
20705
21438
 	add	r3, r3, r3, lsr #31
20706
21439
 	cmp	r1, r3, asr #1
20707
-	ble	.L3466
20708
-	ldrh	r3, [r7, #-8]
20709
-	sub	r2, r9, #1
20710
-	cmp	r3, r2
20711
-	blt	.L3466
20712
-	bl	FtlReadRefresh
20713
-	b	.L3578
20714
-.L3466:
20715
-	cmp	r1, #0
20716
-	bne	.L3465
20717
-	movw	r0, #65535
20718
-	bl	decrement_vpc_count
20719
-	ldrh	r0, [r8, #-8]
20720
-	add	r0, r0, #1
20721
-	b	.L3572
20722
-.L3460:
20723
-	ldr	r3, .L3583+16
20724
-	ldr	r3, [r3, #2244]
20725
-	cmp	r3, #0
20726
-	moveq	r9, #1
20727
-	movne	r9, #2
20728
-.L3459:
20729
-	ldrh	r3, [r6, #-4]
20730
-	movw	r0, #65535
20731
-	ldr	r2, .L3583
20732
-	cmp	r3, r0
20733
-	sub	r1, r2, #3280
20734
-	bne	.L3468
20735
-	cmp	fp, r3
20736
-	strneh	fp, [r1, #-4]	@ movhi
20737
-	bne	.L3470
20738
-	ldrh	r3, [r4, #-10]
20739
-	sub	r1, r2, #2656
20740
-	cmp	r3, fp
20741
-	beq	.L3470
20742
-	ldr	r2, [r2, #-3544]
20743
-	mov	r3, r3, asl #1
20744
-	ldrh	r3, [r2, r3]
20745
-	cmp	r3, #0
20746
-	mvneq	r3, #0
20747
-	streqh	r3, [r1, #-10]	@ movhi
20748
-	ldrh	r3, [r4, #-10]
20749
-	strh	r3, [r6, #-4]	@ movhi
20750
-	mvn	r3, #0
20751
-	strh	r3, [r4, #-10]	@ movhi
20752
-.L3470:
20753
-	ldrh	r0, [r6, #-4]
20754
-	mov	r3, #0
20755
-	strb	r3, [r5, #-3276]
20756
-	movw	r3, #65535
20757
-	cmp	r0, r3
20758
-	beq	.L3468
20759
-	bl	IsBlkInGcList
20760
-	cmp	r0, #0
20761
-	ldrne	r3, .L3583+12
20762
-	mvnne	r2, #0
20763
-	strneh	r2, [r3, #-4]	@ movhi
20764
-	ldr	r3, .L3583+16
20765
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
20766
-	cmp	r3, #0
20767
-	beq	.L3474
20768
-	ldrh	r0, [r6, #-4]
20769
-	bl	ftl_get_blk_mode
20770
-	strb	r0, [r5, #-3276]
20771
-.L3474:
20772
-	ldrh	r2, [r6, #-4]
20773
-	movw	r3, #65535
20774
-	ldr	r5, .L3583
20775
-	cmp	r2, r3
20776
-	sub	r7, r5, #3280
20777
-	sub	r4, r7, #4
20778
-	beq	.L3468
20779
-	mov	r0, r4
20780
-	bl	make_superblock
20781
-	ldr	r2, .L3583+40
20782
-	movw	r1, #1986
20783
-	mov	r3, #0
20784
-	strh	r3, [r7, #-2]	@ movhi
20785
-	strh	r3, [r2, r1]	@ movhi
20786
-	strb	r3, [r5, #-3278]
20787
-	ldrh	r3, [r7, #-4]
20788
-	ldr	r1, [r5, #-3544]
20789
-	mov	r3, r3, asl #1
20790
-	ldrh	r1, [r1, r3]
20791
-	movw	r3, #1988
20792
-	strh	r1, [r2, r3]	@ movhi
20793
-.L3468:
20794
-	ldrh	r3, [r6, #-4]
21440
+	ble	.L3392
20795
21441
 	ldrh	r2, [r8, #-4]
21442
+	sub	r3, r9, #1
20796
21443
 	cmp	r2, r3
20797
-	beq	.L3475
20798
-	ldr	r2, .L3583+44
20799
-	ldrh	r1, [r2, #-4]
20800
-	cmp	r1, r3
20801
-	beq	.L3475
20802
-	ldrh	r2, [r2, #44]
20803
-	cmp	r2, r3
20804
-	bne	.L3509
20805
-.L3475:
20806
-	mvn	r3, #0
20807
-	strh	r3, [r6, #-4]	@ movhi
20808
-.L3509:
20809
-	ldr	r6, .L3583+48
20810
-	movw	r3, #65535
20811
-	ldr	r5, .L3583
20812
-	ldrh	r2, [r6]
20813
-	mov	r10, r6
20814
-	cmp	r2, r3
20815
-	bne	.L3477
20816
-	mov	r3, #0
20817
-	str	r5, [sp, #12]
20818
-	str	r3, [r5, #-2708]
20819
-.L3478:
20820
-	ldr	r8, .L3583+52
20821
-	ldrh	r4, [r8]
20822
-	mov	r0, r4
20823
-	bl	List_get_gc_head_node
20824
-	movw	r3, #65535
20825
-	uxth	r7, r0
20826
-	strh	r7, [r10]	@ movhi
20827
-	cmp	r7, r3
20828
-	moveq	r3, #0
20829
-	moveq	r0, #8
20830
-	streqh	r3, [r8]	@ movhi
20831
-	beq	.L3572
20832
-.L3479:
20833
-	mov	r0, r7
20834
-	add	r4, r4, #1
20835
-	bl	IsBlkInGcList
20836
-	cmp	r0, #0
20837
-	ldrne	r3, .L3583+52
20838
-	strneh	r4, [r3]	@ movhi
20839
-	bne	.L3478
20840
-	ldr	r3, .L3583+52
20841
-	uxth	r4, r4
20842
-	mov	r2, r7, asl #1
20843
-	strh	r4, [r3]	@ movhi
20844
-	ldr	r3, [sp, #12]
20845
-	ldr	r1, [r3, #-3544]
20846
-	ldr	r3, .L3583+56
20847
-	ldrh	r0, [r1, r2]
20848
-	ldrh	ip, [r3]
20849
-	ldrh	r3, [r3, #-68]
20850
-	mul	r3, r3, ip
20851
-	add	ip, r3, r3, lsr #31
20852
-	cmp	r0, ip, asr #1
20853
-	bgt	.L3482
20854
-	cmp	r0, #8
20855
-	cmphi	r4, #48
20856
-	bls	.L3483
20857
-	ldrh	r0, [r8, #36]
20858
-	cmp	r0, #35
20859
-	bhi	.L3483
20860
-.L3482:
20861
-	ldr	ip, .L3583+52
20862
-	mov	r0, #0
20863
-	strh	r0, [ip]	@ movhi
20864
-.L3483:
20865
-	ldrh	r2, [r1, r2]
20866
-	movw	r1, #65535
20867
-	cmp	r2, r3
20868
-	cmpge	fp, r1
20869
-	bne	.L3484
20870
-	ldr	r3, .L3583+52
20871
-	ldrh	r1, [r3]
20872
-	cmp	r1, #3
20873
-	bhi	.L3484
20874
-	sub	r2, r3, #568
20875
-	mvn	r1, #0
20876
-	strh	r1, [r2, #-4]	@ movhi
20877
-	mov	r2, #0
20878
-	strh	r2, [r3]	@ movhi
20879
-.L3578:
20880
-	ldr	r3, .L3583+20
20881
-	ldrh	r0, [r3]
20882
-	b	.L3572
20883
-.L3484:
20884
-	cmp	r2, #0
20885
-	bne	.L3485
21444
+	blt	.L3392
21445
+	bl	FtlReadRefresh
21446
+	b	.L3504
21447
+.L3392:
21448
+	cmp	r1, #0
21449
+	bne	.L3391
20886
21450
 	movw	r0, #65535
20887
21451
 	bl	decrement_vpc_count
20888
-	ldr	r3, .L3583+52
20889
-	ldr	r2, .L3583+52
21452
+	ldrh	r0, [r8, #-4]
21453
+	add	r0, r0, #1
21454
+	b	.L3343
21455
+.L3405:
21456
+	str	r0, [sp, #12]
21457
+	mov	r0, r2
21458
+	str	r2, [sp, #8]
21459
+	add	r8, r8, #1
21460
+	bl	IsBlkInGcList
21461
+	cmp	r0, #0
21462
+	ldr	r2, [sp, #8]
21463
+	ldr	r3, [sp, #12]
21464
+	strhne	r8, [fp]	@ movhi
21465
+	bne	.L3404
21466
+	uxth	r3, r3
21467
+	ldrh	lr, [r10]
21468
+	ldr	r0, [r4, #-3540]
21469
+	uxth	r8, r8
21470
+	lsl	r1, r3, #1
21471
+	ldr	r3, .L3507+60
21472
+	strh	r8, [fp]	@ movhi
21473
+	ldrh	ip, [r0, r1]
20890
21474
 	ldrh	r3, [r3]
21475
+	mul	r3, r3, lr
21476
+	add	lr, r3, r3, lsr #31
21477
+	cmp	ip, lr, asr #1
21478
+	bgt	.L3408
21479
+	cmp	r8, #48
21480
+	cmphi	ip, #8
21481
+	bls	.L3409
21482
+	ldrh	ip, [fp, #36]
21483
+	cmp	ip, #35
21484
+	bhi	.L3409
21485
+.L3408:
21486
+	mov	ip, #0
21487
+	strh	ip, [r9, #-8]	@ movhi
21488
+.L3409:
21489
+	ldrh	r1, [r0, r1]
21490
+	movw	r0, #65535
21491
+	cmp	r3, r1
21492
+	cmple	r5, r0
21493
+	bne	.L3410
21494
+	ldrh	r0, [r9, #-8]
21495
+	cmp	r0, #3
21496
+	bhi	.L3410
21497
+	ldr	r1, .L3507+20
21498
+	mvn	r2, #0
21499
+	strh	r2, [r1, #-4]	@ movhi
21500
+	mov	r2, #0
21501
+	strh	r2, [r9, #-8]	@ movhi
21502
+.L3506:
21503
+	ldr	r3, .L3507+16
21504
+	b	.L3505
21505
+.L3410:
21506
+	cmp	r1, #0
21507
+	bne	.L3411
21508
+	movw	r0, #65535
21509
+	bl	decrement_vpc_count
21510
+	ldrh	r3, [r9, #-8]
20891
21511
 	add	r3, r3, #1
20892
-	strh	r3, [r2]	@ movhi
20893
-	b	.L3478
20894
-.L3485:
21512
+	strh	r3, [r9, #-8]	@ movhi
21513
+	b	.L3404
21514
+.L3411:
20895
21515
 	mov	r3, #0
20896
-	strb	r3, [r5, #-3276]
20897
-	ldr	r3, .L3583+16
20898
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
21516
+	strb	r3, [r4, #-3276]
21517
+	ldr	r3, .L3507+12
21518
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
20899
21519
 	cmp	r3, #0
20900
-	beq	.L3486
20901
-	mov	r0, r7
21520
+	beq	.L3412
21521
+	mov	r0, r2
20902
21522
 	bl	ftl_get_blk_mode
20903
-	ldr	r3, .L3583
20904
-	strb	r0, [r3, #-3276]
20905
-.L3486:
20906
-	ldr	r0, .L3583+48
21523
+	strb	r0, [r4, #-3276]
21524
+.L3412:
21525
+	ldr	r3, .L3507+20
21526
+	sub	r8, r3, #4
21527
+	mov	r0, r8
20907
21528
 	bl	make_superblock
20908
-	ldrh	r2, [r6]
20909
-	ldr	r1, .L3583+60
21529
+	add	r2, r8, #4
21530
+	ldr	r1, .L3507+64
21531
+	ldrh	r2, [r2, #-4]
20910
21532
 	mov	r3, #0
20911
-	ldr	r0, [r5, #-3544]
20912
-	mov	r2, r2, asl #1
21533
+	ldr	r0, [r4, #-3540]
20913
21534
 	strh	r3, [r1]	@ movhi
21535
+	lsl	r2, r2, #1
20914
21536
 	ldrh	r2, [r0, r2]
20915
-	strh	r3, [r6, #2]	@ movhi
20916
-	strb	r3, [r5, #-3278]
21537
+	strh	r3, [r8, #2]	@ movhi
21538
+	strb	r3, [r4, #-3278]
20917
21539
 	strh	r2, [r1, #2]	@ movhi
20918
-.L3477:
21540
+.L3403:
20919
21541
 	ldr	r3, [sp, #16]
20920
21542
 	cmp	r3, #1
20921
-	bne	.L3487
21543
+	bne	.L3413
20922
21544
 	bl	FtlReadRefresh
20923
-.L3487:
21545
+.L3413:
20924
21546
 	mov	r3, #1
20925
-	str	r3, [r5, #-560]
20926
-	ldr	r3, .L3583+56
21547
+	str	r3, [r4, #-560]
21548
+	ldr	r3, .L3507+52
20927
21549
 	ldrh	r3, [r3]
20928
-	str	r3, [sp, #12]
20929
-	ldr	r3, .L3583+16
20930
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
21550
+	str	r3, [sp, #8]
21551
+	ldr	r3, .L3507+12
21552
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
20931
21553
 	cmp	r3, #0
20932
-	beq	.L3488
20933
-	ldr	r3, .L3583
20934
-	ldrb	r3, [r3, #-3276]	@ zero_extendqisi2
21554
+	beq	.L3414
21555
+	ldrb	r3, [r4, #-3276]	@ zero_extendqisi2
20935
21556
 	cmp	r3, #1
20936
-	ldreq	r3, .L3583+64
20937
-	ldreqh	r3, [r3]
20938
-	streq	r3, [sp, #12]
20939
-.L3488:
20940
-	ldrh	r3, [r6, #2]
20941
-	mov	r6, #0
20942
-	ldr	r1, [sp, #12]
20943
-	add	r2, r3, r9
20944
-	ldr	r4, .L3583
21557
+	ldreq	r3, .L3507+68
21558
+	ldrheq	r3, [r3]
21559
+	streq	r3, [sp, #8]
21560
+.L3414:
21561
+	ldr	r3, .L3507+20
21562
+	ldr	r1, [sp, #8]
21563
+	ldrh	r3, [r3, #-2]
21564
+	add	r2, r3, r6
20945
21565
 	cmp	r2, r1
20946
21566
 	movgt	r2, r1
20947
-	rsbgt	r3, r3, r2
20948
-	uxthgt	r9, r3
20949
-.L3490:
20950
-	uxth	r3, r6
20951
-	ldr	r7, .L3583
20952
-	cmp	r3, r9
20953
-	ldr	r5, .L3583+48
20954
-	bcs	.L3497
20955
-	ldr	r3, .L3583+24
20956
-	add	r0, r5, #14
20957
-	ldrh	r1, [r5, #2]
20958
-	movw	lr, #65535
20959
-	ldr	r7, [r4, #-2688]
20960
-	mov	ip, #36
20961
-	ldrh	r8, [r3]
20962
-	add	r1, r1, r6
21567
+	subgt	r6, r2, r3
20963
21568
 	mov	r3, #0
20964
-	mov	r5, r3
20965
-.L3498:
20966
-	uxth	r2, r3
20967
-	cmp	r2, r8
20968
-	bcs	.L3581
20969
-	ldrh	r2, [r0, #2]!
20970
-	add	r3, r3, #1
20971
-	cmp	r2, lr
20972
-	orrne	r2, r1, r2, asl #10
20973
-	mlane	r10, ip, r5, r7
20974
-	addne	r5, r5, #1
20975
-	uxthne	r5, r5
20976
-	strne	r2, [r10, #4]
20977
-	b	.L3498
20978
-.L3581:
21569
+	uxthgt	r6, r6
21570
+	str	r3, [sp, #12]
21571
+	sub	r3, r7, #4
21572
+	str	r3, [sp, #20]
21573
+.L3416:
21574
+	ldrh	r3, [sp, #12]
21575
+	cmp	r6, r3
21576
+	bls	.L3423
21577
+	ldr	r3, .L3507+60
21578
+	add	ip, r7, #10
20979
21579
 	ldr	r0, [r4, #-2688]
20980
-	mov	r1, r5
21580
+	movw	r9, #65535
21581
+	mov	lr, #36
21582
+	ldrh	r10, [r3]
21583
+	ldr	r3, [sp, #20]
21584
+	ldrh	r1, [r3, #2]
21585
+	ldr	r3, [sp, #12]
21586
+	add	r1, r1, r3
21587
+	mov	r3, #0
21588
+	mov	r8, r3
21589
+	b	.L3424
21590
+.L3418:
21591
+	ldrh	r2, [ip, #2]!
21592
+	add	r3, r3, #1
21593
+	cmp	r2, r9
21594
+	mlane	fp, lr, r8, r0
21595
+	addne	r8, r8, #1
21596
+	orrne	r2, r1, r2, lsl #10
21597
+	uxthne	r8, r8
21598
+	strne	r2, [fp, #4]
21599
+.L3424:
21600
+	uxth	r2, r3
21601
+	cmp	r10, r2
21602
+	bhi	.L3418
21603
+	mov	fp, #0
20981
21604
 	ldrb	r2, [r4, #-3276]	@ zero_extendqisi2
20982
-	mov	r8, #0
21605
+	mov	r1, r8
20983
21606
 	bl	FlashReadPages
20984
-.L3493:
20985
-	uxth	r3, r8
20986
-	cmp	r3, r5
20987
-	bcs	.L3582
21607
+.L3419:
21608
+	uxth	r3, fp
21609
+	cmp	r8, r3
21610
+	ldrls	r3, [sp, #12]
21611
+	addls	r3, r3, #1
21612
+	strls	r3, [sp, #12]
21613
+	bls	.L3416
21614
+.L3422:
20988
21615
 	mov	r3, #36
20989
21616
 	ldr	r2, [r4, #-2688]
20990
-	mul	r7, r3, r8
20991
-	add	r1, r2, r7
20992
-	ldr	r2, [r2, r7]
20993
-	ldr	r10, [r1, #12]
21617
+	mul	r9, r3, fp
21618
+	add	r1, r2, r9
21619
+	ldr	r2, [r2, r9]
20994
21620
 	cmn	r2, #1
20995
-	beq	.L3529
20996
-	ldrh	r1, [r10]
21621
+	beq	.L3420
21622
+	ldr	r10, [r1, #12]
20997
21623
 	movw	r2, #61589
21624
+	ldrh	r1, [r10]
20998
21625
 	cmp	r1, r2
20999
-	bne	.L3529
21000
-	add	r1, sp, #32
21626
+	bne	.L3420
21001
21627
 	mov	r2, #0
21628
+	add	r1, sp, #32
21002
21629
 	ldr	r0, [r10, #8]
21003
-	str	r3, [sp, #20]
21004
-	bl	log2phys
21005
-	ldr	r2, [r4, #-2688]
21006
-	add	r2, r2, r7
21007
-	ldr	r0, [r2, #4]
21008
-	ldr	r1, [sp, #32]
21009
-	ldr	r3, [sp, #20]
21010
-	bic	r1, r1, #-2147483648
21011
-	cmp	r1, r0
21012
-	bne	.L3529
21013
-	ldr	r1, .L3583+60
21014
-	ldr	r0, .L3583+60
21015
-	ldr	r2, [r2, #16]
21016
-	ldrh	r1, [r1]
21017
21630
 	str	r3, [sp, #24]
21018
-	add	r1, r1, #1
21019
-	strh	r1, [r0]	@ movhi
21020
-	ldr	r0, [r4, #-2704]
21021
-	ldr	r1, [r4, #-532]
21022
-	mla	r1, r3, r0, r1
21023
-	str	r2, [r1, #16]
21024
-	str	r1, [sp, #20]
21025
-	bl	Ftl_get_new_temp_ppa
21026
-	ldr	r2, [r4, #-532]
21027
-	ldr	r1, [sp, #20]
21631
+	bl	log2phys
21632
+	ldr	r1, [r4, #-2688]
21633
+	ldr	r2, [sp, #32]
21028
21634
 	ldr	r3, [sp, #24]
21029
-	str	r0, [r1, #4]
21030
-	ldr	r1, [r4, #-2704]
21031
-	mla	r3, r3, r1, r2
21635
+	add	r1, r1, r9
21636
+	ldr	r0, [r1, #4]
21637
+	bic	r2, r2, #-2147483648
21638
+	cmp	r2, r0
21639
+	bne	.L3420
21640
+	ldr	r2, .L3507+64
21641
+	ldr	r0, .L3507+64
21642
+	ldr	r1, [r1, #16]
21643
+	ldrh	r2, [r2]
21644
+	str	r3, [sp, #28]
21645
+	add	r2, r2, #1
21646
+	strh	r2, [r0]	@ movhi
21647
+	ldr	r0, [r4, #-2704]
21648
+	ldr	r2, [r4, #-532]
21649
+	mla	r2, r3, r0, r2
21650
+	str	r1, [r2, #16]
21651
+	str	r2, [sp, #24]
21652
+	bl	Ftl_get_new_temp_ppa
21653
+	ldr	r2, [sp, #24]
21654
+	ldr	r1, [r4, #-532]
21655
+	ldr	r3, [sp, #28]
21656
+	str	r0, [r2, #4]
21657
+	ldr	r2, [r4, #-2704]
21658
+	mla	r3, r3, r2, r1
21032
21659
 	ldr	r2, [r4, #-2688]
21033
-	add	r2, r2, r7
21660
+	add	r2, r2, r9
21034
21661
 	ldr	r1, [r2, #8]
21035
21662
 	str	r1, [r3, #8]
21036
21663
 	mov	r1, #1
..
..
@@ -21038,592 +21665,479 @@
21038
21665
 	str	r2, [r3, #12]
21039
21666
 	ldr	r3, [sp, #32]
21040
21667
 	str	r3, [r10, #12]
21041
-	ldr	r3, .L3583+68
21668
+	ldr	r3, .L3507+40
21042
21669
 	ldrh	r3, [r3]
21043
21670
 	strh	r3, [r10, #2]	@ movhi
21044
21671
 	ldr	r3, [r4, #-3328]
21045
21672
 	ldr	r0, [r4, #-2688]
21046
21673
 	str	r3, [r10, #4]
21047
-	add	r0, r0, r7
21048
21674
 	ldr	r3, [r4, #-2704]
21675
+	add	r0, r0, r9
21049
21676
 	add	r3, r3, #1
21050
21677
 	str	r3, [r4, #-2704]
21051
21678
 	bl	FtlGcBufAlloc
21052
-	ldr	r3, .L3583+16
21053
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
21679
+	ldr	r3, .L3507+12
21680
+	ldrb	r3, [r3, #152]	@ zero_extendqisi2
21054
21681
 	cmp	r3, #0
21055
-	bne	.L3495
21056
-	ldrb	r3, [r4, #-3421]	@ zero_extendqisi2
21057
-	ldr	r2, [r4, #-2704]
21682
+	bne	.L3421
21683
+	ldrb	r2, [r4, #-3417]	@ zero_extendqisi2
21684
+	ldr	r3, [r4, #-2704]
21058
21685
 	cmp	r2, r3
21059
-	beq	.L3495
21060
-	ldr	r3, .L3583+68
21686
+	beq	.L3421
21687
+	ldr	r3, .L3507+40
21061
21688
 	ldrh	r3, [r3, #4]
21062
21689
 	cmp	r3, #0
21063
-	bne	.L3529
21064
-.L3495:
21690
+	bne	.L3420
21691
+.L3421:
21065
21692
 	bl	Ftl_gc_temp_data_write_back
21066
21693
 	cmp	r0, #0
21067
-	beq	.L3529
21068
-	ldr	r3, .L3583
21694
+	beq	.L3420
21695
+	ldr	r3, .L3507
21069
21696
 	mov	r2, #0
21070
-	mvn	r1, #0
21071
-	sub	r3, r3, #3280
21072
-	str	r2, [r3, #2720]
21073
-	strh	r1, [r3, #-4]	@ movhi
21074
-	strh	r2, [r3, #-2]	@ movhi
21075
-	b	.L3578
21076
-.L3529:
21077
-	add	r8, r8, #1
21078
-	b	.L3493
21079
-.L3582:
21080
-	add	r6, r6, #1
21081
-	b	.L3490
21082
-.L3497:
21083
-	ldrh	r3, [r5, #2]
21084
-	add	r9, r9, r3
21085
-	ldr	r3, [sp, #12]
21086
-	uxth	r9, r9
21087
-	strh	r9, [r5, #2]	@ movhi
21088
-	cmp	r9, r3
21089
-	bcc	.L3499
21090
-	ldr	r3, [r7, #-2704]
21697
+	mvn	ip, #0
21698
+	sub	r1, r3, #3280
21699
+	str	r2, [r3, #-560]
21700
+	add	r3, r3, #1984
21701
+	strh	ip, [r1, #-4]	@ movhi
21702
+	strh	r2, [r1, #-2]	@ movhi
21703
+.L3505:
21704
+	ldrh	r0, [r3]
21705
+	b	.L3343
21706
+.L3420:
21707
+	add	fp, fp, #1
21708
+	b	.L3419
21709
+.L3423:
21710
+	ldrh	r3, [r7, #-2]
21711
+	add	r6, r6, r3
21712
+	ldr	r3, [sp, #8]
21713
+	uxth	r6, r6
21714
+	cmp	r3, r6
21715
+	strh	r6, [r7, #-2]	@ movhi
21716
+	bhi	.L3425
21717
+	ldr	r3, [r4, #-2704]
21091
21718
 	cmp	r3, #0
21092
-	beq	.L3500
21719
+	beq	.L3426
21093
21720
 	bl	Ftl_gc_temp_data_write_back
21094
21721
 	cmp	r0, #0
21095
21722
 	movne	r3, #0
21096
-	strne	r3, [r7, #-560]
21097
-	bne	.L3578
21098
-.L3500:
21099
-	ldr	r3, .L3583+60
21100
-	ldrh	r4, [r3]
21101
-	cmp	r4, #0
21102
-	bne	.L3501
21103
-	ldrh	r3, [r5]
21104
-	ldr	r2, [r7, #-3544]
21105
-	mov	r3, r3, asl #1
21723
+	strne	r3, [r4, #-560]
21724
+	bne	.L3506
21725
+.L3426:
21726
+	ldr	r3, .L3507+64
21727
+	ldrh	r0, [r3]
21728
+	cmp	r0, #0
21729
+	bne	.L3427
21730
+	ldrh	r3, [r7, #-4]
21731
+	ldr	r2, [r4, #-3540]
21732
+	lsl	r3, r3, #1
21106
21733
 	ldrh	r3, [r2, r3]
21107
21734
 	cmp	r3, #0
21108
-	beq	.L3501
21109
-	ldr	r6, .L3583+16
21110
-.L3502:
21111
-	ldr	r3, [r6, #2448]
21112
-	cmp	r4, r3
21113
-	bcs	.L3507
21114
-	mov	r0, r4
21115
-	add	r1, sp, #36
21735
+	movne	r6, r0
21736
+	ldrne	r8, .L3507+12
21737
+	bne	.L3428
21738
+.L3427:
21739
+	mvn	r3, #0
21740
+	strh	r3, [r7, #-4]	@ movhi
21741
+.L3425:
21742
+	ldr	r3, .L3507+72
21743
+	ldrh	r3, [r3]
21744
+	cmp	r3, #2
21745
+	bhi	.L3434
21746
+	ldr	r3, .L3507+52
21747
+	ldrh	r6, [r3]
21748
+	b	.L3435
21749
+.L3429:
21750
+	add	r6, r6, #1
21751
+.L3428:
21752
+	ldr	r3, [r8, #2452]
21753
+	cmp	r6, r3
21754
+	bcs	.L3433
21116
21755
 	mov	r2, #0
21756
+	add	r1, sp, #36
21757
+	mov	r0, r6
21117
21758
 	bl	log2phys
21118
21759
 	ldr	r0, [sp, #36]
21119
21760
 	cmn	r0, #1
21120
-	beq	.L3503
21761
+	beq	.L3429
21121
21762
 	ubfx	r0, r0, #10, #16
21122
21763
 	bl	P2V_block_in_plane
21123
-	ldrh	r3, [r5]
21764
+	ldrh	r3, [r7, #-4]
21124
21765
 	cmp	r3, r0
21125
-	bne	.L3503
21126
-.L3507:
21127
-	ldr	r3, .L3583+16
21128
-	ldr	r3, [r3, #2448]
21129
-	cmp	r4, r3
21130
-	bcc	.L3501
21131
-	ldrh	r3, [r5]
21766
+	bne	.L3429
21767
+.L3433:
21768
+	ldr	r3, [r8, #2452]
21769
+	cmp	r6, r3
21770
+	bcc	.L3427
21771
+	ldrh	r3, [r7, #-4]
21132
21772
 	mov	r1, #0
21133
-	ldr	r2, [r7, #-3544]
21134
-	mov	r3, r3, asl #1
21773
+	ldr	r2, [r4, #-3540]
21774
+	lsl	r3, r3, #1
21135
21775
 	strh	r1, [r2, r3]	@ movhi
21136
-	ldrh	r0, [r5]
21776
+	ldrh	r0, [r7, #-4]
21137
21777
 	bl	update_vpc_list
21138
21778
 	bl	FtlCacheWriteBack
21139
21779
 	bl	l2p_flush
21140
21780
 	bl	FtlVpcTblFlush
21141
-	b	.L3501
21142
-.L3503:
21143
-	add	r4, r4, #1
21144
-	b	.L3502
21145
-.L3501:
21146
-	mvn	r3, #0
21147
-	strh	r3, [r5]	@ movhi
21148
-.L3499:
21149
-	ldr	r3, .L3583+72
21150
-	ldrh	r3, [r3]
21151
-	cmp	r3, #2
21152
-	ldrls	r3, .L3583+56
21153
-	ldrlsh	r9, [r3]
21154
-	bls	.L3509
21155
-.L3508:
21156
-	ldr	r2, .L3583
21157
-	mov	r1, #0
21158
-	str	r1, [r2, #-560]
21159
-	ldr	r2, .L3583+20
21781
+	b	.L3427
21782
+.L3434:
21783
+	mov	r2, #0
21784
+	str	r2, [r4, #-560]
21785
+	ldr	r2, .L3507+16
21160
21786
 	ldrh	r0, [r2]
21161
-	cmp	r0, r1
21162
-	addeq	r0, r3, #1
21163
-	b	.L3572
21164
-.L3513:
21165
-	mov	r0, #0
21166
-	bx	lr
21167
-.L3515:
21168
-	mov	r0, ip
21169
-	b	.L3572
21170
-.L3580:
21171
-	ldrh	r9, [r4, #-10]
21172
-	cmp	r9, r3
21173
-	bne	.L3577
21174
-	sub	r3, r8, #3520
21175
-	ldr	r2, [r8, #-2716]
21176
-	ldrh	r3, [r3, #-8]
21177
-	cmp	r3, #24
21178
-	movcc	r3, #5120
21179
-	movcs	r3, #1024
21180
-	cmp	r2, r3
21181
-	movls	fp, r9
21182
-	bls	.L3436
21183
-	ldr	r2, .L3583+20
21184
-	mov	r3, #0
21185
-	str	r3, [r5, #-2716]
21186
-	strh	r3, [r2]	@ movhi
21187
-	bl	GetSwlReplaceBlock
21188
-	cmp	r0, r9
21189
-	mov	fp, r0
21190
-	bne	.L3438
21191
-	sub	r3, r8, #2704
21192
-	ldrh	r1, [r7, #-8]
21193
-	ldrh	r2, [r3, #-14]
21194
-	mov	r9, r3
21195
-	cmp	r1, r2
21196
-	movcs	r2, #80
21197
-	strcsh	r2, [r3, #-14]	@ movhi
21198
-	bcs	.L3448
21199
-	mov	r0, #64
21200
-	bl	List_get_gc_head_node
21201
-	uxth	r3, r0
21202
-	cmp	r3, fp
21203
-	beq	.L3448
21204
-	ldr	r2, [r8, #-564]
21205
-	ldr	r10, .L3583+16
21206
-	cmp	r2, #0
21207
-	bne	.L3441
21208
-	movw	r1, #2340
21209
-	ldrh	r1, [r10, r1]
21210
-	cmp	r1, #3
21211
-	beq	.L3441
21212
-	ldr	r1, [r8, #-3236]
21213
-	cmp	r1, #0
21214
-	bne	.L3441
21215
-	ldr	r1, [r10, #2244]
21216
-	cmp	r1, #0
21217
-	bne	.L3441
21218
-	ldrb	r0, [r10, #144]	@ zero_extendqisi2
21219
21787
 	cmp	r0, #0
21220
-	beq	.L3442
21221
-.L3441:
21222
-	ldr	r2, [r5, #-3544]
21223
-	mov	r3, r3, asl #1
21224
-	movw	r0, #2340
21225
-	ldrh	r0, [r10, r0]
21226
-	ldrh	r1, [r2, r3]
21227
-	movw	r3, #2390
21228
-	ldr	r2, .L3583+24
21229
-	cmp	r0, #3
21230
-	ldrh	r3, [r10, r3]
21231
-	ldrh	r2, [r2]
21232
-	mul	r2, r2, r3
21233
-	moveq	r3, r3, lsr #1
21234
-	movne	r3, #0
21235
-	add	r3, r2, r3
21236
-	cmp	r1, r3
21237
-	bgt	.L3444
21788
+	addeq	r0, r3, #1
21789
+	b	.L3343
21790
+.L3439:
21238
21791
 	mov	r0, #0
21239
-	bl	List_get_gc_head_node
21240
-	ldr	r3, [r10, #2448]
21241
-	ldr	r2, [r5, #-3372]
21242
-	add	r3, r3, r3, asl #1
21243
-	cmp	r2, r3, lsr #2
21244
-	movls	r3, #160
21245
-	uxth	fp, r0
21246
-	bls	.L3575
21247
-	b	.L3579
21248
-.L3442:
21249
-	ldr	r2, [r8, #-3544]
21250
-	mov	r3, r3, asl #1
21251
-	ldrh	r3, [r2, r3]
21252
-	cmp	r3, #7
21253
-	bhi	.L3447
21254
-	bl	List_get_gc_head_node
21255
-	uxth	fp, r0
21256
-.L3579:
21257
-	mov	r3, #128
21258
-.L3575:
21259
-	strh	r3, [r9, #-14]	@ movhi
21260
-	movw	r3, #65535
21261
-	cmp	fp, r3
21262
-	beq	.L3448
21263
-	b	.L3438
21264
-.L3444:
21265
-	mov	r3, #128
21266
-	b	.L3576
21267
-.L3447:
21268
-	mov	r3, #64
21269
-.L3576:
21270
-	strh	r3, [r9, #-14]	@ movhi
21271
-	b	.L3448
21272
-.L3438:
21273
-	ldr	r0, [r5, #-3608]
21274
-	mov	r1, fp, asl #1
21275
-	ldr	r3, [r5, #-3544]
21276
-	ldrh	r2, [r7, #-8]
21277
-	ldrh	r3, [r3, r1]
21278
-	ldrh	r1, [r0, r1]
21279
-	ldr	r0, .L3583+76
21280
-	str	r1, [sp]
21281
-	ldr	r1, .L3583+80
21282
-	ldrh	r1, [r1]
21283
-	str	r1, [sp, #4]
21284
-	mov	r1, fp
21285
-	bl	printk
21286
-.L3448:
21287
-	bl	FtlGcReFreshBadBlk
21288
-	b	.L3436
21289
-.L3577:
21290
-	mov	fp, r3
21291
-	b	.L3436
21292
-.L3572:
21293
-	add	sp, sp, #44
21294
-	@ sp needed
21295
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
21296
-.L3584:
21792
+	b	.L3343
21793
+.L3508:
21297
21794
 	.align	2
21298
-.L3583:
21795
+.L3507:
21299
21796
 	.word	.LANCHOR2
21300
21797
 	.word	.LANCHOR1
21301
21798
 	.word	.LANCHOR2-2656
21302
-	.word	.LANCHOR2-3280
21303
21799
 	.word	.LANCHOR0
21304
-	.word	.LANCHOR4+1984
21305
-	.word	.LANCHOR0+2320
21800
+	.word	.LANCHOR2+1984
21801
+	.word	.LANCHOR2-3280
21802
+	.word	.LANCHOR2-2704
21306
21803
 	.word	.LC157
21307
-	.word	.LANCHOR2-3520
21308
-	.word	.LANCHOR2-3296
21309
-	.word	.LANCHOR4
21310
-	.word	.LANCHOR2-3472
21311
-	.word	.LANCHOR2-3284
21312
-	.word	.LANCHOR2-2712
21313
-	.word	.LANCHOR0+2388
21314
-	.word	.LANCHOR4+1986
21315
-	.word	.LANCHOR0+2390
21316
-	.word	.LANCHOR2-3428
21317
-	.word	.LANCHOR2-3528
21318
-	.word	.LC158
21319
21804
 	.word	.LANCHOR2-2720
21805
+	.word	.LANCHOR2-3296
21806
+	.word	.LANCHOR2-3424
21807
+	.word	.LC158
21808
+	.word	.LANCHOR2-3472
21809
+	.word	.LANCHOR0+2390
21810
+	.word	.LANCHOR2-2712
21811
+	.word	.LANCHOR0+2324
21812
+	.word	.LANCHOR2+1986
21813
+	.word	.LANCHOR0+2392
21814
+	.word	.LANCHOR2-3524
21320
21815
 	.fnend
21321
21816
 	.size	ftl_do_gc, .-ftl_do_gc
21322
21817
 	.align	2
21323
21818
 	.global	FtlCacheWriteBack
21819
+	.syntax unified
21820
+	.arm
21821
+	.fpu softvfp
21324
21822
 	.type	FtlCacheWriteBack, %function
21325
21823
 FtlCacheWriteBack:
21326
21824
 	.fnstart
21327
-	@ args = 0, pretend = 0, frame = 8
21825
+	@ args = 0, pretend = 0, frame = 16
21328
21826
 	@ frame_needed = 0, uses_anonymous_args = 0
21329
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
21827
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
21330
21828
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
21331
-	.pad #12
21332
-	ldr	r3, .L3629
21333
-	ldr	r7, .L3629+4
21334
-	ldr	r5, [r3, #1992]
21335
-	ldr	r3, [r7, #-3616]
21336
-	cmp	r3, #0
21337
-	bne	.L3587
21338
-	ldr	r4, .L3629+8
21339
-	ldr	r1, [r4, #2440]
21829
+	.pad #20
21830
+	sub	sp, sp, #20
21831
+	ldr	r6, .L3552
21832
+	ldr	r9, [r6, #-3612]
21833
+	cmp	r9, #0
21834
+	bne	.L3511
21835
+	ldr	r4, .L3552+4
21836
+	ldr	r1, [r4, #2444]
21340
21837
 	cmp	r1, #0
21341
-	beq	.L3587
21342
-	ldrb	r6, [r4, #144]	@ zero_extendqisi2
21343
-	mov	r8, #0
21344
-	ldr	r0, [r4, #2444]
21838
+	beq	.L3511
21839
+	ldrb	r3, [r4, #152]	@ zero_extendqisi2
21840
+	mov	r7, #0
21841
+	ldr	r5, [r6, #1992]
21345
21842
 	mov	r10, #36
21346
-	cmp	r6, #0
21843
+	ldr	fp, .L3552+8
21844
+	cmp	r3, #0
21845
+	ldr	r0, [r4, #2448]
21846
+	ldrbne	r8, [r5, #8]	@ zero_extendqisi2
21847
+	moveq	r8, r9
21347
21848
 	ldrb	r3, [r5, #9]	@ zero_extendqisi2
21348
-	ldr	r9, .L3629+8
21349
-	ldrneb	r6, [r5, #8]	@ zero_extendqisi2
21350
-	subne	r6, r6, #1
21351
-	clzne	r6, r6
21352
-	movne	r6, r6, lsr #5
21353
-	mov	r2, r6
21849
+	subne	r8, r8, #1
21850
+	clzne	r8, r8
21851
+	lsrne	r8, r8, #5
21852
+	mov	r2, r8
21354
21853
 	bl	FlashProgPages
21355
-.L3590:
21356
-	ldr	r3, [r4, #2440]
21357
-	cmp	r8, r3
21358
-	bcs	.L3608
21359
-	mul	fp, r10, r8
21360
-	ldr	r3, [r9, #2444]
21361
-	add	r2, r3, fp
21362
-	ldr	r3, [r3, fp]
21363
-	cmn	r3, #1
21364
-	beq	.L3611
21365
-	ldr	r3, [r2, #4]
21366
-	cmp	r6, #0
21367
-	ldr	r0, [r2, #16]
21368
-	add	r1, sp, #4
21369
-	mov	r2, #1
21370
-	orrne	r3, r3, #-2147483648
21371
-	str	r3, [sp, #4]
21372
-	bl	log2phys
21854
+.L3514:
21373
21855
 	ldr	r3, [r4, #2444]
21374
-	add	r3, r3, fp
21856
+	cmp	r7, r3
21857
+	bcc	.L3521
21858
+.L3533:
21859
+	mov	r3, #0
21860
+	str	r3, [r4, #2444]
21861
+.L3511:
21862
+	mov	r0, #0
21863
+	add	sp, sp, #20
21864
+	@ sp needed
21865
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
21866
+.L3521:
21867
+	mul	r3, r10, r7
21868
+	ldr	r2, [r4, #2448]
21869
+	add	r0, r2, r3
21870
+	ldr	r2, [r2, r3]
21871
+	cmn	r2, #1
21872
+	beq	.L3516
21873
+	ldr	r2, [r0, #4]
21874
+	cmp	r8, #0
21875
+	add	r1, sp, #12
21876
+	ldr	r0, [r0, #16]
21877
+	str	r3, [sp, #4]
21878
+	orrne	r2, r2, #-2147483648
21879
+	str	r2, [sp, #12]
21880
+	mov	r2, #1
21881
+	bl	log2phys
21882
+	ldr	r2, [r4, #2448]
21883
+	ldr	r3, [sp, #4]
21884
+	add	r3, r2, r3
21375
21885
 	ldr	r3, [r3, #12]
21376
21886
 	ldr	r0, [r3, #12]
21377
21887
 	cmn	r0, #1
21378
-	beq	.L3594
21888
+	beq	.L3519
21379
21889
 	ubfx	r0, r0, #10, #16
21380
21890
 	bl	P2V_block_in_plane
21381
-	ldr	r2, [r7, #-3544]
21382
-	mov	r3, r0, asl #1
21383
-	mov	fp, r0
21891
+	ldr	r1, [r6, #-3540]
21892
+	lsl	r2, r0, #1
21893
+	mov	r3, r0
21894
+	ldrh	r2, [r1, r2]
21895
+	cmp	r2, #0
21896
+	bne	.L3520
21897
+	mov	r1, r0
21898
+	str	r0, [sp, #4]
21899
+	mov	r0, fp
21900
+	bl	printk
21901
+	ldr	r3, [sp, #4]
21902
+.L3520:
21903
+	mov	r0, r3
21904
+	bl	decrement_vpc_count
21905
+.L3519:
21906
+	add	r7, r7, #1
21907
+	b	.L3514
21908
+.L3531:
21909
+	mov	r7, #36
21910
+	ldr	r3, [r4, #2448]
21911
+	mul	r7, r7, r9
21912
+	mov	r10, #0
21913
+	mov	fp, #1
21914
+	mvn	r2, #0
21915
+	str	r2, [r3, r7]
21916
+.L3522:
21917
+	ldr	r2, [r4, #2448]
21918
+	add	r3, r2, r7
21919
+	ldr	r2, [r2, r7]
21920
+	ldr	r0, [r3, #4]
21921
+	cmn	r2, #1
21922
+	beq	.L3526
21923
+	cmp	r8, #0
21924
+	mov	r2, #1
21925
+	orrne	r0, r0, #-2147483648
21926
+	add	r1, sp, #12
21927
+	str	r0, [sp, #12]
21928
+	ldr	r0, [r3, #16]
21929
+	bl	log2phys
21930
+	ldr	r3, [r4, #2448]
21931
+	add	r7, r3, r7
21932
+	ldr	r3, [r7, #12]
21933
+	ldr	r0, [r3, #12]
21934
+	cmn	r0, #1
21935
+	beq	.L3529
21936
+	ubfx	r0, r0, #10, #16
21937
+	bl	P2V_block_in_plane
21938
+	ldr	r2, [r6, #-3540]
21939
+	lsl	r3, r0, #1
21940
+	mov	r7, r0
21384
21941
 	ldrh	r2, [r2, r3]
21385
21942
 	cmp	r2, #0
21386
-	bne	.L3595
21387
-	ldr	r0, .L3629+12
21388
-	mov	r1, fp
21389
-	bl	printk
21390
-.L3595:
21391
-	mov	r0, fp
21392
-	bl	decrement_vpc_count
21393
-.L3594:
21394
-	add	r8, r8, #1
21395
-	b	.L3590
21396
-.L3627:
21397
-	ldr	r6, .L3629+16
21398
-	movw	r5, #16386
21399
-.L3607:
21400
-	ldrh	r3, [r6]
21401
-	cmp	r3, #0
21402
-	beq	.L3608
21403
-	mov	r0, #1
21943
+	bne	.L3530
21404
21944
 	mov	r1, r0
21945
+	ldr	r0, .L3552+8
21946
+	bl	printk
21947
+.L3530:
21948
+	mov	r0, r7
21949
+	bl	decrement_vpc_count
21950
+.L3529:
21951
+	add	r9, r9, #1
21952
+.L3516:
21953
+	ldr	r3, [r4, #2444]
21954
+	cmp	r9, r3
21955
+	bcc	.L3531
21956
+	movw	r5, #16386
21957
+.L3534:
21958
+	ldr	r3, .L3552+12
21959
+	ldrh	r3, [r3]
21960
+	cmp	r3, #0
21961
+	beq	.L3533
21962
+	mov	r1, #1
21963
+	mov	r0, r1
21405
21964
 	bl	ftl_do_gc
21406
21965
 	subs	r5, r5, #1
21407
-	bne	.L3607
21408
-.L3608:
21409
-	mov	r3, #0
21410
-	str	r3, [r4, #2440]
21411
-	b	.L3587
21412
-.L3611:
21413
-	ldr	fp, .L3629+8
21414
-	mov	r9, #0
21415
-.L3591:
21416
-	ldr	r3, [r4, #2440]
21417
-	cmp	r9, r3
21418
-	bcs	.L3627
21419
-	mov	r8, #36
21420
-	ldr	r3, [fp, #2444]
21421
-	mul	r8, r8, r9
21422
-	mov	r10, #0
21423
-	mvn	r2, #0
21424
-	str	r2, [r3, r8]
21425
-.L3597:
21426
-	ldr	r3, [r4, #2444]
21427
-	add	r2, r3, r8
21428
-	ldr	r3, [r3, r8]
21429
-	cmn	r3, #1
21430
-	bne	.L3628
21431
-	ldr	r0, [r2, #4]
21966
+	bne	.L3534
21967
+	b	.L3533
21968
+.L3526:
21432
21969
 	ubfx	r0, r0, #10, #16
21433
21970
 	bl	P2V_block_in_plane
21434
21971
 	ldrh	r3, [r5]
21435
21972
 	cmp	r3, r0
21436
-	bne	.L3598
21437
-	ldr	r1, [r7, #-3544]
21438
-	mov	r3, r3, asl #1
21973
+	bne	.L3523
21974
+	ldr	r1, [r6, #-3540]
21975
+	lsl	r3, r3, #1
21439
21976
 	ldrh	r0, [r5, #4]
21440
21977
 	ldrh	r2, [r1, r3]
21441
-	rsb	r2, r0, r2
21978
+	sub	r2, r2, r0
21442
21979
 	strh	r2, [r1, r3]	@ movhi
21443
-	ldr	r3, .L3629+20
21980
+	ldr	r3, .L3552+16
21444
21981
 	strb	r10, [r5, #6]
21445
21982
 	strh	r10, [r5, #4]	@ movhi
21446
21983
 	ldrh	r3, [r3]
21447
21984
 	strh	r3, [r5, #2]	@ movhi
21448
-.L3598:
21985
+.L3523:
21449
21986
 	ldrh	r3, [r5, #4]
21450
21987
 	cmp	r3, #0
21451
-	bne	.L3599
21988
+	bne	.L3524
21452
21989
 	mov	r0, r5
21453
21990
 	bl	allocate_new_data_superblock
21454
-.L3599:
21455
-	ldr	r3, [r7, #-3136]
21991
+.L3524:
21992
+	ldr	r3, [r6, #-3140]
21456
21993
 	add	r3, r3, #1
21457
-	str	r3, [r7, #-3136]
21458
-	ldr	r3, [r4, #2444]
21459
-	add	r3, r3, r8
21994
+	str	r3, [r6, #-3140]
21995
+	ldr	r3, [r4, #2448]
21996
+	add	r3, r3, r7
21460
21997
 	ldr	r0, [r3, #4]
21461
21998
 	ubfx	r0, r0, #10, #16
21462
21999
 	bl	FtlGcMarkBadPhyBlk
21463
22000
 	mov	r0, r5
21464
22001
 	bl	get_new_active_ppa
21465
-	ldr	r3, [r4, #2444]
21466
-	mov	r2, r6
22002
+	ldr	r3, [r4, #2448]
22003
+	mov	r2, r0
22004
+	str	r0, [sp, #12]
21467
22005
 	mov	r1, #1
21468
-	add	r3, r3, r8
21469
-	str	r0, [sp, #4]
21470
-	str	r0, [r3, #4]
21471
-	mov	r0, r3
22006
+	add	r0, r3, r7
22007
+	str	r2, [r0, #4]
22008
+	mov	r2, r8
21472
22009
 	ldrb	r3, [r5, #9]	@ zero_extendqisi2
21473
22010
 	bl	FlashProgPages
21474
-	ldr	r3, [r4, #2444]
21475
-	ldr	r3, [r3, r8]
22011
+	ldr	r3, [r4, #2448]
22012
+	ldr	r3, [r3, r7]
21476
22013
 	cmn	r3, #1
21477
-	ldreq	r2, .L3629+4
21478
-	moveq	r3, #1
21479
-	streq	r3, [r2, #-3616]
21480
-	ldr	r3, [r7, #-3616]
22014
+	streq	fp, [r6, #-3612]
22015
+	ldr	r3, [r6, #-3612]
21481
22016
 	cmp	r3, #0
21482
-	beq	.L3597
21483
-	b	.L3587
21484
-.L3628:
21485
-	ldr	r3, [r2, #4]
21486
-	cmp	r6, #0
21487
-	ldr	r0, [r2, #16]
21488
-	add	r1, sp, #4
21489
-	mov	r2, #1
21490
-	orrne	r3, r3, #-2147483648
21491
-	str	r3, [sp, #4]
21492
-	bl	log2phys
21493
-	ldr	r3, [r4, #2444]
21494
-	add	r8, r3, r8
21495
-	ldr	r3, [r8, #12]
21496
-	ldr	r0, [r3, #12]
21497
-	cmn	r0, #1
21498
-	beq	.L3604
21499
-	ubfx	r0, r0, #10, #16
21500
-	bl	P2V_block_in_plane
21501
-	ldr	r2, [r7, #-3544]
21502
-	mov	r3, r0, asl #1
21503
-	mov	r8, r0
21504
-	ldrh	r2, [r2, r3]
21505
-	cmp	r2, #0
21506
-	bne	.L3605
21507
-	ldr	r0, .L3629+12
21508
-	mov	r1, r8
21509
-	bl	printk
21510
-.L3605:
21511
-	mov	r0, r8
21512
-	bl	decrement_vpc_count
21513
-.L3604:
21514
-	add	r9, r9, #1
21515
-	b	.L3591
21516
-.L3587:
21517
-	mov	r0, #0
21518
-	add	sp, sp, #12
21519
-	@ sp needed
21520
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
21521
-.L3630:
22017
+	beq	.L3522
22018
+	b	.L3511
22019
+.L3553:
21522
22020
 	.align	2
21523
-.L3629:
21524
-	.word	.LANCHOR4
22021
+.L3552:
21525
22022
 	.word	.LANCHOR2
21526
22023
 	.word	.LANCHOR0
21527
22024
 	.word	.LC159
21528
22025
 	.word	.LANCHOR2-2658
21529
-	.word	.LANCHOR0+2388
22026
+	.word	.LANCHOR0+2390
21530
22027
 	.fnend
21531
22028
 	.size	FtlCacheWriteBack, .-FtlCacheWriteBack
21532
22029
 	.align	2
21533
22030
 	.global	FtlSysFlush
22031
+	.syntax unified
22032
+	.arm
22033
+	.fpu softvfp
21534
22034
 	.type	FtlSysFlush, %function
21535
22035
 FtlSysFlush:
21536
22036
 	.fnstart
21537
22037
 	@ args = 0, pretend = 0, frame = 0
21538
22038
 	@ frame_needed = 0, uses_anonymous_args = 0
21539
-	ldr	r3, .L3635
21540
-	ldr	r3, [r3, #-3616]
22039
+	ldr	r3, .L3560
22040
+	ldr	r3, [r3, #-3612]
21541
22041
 	cmp	r3, #0
21542
-	bne	.L3634
21543
-	ldr	r3, .L3635+4
21544
-	stmfd	sp!, {r4, lr}
22042
+	bne	.L3557
22043
+	ldr	r3, .L3560+4
22044
+	push	{r4, lr}
21545
22045
 	.save {r4, lr}
21546
-	ldr	r4, [r3, #504]
22046
+	ldr	r4, [r3, #500]
21547
22047
 	cmp	r4, #1
21548
-	bne	.L3632
22048
+	bne	.L3555
21549
22049
 	bl	FtlCacheWriteBack
21550
22050
 	bl	l2p_flush
21551
22051
 	mov	r0, r4
21552
22052
 	bl	FtlEctTblFlush
21553
22053
 	bl	FtlVpcTblFlush
21554
-.L3632:
22054
+.L3555:
21555
22055
 	mov	r0, #0
21556
-	ldmfd	sp!, {r4, pc}
21557
-.L3634:
22056
+	pop	{r4, pc}
22057
+.L3557:
21558
22058
 	mov	r0, #0
21559
22059
 	bx	lr
21560
-.L3636:
22060
+.L3561:
21561
22061
 	.align	2
21562
-.L3635:
22062
+.L3560:
21563
22063
 	.word	.LANCHOR2
21564
22064
 	.word	.LANCHOR1
21565
22065
 	.fnend
21566
22066
 	.size	FtlSysFlush, .-FtlSysFlush
21567
22067
 	.align	2
21568
22068
 	.global	FtlDeInit
22069
+	.syntax unified
22070
+	.arm
22071
+	.fpu softvfp
21569
22072
 	.type	FtlDeInit, %function
21570
22073
 FtlDeInit:
21571
22074
 	.fnstart
21572
22075
 	@ args = 0, pretend = 0, frame = 0
21573
22076
 	@ frame_needed = 0, uses_anonymous_args = 0
21574
-	stmfd	sp!, {r3, lr}
21575
-	.save {r3, lr}
21576
-	ldr	r3, .L3640
21577
-	ldr	r3, [r3, #504]
22077
+	ldr	r3, .L3568
22078
+	ldr	r3, [r3, #500]
21578
22079
 	cmp	r3, #1
21579
-	bne	.L3638
22080
+	bne	.L3565
22081
+	push	{r4, lr}
22082
+	.save {r4, lr}
21580
22083
 	bl	FtlSysFlush
21581
-.L3638:
21582
22084
 	mov	r0, #0
21583
-	ldmfd	sp!, {r3, pc}
21584
-.L3641:
22085
+	pop	{r4, pc}
22086
+.L3565:
22087
+	mov	r0, #0
22088
+	bx	lr
22089
+.L3569:
21585
22090
 	.align	2
21586
-.L3640:
22091
+.L3568:
21587
22092
 	.word	.LANCHOR1
21588
22093
 	.fnend
21589
22094
 	.size	FtlDeInit, .-FtlDeInit
21590
22095
 	.align	2
21591
22096
 	.global	ftl_deinit
22097
+	.syntax unified
22098
+	.arm
22099
+	.fpu softvfp
21592
22100
 	.type	ftl_deinit, %function
21593
22101
 ftl_deinit:
21594
22102
 	.fnstart
21595
22103
 	@ args = 0, pretend = 0, frame = 0
21596
22104
 	@ frame_needed = 0, uses_anonymous_args = 0
21597
-	stmfd	sp!, {r3, lr}
21598
-	.save {r3, lr}
22105
+	push	{r4, lr}
22106
+	.save {r4, lr}
21599
22107
 	bl	ftl_flash_de_init
21600
22108
 	bl	FtlDeInit
21601
-	ldmfd	sp!, {r3, lr}
22109
+	pop	{r4, lr}
21602
22110
 	b	ftl_flash_de_init
21603
22111
 	.fnend
21604
22112
 	.size	ftl_deinit, .-ftl_deinit
21605
22113
 	.align	2
21606
22114
 	.global	rk_ftl_de_init
22115
+	.syntax unified
22116
+	.arm
22117
+	.fpu softvfp
21607
22118
 	.type	rk_ftl_de_init, %function
21608
22119
 rk_ftl_de_init:
21609
22120
 	.fnstart
21610
22121
 	@ args = 0, pretend = 0, frame = 0
21611
22122
 	@ frame_needed = 0, uses_anonymous_args = 0
21612
-	stmfd	sp!, {r3, lr}
21613
-	.save {r3, lr}
22123
+	push	{r4, lr}
22124
+	.save {r4, lr}
21614
22125
 	mov	r1, #0
21615
-	ldr	r0, .L3646
22126
+	ldr	r0, .L3574
21616
22127
 	bl	printk
21617
-	ldmfd	sp!, {r3, lr}
22128
+	pop	{r4, lr}
21618
22129
 	b	ftl_deinit
21619
-.L3647:
22130
+.L3575:
21620
22131
 	.align	2
21621
-.L3646:
22132
+.L3574:
21622
22133
 	.word	.LC160
21623
22134
 	.fnend
21624
22135
 	.size	rk_ftl_de_init, .-rk_ftl_de_init
21625
22136
 	.align	2
21626
22137
 	.global	ftl_cache_flush
22138
+	.syntax unified
22139
+	.arm
22140
+	.fpu softvfp
21627
22141
 	.type	ftl_cache_flush, %function
21628
22142
 ftl_cache_flush:
21629
22143
 	.fnstart
..
..
@@ -21635,6 +22149,9 @@
21635
22149
 	.size	ftl_cache_flush, .-ftl_cache_flush
21636
22150
 	.align	2
21637
22151
 	.global	rk_ftl_cache_write_back
22152
+	.syntax unified
22153
+	.arm
22154
+	.fpu softvfp
21638
22155
 	.type	rk_ftl_cache_write_back, %function
21639
22156
 rk_ftl_cache_write_back:
21640
22157
 	.fnstart
..
..
@@ -21646,74 +22163,89 @@
21646
22163
 	.size	rk_ftl_cache_write_back, .-rk_ftl_cache_write_back
21647
22164
 	.align	2
21648
22165
 	.global	ftl_discard
22166
+	.syntax unified
22167
+	.arm
22168
+	.fpu softvfp
21649
22169
 	.type	ftl_discard, %function
21650
22170
 ftl_discard:
21651
22171
 	.fnstart
21652
22172
 	@ args = 0, pretend = 0, frame = 8
21653
22173
 	@ frame_needed = 0, uses_anonymous_args = 0
21654
-	stmfd	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
21655
-	.save {r4, r5, r6, r7, r8, r9, lr}
21656
-	.pad #12
22174
+	push	{r0, r1, r4, r5, r6, r7, r8, lr}
22175
+	.save {r4, r5, r6, r7, r8, lr}
22176
+	.pad #8
21657
22177
 	mov	r6, r0
21658
-	ldr	r8, .L3669
22178
+	ldr	r5, .L3596
22179
+	ldr	r3, [r5, #2432]
22180
+	cmp	r3, r1
22181
+	cmpcs	r3, r0
22182
+	movls	r0, #1
22183
+	movhi	r0, #0
22184
+	bls	.L3586
22185
+	add	r2, r6, r1
21659
22186
 	mov	r4, r1
21660
-	ldr	r3, [r8, #2428]
21661
-	cmp	r1, r3
21662
-	cmpls	r0, r3
21663
-	movcs	r5, #1
21664
-	movcc	r5, #0
21665
-	bcs	.L3658
21666
-	add	r2, r0, r1
21667
-	cmp	r2, r3
21668
-	bhi	.L3658
22187
+	cmp	r3, r2
22188
+	bcc	.L3586
21669
22189
 	cmp	r1, #31
21670
-	bls	.L3656
21671
-	ldr	r7, .L3669+4
21672
-	ldr	r3, [r7, #-3616]
22190
+	bls	.L3578
22191
+	ldr	r7, .L3596+4
22192
+	ldr	r3, [r7, #-3612]
21673
22193
 	cmp	r3, #0
21674
-	movne	r0, r5
21675
-	bne	.L3651
22194
+	bne	.L3578
21676
22195
 	bl	FtlCacheWriteBack
21677
-	movw	r3, #2394
21678
-	ldrh	r5, [r8, r3]
22196
+	movw	r3, #2396
21679
22197
 	mov	r0, r6
22198
+	ldrh	r5, [r5, r3]
21680
22199
 	mov	r1, r5
21681
22200
 	bl	__aeabi_uidiv
21682
22201
 	smulbb	r3, r0, r5
21683
22202
 	mov	r8, r0
21684
-	rsb	r6, r3, r6
22203
+	sub	r6, r6, r3
21685
22204
 	uxth	r6, r6
21686
22205
 	cmp	r6, #0
21687
-	beq	.L3652
21688
-	rsb	r5, r6, r5
22206
+	beq	.L3580
22207
+	sub	r5, r5, r6
21689
22208
 	add	r8, r0, #1
21690
22209
 	cmp	r5, r4
21691
22210
 	movcs	r5, r4
21692
22211
 	uxth	r5, r5
21693
-	rsb	r4, r5, r4
21694
-.L3652:
21695
-	ldr	r5, .L3669+8
22212
+	sub	r4, r4, r5
22213
+.L3580:
22214
+	ldr	r5, .L3596+8
21696
22215
 	mvn	r3, #0
21697
-	ldr	r9, .L3669+12
21698
22216
 	str	r3, [sp, #4]
21699
22217
 	mov	r6, r5
21700
-.L3653:
22218
+.L3581:
21701
22219
 	ldrh	r3, [r5]
21702
22220
 	cmp	r4, r3
21703
-	bcc	.L3668
21704
-	mov	r0, r8
21705
-	mov	r1, sp
22221
+	bcs	.L3583
22222
+	ldr	r3, [r7, #1996]
22223
+	cmp	r3, #32
22224
+	bls	.L3584
22225
+	mov	r3, #0
22226
+	str	r3, [r7, #1996]
22227
+	bl	l2p_flush
22228
+	bl	FtlVpcTblFlush
22229
+.L3584:
22230
+	mov	r0, #0
22231
+.L3578:
22232
+	add	sp, sp, #8
22233
+	@ sp needed
22234
+	pop	{r4, r5, r6, r7, r8, pc}
22235
+.L3583:
21706
22236
 	mov	r2, #0
22237
+	mov	r1, sp
22238
+	mov	r0, r8
21707
22239
 	bl	log2phys
21708
22240
 	ldr	r3, [sp]
21709
22241
 	cmn	r3, #1
21710
-	beq	.L3654
21711
-	ldr	r3, [r9, #1996]
21712
-	add	r1, sp, #4
22242
+	beq	.L3582
22243
+	ldr	r3, [r7, #1996]
21713
22244
 	mov	r2, #1
22245
+	add	r1, sp, #4
21714
22246
 	mov	r0, r8
21715
22247
 	add	r3, r3, #1
21716
-	str	r3, [r9, #1996]
22248
+	str	r3, [r7, #1996]
21717
22249
 	ldr	r3, [r7, #-3360]
21718
22250
 	add	r3, r3, #1
21719
22251
 	str	r3, [r7, #-3360]
..
..
@@ -21722,40 +22254,27 @@
21722
22254
 	ubfx	r0, r0, #10, #16
21723
22255
 	bl	P2V_block_in_plane
21724
22256
 	bl	decrement_vpc_count
21725
-.L3654:
22257
+.L3582:
21726
22258
 	ldrh	r3, [r6]
21727
22259
 	add	r8, r8, #1
21728
-	rsb	r4, r3, r4
21729
-	b	.L3653
21730
-.L3668:
21731
-	ldr	r3, .L3669+12
21732
-	ldr	r2, [r3, #1996]
21733
-	cmp	r2, #32
21734
-	bls	.L3656
21735
-	mov	r2, #0
21736
-	str	r2, [r3, #1996]
21737
-	bl	l2p_flush
21738
-	bl	FtlVpcTblFlush
21739
-.L3656:
21740
-	mov	r0, #0
21741
-	b	.L3651
21742
-.L3658:
22260
+	sub	r4, r4, r3
22261
+	b	.L3581
22262
+.L3586:
21743
22263
 	mvn	r0, #0
21744
-.L3651:
21745
-	add	sp, sp, #12
21746
-	@ sp needed
21747
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, pc}
21748
-.L3670:
22264
+	b	.L3578
22265
+.L3597:
21749
22266
 	.align	2
21750
-.L3669:
22267
+.L3596:
21751
22268
 	.word	.LANCHOR0
21752
22269
 	.word	.LANCHOR2
21753
-	.word	.LANCHOR0+2394
21754
-	.word	.LANCHOR4
22270
+	.word	.LANCHOR0+2396
21755
22271
 	.fnend
21756
22272
 	.size	ftl_discard, .-ftl_discard
21757
22273
 	.align	2
21758
22274
 	.global	FtlDiscard
22275
+	.syntax unified
22276
+	.arm
22277
+	.fpu softvfp
21759
22278
 	.type	FtlDiscard, %function
21760
22279
 FtlDiscard:
21761
22280
 	.fnstart
..
..
@@ -21767,393 +22286,403 @@
21767
22286
 	.size	FtlDiscard, .-FtlDiscard
21768
22287
 	.align	2
21769
22288
 	.global	ftl_read
22289
+	.syntax unified
22290
+	.arm
22291
+	.fpu softvfp
21770
22292
 	.type	ftl_read, %function
21771
22293
 ftl_read:
21772
22294
 	.fnstart
21773
22295
 	@ args = 0, pretend = 0, frame = 56
21774
22296
 	@ frame_needed = 0, uses_anonymous_args = 0
21775
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
22297
+	ldr	ip, .L3643
22298
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
21776
22299
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
21777
-	mov	r5, r1
21778
-	ldr	r1, .L3720
21779
22300
 	.pad #84
21780
22301
 	sub	sp, sp, #84
21781
-	ldr	r1, [r1, #504]
21782
-	cmp	r1, #1
21783
-	bne	.L3697
22302
+	ldr	ip, [ip, #500]
22303
+	cmp	ip, #1
22304
+	bne	.L3623
21784
22305
 	cmp	r0, #16
21785
22306
 	mov	r8, r3
21786
-	mov	r9, r2
21787
-	bne	.L3674
21788
-	mov	r1, r2
21789
-	add	r0, r5, #256
22307
+	str	r2, [sp, #28]
22308
+	mov	r5, r1
22309
+	bne	.L3601
21790
22310
 	mov	r2, r3
22311
+	ldr	r1, [sp, #28]
22312
+	add	r0, r5, #256
21791
22313
 	bl	FtlVendorPartRead
21792
-	b	.L3673
21793
-.L3674:
21794
-	ldr	r2, .L3720+4
21795
-	ldr	r3, [r2, #2428]
21796
-	cmp	r9, r3
21797
-	cmpls	r5, r3
21798
-	bcs	.L3697
21799
-	add	r1, r5, r9
21800
-	str	r1, [sp, #40]
22314
+	mov	r10, r0
22315
+.L3599:
22316
+	mov	r0, r10
22317
+	add	sp, sp, #84
22318
+	@ sp needed
22319
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
22320
+.L3601:
22321
+	ldr	r2, .L3643+4
22322
+	ldr	r1, [sp, #28]
22323
+	ldr	r3, [r2, #2432]
21801
22324
 	cmp	r1, r3
21802
-	bhi	.L3697
21803
-	movw	r3, #2394
22325
+	cmpls	r5, r3
22326
+	bcs	.L3623
22327
+	add	r1, r5, r1
22328
+	cmp	r3, r1
22329
+	str	r1, [sp, #44]
22330
+	bcc	.L3623
22331
+	movw	r3, #2396
21804
22332
 	mov	r0, r5
21805
22333
 	ldrh	r4, [r2, r3]
21806
22334
 	mov	r1, r4
21807
22335
 	bl	__aeabi_uidiv
22336
+	ldr	r3, [sp, #44]
21808
22337
 	mov	r1, r4
21809
-	ldr	r3, [sp, #40]
21810
-	str	r0, [sp, #32]
22338
+	str	r0, [sp, #36]
21811
22339
 	sub	r0, r3, #1
21812
22340
 	bl	__aeabi_uidiv
21813
-	ldr	r3, [sp, #32]
21814
-	str	r0, [sp, #36]
22341
+	ldr	r3, [sp, #36]
22342
+	ldr	r1, [sp, #28]
22343
+	str	r0, [sp, #40]
21815
22344
 	rsb	r3, r3, #1
21816
22345
 	add	r3, r3, r0
21817
-	str	r3, [sp, #28]
21818
-	ldr	r3, .L3720+8
21819
-	ldr	r1, [sp, #28]
21820
-	ldr	r0, [sp, #32]
22346
+	str	r3, [sp, #32]
22347
+	ldr	r3, .L3643+8
21821
22348
 	ldr	r2, [r3, #-3336]
21822
-	add	r2, r9, r2
22349
+	add	r2, r2, r1
22350
+	ldr	r1, [sp, #32]
21823
22351
 	str	r2, [r3, #-3336]
21824
22352
 	ldr	r2, [r3, #-3364]
21825
-	add	r2, r1, r2
21826
-	ldr	r1, [sp, #36]
22353
+	add	r2, r2, r1
22354
+	mov	r1, r0
22355
+	ldr	r0, [sp, #36]
21827
22356
 	str	r2, [r3, #-3364]
21828
22357
 	bl	FtlCacheMetchLpa
21829
22358
 	cmp	r0, #0
21830
-	beq	.L3675
22359
+	beq	.L3602
21831
22360
 	bl	FtlCacheWriteBack
21832
-.L3675:
21833
-	ldr	r6, [sp, #32]
21834
-	mov	r10, #0
21835
-	ldr	r4, .L3720+8
21836
-	mov	r7, r10
21837
-	str	r10, [sp, #48]
21838
-	str	r10, [sp, #52]
21839
-.L3676:
21840
-	ldr	r3, [sp, #28]
22361
+.L3602:
22362
+	ldr	r6, [sp, #36]
22363
+	mov	r3, #0
22364
+	ldr	r4, .L3643+8
22365
+	mov	r7, r3
22366
+	mov	r10, r3
22367
+	str	r3, [sp, #52]
22368
+	str	r3, [sp, #48]
22369
+.L3603:
22370
+	ldr	r3, [sp, #32]
21841
22371
 	cmp	r3, #0
21842
-	beq	.L3719
21843
-	mov	r0, r6
21844
-	add	r1, sp, #76
22372
+	bne	.L3620
22373
+	ldr	r3, .L3643+12
22374
+	ldrh	r3, [r3, #-2]
22375
+	cmp	r3, #0
22376
+	beq	.L3599
22377
+	mov	r1, #1
22378
+	ldr	r0, [sp, #32]
22379
+	bl	ftl_do_gc
22380
+	b	.L3599
22381
+.L3620:
21845
22382
 	mov	r2, #0
22383
+	add	r1, sp, #76
22384
+	mov	r0, r6
21846
22385
 	bl	log2phys
21847
22386
 	ldr	r3, [sp, #76]
21848
22387
 	cmn	r3, #1
21849
-	bne	.L3715
21850
-	mov	fp, #0
21851
-.L3677:
21852
-	ldr	r3, .L3720+12
21853
-	ldrh	r0, [r3]
21854
-	cmp	fp, r0
21855
-	bcs	.L3681
21856
-	mla	r0, r0, r6, fp
21857
-	ldr	r2, [sp, #40]
21858
-	cmp	r0, r5
21859
-	movcs	r3, #1
21860
-	movcc	r3, #0
21861
-	cmp	r0, r2
21862
-	movcs	r3, #0
21863
-	cmp	r3, #0
21864
-	beq	.L3679
21865
-	rsb	r0, r5, r0
21866
-	mov	r1, #0
21867
-	mov	r2, #512
21868
-	add	r0, r8, r0, asl #9
21869
-	bl	ftl_memset
21870
-.L3679:
21871
-	add	fp, fp, #1
21872
-	b	.L3677
21873
-.L3715:
22388
+	moveq	r9, #0
22389
+	beq	.L3605
21874
22390
 	ldr	r2, [r4, #-536]
21875
-	mov	fp, #36
21876
-	mla	fp, fp, r7, r2
21877
-	str	r3, [fp, #4]
21878
-	ldr	r3, [sp, #32]
21879
-	cmp	r6, r3
21880
-	bne	.L3682
21881
-	ldr	r3, [r4, #-508]
21882
-	mov	r0, r5
21883
-	str	r3, [fp, #8]
21884
-	ldr	r3, .L3720+12
21885
-	ldrh	ip, [r3]
21886
-	mov	r1, ip
21887
-	str	ip, [sp, #44]
21888
-	bl	__aeabi_uidivmod
21889
-	ldr	ip, [sp, #44]
21890
-	str	r1, [sp, #56]
21891
-	rsb	r3, r1, ip
21892
-	cmp	r3, r9
21893
-	movcs	r3, r9
21894
-	cmp	r3, ip
21895
-	str	r3, [sp, #48]
21896
-	streq	r8, [fp, #8]
21897
-	b	.L3683
21898
-.L3682:
22391
+	mov	r9, #36
22392
+	mla	r9, r9, r7, r2
22393
+	str	r3, [r9, #4]
21899
22394
 	ldr	r3, [sp, #36]
21900
22395
 	cmp	r6, r3
21901
-	bne	.L3684
21902
-	ldr	r3, [r4, #-504]
21903
-	ldr	r1, [sp, #40]
21904
-	str	r3, [fp, #8]
21905
-	ldr	r3, .L3720+12
21906
-	ldrh	r2, [r3]
21907
-	mul	r3, r2, r6
21908
-	rsb	r10, r3, r1
21909
-	cmp	r10, r2
21910
-	bne	.L3683
21911
-	b	.L3717
21912
-.L3684:
21913
-	ldr	r3, .L3720+12
21914
-	ldrh	r3, [r3]
21915
-	mul	r3, r3, r6
21916
-.L3717:
21917
-	rsb	r3, r5, r3
21918
-	add	r3, r8, r3, asl #9
21919
-	str	r3, [fp, #8]
21920
-.L3683:
21921
-	ldr	r3, .L3720+16
22396
+	bne	.L3609
22397
+	ldr	r3, [r4, #-508]
22398
+	mov	r0, r5
22399
+	str	r3, [r9, #8]
22400
+	ldr	r3, .L3643+16
22401
+	ldrh	fp, [r3]
22402
+	mov	r1, fp
22403
+	bl	__aeabi_uidivmod
22404
+	ldr	r2, [sp, #28]
22405
+	sub	r3, fp, r1
22406
+	str	r1, [sp, #56]
22407
+	cmp	r2, r3
22408
+	movcc	r3, r2
22409
+	cmp	r3, fp
22410
+	str	r3, [sp, #48]
22411
+	streq	r8, [r9, #8]
22412
+.L3610:
22413
+	ldr	r3, .L3643+20
21922
22414
 	ldr	r2, [r4, #-496]
21923
-	str	r6, [fp, #16]
22415
+	str	r6, [r9, #16]
21924
22416
 	ldrh	r3, [r3]
21925
-	mul	r3, r3, r7
22417
+	mul	r3, r7, r3
21926
22418
 	add	r7, r7, #1
21927
22419
 	bic	r3, r3, #3
21928
22420
 	add	r3, r2, r3
21929
-	str	r3, [fp, #12]
21930
-.L3681:
21931
-	ldr	r3, [sp, #28]
22421
+	str	r3, [r9, #12]
22422
+	b	.L3608
22423
+.L3607:
22424
+	mla	r0, r0, r6, r9
22425
+	ldr	r2, [sp, #44]
22426
+	cmp	r5, r0
22427
+	movls	r3, #1
22428
+	movhi	r3, #0
22429
+	cmp	r2, r0
22430
+	movls	r3, #0
22431
+	cmp	r3, #0
22432
+	beq	.L3606
22433
+	sub	r0, r0, r5
22434
+	mov	r2, #512
22435
+	mov	r1, #0
22436
+	add	r0, r8, r0, lsl #9
22437
+	bl	ftl_memset
22438
+.L3606:
22439
+	add	r9, r9, #1
22440
+.L3605:
22441
+	ldr	r3, .L3643+16
22442
+	ldrh	r0, [r3]
22443
+	cmp	r9, r0
22444
+	bcc	.L3607
22445
+.L3608:
22446
+	ldr	r3, [sp, #32]
21932
22447
 	add	r6, r6, #1
21933
22448
 	subs	r3, r3, #1
21934
-	str	r3, [sp, #28]
21935
-	beq	.L3685
21936
-	ldr	r3, .L3720+20
22449
+	str	r3, [sp, #32]
22450
+	beq	.L3612
22451
+	ldr	r3, .L3643+24
21937
22452
 	ldrh	r3, [r3]
21938
-	cmp	r7, r3, asl #3
21939
-	bne	.L3676
21940
-.L3685:
22453
+	cmp	r7, r3, lsl #3
22454
+	bne	.L3603
22455
+.L3612:
21941
22456
 	cmp	r7, #0
21942
-	beq	.L3676
21943
-	ldr	r0, [r4, #-536]
21944
-	mov	r1, r7
22457
+	beq	.L3603
21945
22458
 	mov	r2, #0
22459
+	mov	r1, r7
22460
+	ldr	r0, [r4, #-536]
22461
+	mov	fp, #0
21946
22462
 	bl	FlashReadPages
22463
+	ldr	r3, [sp, #52]
22464
+	lsl	r3, r3, #9
22465
+	str	r3, [sp, #68]
21947
22466
 	ldr	r3, [sp, #56]
21948
-	mov	r3, r3, asl #9
22467
+	lsl	r3, r3, #9
21949
22468
 	str	r3, [sp, #60]
21950
22469
 	ldr	r3, [sp, #48]
21951
-	mov	r3, r3, asl #9
22470
+	lsl	r3, r3, #9
21952
22471
 	str	r3, [sp, #64]
21953
-	mov	r3, r10, asl #9
21954
-	str	r3, [sp, #68]
21955
-	mov	r3, #0
21956
-	str	r3, [sp, #44]
21957
-.L3692:
21958
-	ldr	r3, [sp, #44]
21959
-	mov	ip, #36
21960
-	ldr	r1, [sp, #32]
21961
-	mul	fp, ip, r3
22472
+.L3619:
22473
+	mov	r9, #36
21962
22474
 	ldr	r3, [r4, #-536]
21963
-	add	r3, r3, fp
22475
+	mul	r9, r9, fp
22476
+	ldr	r1, [sp, #36]
22477
+	add	r3, r3, r9
21964
22478
 	ldr	r2, [r3, #16]
21965
-	cmp	r2, r1
21966
-	bne	.L3687
22479
+	cmp	r1, r2
22480
+	bne	.L3614
21967
22481
 	ldr	r1, [r3, #8]
21968
22482
 	ldr	r3, [r4, #-508]
21969
22483
 	cmp	r1, r3
21970
-	bne	.L3688
22484
+	bne	.L3615
21971
22485
 	ldr	r3, [sp, #60]
21972
22486
 	mov	r0, r8
21973
22487
 	ldr	r2, [sp, #64]
21974
22488
 	add	r1, r1, r3
21975
-	b	.L3718
21976
-.L3687:
21977
-	ldr	r1, [sp, #36]
21978
-	cmp	r2, r1
21979
-	bne	.L3688
21980
-	ldr	r1, [r3, #8]
21981
-	ldr	r3, [r4, #-504]
21982
-	cmp	r1, r3
21983
-	bne	.L3688
21984
-	ldr	r3, .L3720+12
21985
-	ldr	r2, [sp, #68]
21986
-	ldrh	r0, [r3]
21987
-	ldr	r3, [sp, #36]
21988
-	mul	r0, r0, r3
21989
-	rsb	r0, r5, r0
21990
-	add	r0, r8, r0, asl #9
21991
-.L3718:
22489
+.L3642:
21992
22490
 	bl	ftl_memcpy
21993
-.L3688:
21994
-	ldr	r2, [r4, #-536]
21995
-	add	r3, r2, fp
21996
-	ldr	r1, [r2, fp]
21997
-	cmn	r1, #1
21998
-	streq	r1, [sp, #52]
21999
-	ldreq	r2, [r4, #-3160]
22000
-	addeq	r2, r2, #1
22001
-	streq	r2, [r4, #-3160]
22002
-	ldr	r2, [r3, #12]
22003
-	ldr	r1, [r3, #16]
22004
-	ldr	r2, [r2, #8]
22005
-	cmp	r1, r2
22006
-	beq	.L3690
22007
-	ldr	r2, [r4, #-3160]
22008
-	ldr	r0, .L3720+24
22009
-	add	r2, r2, #1
22010
-	str	r2, [r4, #-3160]
22011
-	ldr	lr, [r3, #12]
22012
-	ldr	r2, [r3, #8]
22013
-	ldr	r1, [lr, #4]
22014
-	str	r1, [sp]
22015
-	ldr	r1, [lr, #8]
22016
-	str	r1, [sp, #4]
22017
-	ldr	r1, [lr, #12]
22018
-	str	r1, [sp, #8]
22019
-	ldr	r1, [r2]
22020
-	str	r1, [sp, #12]
22021
-	ldr	r2, [r2, #4]
22022
-	str	r2, [sp, #16]
22023
-	ldr	r1, [r3, #16]
22024
-	ldr	r2, [r3, #4]
22025
-	ldr	r3, [lr]
22026
-	bl	printk
22027
-.L3690:
22491
+.L3615:
22028
22492
 	ldr	r3, [r4, #-536]
22029
-	add	r2, r3, fp
22030
-	ldr	r3, [r3, fp]
22493
+	ldr	r2, [r3, r9]
22494
+	add	r1, r3, r9
22495
+	cmn	r2, #1
22496
+	ldreq	r3, [r4, #-3164]
22497
+	moveq	r10, r2
22498
+	addeq	r3, r3, #1
22499
+	streq	r3, [r4, #-3164]
22500
+	ldr	r3, [r1, #12]
22501
+	ldr	r2, [r1, #16]
22502
+	ldr	r3, [r3, #8]
22503
+	cmp	r2, r3
22504
+	beq	.L3617
22505
+	ldr	r3, [r4, #-3164]
22506
+	add	r3, r3, #1
22507
+	str	r3, [r4, #-3164]
22508
+	ldr	r2, [r1, #8]
22509
+	ldr	r3, [r1, #12]
22510
+	ldr	r0, [r2, #4]
22511
+	str	r0, [sp, #16]
22512
+	ldr	r2, [r2]
22513
+	ldr	r0, .L3643+28
22514
+	str	r2, [sp, #12]
22515
+	ldr	r2, [r3, #12]
22516
+	str	r2, [sp, #8]
22517
+	ldr	r2, [r3, #8]
22518
+	str	r2, [sp, #4]
22519
+	ldr	r2, [r3, #4]
22520
+	str	r2, [sp]
22521
+	ldr	r2, [r1, #4]
22522
+	ldr	r3, [r3]
22523
+	ldr	r1, [r1, #16]
22524
+	bl	printk
22525
+.L3617:
22526
+	ldr	r3, [r4, #-536]
22527
+	add	r2, r3, r9
22528
+	ldr	r3, [r3, r9]
22031
22529
 	cmp	r3, #256
22032
-	bne	.L3691
22530
+	bne	.L3618
22033
22531
 	ldr	r0, [r2, #4]
22034
22532
 	ubfx	r0, r0, #10, #16
22035
22533
 	bl	P2V_block_in_plane
22036
22534
 	bl	FtlGcRefreshBlock
22037
-.L3691:
22038
-	ldr	r3, [sp, #44]
22039
-	add	r3, r3, #1
22040
-	str	r3, [sp, #44]
22041
-	cmp	r3, r7
22042
-	bne	.L3692
22535
+.L3618:
22536
+	add	fp, fp, #1
22537
+	cmp	r7, fp
22538
+	bne	.L3619
22043
22539
 	mov	r7, #0
22044
-	b	.L3676
22045
-.L3719:
22046
-	ldr	r3, .L3720+28
22047
-	ldrh	r3, [r3, #-2]
22048
-	cmp	r3, #0
22049
-	beq	.L3694
22050
-	ldr	r0, [sp, #28]
22051
-	mov	r1, #1
22052
-	bl	ftl_do_gc
22053
-.L3694:
22054
-	ldr	r0, [sp, #52]
22055
-	b	.L3673
22056
-.L3697:
22057
-	mvn	r0, #0
22058
-.L3673:
22059
-	add	sp, sp, #84
22060
-	@ sp needed
22061
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
22062
-.L3721:
22540
+	b	.L3603
22541
+.L3609:
22542
+	ldr	r3, [sp, #40]
22543
+	cmp	r6, r3
22544
+	bne	.L3611
22545
+	ldr	r3, [r4, #-504]
22546
+	ldr	r1, [sp, #44]
22547
+	str	r3, [r9, #8]
22548
+	ldr	r3, .L3643+16
22549
+	ldrh	r2, [r3]
22550
+	mul	r3, r2, r6
22551
+	sub	r1, r1, r3
22552
+	cmp	r2, r1
22553
+	str	r1, [sp, #52]
22554
+	bne	.L3610
22555
+.L3641:
22556
+	sub	r3, r3, r5
22557
+	add	r3, r8, r3, lsl #9
22558
+	str	r3, [r9, #8]
22559
+	b	.L3610
22560
+.L3611:
22561
+	ldr	r3, .L3643+16
22562
+	ldrh	r3, [r3]
22563
+	mul	r3, r6, r3
22564
+	b	.L3641
22565
+.L3614:
22566
+	ldr	r1, [sp, #40]
22567
+	cmp	r1, r2
22568
+	bne	.L3615
22569
+	ldr	r1, [r3, #8]
22570
+	ldr	r3, [r4, #-504]
22571
+	cmp	r1, r3
22572
+	bne	.L3615
22573
+	ldr	r3, .L3643+16
22574
+	ldr	r2, [sp, #68]
22575
+	ldrh	r0, [r3]
22576
+	ldr	r3, [sp, #40]
22577
+	mul	r0, r3, r0
22578
+	sub	r0, r0, r5
22579
+	add	r0, r8, r0, lsl #9
22580
+	b	.L3642
22581
+.L3623:
22582
+	mvn	r10, #0
22583
+	b	.L3599
22584
+.L3644:
22063
22585
 	.align	2
22064
-.L3720:
22586
+.L3643:
22065
22587
 	.word	.LANCHOR1
22066
22588
 	.word	.LANCHOR0
22067
22589
 	.word	.LANCHOR2
22068
-	.word	.LANCHOR0+2394
22069
-	.word	.LANCHOR0+2400
22070
-	.word	.LANCHOR0+2320
22071
-	.word	.LC148
22072
22590
 	.word	.LANCHOR2-2656
22591
+	.word	.LANCHOR0+2396
22592
+	.word	.LANCHOR0+2402
22593
+	.word	.LANCHOR0+2324
22594
+	.word	.LC148
22073
22595
 	.fnend
22074
22596
 	.size	ftl_read, .-ftl_read
22075
22597
 	.align	2
22076
22598
 	.global	ftl_vendor_read
22599
+	.syntax unified
22600
+	.arm
22601
+	.fpu softvfp
22077
22602
 	.type	ftl_vendor_read, %function
22078
22603
 ftl_vendor_read:
22079
22604
 	.fnstart
22080
22605
 	@ args = 0, pretend = 0, frame = 0
22081
22606
 	@ frame_needed = 0, uses_anonymous_args = 0
22082
-	str	lr, [sp, #-4]!
22083
-	.save {lr}
22084
-	mov	ip, r1
22085
-	mov	lr, r0
22607
+	@ link register save eliminated.
22086
22608
 	mov	r3, r2
22087
-	mov	r1, lr
22609
+	mov	r2, r1
22610
+	mov	r1, r0
22088
22611
 	mov	r0, #16
22089
-	mov	r2, ip
22090
-	ldr	lr, [sp], #4
22091
22612
 	b	ftl_read
22092
22613
 	.fnend
22093
22614
 	.size	ftl_vendor_read, .-ftl_vendor_read
22094
22615
 	.align	2
22095
22616
 	.global	FlashBootVendorRead
22617
+	.syntax unified
22618
+	.arm
22619
+	.fpu softvfp
22096
22620
 	.type	FlashBootVendorRead, %function
22097
22621
 FlashBootVendorRead:
22098
22622
 	.fnstart
22099
22623
 	@ args = 0, pretend = 0, frame = 0
22100
22624
 	@ frame_needed = 0, uses_anonymous_args = 0
22101
-	stmfd	sp!, {r4, r5, r6, lr}
22625
+	push	{r4, r5, r6, lr}
22102
22626
 	.save {r4, r5, r6, lr}
22103
-	mov	r4, r2
22104
-	mov	r6, r0
22627
+	mov	r4, r0
22105
22628
 	mov	r5, r1
22629
+	mov	r6, r2
22106
22630
 	bl	rknand_device_lock
22107
-	ldr	r3, .L3728
22108
-	ldr	r3, [r3, #504]
22631
+	ldr	r3, .L3650
22632
+	ldr	r3, [r3, #500]
22109
22633
 	cmp	r3, #1
22110
22634
 	mvnne	r4, #0
22111
-	bne	.L3725
22112
-	mov	r2, r4
22113
-	mov	r0, r6
22635
+	bne	.L3647
22636
+	mov	r0, r4
22637
+	mov	r2, r6
22114
22638
 	mov	r1, r5
22115
22639
 	bl	ftl_vendor_read
22116
22640
 	mov	r4, r0
22117
-.L3725:
22641
+.L3647:
22118
22642
 	bl	rknand_device_unlock
22119
22643
 	mov	r0, r4
22120
-	ldmfd	sp!, {r4, r5, r6, pc}
22121
-.L3729:
22644
+	pop	{r4, r5, r6, pc}
22645
+.L3651:
22122
22646
 	.align	2
22123
-.L3728:
22647
+.L3650:
22124
22648
 	.word	.LANCHOR1
22125
22649
 	.fnend
22126
22650
 	.size	FlashBootVendorRead, .-FlashBootVendorRead
22127
22651
 	.align	2
22128
22652
 	.global	ftl_sys_read
22653
+	.syntax unified
22654
+	.arm
22655
+	.fpu softvfp
22129
22656
 	.type	ftl_sys_read, %function
22130
22657
 ftl_sys_read:
22131
22658
 	.fnstart
22132
22659
 	@ args = 0, pretend = 0, frame = 0
22133
22660
 	@ frame_needed = 0, uses_anonymous_args = 0
22134
22661
 	@ link register save eliminated.
22135
-	mov	ip, r1
22136
22662
 	mov	r3, r2
22663
+	mov	r2, r1
22137
22664
 	add	r1, r0, #256
22138
-	mov	r2, ip
22139
22665
 	mov	r0, #16
22140
22666
 	b	ftl_read
22141
22667
 	.fnend
22142
22668
 	.size	ftl_sys_read, .-ftl_sys_read
22143
22669
 	.align	2
22144
22670
 	.global	StorageSysDataLoad
22671
+	.syntax unified
22672
+	.arm
22673
+	.fpu softvfp
22145
22674
 	.type	StorageSysDataLoad, %function
22146
22675
 StorageSysDataLoad:
22147
22676
 	.fnstart
22148
22677
 	@ args = 0, pretend = 0, frame = 0
22149
22678
 	@ frame_needed = 0, uses_anonymous_args = 0
22150
-	stmfd	sp!, {r3, r4, r5, lr}
22151
-	.save {r3, r4, r5, lr}
22152
-	mov	r2, #512
22153
-	mov	r5, r0
22679
+	push	{r4, r5, r6, lr}
22680
+	.save {r4, r5, r6, lr}
22154
22681
 	mov	r4, r1
22155
-	mov	r0, r1
22682
+	mov	r5, r0
22683
+	mov	r2, #512
22156
22684
 	mov	r1, #0
22685
+	mov	r0, r4
22157
22686
 	bl	ftl_memset
22158
22687
 	bl	rknand_device_lock
22159
22688
 	mov	r2, r4
..
..
@@ -22163,11 +22692,14 @@
22163
22692
 	mov	r4, r0
22164
22693
 	bl	rknand_device_unlock
22165
22694
 	mov	r0, r4
22166
-	ldmfd	sp!, {r3, r4, r5, pc}
22695
+	pop	{r4, r5, r6, pc}
22167
22696
 	.fnend
22168
22697
 	.size	StorageSysDataLoad, .-StorageSysDataLoad
22169
22698
 	.align	2
22170
22699
 	.global	FtlRead
22700
+	.syntax unified
22701
+	.arm
22702
+	.fpu softvfp
22171
22703
 	.type	FtlRead, %function
22172
22704
 FtlRead:
22173
22705
 	.fnstart
..
..
@@ -22179,284 +22711,288 @@
22179
22711
 	.size	FtlRead, .-FtlRead
22180
22712
 	.align	2
22181
22713
 	.global	FtlInit
22714
+	.syntax unified
22715
+	.arm
22716
+	.fpu softvfp
22182
22717
 	.type	FtlInit, %function
22183
22718
 FtlInit:
22184
22719
 	.fnstart
22185
22720
 	@ args = 0, pretend = 0, frame = 0
22186
22721
 	@ frame_needed = 0, uses_anonymous_args = 0
22187
-	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
22722
+	push	{r4, r5, r6, r7, r8, lr}
22188
22723
 	.save {r4, r5, r6, r7, r8, lr}
22189
22724
 	mvn	r3, #0
22190
-	ldr	r2, .L3751
22191
-	ldr	r7, .L3751+4
22192
-	ldr	r5, .L3751+8
22193
-	ldr	r6, .L3751+12
22194
-	ldr	r1, .L3751+16
22195
-	ldr	r0, .L3751+20
22196
-	str	r3, [r7, #504]
22725
+	ldr	r7, .L3673
22726
+	ldr	r5, .L3673+4
22727
+	ldr	r6, .L3673+8
22728
+	ldr	r1, .L3673+12
22729
+	str	r3, [r7, #500]
22197
22730
 	mov	r3, #0
22198
-	str	r3, [r2, #2000]
22199
-	str	r3, [r5, #-3616]
22731
+	ldr	r0, .L3673+16
22732
+	str	r3, [r5, #2000]
22733
+	str	r3, [r5, #-3612]
22200
22734
 	bl	printk
22201
-	add	r0, r6, #116
22735
+	add	r0, r6, #124
22202
22736
 	bl	FtlConstantsInit
22203
22737
 	bl	FtlMemInit
22204
22738
 	bl	FtlVariablesInit
22205
-	ldr	r3, [r6, #2324]
22206
-	uxth	r0, r3
22739
+	add	r3, r6, #2320
22740
+	add	r3, r3, #8
22741
+	ldrh	r0, [r3]
22207
22742
 	bl	FtlFreeSysBlkQueueInit
22208
22743
 	bl	FtlLoadBbt
22209
22744
 	cmp	r0, #0
22210
-	ldrne	r0, .L3751+24
22211
-	bne	.L3750
22745
+	beq	.L3657
22746
+	ldr	r1, .L3673+20
22747
+	ldr	r0, .L3673+24
22748
+.L3672:
22749
+	bl	printk
22750
+.L3658:
22751
+	mov	r0, #0
22752
+	pop	{r4, r5, r6, r7, r8, pc}
22753
+.L3657:
22212
22754
 	bl	FtlSysBlkInit
22213
22755
 	subs	r4, r0, #0
22214
-	beq	.L3737
22215
-	ldr	r0, .L3751+28
22216
-.L3750:
22217
-	ldr	r1, .L3751+32
22218
-	bl	printk
22219
-	b	.L3736
22220
-.L3737:
22221
-	sub	r5, r5, #3520
22756
+	ldrne	r1, .L3673+20
22757
+	ldrne	r0, .L3673+28
22758
+	bne	.L3672
22759
+.L3659:
22222
22760
 	mov	r1, #1
22223
-	str	r1, [r7, #504]
22761
+	sub	r5, r5, #3520
22762
+	str	r1, [r7, #500]
22224
22763
 	bl	ftl_do_gc
22225
-	ldrh	r5, [r5, #-8]
22226
-	cmp	r5, #15
22227
-	bhi	.L3738
22228
-	ldr	r6, .L3751+36
22229
-	ldr	r7, .L3751+40
22230
-	sub	r8, r6, #244
22231
-.L3741:
22232
-	ldrh	r3, [r6]
22764
+	ldrh	r7, [r5, #-4]
22765
+	cmp	r7, #15
22766
+	bhi	.L3660
22767
+.L3663:
22768
+	ldr	r3, .L3673+32
22233
22769
 	movw	r2, #65535
22770
+	ldrh	r3, [r3]
22234
22771
 	cmp	r3, r2
22235
-	bne	.L3739
22236
-	ldrh	r2, [r7]
22772
+	bne	.L3661
22773
+	ldr	r2, .L3673+36
22774
+	ldrh	r2, [r2]
22237
22775
 	cmp	r2, r3
22238
-	bne	.L3739
22776
+	bne	.L3661
22239
22777
 	and	r0, r4, #63
22240
22778
 	bl	List_get_gc_head_node
22241
22779
 	uxth	r0, r0
22242
22780
 	bl	FtlGcRefreshBlock
22243
-.L3739:
22244
-	mov	r0, #1
22245
-	mov	r1, r0
22246
-	bl	ftl_do_gc
22247
-	mov	r0, #0
22781
+.L3661:
22248
22782
 	mov	r1, #1
22783
+	mov	r0, r1
22249
22784
 	bl	ftl_do_gc
22250
-	ldrh	r2, [r8]
22251
-	add	r3, r5, #2
22785
+	mov	r1, #1
22786
+	mov	r0, #0
22787
+	bl	ftl_do_gc
22788
+	ldrh	r2, [r5, #-4]
22789
+	add	r3, r7, #2
22252
22790
 	cmp	r2, r3
22253
-	bhi	.L3736
22791
+	bhi	.L3658
22254
22792
 	add	r4, r4, #1
22255
22793
 	cmp	r4, #4096
22256
-	bne	.L3741
22257
-	b	.L3736
22258
-.L3738:
22259
-	ldrb	r3, [r6, #144]	@ zero_extendqisi2
22794
+	bne	.L3663
22795
+	b	.L3658
22796
+.L3660:
22797
+	ldrb	r3, [r6, #152]	@ zero_extendqisi2
22260
22798
 	cmp	r3, #0
22261
-	beq	.L3736
22799
+	beq	.L3658
22262
22800
 	mov	r4, #128
22263
-.L3743:
22264
-	mov	r0, #1
22265
-	mov	r1, r0
22801
+.L3665:
22802
+	mov	r1, #1
22803
+	mov	r0, r1
22266
22804
 	bl	ftl_do_gc
22267
22805
 	subs	r4, r4, #1
22268
-	bne	.L3743
22269
-.L3736:
22270
-	mov	r0, #0
22271
-	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
22272
-.L3752:
22806
+	bne	.L3665
22807
+	b	.L3658
22808
+.L3674:
22273
22809
 	.align	2
22274
-.L3751:
22275
-	.word	.LANCHOR4
22810
+.L3673:
22276
22811
 	.word	.LANCHOR1
22277
22812
 	.word	.LANCHOR2
22278
22813
 	.word	.LANCHOR0
22279
-	.word	.LC77
22280
22814
 	.word	.LC76
22815
+	.word	.LC77
22816
+	.word	.LANCHOR3+224
22281
22817
 	.word	.LC161
22282
22818
 	.word	.LC162
22283
-	.word	.LANCHOR3+240
22284
22819
 	.word	.LANCHOR2-3284
22285
22820
 	.word	.LANCHOR2-2666
22286
22821
 	.fnend
22287
22822
 	.size	FtlInit, .-FtlInit
22288
22823
 	.align	2
22289
22824
 	.global	rk_ftl_init
22825
+	.syntax unified
22826
+	.arm
22827
+	.fpu softvfp
22290
22828
 	.type	rk_ftl_init, %function
22291
22829
 rk_ftl_init:
22292
22830
 	.fnstart
22293
22831
 	@ args = 0, pretend = 0, frame = 0
22294
22832
 	@ frame_needed = 0, uses_anonymous_args = 0
22295
-	stmfd	sp!, {r4, r5, r6, lr}
22833
+	push	{r4, r5, r6, lr}
22296
22834
 	.save {r4, r5, r6, lr}
22297
22835
 	mov	r0, #2048
22298
-	bl	ftl_malloc
22299
-	ldr	r6, .L3758
22300
-	ldr	r4, .L3758+4
22836
+	bl	ftl_dma32_malloc
22301
22837
 	mov	r5, #0
22302
-	ldr	r1, .L3758+8
22303
-	str	r5, [r6, #2008]
22838
+	ldr	r4, .L3680
22839
+	ldr	r1, .L3680+4
22840
+	str	r0, [r4, #2004]
22841
+	sub	r0, r1, #324
22842
+	str	r5, [r4, #1688]
22304
22843
 	str	r5, [r4, #1684]
22305
-	str	r0, [r6, #2004]
22306
-	ldr	r0, .L3758+12
22844
+	str	r5, [r4, #2008]
22307
22845
 	bl	rknand_get_reg_addr
22308
22846
 	ldr	r3, [r4, #1684]
22309
22847
 	cmp	r3, r5
22310
-	beq	.L3756
22848
+	mvneq	r4, #0
22849
+	beq	.L3675
22311
22850
 	bl	rk_nandc_irq_init
22312
-	mov	r1, r5
22313
-	mov	r2, r5
22314
22851
 	mov	r3, #2048
22315
-	ldr	r0, [r6, #2004]
22852
+	mov	r2, r5
22853
+	mov	r1, r5
22854
+	ldr	r0, [r4, #2004]
22316
22855
 	bl	FlashSramLoadStore
22317
22856
 	bl	rknand_flash_cs_init
22318
22857
 	ldr	r0, [r4, #1684]
22319
22858
 	bl	FlashInit
22320
22859
 	subs	r4, r0, #0
22321
-	bne	.L3755
22860
+	bne	.L3677
22322
22861
 	bl	FtlInit
22323
-.L3755:
22862
+.L3677:
22324
22863
 	mov	r1, r4
22325
-	ldr	r0, .L3758+16
22864
+	ldr	r0, .L3680+8
22326
22865
 	bl	printk
22866
+.L3675:
22327
22867
 	mov	r0, r4
22328
-	ldmfd	sp!, {r4, r5, r6, pc}
22329
-.L3756:
22330
-	mvn	r0, #0
22331
-	ldmfd	sp!, {r4, r5, r6, pc}
22332
-.L3759:
22868
+	pop	{r4, r5, r6, pc}
22869
+.L3681:
22333
22870
 	.align	2
22334
-.L3758:
22335
-	.word	.LANCHOR4
22871
+.L3680:
22336
22872
 	.word	.LANCHOR2
22337
-	.word	.LANCHOR4+2008
22338
-	.word	.LANCHOR2+1684
22873
+	.word	.LANCHOR2+2008
22339
22874
 	.word	.LC163
22340
22875
 	.fnend
22341
22876
 	.size	rk_ftl_init, .-rk_ftl_init
22342
22877
 	.align	2
22343
22878
 	.global	ftl_fix_nand_power_lost_error
22879
+	.syntax unified
22880
+	.arm
22881
+	.fpu softvfp
22344
22882
 	.type	ftl_fix_nand_power_lost_error, %function
22345
22883
 ftl_fix_nand_power_lost_error:
22346
22884
 	.fnstart
22347
22885
 	@ args = 0, pretend = 0, frame = 48
22348
22886
 	@ frame_needed = 0, uses_anonymous_args = 0
22349
-	ldr	r3, .L3777
22350
-	ldrb	r3, [r3, #144]	@ zero_extendqisi2
22887
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
22888
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
22889
+	.pad #48
22890
+	sub	sp, sp, #48
22891
+	ldr	r8, .L3697
22892
+	ldrb	r3, [r8, #152]	@ zero_extendqisi2
22351
22893
 	cmp	r3, #0
22352
-	bxeq	lr
22353
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
22354
-	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
22355
-	movw	r3, #1848
22356
-	ldr	r8, .L3777+4
22357
-	.pad #52
22358
-	sub	sp, sp, #52
22359
-	ldr	r4, .L3777+8
22894
+	beq	.L3682
22895
+	ldr	r4, .L3697+4
22896
+	movw	r3, #1846
22897
+	ldr	r0, .L3697+8
22898
+	ldrh	r6, [r4, r3]
22899
+	sub	r9, r4, #3520
22900
+	ldr	r3, [r4, #-3540]
22901
+	sub	r5, r4, #3472
22902
+	mov	r1, r6
22903
+	lsl	r7, r6, #1
22904
+	ldrh	r2, [r3, r7]
22905
+	bl	printk
22906
+	ldrh	r0, [r9]
22907
+	bl	FtlGcRefreshOpenBlock
22908
+	ldrh	r0, [r5]
22909
+	bl	FtlGcRefreshOpenBlock
22910
+	mov	r0, r9
22911
+	bl	allocate_new_data_superblock
22912
+	mov	r0, r5
22360
22913
 	movw	r5, #4097
22361
-	ldr	r0, .L3777+12
22362
-	ldrh	r7, [r8, r3]
22363
-	ldr	r3, [r4, #-3544]
22364
-	mov	r6, r7, asl #1
22365
-	mov	r1, r7
22366
-	ldrh	r2, [r3, r6]
22367
-	bl	printk
22368
-	sub	r3, r4, #3520
22369
-	ldrh	r0, [r3, #-4]
22370
-	bl	FtlGcRefreshOpenBlock
22371
-	sub	r3, r4, #3472
22372
-	ldrh	r0, [r3, #-4]
22373
-	bl	FtlGcRefreshOpenBlock
22374
-	ldr	r0, .L3777+16
22375
22914
 	bl	allocate_new_data_superblock
22376
-	ldr	r0, .L3777+20
22377
-	bl	allocate_new_data_superblock
22378
-.L3762:
22915
+.L3684:
22379
22916
 	subs	r5, r5, #1
22380
-	beq	.L3766
22381
-	mov	r0, #1
22382
-	mov	r1, r0
22917
+	beq	.L3688
22918
+	mov	r1, #1
22919
+	mov	r0, r1
22383
22920
 	bl	ftl_do_gc
22384
-	ldr	r3, [r4, #-3544]
22385
-	ldrh	r3, [r3, r6]
22921
+	ldr	r3, [r4, #-3540]
22922
+	ldrh	r3, [r3, r7]
22386
22923
 	cmp	r3, #0
22387
-	bne	.L3762
22388
-.L3766:
22389
-	ldr	r3, [r4, #-3544]
22390
-	mov	r1, r7
22391
-	ldr	r0, .L3777+12
22392
-	ldrh	r2, [r3, r6]
22924
+	bne	.L3684
22925
+.L3688:
22926
+	ldr	r3, [r4, #-3540]
22927
+	mov	r1, r6
22928
+	ldr	r0, .L3697+8
22929
+	ldrh	r2, [r3, r7]
22393
22930
 	bl	printk
22394
-	ldr	r3, [r4, #-3544]
22395
-	ldrh	r5, [r3, r6]
22931
+	ldr	r3, [r4, #-3540]
22932
+	ldrh	r5, [r3, r7]
22396
22933
 	cmp	r5, #0
22397
-	bne	.L3764
22934
+	bne	.L3686
22398
22935
 	add	r0, sp, #48
22399
-	movw	r10, #65535
22400
-	mov	fp, #36
22401
-	strh	r7, [r0, #-48]!	@ movhi
22936
+	movw	r9, #65535
22937
+	strh	r6, [r0, #-48]!	@ movhi
22938
+	mov	r10, #36
22402
22939
 	bl	make_superblock
22403
-	ldr	r3, .L3777+24
22404
-	ldrh	lr, [r3]
22405
-	ldr	r3, .L3777+8
22406
-	ldr	r9, [r3, #-3612]
22407
-	mov	r3, r5
22408
-	mov	ip, r3
22940
+	movw	r3, #2324
22409
22941
 	add	r0, sp, #14
22410
-.L3767:
22411
-	uxth	r2, r3
22412
-	cmp	r2, lr
22413
-	bcs	.L3776
22414
-	ldrh	r2, [r0, #2]!
22415
-	add	r3, r3, #1
22416
-	cmp	r2, r10
22417
-	movne	r2, r2, asl #10
22418
-	mlane	r1, fp, r5, r9
22942
+	ldrh	lr, [r8, r3]
22943
+	mov	r2, r5
22944
+	ldr	r8, [r4, #-3608]
22945
+	mov	ip, r5
22946
+.L3689:
22947
+	uxth	r3, r2
22948
+	cmp	lr, r3
22949
+	bhi	.L3691
22950
+	ldr	r3, [r4, #-3540]
22951
+	mov	r1, r6
22952
+	ldr	r0, .L3697+12
22953
+	ldrh	r2, [r3, r7]
22954
+	bl	printk
22955
+	mov	r2, r5
22956
+	mov	r1, #0
22957
+	ldr	r0, [r4, #-3608]
22958
+	bl	FlashEraseBlocks
22959
+	mov	r2, r5
22960
+	mov	r1, #1
22961
+	ldr	r0, [r4, #-3608]
22962
+	bl	FlashEraseBlocks
22963
+.L3686:
22964
+	mvn	r2, #0
22965
+	movw	r3, #1846
22966
+	strh	r2, [r4, r3]	@ movhi
22967
+.L3682:
22968
+	add	sp, sp, #48
22969
+	@ sp needed
22970
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
22971
+.L3691:
22972
+	ldrh	r3, [r0, #2]!
22973
+	add	r2, r2, #1
22974
+	cmp	r3, r9
22975
+	mlane	r1, r10, r5, r8
22976
+	lslne	r3, r3, #10
22419
22977
 	addne	r5, r5, #1
22420
22978
 	uxthne	r5, r5
22421
-	stmneib	r1, {r2, ip}
22979
+	stmibne	r1, {r3, ip}
22422
22980
 	strne	ip, [r1, #12]
22423
-	b	.L3767
22424
-.L3776:
22425
-	ldr	r3, [r4, #-3544]
22426
-	mov	r1, r7
22427
-	ldr	r0, .L3777+28
22428
-	ldrh	r2, [r3, r6]
22429
-	bl	printk
22430
-	mov	r1, #0
22431
-	mov	r2, r5
22432
-	ldr	r0, [r4, #-3612]
22433
-	bl	FlashEraseBlocks
22434
-	ldr	r0, [r4, #-3612]
22435
-	mov	r1, #1
22436
-	mov	r2, r5
22437
-	bl	FlashEraseBlocks
22438
-.L3764:
22439
-	movw	r3, #1848
22440
-	mvn	r2, #0
22441
-	strh	r2, [r8, r3]	@ movhi
22442
-	add	sp, sp, #52
22443
-	@ sp needed
22444
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
22445
-.L3778:
22981
+	b	.L3689
22982
+.L3698:
22446
22983
 	.align	2
22447
-.L3777:
22984
+.L3697:
22448
22985
 	.word	.LANCHOR0
22449
-	.word	.LANCHOR4
22450
22986
 	.word	.LANCHOR2
22451
22987
 	.word	.LC164
22452
-	.word	.LANCHOR2-3524
22453
-	.word	.LANCHOR2-3476
22454
-	.word	.LANCHOR0+2320
22455
22988
 	.word	.LC165
22456
22989
 	.fnend
22457
22990
 	.size	ftl_fix_nand_power_lost_error, .-ftl_fix_nand_power_lost_error
22458
22991
 	.align	2
22459
22992
 	.global	rk_ftl_garbage_collect
22993
+	.syntax unified
22994
+	.arm
22995
+	.fpu softvfp
22460
22996
 	.type	rk_ftl_garbage_collect, %function
22461
22997
 rk_ftl_garbage_collect:
22462
22998
 	.fnstart
..
..
@@ -22468,907 +23004,910 @@
22468
23004
 	.size	rk_ftl_garbage_collect, .-rk_ftl_garbage_collect
22469
23005
 	.align	2
22470
23006
 	.global	ftl_write
23007
+	.syntax unified
23008
+	.arm
23009
+	.fpu softvfp
22471
23010
 	.type	ftl_write, %function
22472
23011
 ftl_write:
22473
23012
 	.fnstart
22474
-	@ args = 0, pretend = 0, frame = 96
23013
+	@ args = 0, pretend = 0, frame = 80
22475
23014
 	@ frame_needed = 0, uses_anonymous_args = 0
22476
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
23015
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
22477
23016
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
22478
-	.pad #100
22479
-	sub	sp, sp, #100
22480
-	ldr	r10, .L3854
22481
-	str	r3, [sp, #4]
22482
-	ldr	r3, [r10, #-3616]
23017
+	mov	fp, r3
23018
+	ldr	r4, .L3768
23019
+	.pad #84
23020
+	sub	sp, sp, #84
23021
+	ldr	r3, [r4, #-3612]
22483
23022
 	cmp	r3, #0
22484
-	bne	.L3821
22485
-	mov	r8, r2
22486
-	ldr	r2, .L3854+4
22487
-	ldr	r2, [r2, #504]
23023
+	bne	.L3741
23024
+	mov	r9, r2
23025
+	ldr	r2, .L3768+4
23026
+	ldr	r2, [r2, #500]
22488
23027
 	cmp	r2, #1
22489
23028
 	movne	r0, r3
22490
-	bne	.L3781
23029
+	bne	.L3700
22491
23030
 	cmp	r0, #16
22492
23031
 	mov	r7, r1
22493
-	bne	.L3782
22494
-	add	r0, r1, #256
22495
-	ldr	r2, [sp, #4]
22496
-	mov	r1, r8
23032
+	bne	.L3702
23033
+	mov	r2, fp
23034
+	mov	r1, r9
23035
+	add	r0, r7, #256
22497
23036
 	bl	FtlVendorPartWrite
22498
-	b	.L3781
22499
-.L3782:
22500
-	ldr	fp, .L3854+8
22501
-	ldr	r3, [fp, #2428]
22502
-	cmp	r8, r3
23037
+.L3700:
23038
+	add	sp, sp, #84
23039
+	@ sp needed
23040
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
23041
+.L3702:
23042
+	ldr	r10, .L3768+8
23043
+	ldr	r3, [r10, #2432]
23044
+	cmp	r9, r3
22503
23045
 	cmpls	r1, r3
22504
-	bcs	.L3824
22505
-	add	r5, r1, r8
22506
-	cmp	r5, r3
22507
-	bhi	.L3824
22508
-	ldr	r6, .L3854+12
23046
+	bcs	.L3744
23047
+	add	r6, r1, r9
23048
+	cmp	r3, r6
23049
+	bcc	.L3744
22509
23050
 	mov	r3, #2048
22510
-	mov	r0, r1
22511
-	str	r3, [r6, #2012]
22512
-	movw	r3, #2394
22513
-	ldrh	r4, [fp, r3]
22514
-	mov	r1, r4
23051
+	mov	r0, r7
23052
+	str	r3, [r4, #2012]
23053
+	movw	r3, #2396
23054
+	ldrh	r5, [r10, r3]
23055
+	mov	r1, r5
22515
23056
 	bl	__aeabi_uidiv
22516
-	mov	r1, r4
22517
-	str	r0, [sp, #8]
22518
-	sub	r0, r5, #1
23057
+	mov	r1, r5
23058
+	str	r0, [sp, #4]
23059
+	sub	r0, r6, #1
22519
23060
 	bl	__aeabi_uidiv
22520
-	cmp	r8, r4, asl #1
22521
-	ldr	r2, [sp, #8]
22522
-	str	r0, [sp, #28]
22523
-	rsb	r5, r2, r0
22524
-	add	r3, r5, #1
22525
-	str	r3, [sp]
22526
-	ldr	r2, [sp]
22527
-	ldr	r3, [r10, #-3356]
22528
-	add	r3, r2, r3
22529
-	ldr	r2, [fp, #2440]
22530
-	str	r3, [r10, #-3356]
22531
-	ldr	r3, [r10, #-3340]
22532
-	add	r3, r8, r3
22533
-	str	r3, [r10, #-3340]
23061
+	ldr	r2, [sp, #4]
23062
+	cmp	r9, r5, lsl #1
23063
+	ldr	r3, [r4, #-3356]
23064
+	ldr	r1, [r10, #2444]
23065
+	sub	r6, r0, r2
23066
+	str	r0, [sp, #24]
23067
+	add	r8, r6, #1
23068
+	add	r3, r3, r8
23069
+	str	r3, [r4, #-3356]
23070
+	ldr	r3, [r4, #-3340]
23071
+	add	r3, r3, r9
23072
+	str	r3, [r4, #-3340]
22534
23073
 	movcs	r3, #1
22535
23074
 	movcc	r3, #0
22536
-	cmp	r2, #0
22537
-	str	r3, [sp, #20]
22538
-	beq	.L3784
23075
+	cmp	r1, #0
23076
+	str	r3, [sp, #16]
23077
+	beq	.L3745
22539
23078
 	mov	r3, #36
22540
-	ldr	r9, [fp, #2444]
22541
-	mul	r3, r3, r2
22542
-	ldr	r2, [sp, #8]
23079
+	ldr	r2, [r10, #2448]
23080
+	mul	r3, r3, r1
22543
23081
 	sub	r3, r3, #36
22544
-	add	r9, r9, r3
22545
-	ldr	r3, [r9, #16]
22546
-	cmp	r2, r3
22547
-	bne	.L3785
22548
-	ldr	r3, [r10, #-3352]
22549
-	mov	r1, r4
22550
-	mov	r0, r7
22551
-	add	r3, r3, #1
22552
-	str	r3, [r10, #-3352]
22553
-	ldr	r3, [r6, #2016]
22554
-	add	r3, r3, #1
22555
-	str	r3, [r6, #2016]
22556
-	bl	__aeabi_uidivmod
22557
-	ldr	r0, [r9, #8]
22558
-	rsb	r4, r1, r4
22559
-	add	r0, r0, r1, asl #9
22560
-	cmp	r4, r8
22561
-	ldr	r1, [sp, #4]
22562
-	movcs	r4, r8
22563
-	mov	r10, r4, asl #9
22564
-	mov	r2, r10
22565
-	bl	ftl_memcpy
22566
-	cmp	r5, #0
22567
-	bne	.L3786
22568
-	ldr	r3, [r6, #2016]
22569
-	cmp	r3, #2
22570
-	ble	.L3821
22571
-.L3786:
23082
+	add	r10, r2, r3
22572
23083
 	ldr	r3, [sp, #4]
22573
-	rsb	r8, r4, r8
22574
-	add	r7, r7, r4
22575
-	str	r5, [sp]
22576
-	add	r3, r3, r10
22577
-	str	r3, [sp, #4]
22578
-	ldr	r3, [sp, #8]
23084
+	ldr	r2, [r10, #16]
23085
+	cmp	r3, r2
23086
+	strne	fp, [sp, #12]
23087
+	bne	.L3705
23088
+	ldr	r2, [r4, #-3352]
23089
+	mov	r1, r5
23090
+	mov	r0, r7
23091
+	add	r2, r2, #1
23092
+	str	r2, [r4, #-3352]
23093
+	ldr	r2, [r4, #2016]
23094
+	add	r2, r2, #1
23095
+	str	r2, [r4, #2016]
23096
+	bl	__aeabi_uidivmod
23097
+	sub	r5, r5, r1
23098
+	ldr	r3, [r10, #8]
23099
+	cmp	r9, r5
23100
+	mov	r0, r1
23101
+	movcc	r5, r9
23102
+	mov	r1, fp
23103
+	lsl	r8, r5, #9
23104
+	add	r0, r3, r0, lsl #9
23105
+	mov	r2, r8
23106
+	bl	ftl_memcpy
23107
+	cmp	r6, #0
23108
+	bne	.L3706
23109
+	ldr	r3, [r4, #2016]
23110
+	cmp	r3, #2
23111
+	bgt	.L3706
23112
+.L3741:
23113
+	mov	r0, #0
23114
+	b	.L3700
23115
+.L3706:
23116
+	add	r3, fp, r8
23117
+	sub	r9, r9, r5
23118
+	str	r3, [sp, #12]
23119
+	add	r7, r7, r5
23120
+	ldr	r3, [sp, #4]
23121
+	mov	r8, r6
22579
23122
 	add	r3, r3, #1
22580
-	str	r3, [sp, #8]
22581
-.L3785:
23123
+	str	r3, [sp, #4]
23124
+.L3705:
22582
23125
 	mov	r3, #0
22583
-	str	r3, [r6, #2016]
22584
-.L3784:
22585
-	ldr	r0, [sp, #8]
22586
-	ldr	r1, [sp, #28]
23126
+	str	r3, [r4, #2016]
23127
+.L3704:
23128
+	ldr	r1, [sp, #24]
23129
+	ldr	r0, [sp, #4]
22587
23130
 	bl	FtlCacheMetchLpa
22588
23131
 	cmp	r0, #0
22589
-	beq	.L3787
23132
+	beq	.L3707
22590
23133
 	bl	FtlCacheWriteBack
22591
-.L3787:
22592
-	ldr	r5, .L3854+16
22593
-	mov	r3, #0
22594
-	ldr	r4, .L3854+8
22595
-	str	r3, [sp, #12]
22596
-	str	r5, [r6, #1992]
22597
-	ldr	r6, [sp, #8]
22598
-	mov	r10, r4
22599
-	str	r3, [sp, #32]
22600
-.L3788:
22601
-	ldr	r3, [sp]
22602
-	cmp	r3, #0
22603
-	beq	.L3853
22604
-	ldrh	r2, [r5, #4]
22605
-	cmp	r2, #0
22606
-	bne	.L3789
22607
-	ldr	r3, .L3854+16
22608
-	ldr	r9, .L3854+4
22609
-	cmp	r5, r3
22610
-	bne	.L3790
22611
-	add	r0, r3, #48
22612
-	ldrh	r5, [r0, #4]
22613
-	cmp	r5, #0
22614
-	bne	.L3791
22615
-	bl	allocate_new_data_superblock
22616
-	str	r5, [r9, #3452]
22617
-.L3791:
22618
-	ldr	r0, .L3854+16
22619
-	bl	allocate_new_data_superblock
22620
-	ldr	r3, [r9, #3452]
22621
-	cmp	r3, #0
22622
-	ldrne	r5, .L3854+20
22623
-	bne	.L3792
22624
-.L3793:
22625
-	ldr	r5, .L3854+16
22626
-	b	.L3792
22627
-.L3790:
22628
-	ldrh	r3, [r3, #4]
22629
-	str	r2, [r9, #3452]
22630
-	cmp	r3, #0
22631
-	bne	.L3793
22632
-	mov	r0, r5
22633
-	bl	allocate_new_data_superblock
22634
-.L3792:
22635
-	ldrh	r3, [r5, #4]
22636
-	cmp	r3, #0
22637
-	bne	.L3794
22638
-	mov	r0, r5
22639
-	bl	allocate_new_data_superblock
22640
-.L3794:
22641
-	ldr	r3, .L3854+12
22642
-	str	r5, [r3, #1992]
22643
-.L3789:
22644
-	ldr	r2, .L3854
22645
-	ldr	r1, [r4, #2440]
22646
-	ldrh	r3, [r5, #4]
22647
-	ldr	r2, [r2, #-540]
22648
-	rsb	r2, r1, r2
22649
-	cmp	r3, r2
22650
-	movcs	r3, r2
22651
-	ldr	r2, [sp]
22652
-	cmp	r3, r2
22653
-	movcs	r3, r2
22654
-	str	r3, [sp, #44]
22655
-	mov	r3, #0
22656
-.L3851:
22657
-	str	r3, [sp, #16]
22658
-	ldr	r3, [sp, #16]
22659
-	ldr	r2, [sp, #44]
22660
-	cmp	r3, r2
22661
-	beq	.L3796
22662
-	ldrh	r3, [r5, #4]
22663
-	cmp	r3, #0
22664
-	beq	.L3796
22665
-	ldr	r3, [sp, #28]
22666
-	ldr	r2, [sp, #16]
22667
-	rsb	ip, r3, r6
22668
-	ldr	r3, [sp, #20]
22669
-	clz	ip, ip
22670
-	mov	ip, ip, lsr #5
22671
-	and	r3, ip, r3
22672
-	cmp	r2, #0
22673
-	moveq	r3, #0
22674
-	andne	r3, r3, #1
22675
-	cmp	r3, #0
22676
-	beq	.L3797
22677
-	ldr	r3, .L3854+24
22678
-	ldrh	r2, [r3]
22679
-	add	r3, r8, r7
22680
-	mls	r3, r2, r6, r3
22681
-	cmp	r3, r2
22682
-	bne	.L3796
22683
-.L3797:
22684
-	add	r1, sp, #56
22685
-	mov	r2, #0
22686
-	mov	r0, r6
22687
-	str	ip, [sp, #52]
22688
-	bl	log2phys
22689
-	mov	r0, r5
22690
-	bl	get_new_active_ppa
22691
-	ldr	r2, [r4, #2440]
22692
-	ldr	r1, [r4, #2444]
22693
-	mov	r3, #36
22694
-	ldr	fp, .L3854+28
22695
-	mla	r1, r3, r2, r1
22696
-	ldrh	r2, [fp]
22697
-	str	r6, [r1, #16]
22698
-	str	r3, [sp, #48]
22699
-	ldr	r3, [r4, #2440]
22700
-	str	r0, [r1, #4]
22701
-	ldr	r0, .L3854
22702
-	mul	lr, r3, r2
22703
-	bic	r3, lr, #3
22704
-	str	r3, [sp, #36]
22705
-	ldr	r3, [r0, #-492]
22706
-	ldr	ip, [sp, #36]
22707
-	ldrh	lr, [fp, #-2]
22708
-	add	r9, r3, ip
22709
-	str	r3, [sp, #40]
22710
-	ldr	r3, [r4, #2440]
22711
-	ldr	r0, [r0, #-512]
22712
-	str	r9, [r1, #12]
22713
-	mul	lr, r3, lr
22714
-	bic	lr, lr, #3
22715
-	add	lr, r0, lr
22716
-	mov	r0, r9
22717
-	str	lr, [r1, #8]
22718
-	mov	r1, #0
22719
-	bl	ftl_memset
22720
-	ldr	r3, [sp, #8]
22721
-	ldr	ip, [sp, #52]
22722
-	rsb	r3, r3, r6
22723
-	clz	r3, r3
22724
-	mov	r3, r3, lsr #5
22725
-	str	r3, [sp, #24]
22726
-	orrs	r3, r3, ip
22727
-	ldr	r3, [sp, #48]
22728
-	beq	.L3798
23134
+.L3707:
23135
+	ldr	r6, [sp, #4]
23136
+	ldr	r10, .L3768+8
23137
+	ldr	r5, .L3768+12
23138
+	str	r5, [r4, #1992]
23139
+.L3708:
23140
+	cmp	r8, #0
23141
+	bne	.L3736
22729
23142
 	ldr	r3, [sp, #24]
22730
-	cmp	r3, #0
22731
-	beq	.L3799
22732
-	ldrh	fp, [fp, #-6]
22733
-	mov	r0, r7
22734
-	mov	r1, fp
22735
-	bl	__aeabi_uidivmod
22736
-	rsb	fp, r1, fp
22737
-	mov	r3, r1
22738
-	cmp	fp, r8
22739
-	str	r1, [sp, #32]
22740
-	movcc	r3, fp
22741
-	movcs	r3, r8
22742
-	str	r3, [sp, #12]
22743
-	b	.L3800
22744
-.L3799:
22745
-	cmp	ip, #0
22746
-	beq	.L3800
22747
-	ldr	r2, .L3854+24
22748
-	add	r3, r8, r7
22749
-	ldrh	r2, [r2]
22750
-	smulbb	r2, r2, r6
22751
-	rsb	r3, r2, r3
22752
-	uxth	r3, r3
22753
-	str	r3, [sp, #12]
22754
-	ldr	r3, [sp, #24]
22755
-	str	r3, [sp, #32]
22756
-.L3800:
22757
-	ldr	r3, .L3854+24
22758
-	ldr	r2, [sp, #12]
22759
-	ldrh	r3, [r3]
22760
-	cmp	r2, r3
22761
-	bne	.L3801
22762
-	ldr	r3, [sp, #24]
22763
-	ldr	r0, [r10, #2444]
22764
-	cmp	r3, #0
22765
-	moveq	r3, r2
22766
-	ldr	r2, [r10, #2440]
22767
-	muleq	r1, r6, r3
22768
-	ldreq	r3, [sp, #4]
22769
-	ldrne	r1, [sp, #4]
22770
-	rsbeq	r1, r7, r1
22771
-	addeq	r1, r3, r1, asl #9
22772
-	ldr	r3, [sp, #20]
22773
-	cmp	r3, #0
22774
-	mov	r3, #36
22775
-	mla	r3, r3, r2, r0
22776
-	strne	r1, [r3, #8]
22777
-	bne	.L3804
22778
-	ldr	r0, [r3, #8]
22779
-	ldr	r3, .L3854+32
22780
-	ldrh	r2, [r3]
22781
-	b	.L3849
22782
-.L3801:
22783
-	ldr	r2, [sp, #56]
22784
-	mov	r3, #36
22785
-	cmn	r2, #1
22786
-	beq	.L3805
22787
-	ldr	r1, [r4, #2444]
22788
-	add	r0, sp, #60
22789
-	str	r2, [sp, #64]
22790
-	ldr	r2, [r4, #2440]
22791
-	str	r6, [sp, #76]
22792
-	mla	r3, r3, r2, r1
22793
-	mov	r1, #1
22794
-	ldr	r2, [r3, #8]
22795
-	ldr	r3, [r3, #12]
22796
-	str	r2, [sp, #68]
22797
-	mov	r2, #0
22798
-	str	r3, [sp, #72]
22799
-	bl	FlashReadPages
22800
-	ldr	r3, [sp, #60]
22801
-	cmn	r3, #1
22802
-	ldr	r3, .L3854
22803
-	ldreq	r2, [r3, #-3160]
22804
-	addeq	r2, r2, #1
22805
-	streq	r2, [r3, #-3160]
22806
-	beq	.L3808
22807
-	ldr	r2, [r9, #8]
22808
-	cmp	r2, r6
22809
-	beq	.L3808
22810
-	ldr	r2, [r3, #-3160]
22811
-	ldr	r0, .L3854+36
22812
-	add	r2, r2, #1
22813
-	str	r2, [r3, #-3160]
22814
-	mov	r2, r6
22815
-	ldr	r1, [r9, #8]
22816
-	bl	printk
22817
-	b	.L3808
22818
-.L3805:
22819
-	ldr	r2, [r4, #2440]
22820
-	ldr	r1, [r4, #2444]
22821
-	mla	r3, r3, r2, r1
22822
-	mov	r1, #0
22823
-	ldr	r0, [r3, #8]
22824
-	ldr	r3, .L3854+32
22825
-	ldrh	r2, [r3]
22826
-	bl	ftl_memset
22827
-.L3808:
22828
-	ldr	r3, [sp, #24]
22829
-	cmp	r3, #0
22830
-	mov	r3, #36
22831
-	beq	.L3809
22832
-	ldr	r1, [r4, #2444]
22833
-	ldr	r2, [r4, #2440]
22834
-	mla	r3, r3, r2, r1
22835
-	ldr	r1, [sp, #4]
22836
-	ldr	r0, [r3, #8]
22837
-	ldr	r3, [sp, #32]
22838
-	add	r0, r0, r3, asl #9
22839
-	b	.L3852
22840
-.L3809:
22841
-	ldr	r1, [r4, #2440]
22842
-	ldr	r2, [r4, #2444]
22843
-	mla	r3, r3, r1, r2
22844
-	ldr	r2, .L3854+24
22845
-	ldrh	r1, [r2]
22846
-	ldr	r0, [r3, #8]
22847
-	mul	r1, r1, r6
22848
-	ldr	r3, [sp, #4]
22849
-	rsb	r1, r7, r1
22850
-	add	r1, r3, r1, asl #9
22851
-.L3852:
22852
-	ldr	r3, [sp, #12]
22853
-	mov	r2, r3, asl #9
22854
-	b	.L3849
22855
-.L3798:
22856
-	ldr	r2, [sp, #20]
22857
-	cmp	r2, #0
22858
-	ldr	r2, [r4, #2440]
22859
-	beq	.L3810
22860
-	ldr	r1, [r4, #2444]
22861
-	mla	r3, r3, r2, r1
22862
-	ldr	r2, .L3854+24
22863
-	ldrh	fp, [r2]
23143
+	mov	r0, r8
22864
23144
 	ldr	r2, [sp, #4]
22865
-	mul	fp, fp, r6
22866
-	rsb	fp, r7, fp
22867
-	add	fp, r2, fp, asl #9
22868
-	str	fp, [r3, #8]
22869
-	b	.L3804
22870
-.L3810:
22871
-	ldr	r0, [r4, #2444]
22872
-	mla	r3, r3, r2, r0
22873
-	ldr	r2, .L3854+24
22874
-	ldrh	r1, [r2]
22875
-	ldrh	r2, [fp, #-2]
22876
-	ldr	r0, [r3, #8]
22877
-	mul	r1, r1, r6
22878
-	ldr	r3, [sp, #4]
22879
-	rsb	r1, r7, r1
22880
-	add	r1, r3, r1, asl #9
22881
-.L3849:
22882
-	bl	ftl_memcpy
22883
-.L3804:
22884
-	ldr	r3, .L3854+40
22885
-	ldr	r2, [sp, #40]
22886
-	ldr	r1, [sp, #36]
22887
-	strh	r3, [r2, r1]	@ movhi
22888
-	ldr	r2, .L3854
22889
-	str	r6, [r9, #8]
22890
-	add	r6, r6, #1
22891
-	ldr	r3, [r2, #-3328]
22892
-	str	r3, [r9, #4]
22893
-	add	r3, r3, #1
22894
-	cmn	r3, #1
22895
-	moveq	r3, #0
22896
-	str	r3, [r2, #-3328]
22897
-	ldr	r3, [sp, #56]
22898
-	str	r3, [r9, #12]
22899
-	ldrh	r3, [r5]
22900
-	strh	r3, [r9, #2]	@ movhi
22901
-	ldr	r3, [r4, #2440]
22902
-	add	r3, r3, #1
22903
-	str	r3, [r4, #2440]
22904
-	ldr	r3, [sp, #16]
22905
-	add	r3, r3, #1
22906
-	b	.L3851
22907
-.L3796:
22908
-	ldr	r3, [sp]
22909
-	ldr	r2, [sp, #16]
22910
-	ldr	r1, [sp, #20]
22911
-	rsb	r3, r2, r3
22912
-	ldr	r2, .L3854
22913
-	str	r3, [sp]
22914
-	ldr	r3, [r4, #2440]
22915
-	ldr	r2, [r2, #-540]
22916
-	cmp	r3, r2
22917
-	orrcs	r1, r1, #1
22918
-	cmp	r1, #0
22919
-	bne	.L3814
22920
-	ldrh	r3, [r5, #4]
22921
-	cmp	r3, #0
22922
-	beq	.L3814
22923
-.L3816:
22924
-	mov	r3, #0
22925
-	str	r3, [sp, #20]
22926
-	b	.L3788
22927
-.L3814:
22928
-	bl	FtlCacheWriteBack
22929
-	mov	r3, #0
22930
-	str	r3, [r10, #2440]
22931
-	ldr	r3, [sp]
22932
-	cmp	r3, #1
22933
-	bhi	.L3788
22934
-	b	.L3816
22935
-.L3853:
22936
-	mov	r0, r3
22937
-	ldr	r2, [sp, #8]
22938
-	ldr	r3, [sp, #28]
22939
-	rsb	r1, r2, r3
23145
+	sub	r1, r3, r2
22940
23146
 	bl	ftl_do_gc
22941
-	ldr	r3, .L3854+44
22942
-	ldrh	r3, [r3, #-8]
23147
+	ldr	r2, .L3768+12
23148
+	ldrh	r3, [r2, #-4]
23149
+	mov	r4, r2
22943
23150
 	cmp	r3, #5
22944
-	bls	.L3827
23151
+	bls	.L3737
22945
23152
 	cmp	r3, #31
22946
-	bhi	.L3821
22947
-	ldr	r3, .L3854+8
22948
-	ldrb	r3, [r3]	@ zero_extendqisi2
23153
+	bhi	.L3741
23154
+	ldr	r3, .L3768+8
23155
+	ldrb	r3, [r3, #36]	@ zero_extendqisi2
22949
23156
 	cmp	r3, #0
22950
-	bne	.L3821
22951
-.L3827:
22952
-	ldr	r4, [sp]
22953
-	ldr	r5, .L3854+48
22954
-	ldr	r6, .L3854
22955
-	ldr	r7, .L3854+52
22956
-.L3840:
22957
-	ldrh	r2, [r5]
23157
+	bne	.L3741
23158
+.L3737:
23159
+	ldr	r5, .L3768+16
23160
+.L3740:
23161
+	ldr	r3, .L3768+20
23162
+	ldrh	r2, [r3]
22958
23163
 	movw	r3, #65535
22959
23164
 	cmp	r2, r3
22960
-	bne	.L3820
22961
-	ldrh	r3, [r7]
23165
+	bne	.L3739
23166
+	ldr	r3, .L3768+24
23167
+	ldrh	r3, [r3]
22962
23168
 	cmp	r3, r2
22963
-	bne	.L3820
22964
-	ldr	r2, .L3854+56
22965
-	ldrh	r2, [r2]
23169
+	bne	.L3739
23170
+	ldrh	r2, [r5, #-8]
22966
23171
 	cmp	r2, r3
22967
-	bne	.L3820
22968
-	and	r0, r4, #7
23172
+	bne	.L3739
23173
+	and	r0, r8, #7
22969
23174
 	bl	List_get_gc_head_node
22970
23175
 	uxth	r0, r0
22971
23176
 	bl	FtlGcRefreshBlock
22972
-.L3820:
22973
-	ldr	r3, .L3854+60
22974
-	mov	r0, #1
22975
-	mov	r1, r0
23177
+.L3739:
23178
+	ldr	r3, .L3768+28
23179
+	mov	r1, #1
22976
23180
 	mov	r2, #128
23181
+	mov	r0, r1
22977
23182
 	strh	r2, [r3]	@ movhi
22978
23183
 	strh	r2, [r3, #-2]	@ movhi
22979
23184
 	bl	ftl_do_gc
22980
-	mov	r0, #0
22981
23185
 	mov	r1, #1
22982
-	bl	ftl_do_gc
22983
-	ldr	r3, [r6, #-3616]
22984
-	cmp	r3, #0
22985
-	bne	.L3821
22986
-	ldr	r3, .L3854+64
22987
-	ldrh	r3, [r3]
22988
-	cmp	r3, #2
22989
-	bhi	.L3821
22990
-	add	r4, r4, #1
22991
-	cmp	r4, #256
22992
-	bne	.L3840
22993
-	b	.L3821
22994
-.L3824:
22995
-	mvn	r0, #0
22996
-	b	.L3781
22997
-.L3821:
22998
23186
 	mov	r0, #0
22999
-.L3781:
23000
-	add	sp, sp, #100
23001
-	@ sp needed
23002
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
23003
-.L3855:
23187
+	bl	ftl_do_gc
23188
+	ldr	r3, .L3768
23189
+	ldr	r3, [r3, #-3612]
23190
+	cmp	r3, #0
23191
+	bne	.L3741
23192
+	ldrh	r3, [r4, #-4]
23193
+	cmp	r3, #2
23194
+	bhi	.L3741
23195
+	add	r8, r8, #1
23196
+	cmp	r8, #256
23197
+	bne	.L3740
23198
+	b	.L3741
23199
+.L3745:
23200
+	str	fp, [sp, #12]
23201
+	b	.L3704
23202
+.L3736:
23203
+	ldrh	r1, [r5, #4]
23204
+	ldr	r4, .L3768
23205
+	cmp	r1, #0
23206
+	bne	.L3709
23207
+	sub	r2, r4, #3520
23208
+	ldr	fp, .L3768+4
23209
+	cmp	r5, r2
23210
+	bne	.L3710
23211
+	sub	r0, r4, #3472
23212
+	ldrh	r5, [r0, #4]
23213
+	cmp	r5, #0
23214
+	bne	.L3711
23215
+	bl	allocate_new_data_superblock
23216
+	str	r5, [fp, #3448]
23217
+.L3711:
23218
+	ldr	r0, .L3768+12
23219
+	bl	allocate_new_data_superblock
23220
+	ldr	r5, .L3768+12
23221
+	ldr	r1, [fp, #3448]
23222
+	add	r2, r5, #48
23223
+	cmp	r1, #0
23224
+	movne	r5, r2
23225
+.L3712:
23226
+	ldrh	r2, [r5, #4]
23227
+	cmp	r2, #0
23228
+	bne	.L3713
23229
+	mov	r0, r5
23230
+	bl	allocate_new_data_superblock
23231
+.L3713:
23232
+	str	r5, [r4, #1992]
23233
+.L3709:
23234
+	ldr	r1, [r10, #2444]
23235
+	ldr	r2, [r4, #-540]
23236
+	sub	r2, r2, r1
23237
+	ldrh	r1, [r5, #4]
23238
+	cmp	r2, r8
23239
+	movcs	r2, r8
23240
+	cmp	r1, r2
23241
+	movcc	r3, r1
23242
+	movcs	r3, r2
23243
+	str	r3, [sp, #36]
23244
+	mov	r3, #0
23245
+.L3766:
23246
+	str	r3, [sp, #20]
23247
+	ldr	r3, [sp, #20]
23248
+	ldr	r2, [sp, #36]
23249
+	cmp	r3, r2
23250
+	bne	.L3732
23251
+.L3715:
23252
+	ldr	r3, [sp, #20]
23253
+	ldr	r1, .L3768
23254
+	ldr	r2, [r10, #2444]
23255
+	sub	r8, r8, r3
23256
+	ldr	r3, [sp, #16]
23257
+	ldr	r1, [r1, #-540]
23258
+	cmp	r2, r1
23259
+	orrcs	r3, r3, #1
23260
+	cmp	r3, #0
23261
+	bne	.L3733
23262
+	ldrh	r2, [r5, #4]
23263
+	cmp	r2, #0
23264
+	beq	.L3733
23265
+.L3735:
23266
+	mov	r3, #0
23267
+	str	r3, [sp, #16]
23268
+	b	.L3708
23269
+.L3710:
23270
+	str	r1, [fp, #3448]
23271
+	ldrh	r1, [r2, #4]
23272
+	cmp	r1, #0
23273
+	movne	r5, r2
23274
+	bne	.L3713
23275
+	mov	r0, r5
23276
+	bl	allocate_new_data_superblock
23277
+	b	.L3712
23278
+.L3732:
23279
+	ldrh	r2, [r5, #4]
23280
+	cmp	r2, #0
23281
+	beq	.L3715
23282
+	ldr	r3, [sp, #24]
23283
+	sub	r4, r3, r6
23284
+	ldr	r3, [sp, #16]
23285
+	clz	r4, r4
23286
+	lsr	r4, r4, #5
23287
+	and	r2, r4, r3
23288
+	ldr	r3, [sp, #20]
23289
+	cmp	r3, #0
23290
+	moveq	r2, #0
23291
+	andne	r2, r2, #1
23292
+	cmp	r2, #0
23293
+	beq	.L3716
23294
+	ldr	r3, .L3768+32
23295
+	add	r2, r7, r9
23296
+	ldrh	r1, [r3]
23297
+	mls	r2, r1, r6, r2
23298
+	cmp	r1, r2
23299
+	bne	.L3715
23300
+.L3716:
23301
+	mov	r2, #0
23302
+	add	r1, sp, #40
23303
+	mov	r0, r6
23304
+	mov	fp, #36
23305
+	bl	log2phys
23306
+	mov	r0, r5
23307
+	bl	get_new_active_ppa
23308
+	ldr	r2, .L3768+36
23309
+	ldr	r1, [r10, #2444]
23310
+	ldr	ip, [r10, #2448]
23311
+	ldrh	r2, [r2]
23312
+	mla	ip, fp, r1, ip
23313
+	mul	lr, r2, r1
23314
+	str	r0, [ip, #4]
23315
+	ldr	r0, .L3768
23316
+	bic	r3, lr, #3
23317
+	str	r6, [ip, #16]
23318
+	str	r3, [sp, #28]
23319
+	ldr	lr, [sp, #28]
23320
+	ldr	r3, [r0, #-492]
23321
+	ldr	r0, [r0, #-512]
23322
+	str	r3, [sp, #32]
23323
+	add	r3, r3, lr
23324
+	str	r3, [sp, #8]
23325
+	str	r3, [ip, #12]
23326
+	ldr	r3, .L3768+40
23327
+	ldrh	lr, [r3]
23328
+	mul	r1, r1, lr
23329
+	bic	r1, r1, #3
23330
+	add	r1, r0, r1
23331
+	ldr	r0, [sp, #8]
23332
+	str	r1, [ip, #8]
23333
+	mov	r1, #0
23334
+	bl	ftl_memset
23335
+	ldr	r3, [sp, #4]
23336
+	cmp	r3, r6
23337
+	orreq	r4, r4, #1
23338
+	cmp	r4, #0
23339
+	beq	.L3717
23340
+	cmp	r3, r6
23341
+	bne	.L3718
23342
+	ldr	r3, .L3768+32
23343
+	mov	r0, r7
23344
+	ldrh	r4, [r3]
23345
+	mov	r1, r4
23346
+	bl	__aeabi_uidivmod
23347
+	sub	r4, r4, r1
23348
+	mov	fp, r1
23349
+	cmp	r4, r9
23350
+	movcs	r4, r9
23351
+.L3719:
23352
+	ldr	r3, .L3768+32
23353
+	ldrh	r2, [r3]
23354
+	cmp	r2, r4
23355
+	bne	.L3720
23356
+	ldr	r3, [sp, #4]
23357
+	cmp	r3, r6
23358
+	mulne	r1, r4, r6
23359
+	ldrne	r3, [sp, #12]
23360
+	ldreq	r1, [sp, #12]
23361
+	subne	r1, r1, r7
23362
+	addne	r1, r3, r1, lsl #9
23363
+	ldr	r3, [sp, #16]
23364
+	cmp	r3, #0
23365
+	beq	.L3722
23366
+	ldr	r2, [r10, #2444]
23367
+	mov	ip, #36
23368
+	ldr	r0, [r10, #2448]
23369
+	mla	r2, ip, r2, r0
23370
+	str	r1, [r2, #8]
23371
+.L3723:
23372
+	ldr	r2, .L3768+44
23373
+	ldr	r3, [sp, #32]
23374
+	ldr	r1, [sp, #28]
23375
+	strh	r2, [r3, r1]	@ movhi
23376
+	ldr	r1, .L3768
23377
+	ldr	r3, [sp, #8]
23378
+	ldr	r2, [r1, #-3328]
23379
+	str	r2, [r3, #4]
23380
+	add	r2, r2, #1
23381
+	cmn	r2, #1
23382
+	ldr	r3, [sp, #8]
23383
+	moveq	r2, #0
23384
+	str	r2, [r1, #-3328]
23385
+	ldr	r2, [sp, #40]
23386
+	str	r6, [r3, #8]
23387
+	add	r6, r6, #1
23388
+	str	r2, [r3, #12]
23389
+	ldrh	r2, [r5]
23390
+	strh	r2, [r3, #2]	@ movhi
23391
+	ldr	r2, [r10, #2444]
23392
+	ldr	r3, [sp, #20]
23393
+	add	r2, r2, #1
23394
+	str	r2, [r10, #2444]
23395
+	add	r3, r3, #1
23396
+	b	.L3766
23397
+.L3718:
23398
+	ldr	r3, .L3768+32
23399
+	add	r4, r7, r9
23400
+	mov	fp, #0
23401
+	ldrh	r2, [r3]
23402
+	smulbb	r2, r2, r6
23403
+	sub	r4, r4, r2
23404
+	uxth	r4, r4
23405
+	b	.L3719
23406
+.L3722:
23407
+	ldr	r2, [r10, #2448]
23408
+	mov	ip, #36
23409
+	ldr	r0, [r10, #2444]
23410
+	mla	r0, ip, r0, r2
23411
+	ldr	r2, .L3768+40
23412
+	ldrh	r2, [r2]
23413
+.L3767:
23414
+	ldr	r0, [r0, #8]
23415
+	b	.L3764
23416
+.L3720:
23417
+	ldr	r2, [sp, #40]
23418
+	cmn	r2, #1
23419
+	beq	.L3724
23420
+	ldr	r1, [r10, #2448]
23421
+	mov	r0, #36
23422
+	str	r2, [sp, #48]
23423
+	ldr	r2, [r10, #2444]
23424
+	str	r6, [sp, #60]
23425
+	mla	r2, r0, r2, r1
23426
+	add	r0, sp, #44
23427
+	ldr	r1, [r2, #8]
23428
+	ldr	r2, [r2, #12]
23429
+	str	r1, [sp, #52]
23430
+	mov	r1, #1
23431
+	str	r2, [sp, #56]
23432
+	mov	r2, #0
23433
+	bl	FlashReadPages
23434
+	ldr	r2, [sp, #44]
23435
+	cmn	r2, #1
23436
+	ldr	r2, .L3768
23437
+	ldreq	r1, [r2, #-3164]
23438
+	addeq	r1, r1, #1
23439
+	streq	r1, [r2, #-3164]
23440
+	beq	.L3727
23441
+	ldr	r3, [sp, #8]
23442
+	ldr	r1, [r3, #8]
23443
+	cmp	r6, r1
23444
+	beq	.L3727
23445
+	ldr	r1, [r2, #-3164]
23446
+	ldr	r0, .L3768+48
23447
+	add	r1, r1, #1
23448
+	str	r1, [r2, #-3164]
23449
+	mov	r2, r6
23450
+	ldr	r1, [r3, #8]
23451
+	bl	printk
23452
+.L3727:
23453
+	ldr	r3, [sp, #4]
23454
+	lsl	r2, r4, #9
23455
+	cmp	r3, r6
23456
+	bne	.L3728
23457
+	ldr	r0, [r10, #2448]
23458
+	mov	ip, #36
23459
+	ldr	r1, [r10, #2444]
23460
+	mla	r1, ip, r1, r0
23461
+	ldr	r0, [r1, #8]
23462
+	ldr	r1, [sp, #12]
23463
+	add	r0, r0, fp, lsl #9
23464
+.L3764:
23465
+	bl	ftl_memcpy
23466
+	b	.L3723
23467
+.L3724:
23468
+	ldr	r2, [r10, #2448]
23469
+	mov	r1, #36
23470
+	ldr	r0, [r10, #2444]
23471
+	mla	r0, r1, r0, r2
23472
+	ldr	r2, .L3768+40
23473
+	mov	r1, #0
23474
+	ldrh	r2, [r2]
23475
+	ldr	r0, [r0, #8]
23476
+	bl	ftl_memset
23477
+	b	.L3727
23478
+.L3728:
23479
+	ldr	r3, .L3768+32
23480
+	mov	lr, #36
23481
+	ldr	r0, [r10, #2444]
23482
+	ldr	ip, [r10, #2448]
23483
+	ldrh	r1, [r3]
23484
+	ldr	r3, [sp, #12]
23485
+	mla	r0, lr, r0, ip
23486
+	mul	r1, r6, r1
23487
+	sub	r1, r1, r7
23488
+	add	r1, r3, r1, lsl #9
23489
+	b	.L3767
23490
+.L3717:
23491
+	ldr	r3, [sp, #16]
23492
+	cmp	r3, #0
23493
+	beq	.L3729
23494
+	ldr	r2, [r10, #2444]
23495
+	ldr	r1, [r10, #2448]
23496
+	ldr	r3, .L3768+32
23497
+	mla	fp, fp, r2, r1
23498
+	ldrh	r2, [r3]
23499
+	ldr	r3, [sp, #12]
23500
+	mul	r2, r6, r2
23501
+	sub	r2, r2, r7
23502
+	add	r2, r3, r2, lsl #9
23503
+	str	r2, [fp, #8]
23504
+	b	.L3723
23505
+.L3729:
23506
+	ldr	r3, .L3768+32
23507
+	ldr	r2, [r10, #2444]
23508
+	ldr	r0, [r10, #2448]
23509
+	ldrh	r1, [r3]
23510
+	mla	fp, fp, r2, r0
23511
+	ldrh	r2, [r3, #4]
23512
+	ldr	r3, [sp, #12]
23513
+	mul	r1, r6, r1
23514
+	ldr	r0, [fp, #8]
23515
+	sub	r1, r1, r7
23516
+	add	r1, r3, r1, lsl #9
23517
+	b	.L3764
23518
+.L3733:
23519
+	bl	FtlCacheWriteBack
23520
+	cmp	r8, #1
23521
+	mov	r2, #0
23522
+	str	r2, [r10, #2444]
23523
+	bhi	.L3708
23524
+	b	.L3735
23525
+.L3744:
23526
+	mvn	r0, #0
23527
+	b	.L3700
23528
+.L3769:
23004
23529
 	.align	2
23005
-.L3854:
23530
+.L3768:
23006
23531
 	.word	.LANCHOR2
23007
23532
 	.word	.LANCHOR1
23008
23533
 	.word	.LANCHOR0
23009
-	.word	.LANCHOR4
23010
-	.word	.LANCHOR2-3524
23011
-	.word	.LANCHOR2-3476
23012
-	.word	.LANCHOR0+2394
23013
-	.word	.LANCHOR0+2400
23014
-	.word	.LANCHOR0+2398
23015
-	.word	.LC166
23016
-	.word	-3947
23017
23534
 	.word	.LANCHOR2-3520
23535
+	.word	.LANCHOR2-2656
23018
23536
 	.word	.LANCHOR2-3284
23019
23537
 	.word	.LANCHOR2-2666
23020
-	.word	.LANCHOR2-2664
23021
23538
 	.word	.LANCHOR2-2718
23022
-	.word	.LANCHOR2-3528
23539
+	.word	.LANCHOR0+2396
23540
+	.word	.LANCHOR0+2402
23541
+	.word	.LANCHOR0+2400
23542
+	.word	-3947
23543
+	.word	.LC166
23023
23544
 	.fnend
23024
23545
 	.size	ftl_write, .-ftl_write
23025
23546
 	.align	2
23026
23547
 	.global	ftl_vendor_write
23548
+	.syntax unified
23549
+	.arm
23550
+	.fpu softvfp
23027
23551
 	.type	ftl_vendor_write, %function
23028
23552
 ftl_vendor_write:
23029
23553
 	.fnstart
23030
23554
 	@ args = 0, pretend = 0, frame = 0
23031
23555
 	@ frame_needed = 0, uses_anonymous_args = 0
23032
-	str	lr, [sp, #-4]!
23033
-	.save {lr}
23034
-	mov	ip, r1
23035
-	mov	lr, r0
23556
+	@ link register save eliminated.
23036
23557
 	mov	r3, r2
23037
-	mov	r1, lr
23558
+	mov	r2, r1
23559
+	mov	r1, r0
23038
23560
 	mov	r0, #16
23039
-	mov	r2, ip
23040
-	ldr	lr, [sp], #4
23041
23561
 	b	ftl_write
23042
23562
 	.fnend
23043
23563
 	.size	ftl_vendor_write, .-ftl_vendor_write
23044
23564
 	.align	2
23045
23565
 	.global	FlashBootVendorWrite
23566
+	.syntax unified
23567
+	.arm
23568
+	.fpu softvfp
23046
23569
 	.type	FlashBootVendorWrite, %function
23047
23570
 FlashBootVendorWrite:
23048
23571
 	.fnstart
23049
23572
 	@ args = 0, pretend = 0, frame = 0
23050
23573
 	@ frame_needed = 0, uses_anonymous_args = 0
23051
-	stmfd	sp!, {r4, r5, r6, lr}
23574
+	push	{r4, r5, r6, lr}
23052
23575
 	.save {r4, r5, r6, lr}
23053
-	mov	r4, r2
23054
-	mov	r6, r0
23576
+	mov	r4, r0
23055
23577
 	mov	r5, r1
23578
+	mov	r6, r2
23056
23579
 	bl	rknand_device_lock
23057
-	ldr	r3, .L3862
23058
-	ldr	r3, [r3, #504]
23580
+	ldr	r3, .L3775
23581
+	ldr	r3, [r3, #500]
23059
23582
 	cmp	r3, #1
23060
23583
 	mvnne	r4, #0
23061
-	bne	.L3859
23062
-	mov	r2, r4
23063
-	mov	r0, r6
23584
+	bne	.L3772
23585
+	mov	r0, r4
23586
+	mov	r2, r6
23064
23587
 	mov	r1, r5
23065
23588
 	bl	ftl_vendor_write
23066
23589
 	mov	r4, r0
23067
-.L3859:
23590
+.L3772:
23068
23591
 	bl	rknand_device_unlock
23069
23592
 	mov	r0, r4
23070
-	ldmfd	sp!, {r4, r5, r6, pc}
23071
-.L3863:
23593
+	pop	{r4, r5, r6, pc}
23594
+.L3776:
23072
23595
 	.align	2
23073
-.L3862:
23596
+.L3775:
23074
23597
 	.word	.LANCHOR1
23075
23598
 	.fnend
23076
23599
 	.size	FlashBootVendorWrite, .-FlashBootVendorWrite
23077
23600
 	.align	2
23078
23601
 	.global	ftl_sys_write
23602
+	.syntax unified
23603
+	.arm
23604
+	.fpu softvfp
23079
23605
 	.type	ftl_sys_write, %function
23080
23606
 ftl_sys_write:
23081
23607
 	.fnstart
23082
23608
 	@ args = 0, pretend = 0, frame = 0
23083
23609
 	@ frame_needed = 0, uses_anonymous_args = 0
23084
23610
 	@ link register save eliminated.
23085
-	mov	ip, r1
23086
23611
 	mov	r3, r2
23612
+	mov	r2, r1
23087
23613
 	add	r1, r0, #256
23088
-	mov	r2, ip
23089
23614
 	mov	r0, #16
23090
23615
 	b	ftl_write
23091
23616
 	.fnend
23092
23617
 	.size	ftl_sys_write, .-ftl_sys_write
23093
23618
 	.align	2
23094
23619
 	.global	StorageSysDataStore
23620
+	.syntax unified
23621
+	.arm
23622
+	.fpu softvfp
23095
23623
 	.type	StorageSysDataStore, %function
23096
23624
 StorageSysDataStore:
23097
23625
 	.fnstart
23098
23626
 	@ args = 0, pretend = 0, frame = 0
23099
23627
 	@ frame_needed = 0, uses_anonymous_args = 0
23100
-	stmfd	sp!, {r3, r4, r5, lr}
23101
-	.save {r3, r4, r5, lr}
23102
-	mov	r4, r1
23103
-	mov	r5, r0
23628
+	push	{r4, r5, r6, lr}
23629
+	.save {r4, r5, r6, lr}
23630
+	mov	r5, r1
23631
+	mov	r4, r0
23104
23632
 	bl	rknand_device_lock
23105
-	mov	r2, r4
23633
+	mov	r2, r5
23106
23634
 	mov	r1, #1
23107
-	mov	r0, r5
23635
+	mov	r0, r4
23108
23636
 	bl	ftl_sys_write
23109
23637
 	mov	r4, r0
23110
23638
 	bl	rknand_device_unlock
23111
23639
 	mov	r0, r4
23112
-	ldmfd	sp!, {r3, r4, r5, pc}
23640
+	pop	{r4, r5, r6, pc}
23113
23641
 	.fnend
23114
23642
 	.size	StorageSysDataStore, .-StorageSysDataStore
23115
23643
 	.align	2
23116
23644
 	.global	FtlDumpSysBlock
23645
+	.syntax unified
23646
+	.arm
23647
+	.fpu softvfp
23117
23648
 	.type	FtlDumpSysBlock, %function
23118
23649
 FtlDumpSysBlock:
23119
23650
 	.fnstart
23120
23651
 	@ args = 0, pretend = 0, frame = 0
23121
23652
 	@ frame_needed = 0, uses_anonymous_args = 0
23122
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, lr}
23123
-	.save {r4, r5, r6, r7, r8, r9, lr}
23124
-	mov	r8, r0, asl #10
23125
-	ldr	r4, .L3876
23126
-	.pad #28
23127
-	sub	sp, sp, #28
23128
-	ldr	r7, .L3876+4
23653
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
23654
+	.save {r4, r5, r6, r7, r8, r9, r10, lr}
23655
+	lsl	r8, r0, #10
23656
+	ldr	r4, .L3788
23657
+	.pad #24
23658
+	sub	sp, sp, #24
23129
23659
 	mov	r6, r0
23130
23660
 	mov	r5, #0
23661
+	ldr	r7, .L3788+4
23131
23662
 	ldr	r3, [r4, #-524]
23132
-	mov	r9, r4
23133
-	str	r3, [r4, #1760]
23663
+	add	r9, r4, #1760
23664
+	ldr	r10, .L3788+8
23665
+	str	r3, [r4, #1768]
23134
23666
 	ldr	r3, [r4, #-500]
23135
-	str	r3, [r4, #1764]
23136
-.L3868:
23667
+	str	r3, [r4, #1772]
23668
+.L3781:
23137
23669
 	ldrh	r2, [r7]
23138
23670
 	sxth	r3, r5
23139
23671
 	cmp	r3, r2
23140
-	bge	.L3875
23141
-	mov	r1, #1
23142
-	ldr	r0, .L3876+8
23143
-	mov	r2, r1
23672
+	blt	.L3783
23673
+	add	sp, sp, #24
23674
+	@ sp needed
23675
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
23676
+.L3783:
23677
+	mov	r2, #1
23144
23678
 	orr	r3, r3, r8
23145
-	str	r3, [r4, #1756]
23679
+	mov	r1, r2
23680
+	mov	r0, r9
23681
+	str	r3, [r4, #1764]
23146
23682
 	bl	FlashReadPages
23147
-	ldr	r3, [r4, #1764]
23683
+	ldr	r2, [r4, #1768]
23148
23684
 	mov	r1, r6
23149
-	ldr	r0, .L3876+12
23150
-	ldr	r2, [r3]
23151
-	str	r2, [sp]
23152
-	ldr	r2, [r3, #4]
23153
-	str	r2, [sp, #4]
23685
+	ldr	r3, [r4, #1772]
23686
+	mov	r0, r10
23687
+	ldr	r2, [r2]
23688
+	str	r2, [sp, #16]
23689
+	ldr	r2, [r3, #12]
23690
+	str	r2, [sp, #12]
23154
23691
 	ldr	r2, [r3, #8]
23155
23692
 	str	r2, [sp, #8]
23156
-	ldr	r3, [r3, #12]
23157
-	ldr	r2, [r4, #1752]
23158
-	str	r3, [sp, #12]
23159
-	ldr	r3, [r4, #1760]
23693
+	ldr	r2, [r3, #4]
23694
+	str	r2, [sp, #4]
23160
23695
 	ldr	r3, [r3]
23161
-	str	r3, [sp, #16]
23162
-	ldr	r3, [r4, #1756]
23163
-	bl	printk
23696
+	ldr	r2, [r4, #1760]
23697
+	str	r3, [sp]
23164
23698
 	ldr	r3, [r4, #1764]
23699
+	bl	printk
23700
+	ldr	r3, [r4, #1772]
23165
23701
 	ldr	r3, [r3]
23166
23702
 	cmn	r3, #1
23167
-	beq	.L3869
23168
-	ldr	r0, .L3876+16
23169
-	mov	r2, #4
23170
-	ldr	r1, [r9, #-524]
23703
+	beq	.L3782
23171
23704
 	mov	r3, #768
23705
+	mov	r2, #4
23706
+	ldr	r1, [r4, #-524]
23707
+	ldr	r0, .L3788+12
23172
23708
 	bl	rknand_print_hex
23173
-.L3869:
23709
+.L3782:
23174
23710
 	add	r5, r5, #1
23175
-	b	.L3868
23176
-.L3875:
23177
-	add	sp, sp, #28
23178
-	@ sp needed
23179
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, pc}
23180
-.L3877:
23711
+	b	.L3781
23712
+.L3789:
23181
23713
 	.align	2
23182
-.L3876:
23714
+.L3788:
23183
23715
 	.word	.LANCHOR2
23184
-	.word	.LANCHOR0+2390
23185
-	.word	.LANCHOR2+1752
23716
+	.word	.LANCHOR0+2392
23186
23717
 	.word	.LC167
23187
23718
 	.word	.LC168
23188
23719
 	.fnend
23189
23720
 	.size	FtlDumpSysBlock, .-FtlDumpSysBlock
23190
23721
 	.align	2
23191
23722
 	.global	dump_map_info
23723
+	.syntax unified
23724
+	.arm
23725
+	.fpu softvfp
23192
23726
 	.type	dump_map_info, %function
23193
23727
 dump_map_info:
23194
23728
 	.fnstart
23195
-	@ args = 0, pretend = 0, frame = 24
23729
+	@ args = 0, pretend = 0, frame = 16
23196
23730
 	@ frame_needed = 0, uses_anonymous_args = 0
23197
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
23731
+	ldr	r3, .L3805
23732
+	movw	r2, #2332
23733
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
23198
23734
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
23199
-	movw	r3, #2328
23200
-	ldr	r6, .L3896
23201
-	.pad #52
23202
-	sub	sp, sp, #52
23203
-	ldr	r10, .L3896+4
23204
-	ldrh	r7, [r6, r3]
23205
-	add	fp, r10, #18
23206
-.L3879:
23207
-	ldrh	r3, [r10]
23208
-	ldr	r4, .L3896+8
23209
-	cmp	r3, r7
23210
-	bls	.L3892
23211
-	ldr	r1, .L3896+12
23212
-	mov	r8, #0
23213
-	ldr	r2, [r4, #-536]
23214
-	mov	r5, r8
23215
-	ldr	r3, [r4, #-2696]
23216
-	ldrh	ip, [r1]
23217
-	ldr	r9, [r4, #-2692]
23218
-	ldrh	r1, [r1, #80]
23219
-	str	r1, [sp, #28]
23220
-.L3888:
23221
-	uxth	r1, r8
23222
-	cmp	r1, ip
23223
-	bcs	.L3894
23224
-	mov	r1, r7
23225
-	ldrb	r0, [fp, r8]	@ zero_extendqisi2
23226
-	str	r3, [sp, #44]
23227
-	str	r2, [sp, #40]
23228
-	str	ip, [sp, #36]
23735
+	.pad #44
23736
+	sub	sp, sp, #44
23737
+	ldrh	r6, [r3, r2]
23738
+	str	r3, [sp, #24]
23739
+.L3791:
23740
+	ldr	r3, .L3805+4
23741
+	ldr	r4, .L3805+8
23742
+	ldrh	r3, [r3]
23743
+	cmp	r3, r6
23744
+	bhi	.L3798
23745
+	ldr	r10, .L3805+12
23746
+	mov	r7, #0
23747
+	sub	r9, r4, #388
23748
+	add	fp, r4, #1760
23749
+.L3799:
23750
+	ldrh	r3, [r9]
23751
+	sxth	r5, r7
23752
+	cmp	r5, r3
23753
+	bge	.L3802
23754
+	lsl	r5, r5, #1
23755
+	mov	r6, #0
23756
+	ldr	r8, .L3805+16
23757
+	b	.L3803
23758
+.L3793:
23759
+	str	r3, [sp, #32]
23760
+	mov	r1, r6
23761
+	ldr	r3, .L3805+20
23762
+	str	r2, [sp, #36]
23763
+	ldrb	r0, [r3, r7]	@ zero_extendqisi2
23229
23764
 	bl	V2P_block
23230
-	str	r0, [sp, #32]
23765
+	str	r0, [sp, #28]
23231
23766
 	bl	FtlBbmIsBadBlock
23232
23767
 	cmp	r0, #0
23233
-	ldr	r1, [sp, #32]
23234
-	ldr	ip, [sp, #36]
23235
-	ldr	r2, [sp, #40]
23236
-	ldr	r3, [sp, #44]
23237
-	bne	.L3880
23238
-	mov	r0, #36
23239
-	mov	r1, r1, asl #10
23240
-	mla	r0, r0, r5, r2
23241
-	stmib	r0, {r1, r3}
23768
+	ldr	r3, [sp, #32]
23769
+	ldr	r2, [sp, #36]
23770
+	bne	.L3792
23242
23771
 	ldr	r1, [sp, #28]
23243
-	mul	r1, r1, r5
23772
+	mla	r0, r2, r5, r8
23773
+	lsl	r1, r1, #10
23774
+	stmib	r0, {r1, fp}
23775
+	mul	r1, r9, r5
23244
23776
 	add	r5, r5, #1
23245
23777
 	uxth	r5, r5
23246
-	add	lr, r1, #3
23778
+	add	ip, r1, #3
23247
23779
 	cmp	r1, #0
23248
-	movlt	r1, lr
23780
+	movlt	r1, ip
23249
23781
 	bic	r1, r1, #3
23250
-	add	r1, r9, r1
23782
+	add	r1, r10, r1
23251
23783
 	str	r1, [r0, #12]
23252
-.L3880:
23253
-	add	r8, r8, #1
23254
-	b	.L3888
23255
-.L3894:
23784
+.L3792:
23785
+	add	r7, r7, #1
23786
+.L3800:
23787
+	uxth	r1, r7
23788
+	cmp	r3, r1
23789
+	bhi	.L3793
23256
23790
 	cmp	r5, #0
23257
-	beq	.L3883
23258
-	ldr	r0, [r4, #-536]
23259
-	mov	r1, r5
23260
-	mov	r2, #1
23261
-	mov	r8, #0
23262
-	bl	FlashReadPages
23263
-	mov	r9, #36
23264
-.L3884:
23265
-	uxth	r3, r8
23266
-	cmp	r3, r5
23267
-	bcs	.L3883
23268
-	ldr	r3, [r4, #-536]
23269
-	ldr	r0, .L3896+16
23270
-	mla	r3, r9, r8, r3
23271
-	add	r8, r8, #1
23272
-	ldmib	r3, {r2, r3, ip}
23273
-	ldr	r1, [ip, #4]
23274
-	str	r1, [sp]
23275
-	ldr	r1, [ip, #8]
23276
-	str	r1, [sp, #4]
23277
-	ldr	r1, [ip, #12]
23278
-	str	r1, [sp, #8]
23279
-	ldr	r1, [r3]
23280
-	str	r1, [sp, #12]
23281
-	ubfx	r1, r2, #10, #16
23282
-	ldr	r3, [r3, #4]
23283
-	str	r3, [sp, #16]
23284
-	ldr	r3, [ip]
23285
-	bl	printk
23286
-	b	.L3884
23287
-.L3883:
23288
-	add	r7, r7, #1
23289
-	uxth	r7, r7
23290
-	b	.L3879
23291
-.L3892:
23292
-	ldr	r9, .L3896+20
23293
-	mov	r8, #0
23294
-.L3887:
23295
-	ldr	r7, .L3896+8
23296
-	sxth	r5, r8
23297
-	sub	r3, r7, #388
23298
-	ldrh	r3, [r3]
23299
-	cmp	r5, r3
23300
-	bge	.L3890
23301
-	mov	r5, r5, asl #1
23791
+	bne	.L3794
23792
+.L3797:
23793
+	add	r6, r6, #1
23794
+	uxth	r6, r6
23795
+	b	.L3791
23796
+.L3794:
23797
+	ldr	r9, .L3805+24
23798
+	mov	r0, r8
23302
23799
 	mov	r7, #0
23303
-.L3891:
23304
-	ldrh	r2, [r9]
23305
-	sxth	r3, r7
23306
-	add	r7, r7, #1
23307
-	cmp	r3, r2
23308
-	bge	.L3895
23309
-	ldr	r2, [r4, #-472]
23310
-	mov	r1, #1
23311
-	ldr	r0, .L3896+24
23312
-	ldrh	r2, [r2, r5]
23313
-	orr	r3, r3, r2, asl #10
23314
-	mov	r2, r1
23315
-	str	r3, [r4, #1756]
23800
+	mov	r8, #36
23801
+	mov	r2, #1
23802
+	mov	r1, r5
23316
23803
 	bl	FlashReadPages
23317
-	ldr	r3, [r4, #1764]
23318
-	ldr	r1, [r4, #-472]
23319
-	ldr	r2, [r4, #1760]
23320
-	ldr	r0, [r3]
23321
-	ldrh	r1, [r1, r5]
23322
-	str	r0, [sp]
23804
+.L3795:
23805
+	uxth	r3, r7
23806
+	cmp	r5, r3
23807
+	bls	.L3797
23808
+	ldr	r3, [r4, #-536]
23809
+	mla	r3, r8, r7, r3
23810
+	add	r7, r7, #1
23811
+	ldr	r1, [r3, #12]
23812
+	ldr	r2, [r3, #4]
23813
+	ldr	r3, [r3, #8]
23323
23814
 	ldr	r0, [r3, #4]
23324
-	str	r0, [sp, #4]
23325
-	ldr	r0, [r3, #8]
23326
-	str	r0, [sp, #8]
23327
-	ldr	r3, [r3, #12]
23328
-	ldr	r0, .L3896+28
23815
+	str	r0, [sp, #16]
23816
+	mov	r0, r9
23817
+	ldr	r3, [r3]
23329
23818
 	str	r3, [sp, #12]
23330
-	ldr	r3, [r2]
23331
-	str	r3, [sp, #16]
23332
-	ldr	r3, [r2, #4]
23333
-	str	r3, [sp, #20]
23334
-	ldr	r2, [r4, #1752]
23335
-	ldr	r3, [r4, #1756]
23819
+	ldr	r3, [r1, #12]
23820
+	str	r3, [sp, #8]
23821
+	ldr	r3, [r1, #8]
23822
+	str	r3, [sp, #4]
23823
+	ldr	r3, [r1, #4]
23824
+	str	r3, [sp]
23825
+	ldr	r3, [r1]
23826
+	ubfx	r1, r2, #10, #16
23336
23827
 	bl	printk
23337
-	b	.L3891
23338
-.L3895:
23339
-	add	r8, r8, #1
23340
-	b	.L3887
23341
-.L3890:
23342
-	ldr	r1, [r7, #-472]
23343
-	movw	r4, #2424
23344
-	ldr	r3, [r6, #2416]
23828
+	b	.L3795
23829
+.L3798:
23830
+	ldr	r2, .L3805+28
23831
+	mov	r7, #0
23832
+	ldr	r8, [r4, #-536]
23833
+	mov	r5, r7
23834
+	ldr	fp, [r4, #-2696]
23835
+	ldrh	r3, [r2]
23836
+	ldrh	r9, [r2, #78]
23837
+	mov	r2, #36
23838
+	ldr	r10, [r4, #-2692]
23839
+	b	.L3800
23840
+.L3801:
23841
+	ldr	r2, [r4, #-472]
23842
+	mov	r0, fp
23843
+	ldrh	r2, [r2, r5]
23844
+	orr	r3, r3, r2, lsl #10
23845
+	mov	r2, #1
23846
+	mov	r1, r2
23847
+	str	r3, [r4, #1764]
23848
+	bl	FlashReadPages
23849
+	ldr	r2, [r4, #1768]
23850
+	ldr	r1, [r4, #-472]
23851
+	ldr	r3, [r4, #1772]
23852
+	ldr	r0, [r2, #4]
23853
+	ldrh	r1, [r1, r5]
23854
+	str	r0, [sp, #20]
23855
+	mov	r0, r8
23856
+	ldr	r2, [r2]
23857
+	str	r2, [sp, #16]
23858
+	ldr	r2, [r3, #12]
23859
+	str	r2, [sp, #12]
23860
+	ldr	r2, [r3, #8]
23861
+	str	r2, [sp, #8]
23862
+	ldr	r2, [r3, #4]
23863
+	str	r2, [sp, #4]
23864
+	ldr	r3, [r3]
23865
+	ldr	r2, [r4, #1760]
23866
+	str	r3, [sp]
23867
+	ldr	r3, [r4, #1764]
23868
+	bl	printk
23869
+.L3803:
23870
+	ldrh	r2, [r10]
23871
+	sxth	r3, r6
23872
+	add	r6, r6, #1
23873
+	cmp	r3, r2
23874
+	blt	.L3801
23875
+	add	r7, r7, #1
23876
+	b	.L3799
23877
+.L3802:
23878
+	ldr	r3, [sp, #24]
23345
23879
 	mov	r2, #2
23346
-	ldr	r0, .L3896+32
23880
+	ldr	r1, [r4, #-472]
23881
+	movw	r5, #2428
23882
+	ldr	r0, .L3805+32
23883
+	ldr	r3, [r3, #2420]
23347
23884
 	bl	rknand_print_hex
23348
-	ldr	r1, [r7, #-452]
23349
-	ldrh	r3, [r6, r4]
23885
+	ldr	r3, [sp, #24]
23350
23886
 	mov	r2, #4
23351
-	ldr	r0, .L3896+36
23887
+	ldr	r1, [r4, #-452]
23888
+	ldr	r0, .L3805+36
23889
+	ldrh	r3, [r3, r5]
23352
23890
 	bl	rknand_print_hex
23353
-	ldr	r0, .L3896+40
23354
-	ldr	r1, [r7, #-448]
23891
+	ldr	r3, [sp, #24]
23355
23892
 	mov	r2, #4
23356
-	ldrh	r3, [r6, r4]
23357
-	add	sp, sp, #52
23893
+	ldr	r1, [r4, #-448]
23894
+	ldr	r0, .L3805+40
23895
+	ldrh	r3, [r3, r5]
23896
+	add	sp, sp, #44
23358
23897
 	@ sp needed
23359
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
23898
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
23360
23899
 	b	rknand_print_hex
23361
-.L3897:
23900
+.L3806:
23362
23901
 	.align	2
23363
-.L3896:
23902
+.L3805:
23364
23903
 	.word	.LANCHOR0
23365
-	.word	.LANCHOR0+2330
23904
+	.word	.LANCHOR0+2334
23366
23905
 	.word	.LANCHOR2
23367
-	.word	.LANCHOR0+2320
23368
-	.word	.LC169
23369
-	.word	.LANCHOR0+2390
23370
-	.word	.LANCHOR2+1752
23906
+	.word	.LANCHOR0+2392
23371
23907
 	.word	.LC113
23908
+	.word	.LANCHOR0+2350
23909
+	.word	.LC169
23910
+	.word	.LANCHOR0+2324
23372
23911
 	.word	.LC170
23373
23912
 	.word	.LC171
23374
23913
 	.word	.LC172
..
..
@@ -23376,493 +23915,483 @@
23376
23915
 	.size	dump_map_info, .-dump_map_info
23377
23916
 	.align	2
23378
23917
 	.global	flash_boot_enter_slc_mode
23918
+	.syntax unified
23919
+	.arm
23920
+	.fpu softvfp
23379
23921
 	.type	flash_boot_enter_slc_mode, %function
23380
23922
 flash_boot_enter_slc_mode:
23381
23923
 	.fnstart
23382
23924
 	@ args = 0, pretend = 0, frame = 0
23383
23925
 	@ frame_needed = 0, uses_anonymous_args = 0
23384
23926
 	@ link register save eliminated.
23385
-	ldr	r3, .L3900
23386
-	ldr	r2, [r3, #2264]
23387
-	ldr	r3, .L3900+4
23927
+	ldr	r3, .L3809
23928
+	ldr	r2, [r3, #2268]
23929
+	ldr	r3, .L3809+4
23388
23930
 	cmp	r2, r3
23389
23931
 	bxne	lr
23390
23932
 	b	flash_enter_slc_mode
23391
-.L3901:
23933
+.L3810:
23392
23934
 	.align	2
23393
-.L3900:
23935
+.L3809:
23394
23936
 	.word	.LANCHOR0
23395
23937
 	.word	1446522928
23396
23938
 	.fnend
23397
23939
 	.size	flash_boot_enter_slc_mode, .-flash_boot_enter_slc_mode
23398
23940
 	.align	2
23399
23941
 	.global	flash_boot_exit_slc_mode
23942
+	.syntax unified
23943
+	.arm
23944
+	.fpu softvfp
23400
23945
 	.type	flash_boot_exit_slc_mode, %function
23401
23946
 flash_boot_exit_slc_mode:
23402
23947
 	.fnstart
23403
23948
 	@ args = 0, pretend = 0, frame = 0
23404
23949
 	@ frame_needed = 0, uses_anonymous_args = 0
23405
23950
 	@ link register save eliminated.
23406
-	ldr	r3, .L3904
23407
-	ldr	r2, [r3, #2264]
23408
-	ldr	r3, .L3904+4
23951
+	ldr	r3, .L3813
23952
+	ldr	r2, [r3, #2268]
23953
+	ldr	r3, .L3813+4
23409
23954
 	cmp	r2, r3
23410
23955
 	bxne	lr
23411
23956
 	b	flash_exit_slc_mode
23412
-.L3905:
23957
+.L3814:
23413
23958
 	.align	2
23414
-.L3904:
23959
+.L3813:
23415
23960
 	.word	.LANCHOR0
23416
23961
 	.word	1446522928
23417
23962
 	.fnend
23418
23963
 	.size	flash_boot_exit_slc_mode, .-flash_boot_exit_slc_mode
23419
23964
 	.align	2
23420
23965
 	.global	write_idblock
23966
+	.syntax unified
23967
+	.arm
23968
+	.fpu softvfp
23421
23969
 	.type	write_idblock, %function
23422
23970
 write_idblock:
23423
23971
 	.fnstart
23424
-	@ args = 0, pretend = 0, frame = 120
23972
+	@ args = 0, pretend = 0, frame = 112
23425
23973
 	@ frame_needed = 0, uses_anonymous_args = 0
23426
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
23974
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
23427
23975
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
23428
-	mov	r8, r0
23429
-	ldr	r7, .L3959
23430
-	.pad #132
23431
-	sub	sp, sp, #132
23976
+	mov	r6, r0
23977
+	ldr	r4, .L3864
23978
+	.pad #124
23979
+	sub	sp, sp, #124
23432
23980
 	mov	r0, #256000
23433
-	mov	fp, r1
23434
-	mov	r6, r2
23435
-	ldr	r3, [r7, #44]
23436
-	ldr	r4, [r7, #4]
23437
-	ldrb	r5, [r3, #9]	@ zero_extendqisi2
23981
+	mov	r10, r1
23982
+	mov	r5, r2
23983
+	ldr	r3, [r4, #48]
23984
+	ldr	r8, [r4, #40]
23985
+	ldrb	r7, [r3, #9]	@ zero_extendqisi2
23438
23986
 	bl	ftl_malloc
23439
23987
 	subs	r3, r0, #0
23440
23988
 	str	r3, [sp, #8]
23441
-	beq	.L3933
23442
-	add	ip, r8, #508
23443
-	add	ip, ip, #3
23444
-	mov	r10, ip, lsr #9
23445
-	cmp	r10, #8
23446
-	bls	.L3931
23447
-	cmp	r10, #500
23448
-	bhi	.L3933
23449
-	b	.L3908
23450
-.L3931:
23451
-	mov	r10, #8
23452
-.L3908:
23453
-	ldr	r2, [fp]
23454
-	ldr	r3, .L3959+4
23989
+	beq	.L3842
23990
+	add	r0, r6, #508
23991
+	add	r0, r0, #3
23992
+	lsr	r9, r0, #9
23993
+	cmp	r9, #8
23994
+	bls	.L3840
23995
+	cmp	r9, #500
23996
+	bhi	.L3842
23997
+.L3817:
23998
+	ldr	r2, [r10]
23999
+	ldr	r3, .L3864+4
23455
24000
 	cmp	r2, r3
23456
-	bne	.L3933
23457
-	smulbb	r3, r5, r4
23458
-	uxth	r3, r3
23459
-	str	r3, [sp, #12]
23460
-	sub	r0, r3, #1
23461
-	mov	r1, r3
23462
-	add	r0, r0, r10
24001
+	bne	.L3842
24002
+	smulbb	r7, r7, r8
24003
+	uxth	fp, r7
24004
+	sub	r0, fp, #1
24005
+	mov	r1, fp
24006
+	add	r0, r0, r9
23463
24007
 	bl	__aeabi_uidiv
24008
+	str	r0, [sp, #32]
24009
+	add	r0, r10, #254976
24010
+	add	r0, r0, #512
23464
24011
 	mov	r3, #0
23465
24012
 	movw	r2, #63871
23466
-	str	r0, [sp, #36]
23467
-	add	r0, fp, #254976
23468
-	add	r0, r0, #512
23469
-.L3912:
24013
+.L3821:
23470
24014
 	ldr	r1, [r0, #-4]!
23471
24015
 	cmp	r1, #0
23472
-	bne	.L3909
23473
-	ldr	r1, [fp, r3, asl #2]
24016
+	bne	.L3818
24017
+	ldr	r1, [r10, r3, lsl #2]
23474
24018
 	add	r3, r3, #1
23475
24019
 	cmp	r3, #4096
23476
24020
 	sub	r2, r2, #1
23477
24021
 	movhi	r3, #0
23478
24022
 	cmp	r2, #4096
23479
24023
 	str	r1, [r0, #512]
23480
-	bne	.L3912
23481
-	b	.L3911
23482
-.L3909:
23483
-	ldr	r0, .L3959+8
23484
-	bl	printk
23485
-.L3911:
24024
+	bne	.L3821
24025
+.L3820:
23486
24026
 	mov	r3, #5
23487
-	ldr	r0, .L3959+12
23488
-	mov	r1, r6
24027
+	mov	r1, r5
23489
24028
 	mov	r2, #4
24029
+	ldr	r0, .L3864+8
23490
24030
 	bl	rknand_print_hex
23491
-	ldr	r1, [fp, #512]
23492
-	ldrb	r2, [r7, #1]	@ zero_extendqisi2
23493
-	sub	r4, r6, #4
23494
-	ldr	r0, .L3959+16
24031
+	ldrb	r2, [r4, #37]	@ zero_extendqisi2
24032
+	sub	r5, r5, #4
24033
+	ldr	r1, [r10, #512]
24034
+	ldr	r0, .L3864+12
23495
24035
 	bl	printk
23496
-	ldr	r2, .L3959+20
23497
-	ldrh	r3, [r7, #142]
23498
-	mov	r1, r10
23499
-	ldr	r0, .L3959+24
23500
-	ldr	r2, [r2, #1708]
23501
-	ldr	r5, .L3959
24036
+	ldr	r2, .L3864+16
24037
+	mov	r1, r9
24038
+	ldrh	r3, [r4, #150]
24039
+	ldr	r0, .L3864+20
24040
+	ldr	r2, [r2, #1716]
23502
24041
 	str	r2, [sp]
23503
-	mov	r2, r10
24042
+	mov	r2, r9
23504
24043
 	bl	printk
23505
-	ldrb	r3, [r7, #1]	@ zero_extendqisi2
23506
-	ldr	r2, [fp, #512]
24044
+	ldrb	r3, [r4, #37]	@ zero_extendqisi2
24045
+	ldr	r2, [r10, #512]
24046
+	ldr	r4, .L3864
23507
24047
 	cmp	r2, r3
23508
-	strhi	r3, [fp, #512]
23509
-	mov	r3, r10, asl #7
24048
+	strhi	r3, [r10, #512]
24049
+	lsl	r3, r9, #7
23510
24050
 	str	r3, [sp, #40]
23511
24051
 	mov	r3, #0
23512
24052
 	str	r3, [sp, #20]
23513
-	str	r3, [sp, #16]
23514
-.L3929:
23515
-	ldr	r2, [r4, #4]
23516
-	ldrb	r3, [r5, #1]	@ zero_extendqisi2
23517
-	ldr	r7, .L3959
24053
+	str	r3, [sp, #12]
24054
+.L3838:
24055
+	ldr	r2, [r5, #4]
24056
+	ldrb	r3, [r4, #37]	@ zero_extendqisi2
23518
24057
 	cmp	r2, r3
23519
-	bcs	.L3914
23520
-	ldr	r3, .L3959+20
23521
-	ldr	r3, [r3, #1708]
24058
+	bcs	.L3823
24059
+	ldr	r3, .L3864+16
24060
+	ldr	r3, [r3, #1716]
23522
24061
 	cmp	r2, r3
23523
-	bcc	.L3914
23524
-	ldr	r3, [sp, #36]
23525
-	ldr	r1, [sp, #36]
23526
-	cmp	r3, #1
23527
-	movls	r3, #0
23528
-	movhi	r3, #1
23529
-	str	r3, [sp, #44]
23530
-	ldr	r3, [sp, #16]
23531
-	cmp	r3, #0
23532
-	cmpne	r1, #1
23533
-	bls	.L3915
23534
-	ldr	r3, [r4]
24062
+	bcc	.L3823
24063
+	ldr	r3, [sp, #32]
24064
+	ldr	r1, [sp, #12]
24065
+	cmp	r1, #0
24066
+	cmpne	r3, #1
24067
+	bls	.L3824
24068
+	ldr	r3, [r5]
23535
24069
 	add	r3, r3, #1
23536
24070
 	cmp	r2, r3
23537
-	beq	.L3914
23538
-.L3915:
23539
-	mov	r1, #0
24071
+	beq	.L3823
24072
+.L3824:
23540
24073
 	mov	r2, #512
24074
+	mov	r1, #0
23541
24075
 	ldr	r0, [sp, #8]
23542
24076
 	bl	memset
23543
-	ldr	r6, [r4, #4]
23544
-	mov	r2, r10
23545
-	ldr	r0, .L3959+28
23546
-	ldr	r3, [sp, #12]
23547
-	mul	r6, r6, r3
23548
-	ldr	r3, [r7, #44]
23549
-	ldr	r7, [r7, #4]
23550
-	ldrb	r9, [r3, #9]	@ zero_extendqisi2
24077
+	ldr	r3, [r4, #48]
24078
+	mov	r2, r9
24079
+	ldr	r6, [r5, #4]
24080
+	ldr	r7, [r4, #40]
24081
+	ldrb	r3, [r3, #9]	@ zero_extendqisi2
24082
+	ldr	r0, .L3864+24
24083
+	mul	r6, r6, fp
24084
+	str	r3, [sp, #16]
24085
+	ldrh	r3, [sp, #16]
23551
24086
 	mov	r1, r6
24087
+	smulbb	r7, r7, r3
23552
24088
 	bl	printk
23553
24089
 	mov	r0, #0
23554
-	bl	flash_boot_enter_slc_mode
23555
-	mov	r1, r9
23556
-	mov	r0, r6
23557
-	bl	__aeabi_uidiv
23558
-	smulbb	r7, r7, r9
23559
24090
 	uxth	r7, r7
24091
+	bl	flash_boot_enter_slc_mode
24092
+	mov	r0, r6
24093
+	ldr	r1, [sp, #16]
24094
+	bl	__aeabi_uidiv
24095
+	mov	r2, #0
23560
24096
 	mov	r1, r0
23561
-	mov	r0, #0
23562
-	mov	r2, r0
24097
+	mov	r0, r2
23563
24098
 	bl	FlashEraseBlock
23564
-	cmp	r10, r7
23565
-	movls	r8, #1
23566
-	bls	.L3916
23567
-	mov	r0, #0
23568
-	add	r1, r6, r7
23569
-	mov	r2, r0
24099
+	cmp	r7, r9
24100
+	movcs	r8, #1
24101
+	bcs	.L3825
24102
+	mov	r2, #0
23570
24103
 	mov	r8, #2
24104
+	add	r1, r6, r7
24105
+	mov	r0, r2
23571
24106
 	bl	FlashEraseBlock
23572
-.L3916:
24107
+.L3825:
23573
24108
 	mov	r0, #0
23574
24109
 	bl	flash_boot_exit_slc_mode
23575
-	ldr	r3, [r5, #44]
24110
+	ldr	r3, [r4, #48]
23576
24111
 	ldrh	r0, [r3, #10]
23577
24112
 	ldrb	r1, [r3, #12]	@ zero_extendqisi2
23578
-	mov	r0, r0, asl #2
24113
+	lsl	r0, r0, #2
23579
24114
 	mul	r0, r8, r0
24115
+	mov	r8, #0
23580
24116
 	bl	__aeabi_idiv
23581
24117
 	mov	r1, r7
23582
-	mov	r8, #0
23583
-	str	r0, [sp, #48]
24118
+	str	r0, [sp, #44]
23584
24119
 	mov	r0, r6
23585
24120
 	bl	__aeabi_uidivmod
23586
-	mov	ip, r1
23587
-	rsb	r3, r1, r6
23588
-	str	fp, [sp, #24]
23589
-	str	r3, [sp, #28]
23590
-.L3917:
23591
-	ldr	r3, [sp, #48]
23592
-	ldr	r7, .L3959
23593
-	cmp	r8, r3
23594
-	bcs	.L3957
23595
-	add	r3, r8, ip
23596
-	ubfx	r3, r3, #2, #16
23597
-	cmp	r3, #0
23598
-	beq	.L3918
23599
-	add	r2, r3, #1
23600
-	add	r1, r5, r2, asl #1
23601
-	ldrh	r7, [r1, #148]
23602
-	ldrb	r1, [r5, #144]	@ zero_extendqisi2
23603
-	cmp	r1, #0
23604
-	beq	.L3919
23605
-	ldr	r1, [r5, #2264]
23606
-	ldr	r0, .L3959+32
23607
-	cmp	r1, r0
23608
-	moveq	r7, r2
23609
-.L3919:
23610
-	sub	r7, r7, #-1073741823
23611
-	mov	r7, r7, asl #2
23612
-	str	r7, [sp, #64]
23613
-.L3918:
23614
-	movw	r2, #61424
23615
-	str	r2, [sp, #68]
23616
-	add	r2, r5, r3, asl #1
23617
-	ldrh	r7, [r2, #148]
23618
-	ldrb	r2, [r5, #144]	@ zero_extendqisi2
23619
-	cmp	r2, #0
23620
-	beq	.L3920
23621
-	ldr	r2, [r5, #2264]
23622
-	ldr	r1, .L3959+32
23623
-	cmp	r2, r1
23624
-	moveq	r7, r3
23625
-.L3920:
23626
-	ldr	r3, [sp, #28]
23627
-	add	r8, r8, #4
23628
-	str	ip, [sp, #56]
23629
-	uxth	r8, r8
23630
-	mla	r2, r9, r7, r3
23631
-	ldr	r3, .L3959
23632
-	ldrb	r3, [r3, #2312]	@ zero_extendqisi2
23633
-	str	r2, [sp, #52]
23634
-	str	r3, [sp, #32]
23635
-	ldr	r3, .L3959+20
23636
-	ldrb	r0, [r3, #1714]	@ zero_extendqisi2
23637
-	bl	FlashBchSel
23638
-	mov	r0, #0
23639
-	bl	flash_boot_enter_slc_mode
23640
-	ldr	r3, .L3959
23641
-	ldr	r3, [r3, #44]
23642
-	ldrb	r1, [r3, #9]	@ zero_extendqisi2
23643
-	ldr	r2, [sp, #52]
23644
-	mov	r0, r2
23645
-	bl	__aeabi_uidiv
23646
-	add	r3, sp, #64
23647
-	mov	r1, r0
23648
-	ldr	r2, [sp, #24]
23649
-	mov	r0, #0
23650
-	bl	FlashProgPage
23651
-	mov	r0, #0
23652
-	bl	flash_boot_exit_slc_mode
23653
-	ldr	r0, [sp, #32]
23654
-	bl	FlashBchSel
23655
-	mov	r1, r9
23656
-	ldr	r0, [sp, #28]
23657
-	bl	__aeabi_uidiv
23658
-	add	r2, r7, #1
23659
-	uxth	r2, r2
23660
-	mov	r1, r0
23661
-	mov	r0, #0
23662
-	bl	FlashPageProgMsbFFData
23663
-	ldr	r3, [sp, #24]
23664
-	ldr	ip, [sp, #56]
23665
-	add	r3, r3, #2048
23666
-	str	r3, [sp, #24]
23667
-	b	.L3917
23668
-.L3957:
23669
-	mov	r1, r6
23670
-	mov	r2, r10
23671
-	mov	r3, #0
23672
-	ldr	r0, .L3959+36
23673
-	bl	printk
23674
-	ldr	r6, [r4, #4]
23675
-	ldr	r8, [r7, #4]
23676
-	mov	r2, r10
23677
-	ldr	r0, .L3959+40
23678
-	mov	r9, #0
23679
-	ldr	r3, [sp, #12]
23680
-	mul	r6, r6, r3
23681
-	ldr	r3, [r7, #44]
23682
-	ldrb	r3, [r3, #9]	@ zero_extendqisi2
23683
-	mov	r1, r6
23684
-	str	r3, [sp, #24]
23685
-	ldrh	r3, [sp, #24]
23686
-	smulbb	r8, r8, r3
23687
-	bl	printk
23688
-	mov	r0, r6
23689
-	uxth	r8, r8
23690
-	mov	r1, r8
23691
-	bl	__aeabi_uidivmod
23692
-	rsb	r3, r1, r6
23693
-	str	r3, [sp, #48]
23694
-	ldr	r3, [sp, #24]
24121
+	sub	r3, r6, r1
23695
24122
 	str	r1, [sp, #28]
23696
-	mul	ip, r3, r1
23697
-	ldr	r3, [sp, #8]
23698
-	ubfx	ip, ip, #2, #2
23699
-	str	r3, [sp, #32]
23700
-.L3922:
23701
-	cmp	r9, r10
23702
-	bcs	.L3958
23703
-	ldr	r3, [sp, #28]
23704
-	rsb	r8, ip, #4
23705
-	ldrb	r1, [r5, #144]	@ zero_extendqisi2
23706
-	add	r3, r9, r3
23707
-	uxth	r8, r8
23708
-	ubfx	r3, r3, #2, #16
23709
-	cmp	r1, #0
23710
-	add	r2, r5, r3, asl #1
23711
-	ldrh	r2, [r2, #148]
23712
-	beq	.L3923
23713
-	ldr	r1, [r5, #2264]
23714
-	ldr	r0, .L3959+32
23715
-	cmp	r1, r0
23716
-	moveq	r2, r3
23717
-.L3923:
23718
-	ldr	r3, [sp, #48]
23719
-	add	r9, r8, r9
23720
-	ldr	r1, [sp, #24]
23721
-	add	r3, ip, r3
23722
-	ldrb	ip, [r7, #2312]	@ zero_extendqisi2
23723
-	uxth	r9, r9
23724
-	mla	r3, r1, r2, r3
23725
-	ldr	r2, [r7, #44]
23726
-	str	ip, [sp, #52]
23727
-	ldrb	r1, [r2, #9]	@ zero_extendqisi2
23728
-	ldr	r2, .L3959+20
23729
-	str	r3, [sp, #60]
23730
-	str	r1, [sp, #56]
23731
-	ldrb	r0, [r2, #1714]	@ zero_extendqisi2
23732
-	bl	FlashBchSel
23733
-	mov	r0, #0
23734
-	bl	flash_boot_enter_slc_mode
23735
-	ldr	r3, [sp, #60]
23736
-	ldr	r1, [sp, #56]
23737
-	mov	r0, r3
23738
-	bl	__aeabi_uidiv
23739
-	mov	r1, r0
23740
-	mov	r0, #0
23741
-	mov	r3, r0
23742
-	ldr	r2, [sp, #32]
23743
-	bl	FlashReadPage
23744
-	mov	r0, #0
23745
-	bl	flash_boot_exit_slc_mode
23746
-	ldr	ip, [sp, #52]
23747
-	mov	r0, ip
23748
-	bl	FlashBchSel
23749
-	mov	ip, #0
23750
-	ldr	r3, [sp, #32]
23751
-	add	r3, r3, r8, asl #9
23752
-	str	r3, [sp, #32]
23753
-	b	.L3922
23754
-.L3958:
24123
+	str	r3, [sp, #36]
24124
+	str	r10, [sp, #24]
24125
+.L3826:
24126
+	ldr	r3, [sp, #44]
24127
+	cmp	r3, r8
24128
+	bhi	.L3830
23755
24129
 	mov	r1, r6
23756
-	mov	r2, r10
23757
24130
 	mov	r3, #0
23758
-	ldr	r0, .L3959+44
24131
+	mov	r2, r9
24132
+	ldr	r0, .L3864+28
23759
24133
 	bl	printk
23760
-	mov	r6, #0
23761
-	mov	r3, fp
24134
+	ldr	r3, [r4, #48]
24135
+	mov	r2, r9
24136
+	ldr	r6, [r5, #4]
24137
+	mov	r8, #0
24138
+	ldr	r7, [r4, #40]
24139
+	ldrb	r3, [r3, #9]	@ zero_extendqisi2
24140
+	ldr	r0, .L3864+32
24141
+	mul	r6, r6, fp
24142
+	str	r3, [sp, #16]
24143
+	ldrh	r3, [sp, #16]
24144
+	mov	r1, r6
24145
+	smulbb	r7, r7, r3
24146
+	bl	printk
24147
+	uxth	r7, r7
24148
+	mov	r0, r6
24149
+	mov	r1, r7
24150
+	bl	__aeabi_uidivmod
24151
+	sub	r3, r6, r1
23762
24152
 	ldr	r2, [sp, #8]
23763
-.L3928:
23764
-	mov	r8, r2
23765
-	mov	r7, r3
23766
-	ldr	r0, [r8]
24153
+	str	r3, [sp, #36]
24154
+	ldr	r3, [sp, #16]
24155
+	str	r1, [sp, #24]
24156
+	str	r2, [sp, #28]
24157
+	mul	r3, r3, r1
24158
+	ubfx	r3, r3, #2, #2
24159
+.L3831:
24160
+	cmp	r8, r9
24161
+	bcc	.L3833
24162
+	mov	r3, #0
24163
+	mov	r2, r9
24164
+	mov	r1, r6
24165
+	ldr	r0, .L3864+36
24166
+	bl	printk
24167
+	ldr	r2, [sp, #8]
24168
+	mov	r3, r10
24169
+	mov	r6, #0
24170
+.L3836:
24171
+	mov	r7, r2
24172
+	mov	r8, r3
24173
+	ldr	r0, [r7]
23767
24174
 	add	r2, r2, #4
23768
-	ldr	r1, [r7]
24175
+	ldr	r1, [r8]
23769
24176
 	add	r3, r3, #4
23770
24177
 	cmp	r0, r1
23771
-	beq	.L3925
23772
-	mov	r1, #0
24178
+	beq	.L3834
23773
24179
 	mov	r2, #512
24180
+	mov	r1, #0
23774
24181
 	ldr	r0, [sp, #8]
23775
24182
 	bl	memset
23776
24183
 	ldr	r3, [r8]
23777
-	ldr	r0, .L3959+48
23778
-	str	r3, [sp]
23779
-	ldr	r3, [r7]
23780
-	bic	r7, r6, #255
23781
-	ldr	r1, [sp, #16]
23782
-	mov	r7, r7, asl #2
24184
+	ldr	r1, [sp, #12]
24185
+	ldr	r0, .L3864+40
23783
24186
 	str	r3, [sp, #4]
24187
+	ldr	r3, [r7]
24188
+	str	r3, [sp]
23784
24189
 	mov	r3, r6
23785
-	ldr	r2, [r4, #4]
24190
+	bic	r6, r6, #255
24191
+	ldr	r2, [r5, #4]
24192
+	lsl	r6, r6, #2
23786
24193
 	bl	printk
23787
-	ldr	r0, .L3959+52
23788
-	add	r1, fp, r7
23789
-	mov	r2, #4
23790
24194
 	mov	r3, #256
24195
+	mov	r2, #4
24196
+	add	r1, r10, r6
24197
+	ldr	r0, .L3864+44
23791
24198
 	bl	rknand_print_hex
23792
-	mov	r2, #4
23793
-	ldr	r0, .L3959+56
23794
-	ldr	r3, [sp, #8]
23795
-	add	r1, r3, r7
24199
+	ldr	r1, [sp, #8]
23796
24200
 	mov	r3, #256
24201
+	mov	r2, #4
24202
+	ldr	r0, .L3864+48
24203
+	add	r1, r1, r6
23797
24204
 	bl	rknand_print_hex
23798
24205
 	mov	r0, #0
23799
24206
 	bl	flash_boot_enter_slc_mode
23800
-	ldr	r1, [r4, #4]
23801
-	mov	r0, #0
23802
-	mov	r2, r0
23803
-	ldr	r3, [sp, #12]
23804
-	mul	r1, r1, r3
24207
+	ldr	r1, [r5, #4]
24208
+	mov	r2, #0
24209
+	mov	r0, r2
24210
+	mul	r1, r1, fp
23805
24211
 	bl	FlashEraseBlock
23806
-	ldr	r3, [sp, #44]
23807
-	cmp	r3, #0
23808
-	beq	.L3926
23809
-	ldr	r1, [r4, #4]
23810
-	mov	r0, #0
23811
-	ldr	r3, [sp, #12]
23812
-	mov	r2, r0
23813
-	mla	r1, r1, r3, r3
24212
+	ldr	r3, [sp, #32]
24213
+	cmp	r3, #1
24214
+	bls	.L3835
24215
+	ldr	r1, [r5, #4]
24216
+	mov	r2, #0
24217
+	mov	r0, r2
24218
+	mla	r1, r1, fp, fp
23814
24219
 	bl	FlashEraseBlock
23815
-.L3926:
24220
+.L3835:
23816
24221
 	mov	r0, #0
23817
24222
 	bl	flash_boot_exit_slc_mode
23818
-	ldr	r0, .L3959+60
23819
-	ldr	r1, [r4, #4]
24223
+	ldr	r1, [r5, #4]
24224
+	ldr	r0, .L3864+52
23820
24225
 	bl	printk
23821
-	ldr	r3, [sp, #40]
23822
-	cmp	r6, r3
23823
-	bcc	.L3914
23824
-	b	.L3927
23825
-.L3925:
23826
-	ldr	r1, [sp, #40]
23827
-	add	r6, r6, #1
23828
-	cmp	r6, r1
23829
-	bne	.L3928
23830
-.L3927:
23831
-	ldr	r3, [sp, #20]
24226
+.L3823:
24227
+	ldr	r3, [sp, #12]
24228
+	add	r5, r5, #4
23832
24229
 	add	r3, r3, #1
23833
-	str	r3, [sp, #20]
23834
-.L3914:
23835
-	ldr	r3, [sp, #16]
23836
-	add	r4, r4, #4
23837
-	add	r3, r3, #1
23838
-	str	r3, [sp, #16]
23839
24230
 	cmp	r3, #5
23840
-	bne	.L3929
24231
+	str	r3, [sp, #12]
24232
+	bne	.L3838
23841
24233
 	ldr	r0, [sp, #8]
23842
24234
 	bl	ftl_free
23843
24235
 	ldr	r3, [sp, #20]
23844
24236
 	clz	r0, r3
23845
-	mov	r0, r0, lsr #5
24237
+	lsr	r0, r0, #5
23846
24238
 	rsb	r0, r0, #0
23847
-	b	.L3907
23848
-.L3933:
23849
-	mvn	r0, #0
23850
-.L3907:
23851
-	add	sp, sp, #132
24239
+.L3815:
24240
+	add	sp, sp, #124
23852
24241
 	@ sp needed
23853
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
23854
-.L3960:
24242
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
24243
+.L3840:
24244
+	mov	r9, #8
24245
+	b	.L3817
24246
+.L3818:
24247
+	ldr	r0, .L3864+56
24248
+	bl	printk
24249
+	b	.L3820
24250
+.L3830:
24251
+	ldr	r3, [sp, #28]
24252
+	add	r2, r3, r8
24253
+	lsrs	r2, r2, #2
24254
+	beq	.L3827
24255
+	ldrb	r0, [r4, #152]	@ zero_extendqisi2
24256
+	add	r1, r2, #1
24257
+	add	r3, r4, r1, lsl #1
24258
+	cmp	r0, #0
24259
+	ldrh	r3, [r3, #156]
24260
+	beq	.L3828
24261
+	ldr	r0, [r4, #2268]
24262
+	ldr	ip, .L3864+60
24263
+	cmp	r0, ip
24264
+	moveq	r3, r1
24265
+.L3828:
24266
+	sub	r3, r3, #-1073741823
24267
+	lsl	r3, r3, #2
24268
+	str	r3, [sp, #56]
24269
+.L3827:
24270
+	movw	r3, #61424
24271
+	str	r3, [sp, #60]
24272
+	add	r3, r4, r2, lsl #1
24273
+	ldrh	r7, [r3, #156]
24274
+	ldrb	r3, [r4, #152]	@ zero_extendqisi2
24275
+	cmp	r3, #0
24276
+	beq	.L3829
24277
+	ldr	r3, [r4, #2268]
24278
+	ldr	r1, .L3864+60
24279
+	cmp	r3, r1
24280
+	moveq	r7, r2
24281
+.L3829:
24282
+	ldr	r2, [sp, #36]
24283
+	add	r8, r8, #4
24284
+	ldr	r3, [sp, #16]
24285
+	uxth	r8, r8
24286
+	mla	r3, r7, r3, r2
24287
+	ldr	r2, .L3864+16
24288
+	add	r7, r7, #1
24289
+	ldrb	r0, [r2, #1722]	@ zero_extendqisi2
24290
+	uxth	r7, r7
24291
+	str	r3, [sp, #52]
24292
+	ldrb	r3, [r4, #2316]	@ zero_extendqisi2
24293
+	str	r3, [sp, #48]
24294
+	bl	FlashBchSel
24295
+	mov	r0, #0
24296
+	bl	flash_boot_enter_slc_mode
24297
+	ldr	r2, [r4, #48]
24298
+	ldr	r3, [sp, #52]
24299
+	ldrb	r1, [r2, #9]	@ zero_extendqisi2
24300
+	mov	r0, r3
24301
+	bl	__aeabi_uidiv
24302
+	add	r3, sp, #56
24303
+	ldr	r2, [sp, #24]
24304
+	mov	r1, r0
24305
+	mov	r0, #0
24306
+	bl	FlashProgPage
24307
+	mov	r0, #0
24308
+	bl	flash_boot_exit_slc_mode
24309
+	ldr	r0, [sp, #48]
24310
+	bl	FlashBchSel
24311
+	ldr	r1, [sp, #16]
24312
+	ldr	r0, [sp, #36]
24313
+	bl	__aeabi_uidiv
24314
+	mov	r2, r7
24315
+	mov	r1, r0
24316
+	mov	r0, #0
24317
+	bl	FlashPageProgMsbFFData
24318
+	ldr	r3, [sp, #24]
24319
+	add	r3, r3, #2048
24320
+	str	r3, [sp, #24]
24321
+	b	.L3826
24322
+.L3833:
24323
+	ldr	r2, [sp, #24]
24324
+	rsb	r7, r3, #4
24325
+	ldrb	r0, [r4, #152]	@ zero_extendqisi2
24326
+	uxth	r7, r7
24327
+	add	r2, r2, r8
24328
+	lsr	r2, r2, #2
24329
+	cmp	r0, #0
24330
+	add	r1, r4, r2, lsl #1
24331
+	ldrh	r1, [r1, #156]
24332
+	beq	.L3832
24333
+	ldr	r0, [r4, #2268]
24334
+	ldr	ip, .L3864+60
24335
+	cmp	r0, ip
24336
+	moveq	r1, r2
24337
+.L3832:
24338
+	ldr	r2, [sp, #36]
24339
+	add	r8, r7, r8
24340
+	uxth	r8, r8
24341
+	add	r3, r3, r2
24342
+	ldr	r2, [sp, #16]
24343
+	mla	r3, r1, r2, r3
24344
+	ldr	r2, [r4, #48]
24345
+	ldrb	r1, [r2, #9]	@ zero_extendqisi2
24346
+	ldr	r2, .L3864+16
24347
+	str	r3, [sp, #52]
24348
+	ldrb	r3, [r4, #2316]	@ zero_extendqisi2
24349
+	ldrb	r0, [r2, #1722]	@ zero_extendqisi2
24350
+	str	r1, [sp, #48]
24351
+	str	r3, [sp, #44]
24352
+	bl	FlashBchSel
24353
+	mov	r0, #0
24354
+	bl	flash_boot_enter_slc_mode
24355
+	ldr	r3, [sp, #52]
24356
+	ldr	r1, [sp, #48]
24357
+	mov	r0, r3
24358
+	bl	__aeabi_uidiv
24359
+	mov	r3, #0
24360
+	mov	r1, r0
24361
+	ldr	r2, [sp, #28]
24362
+	mov	r0, r3
24363
+	bl	FlashReadPage
24364
+	mov	r0, #0
24365
+	bl	flash_boot_exit_slc_mode
24366
+	ldr	r0, [sp, #44]
24367
+	bl	FlashBchSel
24368
+	ldr	r3, [sp, #28]
24369
+	add	r3, r3, r7, lsl #9
24370
+	str	r3, [sp, #28]
24371
+	mov	r3, #0
24372
+	b	.L3831
24373
+.L3834:
24374
+	ldr	r1, [sp, #40]
24375
+	add	r6, r6, #1
24376
+	cmp	r1, r6
24377
+	bne	.L3836
24378
+	ldr	r3, [sp, #20]
24379
+	add	r3, r3, #1
24380
+	str	r3, [sp, #20]
24381
+	b	.L3823
24382
+.L3842:
24383
+	mvn	r0, #0
24384
+	b	.L3815
24385
+.L3865:
23855
24386
 	.align	2
23856
-.L3959:
24387
+.L3864:
23857
24388
 	.word	.LANCHOR0
23858
24389
 	.word	-52655045
23859
-	.word	.LC173
23860
24390
 	.word	.LC174
23861
24391
 	.word	.LC175
23862
24392
 	.word	.LANCHOR2
23863
24393
 	.word	.LC176
23864
24394
 	.word	.LC177
23865
-	.word	1446522928
23866
24395
 	.word	.LC178
23867
24396
 	.word	.LC179
23868
24397
 	.word	.LC180
..
..
@@ -23870,92 +24399,90 @@
23870
24399
 	.word	.LC182
23871
24400
 	.word	.LC183
23872
24401
 	.word	.LC184
24402
+	.word	.LC173
24403
+	.word	1446522928
23873
24404
 	.fnend
23874
24405
 	.size	write_idblock, .-write_idblock
23875
24406
 	.align	2
23876
24407
 	.global	write_loader_lba
24408
+	.syntax unified
24409
+	.arm
24410
+	.fpu softvfp
23877
24411
 	.type	write_loader_lba, %function
23878
24412
 write_loader_lba:
23879
24413
 	.fnstart
23880
24414
 	@ args = 0, pretend = 0, frame = 40
23881
24415
 	@ frame_needed = 0, uses_anonymous_args = 0
23882
24416
 	cmp	r0, #64
23883
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, lr}
23884
-	.save {r4, r5, r6, r7, r8, r9, lr}
24417
+	push	{r4, r5, r6, r7, r8, lr}
24418
+	.save {r4, r5, r6, r7, r8, lr}
23885
24419
 	mov	r5, r0
23886
-	.pad #52
23887
-	sub	sp, sp, #52
24420
+	.pad #48
24421
+	sub	sp, sp, #48
23888
24422
 	mov	r6, r1
23889
24423
 	mov	r8, r2
23890
-	ldr	r4, .L3984
23891
-	bne	.L3962
24424
+	ldr	r4, .L3890
24425
+	bne	.L3867
23892
24426
 	ldr	r2, [r2]
23893
-	ldr	r3, .L3984+4
24427
+	ldr	r3, .L3890+4
23894
24428
 	cmp	r2, r3
23895
-	bne	.L3962
23896
-	mov	r0, #256000
24429
+	bne	.L3867
23897
24430
 	mov	r3, #1
24431
+	mov	r0, #256000
23898
24432
 	strb	r3, [r4, #2020]
23899
24433
 	bl	ftl_malloc
23900
-	mov	r1, #0
23901
24434
 	mov	r2, #256000
24435
+	mov	r1, #0
23902
24436
 	str	r0, [r4, #2024]
23903
24437
 	bl	ftl_memset
23904
24438
 	str	r5, [r4, #2028]
23905
-.L3962:
24439
+.L3867:
23906
24440
 	str	r6, [sp]
23907
24441
 	mov	r3, r5
23908
-	ldr	r0, .L3984+8
23909
-	ldr	r1, [r4, #2024]
23910
24442
 	ldr	r2, [r8]
24443
+	ldr	r1, [r4, #2024]
24444
+	ldr	r0, .L3890+8
23911
24445
 	bl	printk
23912
24446
 	ldrb	r3, [r4, #2020]	@ zero_extendqisi2
23913
-	ldr	r9, .L3984
23914
24447
 	cmp	r3, #0
23915
-	beq	.L3961
24448
+	beq	.L3866
23916
24449
 	sub	r0, r5, #64
23917
-	ldr	r7, [r9, #2024]
24450
+	ldr	r7, [r4, #2024]
23918
24451
 	cmp	r0, #500
23919
-	bcs	.L3964
24452
+	bcs	.L3869
23920
24453
 	rsb	r2, r5, #564
23921
-	add	r0, r7, r0, asl #9
23922
-	cmp	r2, r6
23923
24454
 	mov	r1, r8
23924
-	movcs	r2, r6
23925
-	mov	r2, r2, asl #9
24455
+	cmp	r6, r2
24456
+	add	r0, r7, r0, lsl #9
24457
+	movcc	r2, r6
24458
+	lsl	r2, r2, #9
23926
24459
 	bl	ftl_memcpy
23927
-	b	.L3965
23928
-.L3964:
23929
-	cmp	r5, #564
23930
-	bcs	.L3973
23931
-.L3965:
24460
+.L3870:
23932
24461
 	ldr	r3, [r4, #2028]
23933
-	cmp	r3, r5
23934
-	beq	.L3971
23935
-	ldr	r2, .L3984
24462
+	cmp	r5, r3
24463
+	beq	.L3879
23936
24464
 	mov	r3, #0
23937
24465
 	cmp	r7, r3
24466
+	strb	r3, [r4, #2020]
23938
24467
 	mov	r8, r3
23939
-	strb	r3, [r2, #2020]
23940
-	beq	.L3972
24468
+	beq	.L3880
23941
24469
 	mov	r0, r7
23942
24470
 	bl	ftl_free
23943
-.L3972:
24471
+.L3880:
23944
24472
 	str	r8, [r4, #2024]
23945
-.L3971:
23946
-	add	r5, r5, r6
23947
-	str	r5, [r4, #2028]
23948
-	b	.L3961
23949
-.L3973:
23950
-	ldr	r3, .L3984+12
23951
-	ldr	r0, [r9, #2028]
23952
-	ldr	r3, [r3, #44]
24473
+	b	.L3879
24474
+.L3869:
24475
+	cmp	r5, #564
24476
+	bcc	.L3870
24477
+	ldr	r3, .L3890+12
24478
+	ldr	r0, [r4, #2028]
24479
+	ldr	r3, [r3, #48]
23953
24480
 	sub	r0, r0, #64
23954
24481
 	cmp	r0, #500
23955
24482
 	ldrb	r3, [r3, #9]	@ zero_extendqisi2
23956
24483
 	movcs	r0, #500
23957
24484
 	cmp	r3, #4
23958
-	beq	.L3974
24485
+	beq	.L3871
23959
24486
 	mov	r3, #2
23960
24487
 	str	r3, [sp, #8]
23961
24488
 	mov	r3, #3
..
..
@@ -23966,49 +24493,52 @@
23966
24493
 	str	r3, [sp, #20]
23967
24494
 	mov	r3, #6
23968
24495
 	str	r3, [sp, #24]
23969
-	b	.L3967
23970
-.L3974:
23971
-	mov	r3, #0
23972
-.L3966:
23973
-	cmp	r0, #256
23974
-	add	r1, sp, #8
23975
-	mov	r2, r3, asl #1
23976
-	movls	r2, r3
23977
-	str	r2, [r1, r3, asl #2]
23978
-	add	r3, r3, #1
23979
-	cmp	r3, #5
23980
-	bne	.L3966
23981
-.L3967:
24496
+.L3872:
23982
24497
 	movw	r3, #63872
23983
-.L3970:
23984
-	ldr	r2, [r7, r3, asl #2]
24498
+.L3878:
24499
+	ldr	r2, [r7, r3, lsl #2]
23985
24500
 	cmp	r2, #0
23986
-	addne	r3, r3, #128
23987
-	movne	r0, r3, asl #2
23988
-	bne	.L3969
23989
-.L3968:
23990
-	sub	r3, r3, #1
23991
-	cmp	r3, #4096
23992
-	bne	.L3970
23993
-	mov	r0, r0, asl #9
23994
-.L3969:
24501
+	beq	.L3876
24502
+	add	r3, r3, #128
24503
+	lsl	r0, r3, #2
24504
+.L3877:
23995
24505
 	mov	r1, r7
23996
24506
 	add	r2, sp, #8
24507
+	mov	r7, #0
23997
24508
 	bl	write_idblock
23998
24509
 	ldr	r0, [r4, #2024]
23999
-	mov	r7, #0
24000
24510
 	strb	r7, [r4, #2020]
24001
24511
 	bl	ftl_free
24002
24512
 	str	r7, [r4, #2024]
24003
-	b	.L3971
24004
-.L3961:
24005
-	add	sp, sp, #52
24513
+.L3879:
24514
+	add	r5, r5, r6
24515
+	str	r5, [r4, #2028]
24516
+.L3866:
24517
+	add	sp, sp, #48
24006
24518
 	@ sp needed
24007
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, pc}
24008
-.L3985:
24519
+	pop	{r4, r5, r6, r7, r8, pc}
24520
+.L3871:
24521
+	mov	r2, #0
24522
+	add	r3, sp, #8
24523
+.L3875:
24524
+	cmp	r0, #256
24525
+	lslhi	r1, r2, #1
24526
+	strls	r2, [r3, r2, lsl #2]
24527
+	strhi	r1, [r3, r2, lsl #2]
24528
+	add	r2, r2, #1
24529
+	cmp	r2, #5
24530
+	bne	.L3875
24531
+	b	.L3872
24532
+.L3876:
24533
+	sub	r3, r3, #1
24534
+	cmp	r3, #4096
24535
+	bne	.L3878
24536
+	lsl	r0, r0, #9
24537
+	b	.L3877
24538
+.L3891:
24009
24539
 	.align	2
24010
-.L3984:
24011
-	.word	.LANCHOR4
24540
+.L3890:
24541
+	.word	.LANCHOR2
24012
24542
 	.word	-52655045
24013
24543
 	.word	.LC185
24014
24544
 	.word	.LANCHOR0
..
..
@@ -24016,281 +24546,381 @@
24016
24546
 	.size	write_loader_lba, .-write_loader_lba
24017
24547
 	.align	2
24018
24548
 	.global	FtlWrite
24549
+	.syntax unified
24550
+	.arm
24551
+	.fpu softvfp
24019
24552
 	.type	FtlWrite, %function
24020
24553
 FtlWrite:
24021
24554
 	.fnstart
24022
24555
 	@ args = 0, pretend = 0, frame = 0
24023
24556
 	@ frame_needed = 0, uses_anonymous_args = 0
24024
-	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
24557
+	push	{r4, r5, r6, r7, r8, lr}
24025
24558
 	.save {r4, r5, r6, r7, r8, lr}
24026
24559
 	mov	r6, r2
24027
24560
 	sub	r2, r1, #64
24028
24561
 	mov	r4, r1
24029
24562
 	cmp	r2, #1984
24030
-	mov	r5, r3
24031
-	mov	r7, r0
24563
+	mov	r7, r3
24032
24564
 	movcs	r2, #0
24033
24565
 	movcc	r2, #1
24034
24566
 	cmp	r0, #0
24567
+	mov	r5, r0
24035
24568
 	movne	r2, #0
24036
24569
 	cmp	r2, #0
24037
-	beq	.L3987
24038
-	mov	r0, r1
24570
+	beq	.L3893
24039
24571
 	mov	r2, r3
24040
24572
 	mov	r1, r6
24573
+	mov	r0, r4
24041
24574
 	bl	write_loader_lba
24042
-.L3987:
24043
-	mov	r0, r7
24044
-	mov	r1, r4
24575
+.L3893:
24576
+	mov	r3, r7
24045
24577
 	mov	r2, r6
24046
-	mov	r3, r5
24047
-	ldmfd	sp!, {r4, r5, r6, r7, r8, lr}
24578
+	mov	r1, r4
24579
+	mov	r0, r5
24580
+	pop	{r4, r5, r6, r7, r8, lr}
24048
24581
 	b	ftl_write
24049
24582
 	.fnend
24050
24583
 	.size	FtlWrite, .-FtlWrite
24051
24584
 	.align	2
24052
24585
 	.global	rknand_sys_storage_ioctl
24586
+	.syntax unified
24587
+	.arm
24588
+	.fpu softvfp
24053
24589
 	.type	rknand_sys_storage_ioctl, %function
24054
24590
 rknand_sys_storage_ioctl:
24055
24591
 	.fnstart
24056
24592
 	@ args = 0, pretend = 0, frame = 520
24057
24593
 	@ frame_needed = 0, uses_anonymous_args = 0
24058
-	ldr	r3, .L4049
24059
-	stmfd	sp!, {r4, r5, r6, r7, lr}
24594
+	ldr	r3, .L3955
24595
+	push	{r4, r5, r6, r7, lr}
24060
24596
 	.save {r4, r5, r6, r7, lr}
24061
-	cmp	r1, r3
24597
+	mov	r4, r1
24062
24598
 	.pad #524
24063
24599
 	sub	sp, sp, #524
24064
-	mov	r4, r1
24065
24600
 	mov	r5, r2
24066
-	beq	.L3994
24067
-	bhi	.L3995
24601
+	cmp	r1, r3
24602
+	beq	.L3900
24603
+	bhi	.L3901
24068
24604
 	sub	r3, r3, #2080
24069
24605
 	sub	r3, r3, #6
24070
24606
 	cmp	r1, r3
24071
-	beq	.L3996
24072
-	bhi	.L3997
24607
+	beq	.L3902
24608
+	bhi	.L3903
24073
24609
 	sub	r3, r3, #238
24074
24610
 	cmp	r1, r3
24075
-	beq	.L3998
24611
+	beq	.L3904
24076
24612
 	add	r3, r3, #237
24077
24613
 	cmp	r1, r3
24078
-	beq	.L3999
24079
-	b	.L4029
24080
-.L3997:
24081
-	ldr	r3, .L4049+4
24614
+	beq	.L3905
24615
+.L3935:
24616
+	mvn	r4, #21
24617
+	b	.L3898
24618
+.L3903:
24619
+	ldr	r3, .L3955+4
24082
24620
 	cmp	r1, r3
24083
-	beq	.L4000
24621
+	beq	.L3906
24084
24622
 	add	r3, r3, #1
24085
24623
 	cmp	r1, r3
24086
-	beq	.L4001
24624
+	beq	.L3907
24087
24625
 	sub	r3, r3, #124
24088
24626
 	cmp	r1, r3
24089
-	bne	.L4029
24090
-	b	.L4047
24091
-.L3995:
24092
-	ldr	r3, .L4049+8
24093
-	cmp	r1, r3
24094
-	mov	r6, r3
24095
-	beq	.L4003
24096
-	bhi	.L4004
24097
-	sub	r3, r3, #2512
24098
-	sub	r3, r3, #14
24099
-	cmp	r1, r3
24100
-	beq	.L3994
24101
-	add	r3, r3, #10
24102
-	cmp	r1, r3
24103
-	beq	.L3994
24104
-	b	.L4029
24105
-.L4004:
24106
-	ldr	r3, .L4049+12
24107
-	cmp	r1, r3
24108
-	beq	.L4003
24109
-	bcc	.L4005
24110
-	add	r3, r3, #1
24111
-	cmp	r1, r3
24112
-	beq	.L4005
24113
-	b	.L4029
24114
-.L3999:
24115
-	ldr	r0, .L4049+16
24627
+	bne	.L3935
24628
+	ldr	r0, .L3955+8
24116
24629
 	bl	printk
24117
-	mov	r1, r5
24118
24630
 	mov	r2, #520
24631
+	mov	r1, r5
24119
24632
 	mov	r0, sp
24120
24633
 	bl	rk_copy_from_user
24121
24634
 	cmp	r0, #0
24122
-	beq	.L4006
24123
-.L4012:
24124
-	ldr	r0, .L4049+20
24125
-	bl	printk
24126
-	b	.L4044
24127
-.L4006:
24635
+	bne	.L3918
24128
24636
 	ldr	r2, [sp]
24129
-	ldr	r3, .L4049+24
24637
+	ldr	r3, .L3955+12
24130
24638
 	cmp	r2, r3
24131
-	beq	.L4007
24132
-.L4009:
24639
+	bne	.L3915
24640
+	ldr	r2, [sp, #4]
24641
+	cmp	r2, #512
24642
+	ldrls	r1, .L3955+16
24643
+	bhi	.L3915
24644
+.L3953:
24645
+	add	r0, sp, #8
24646
+	bl	memcpy
24647
+	b	.L3947
24648
+.L3901:
24649
+	ldr	r3, .L3955+20
24650
+	cmp	r1, r3
24651
+	mov	r6, r3
24652
+	beq	.L3909
24653
+	bhi	.L3910
24654
+	sub	r3, r3, #2512
24655
+	sub	r3, r3, #14
24656
+	cmp	r1, r3
24657
+	beq	.L3900
24658
+	add	r3, r3, #10
24659
+	cmp	r1, r3
24660
+	bne	.L3935
24661
+.L3900:
24662
+	ldr	r3, .L3955+24
24663
+	cmp	r4, r3
24664
+	mov	r7, r3
24665
+	ldreq	r0, .L3955+28
24666
+	beq	.L3949
24667
+	ldr	r3, .L3955+32
24668
+	cmp	r4, r3
24669
+	ldreq	r0, .L3955+36
24670
+	ldrne	r0, .L3955+40
24671
+.L3949:
24672
+	bl	printk
24673
+	mov	r2, #520
24674
+	mov	r1, r5
24675
+	mov	r0, sp
24676
+	bl	rk_copy_from_user
24677
+	cmp	r0, #0
24678
+	bne	.L3918
24679
+	ldr	r2, [sp]
24680
+	ldr	r3, .L3955+44
24681
+	cmp	r2, r3
24682
+	bne	.L3952
24683
+	ldr	r3, .L3955+32
24684
+	ldr	r6, .L3955+48
24685
+	cmp	r4, r3
24686
+	bne	.L3928
24687
+	ldr	r3, [r6, #2032]
24688
+	mov	r2, #16
24689
+	mov	r1, sp
24690
+	mov	r0, r5
24691
+	ldr	r3, [r3, #20]
24692
+	str	r3, [sp, #4]
24693
+	strb	r3, [sp, #8]
24694
+	bl	rk_copy_to_user
24695
+	cmp	r0, #0
24696
+	bne	.L3952
24697
+.L3919:
24698
+	mov	r4, #0
24699
+.L3898:
24700
+	mov	r0, r4
24701
+	add	sp, sp, #524
24702
+	@ sp needed
24703
+	pop	{r4, r5, r6, r7, pc}
24704
+.L3910:
24705
+	ldr	r3, .L3955+52
24706
+	cmp	r1, r3
24707
+	beq	.L3909
24708
+	bcc	.L3911
24709
+	add	r3, r3, #1
24710
+	cmp	r1, r3
24711
+	bne	.L3935
24712
+.L3911:
24713
+	ldr	r0, .L3955+56
24714
+	bl	printk
24715
+	mov	r2, #520
24716
+	mov	r1, r5
24717
+	mov	r0, sp
24718
+	bl	rk_copy_from_user
24719
+	cmp	r0, #0
24720
+	bne	.L3918
24721
+	ldr	r2, [sp]
24722
+	ldr	r3, .L3955+60
24723
+	cmp	r2, r3
24724
+	bne	.L3915
24725
+	ldr	r2, [sp, #4]
24726
+	cmp	r2, #504
24727
+	bhi	.L3915
24728
+	ldr	r3, .L3955+64
24729
+	mov	r1, sp
24730
+	add	r2, r2, #8
24731
+	cmp	r4, r3
24732
+	ldr	r4, .L3955+48
24733
+	bne	.L3934
24734
+	ldr	r0, [r4, #2564]
24735
+	bl	memcpy
24736
+	ldr	r1, [r4, #2564]
24737
+	mov	r0, #2
24738
+	b	.L3950
24739
+.L3905:
24740
+	ldr	r0, .L3955+68
24741
+	bl	printk
24742
+	mov	r2, #520
24743
+	mov	r1, r5
24744
+	mov	r0, sp
24745
+	bl	rk_copy_from_user
24746
+	cmp	r0, #0
24747
+	beq	.L3912
24748
+.L3918:
24749
+	ldr	r0, .L3955+72
24750
+	bl	printk
24751
+.L3952:
24752
+	mvn	r4, #13
24753
+	b	.L3898
24754
+.L3912:
24755
+	ldr	r2, [sp]
24756
+	ldr	r3, .L3955+76
24757
+	cmp	r2, r3
24758
+	beq	.L3913
24759
+.L3915:
24133
24760
 	mvn	r4, #0
24134
-	b	.L4008
24135
-.L4007:
24761
+.L3914:
24762
+	mov	r1, r4
24763
+	ldr	r0, .L3955+80
24764
+	bl	printk
24765
+	b	.L3898
24766
+.L3913:
24136
24767
 	ldr	r3, [sp, #4]
24137
24768
 	cmp	r3, #512
24138
-	bhi	.L4009
24139
-	ldr	r4, .L4049+28
24769
+	bhi	.L3915
24770
+	ldr	r4, .L3955+48
24140
24771
 	mov	r2, #512
24141
24772
 	mov	r0, sp
24142
24773
 	ldr	r1, [r4, #2032]
24143
24774
 	bl	memcpy
24144
24775
 	ldr	r2, [r4, #2036]
24145
-	ldr	r3, .L4049+32
24776
+	ldr	r3, .L3955+84
24146
24777
 	cmp	r2, r3
24147
-	beq	.L4010
24778
+	beq	.L3916
24148
24779
 	mov	r1, #0
24149
-	add	r0, sp, #64
24150
24780
 	mov	r2, #128
24781
+	add	r0, sp, #64
24151
24782
 	str	r1, [sp, #8]
24152
24783
 	str	r1, [sp, #12]
24153
24784
 	bl	memset
24154
-.L4010:
24155
-	mov	r1, #0
24156
-	add	r0, sp, #256
24785
+.L3916:
24157
24786
 	mov	r2, #256
24787
+	mov	r1, #0
24788
+	add	r0, sp, r2
24158
24789
 	str	r1, [sp, #16]
24159
24790
 	bl	memset
24160
-.L4039:
24161
-	mov	r0, r5
24162
-	mov	r1, sp
24791
+.L3947:
24163
24792
 	mov	r2, #520
24793
+	mov	r1, sp
24794
+	mov	r0, r5
24164
24795
 	bl	rk_copy_to_user
24165
24796
 	cmp	r0, #0
24166
-	bne	.L4044
24167
-	b	.L4043
24168
-.L3996:
24169
-	ldr	r0, .L4049+36
24797
+	bne	.L3952
24798
+.L3951:
24799
+	mov	r4, #0
24800
+	b	.L3914
24801
+.L3902:
24802
+	ldr	r0, .L3955+88
24170
24803
 	bl	printk
24171
-	mov	r1, r5
24172
24804
 	mov	r2, #520
24805
+	mov	r1, r5
24173
24806
 	mov	r0, sp
24174
24807
 	bl	rk_copy_from_user
24175
24808
 	cmp	r0, #0
24176
-	bne	.L4012
24809
+	bne	.L3918
24177
24810
 	ldr	r2, [sp]
24178
-	ldr	r3, .L4049+24
24811
+	ldr	r3, .L3955+76
24179
24812
 	cmp	r2, r3
24180
-	bne	.L4009
24813
+	bne	.L3915
24181
24814
 	ldr	r3, [sp, #4]
24182
24815
 	cmp	r3, #512
24183
-	bhi	.L4009
24184
-	ldr	r2, .L4049+28
24185
-	ldr	r3, .L4049+32
24816
+	bhi	.L3915
24817
+	ldr	r2, .L3955+48
24818
+	ldr	r3, .L3955+84
24186
24819
 	ldr	r1, [r2, #2036]
24187
24820
 	cmp	r1, r3
24188
-	mvnne	r0, #1
24189
-	bne	.L3993
24821
+	mvnne	r4, #1
24822
+	bne	.L3898
24190
24823
 	ldr	r3, [sp, #12]
24191
24824
 	sub	r1, r3, #1
24192
24825
 	cmp	r1, #127
24193
-	mvnhi	r0, #2
24194
-	bhi	.L3993
24826
+	mvnhi	r4, #2
24827
+	bhi	.L3898
24195
24828
 	ldr	r4, [r2, #2032]
24196
24829
 	add	r1, sp, #64
24197
-	add	r0, r4, #64
24198
24830
 	str	r3, [r4, #12]
24831
+	add	r0, r4, #64
24199
24832
 	ldr	r2, [sp, #12]
24200
24833
 	bl	memcpy
24201
-	mov	r0, #1
24202
24834
 	mov	r1, r4
24203
-	b	.L4042
24204
-.L4001:
24205
-	ldr	r0, .L4049+40
24835
+	mov	r0, #1
24836
+.L3950:
24837
+	bl	StorageSysDataStore
24838
+	mov	r4, r0
24839
+	b	.L3914
24840
+.L3907:
24841
+	ldr	r0, .L3955+92
24206
24842
 	bl	printk
24207
-	mov	r1, r5
24208
24843
 	mov	r2, #520
24844
+	mov	r1, r5
24209
24845
 	mov	r0, sp
24210
24846
 	bl	rk_copy_from_user
24211
24847
 	cmp	r0, #0
24212
-	bne	.L4012
24848
+	bne	.L3918
24213
24849
 	ldr	r2, [sp]
24214
-	ldr	r3, .L4049+44
24850
+	ldr	r3, .L3955+96
24215
24851
 	cmp	r2, r3
24216
-	bne	.L4009
24852
+	bne	.L3915
24217
24853
 	ldr	r3, [sp, #4]
24218
24854
 	cmp	r3, #512
24219
-	bhi	.L4009
24220
-	ldr	r5, .L4049+28
24855
+	bhi	.L3915
24856
+	ldr	r5, .L3955+48
24221
24857
 	ldr	r3, [r5, #2040]
24222
24858
 	cmp	r3, #0
24223
-	bne	.L4013
24224
-.L4016:
24225
-	mov	r0, #0
24226
-	b	.L3993
24227
-.L4013:
24859
+	beq	.L3919
24228
24860
 	ldr	r3, [r5, #2044]
24229
-	ldr	r2, .L4049+48
24861
+	ldr	r2, .L3955+100
24230
24862
 	ldr	r1, [r3]
24231
24863
 	cmp	r1, r2
24232
-	beq	.L4014
24864
+	beq	.L3920
24233
24865
 	str	r2, [r3]
24234
24866
 	mov	r2, #504
24235
-	ldr	r3, .L4049+28
24236
-	ldr	r3, [r3, #2044]
24867
+	ldr	r3, [r5, #2044]
24237
24868
 	str	r2, [r3, #4]
24238
24869
 	mov	r2, #0
24239
24870
 	str	r2, [r3, #8]
24240
24871
 	str	r2, [r3, #12]
24241
-.L4014:
24872
+.L3920:
24242
24873
 	ldr	r1, [r5, #2044]
24243
24874
 	mov	r4, #0
24244
24875
 	mov	r0, r4
24245
24876
 	str	r4, [r1, #16]
24246
24877
 	bl	StorageSysDataStore
24247
24878
 	ldr	r3, [r5, #2032]
24248
-	ldr	r2, .L4049+24
24879
+	ldr	r2, .L3955+76
24249
24880
 	ldr	r1, [r3]
24250
24881
 	cmp	r1, r2
24251
24882
 	strne	r2, [r3]
24252
-	ldr	r6, [r5, #2032]
24253
-	ldrne	r3, .L4049+28
24254
24883
 	movne	r2, #504
24255
-	add	r0, r6, #64
24256
-	ldrne	r3, [r3, #2032]
24257
-	stmneib	r3, {r2, r4}
24884
+	ldrne	r3, [r5, #2032]
24885
+	ldr	r6, [r5, #2032]
24886
+	stmibne	r3, {r2, r4}
24258
24887
 	mov	r4, #0
24259
-	mov	r1, r4
24260
24888
 	mov	r2, #128
24889
+	mov	r1, r4
24261
24890
 	str	r4, [r6, #12]
24891
+	add	r0, r6, #64
24262
24892
 	bl	memset
24263
-	mov	r0, #1
24264
24893
 	mov	r1, r6
24894
+	mov	r0, #1
24265
24895
 	bl	StorageSysDataStore
24266
24896
 	str	r4, [r5, #2040]
24267
24897
 	str	r4, [r5, #2036]
24268
-	b	.L4008
24269
-.L4000:
24270
-	ldr	r0, .L4049+52
24898
+	b	.L3914
24899
+.L3906:
24900
+	ldr	r0, .L3955+104
24271
24901
 	bl	printk
24272
-	mov	r1, r5
24273
24902
 	mov	r2, #520
24903
+	mov	r1, r5
24274
24904
 	mov	r0, sp
24275
24905
 	bl	rk_copy_from_user
24276
24906
 	cmp	r0, #0
24277
-	bne	.L4012
24907
+	bne	.L3918
24278
24908
 	ldr	r2, [sp]
24279
-	ldr	r3, .L4049+56
24909
+	ldr	r3, .L3955+108
24280
24910
 	cmp	r2, r3
24281
-	bne	.L4009
24911
+	bne	.L3915
24282
24912
 	ldr	r3, [sp, #4]
24283
24913
 	cmp	r3, #512
24284
-	bhi	.L4009
24285
-	ldr	r5, .L4049+28
24914
+	bhi	.L3915
24915
+	ldr	r5, .L3955+48
24286
24916
 	ldr	r3, [r5, #2040]
24287
24917
 	cmp	r3, #1
24288
-	beq	.L4016
24918
+	beq	.L3919
24289
24919
 	ldr	r2, [r5, #2044]
24290
-	ldr	r3, .L4049+48
24920
+	ldr	r3, .L3955+100
24291
24921
 	ldr	r1, [r2]
24292
24922
 	cmp	r1, r3
24293
-	beq	.L4017
24923
+	beq	.L3922
24294
24924
 	str	r3, [r2]
24295
24925
 	mov	r2, #504
24296
24926
 	ldr	r3, [r5, #2044]
..
..
@@ -24298,7 +24928,7 @@
24298
24928
 	mov	r2, #0
24299
24929
 	str	r2, [r3, #8]
24300
24930
 	str	r2, [r3, #12]
24301
-.L4017:
24931
+.L3922:
24302
24932
 	ldr	r1, [r5, #2044]
24303
24933
 	mov	r3, #1
24304
24934
 	mov	r0, #0
..
..
@@ -24306,209 +24936,114 @@
24306
24936
 	str	r3, [r1, #16]
24307
24937
 	bl	StorageSysDataStore
24308
24938
 	ldr	r3, [r5, #2032]
24309
-	ldr	r2, .L4049+24
24939
+	ldr	r2, .L3955+76
24310
24940
 	ldr	r1, [r3]
24311
24941
 	cmp	r1, r2
24312
24942
 	strne	r2, [r3]
24313
-	ldr	r6, [r5, #2032]
24314
-	ldrne	r3, .L4049+28
24315
24943
 	movne	r1, #504
24944
+	ldrne	r3, [r5, #2032]
24316
24945
 	movne	r2, #0
24317
-	add	r0, r6, #64
24318
-	ldrne	r3, [r3, #2032]
24319
-	stmneib	r3, {r1, r2}
24320
-	mov	r1, r4
24946
+	ldr	r6, [r5, #2032]
24947
+	stmibne	r3, {r1, r2}
24321
24948
 	mov	r2, #128
24949
+	mov	r1, r4
24322
24950
 	str	r4, [r6, #12]
24951
+	add	r0, r6, #64
24323
24952
 	bl	memset
24324
-	mov	r0, #1
24325
24953
 	mov	r1, r6
24954
+	mov	r0, #1
24326
24955
 	bl	StorageSysDataStore
24327
24956
 	mov	r3, #1
24328
24957
 	str	r3, [r5, #2040]
24329
-	b	.L4008
24330
-.L4047:
24331
-	ldr	r0, .L4049+60
24332
-	bl	printk
24333
-	mov	r1, r5
24334
-	mov	r2, #520
24335
-	mov	r0, sp
24336
-	bl	rk_copy_from_user
24337
-	cmp	r0, #0
24338
-	bne	.L4012
24339
-	ldr	r2, [sp]
24340
-	ldr	r3, .L4049+64
24341
-	cmp	r2, r3
24342
-	bne	.L4009
24343
-	ldr	r2, [sp, #4]
24344
-	cmp	r2, #512
24345
-	addls	r0, sp, #8
24346
-	ldrls	r1, .L4049+68
24347
-	bls	.L4045
24348
-	b	.L4009
24349
-.L3994:
24350
-	ldr	r0, .L4049+72
24351
-	cmp	r4, r0
24352
-	mov	r7, r0
24353
-	ldreq	r0, .L4049+76
24354
-	beq	.L4041
24355
-	ldr	r3, .L4049+80
24356
-	cmp	r4, r3
24357
-	ldreq	r0, .L4049+84
24358
-	ldrne	r0, .L4049+88
24359
-.L4041:
24360
-	bl	printk
24361
-	mov	r1, r5
24362
-	mov	r2, #520
24363
-	mov	r0, sp
24364
-	bl	rk_copy_from_user
24365
-	cmp	r0, #0
24366
-	bne	.L4012
24367
-	ldr	r2, [sp]
24368
-	ldr	r3, .L4049+92
24369
-	cmp	r2, r3
24370
-	bne	.L4044
24371
-	ldr	r3, .L4049+80
24372
-	ldr	r6, .L4049+28
24373
-	cmp	r4, r3
24374
-	bne	.L4023
24375
-	ldr	r3, [r6, #2032]
24376
-	mov	r0, r5
24377
-	mov	r1, sp
24378
-	mov	r2, #16
24379
-	ldr	r3, [r3, #20]
24380
-	str	r3, [sp, #4]
24381
-	strb	r3, [sp, #8]
24382
-	bl	rk_copy_to_user
24383
-	cmp	r0, #0
24384
-	beq	.L3993
24385
-	b	.L4044
24386
-.L4023:
24958
+	b	.L3914
24959
+.L3928:
24387
24960
 	ldr	r3, [r6, #2560]
24388
24961
 	cmp	r3, #10
24389
-	bhi	.L4044
24390
-	ldr	r1, [r6, #2032]
24391
-	ldr	r2, [sp, #4]
24392
-	ldr	r3, [r1, #24]
24393
-	cmp	r3, r2
24962
+	bhi	.L3952
24963
+	ldr	r2, [r6, #2032]
24964
+	ldr	r1, [sp, #4]
24965
+	ldr	r3, [r2, #24]
24966
+	cmp	r3, r1
24394
24967
 	cmpne	r3, #0
24395
24968
 	movne	r3, #1
24396
24969
 	moveq	r3, #0
24397
-	beq	.L4024
24398
-	ldr	r0, .L4049+96
24399
-	mov	r1, r2
24970
+	beq	.L3929
24971
+	ldr	r0, .L3955+112
24400
24972
 	bl	printk
24401
24973
 	ldr	r3, [r6, #2560]
24402
24974
 	add	r3, r3, #1
24403
24975
 	str	r3, [r6, #2560]
24404
-.L4044:
24405
-	mvn	r0, #13
24406
-	b	.L3993
24407
-.L4024:
24976
+	b	.L3952
24977
+.L3929:
24408
24978
 	cmp	r4, r7
24409
24979
 	str	r3, [r6, #2560]
24410
-	mov	r0, #1
24411
-	moveq	r2, r3
24412
24980
 	movne	r3, #1
24413
-	moveq	r3, r2
24414
-	str	r2, [r1, #24]
24415
-	str	r3, [r1, #20]
24981
+	strne	r1, [r2, #24]
24982
+	streq	r3, [r2, #20]
24983
+	mov	r1, r2
24984
+	streq	r3, [r2, #24]
24985
+	mov	r0, #1
24986
+	strne	r3, [r2, #20]
24416
24987
 	bl	StorageSysDataStore
24417
24988
 	cmn	r0, #1
24418
-	bne	.L4043
24419
-	b	.L4048
24420
-.L4003:
24421
-	ldr	r0, .L4049+100
24989
+	bne	.L3951
24990
+	mvn	r4, #1
24991
+	b	.L3914
24992
+.L3909:
24993
+	ldr	r0, .L3955+116
24422
24994
 	bl	printk
24423
-	mov	r1, r5
24424
24995
 	mov	r2, #520
24996
+	mov	r1, r5
24425
24997
 	mov	r0, sp
24426
24998
 	bl	rk_copy_from_user
24427
24999
 	cmp	r0, #0
24428
-	bne	.L4012
25000
+	bne	.L3918
24429
25001
 	ldr	r2, [sp]
24430
-	ldr	r3, .L4049+104
25002
+	ldr	r3, .L3955+60
24431
25003
 	cmp	r2, r3
24432
-	bne	.L4009
25004
+	bne	.L3915
24433
25005
 	ldr	r2, [sp, #4]
24434
25006
 	cmp	r2, #504
24435
-	bhi	.L4009
24436
-	ldr	r3, .L4049+28
25007
+	bhi	.L3915
25008
+	ldr	r3, .L3955+48
24437
25009
 	cmp	r4, r6
24438
-	add	r0, sp, #8
24439
25010
 	ldreq	r1, [r3, #2564]
24440
25011
 	ldrne	r1, [r3, #2568]
24441
25012
 	add	r1, r1, #8
24442
-.L4045:
24443
-	bl	memcpy
24444
-	b	.L4039
24445
-.L4005:
24446
-	ldr	r0, .L4049+108
24447
-	bl	printk
24448
-	mov	r1, r5
24449
-	mov	r2, #520
24450
-	mov	r0, sp
24451
-	bl	rk_copy_from_user
24452
-	cmp	r0, #0
24453
-	bne	.L4012
24454
-	ldr	r2, [sp]
24455
-	ldr	r3, .L4049+104
24456
-	cmp	r2, r3
24457
-	bne	.L4009
24458
-	ldr	r2, [sp, #4]
24459
-	cmp	r2, #504
24460
-	bhi	.L4009
24461
-	ldr	r3, .L4049+112
24462
-	add	r2, r2, #8
24463
-	cmp	r4, r3
24464
-	ldr	r4, .L4049+28
24465
-	bne	.L4028
24466
-	mov	r1, sp
24467
-	ldr	r0, [r4, #2564]
24468
-	bl	memcpy
24469
-	mov	r0, #2
24470
-	ldr	r1, [r4, #2564]
24471
-	b	.L4042
24472
-.L4028:
24473
-	mov	r1, sp
25013
+	b	.L3953
25014
+.L3934:
24474
25015
 	ldr	r0, [r4, #2568]
24475
25016
 	bl	memcpy
24476
25017
 	ldr	r1, [r4, #2568]
24477
25018
 	mov	r0, #3
24478
-.L4042:
24479
-	bl	StorageSysDataStore
24480
-	mov	r4, r0
24481
-	b	.L4008
24482
-.L3998:
25019
+	b	.L3950
25020
+.L3904:
24483
25021
 	bl	rknand_dev_flush
24484
-.L4043:
24485
-	mov	r4, #0
24486
-	b	.L4008
24487
-.L4048:
24488
-	mvn	r4, #1
24489
-.L4008:
24490
-	ldr	r0, .L4049+116
24491
-	mov	r1, r4
24492
-	bl	printk
24493
-	mov	r0, r4
24494
-	b	.L3993
24495
-.L4029:
24496
-	mvn	r0, #21
24497
-.L3993:
24498
-	add	sp, sp, #524
24499
-	@ sp needed
24500
-	ldmfd	sp!, {r4, r5, r6, r7, pc}
24501
-.L4050:
25022
+	b	.L3951
25023
+.L3956:
24502
25024
 	.align	2
24503
-.L4049:
25025
+.L3955:
24504
25026
 	.word	1074031656
24505
25027
 	.word	1074029694
25028
+	.word	.LC191
25029
+	.word	1094995539
25030
+	.word	.LANCHOR2+2048
24506
25031
 	.word	1074034192
25032
+	.word	1074031666
25033
+	.word	.LC192
25034
+	.word	1074031676
25035
+	.word	.LC193
25036
+	.word	.LC194
25037
+	.word	1280262987
25038
+	.word	.LANCHOR2
24507
25039
 	.word	1074034194
25040
+	.word	.LC197
25041
+	.word	1145980246
25042
+	.word	1074034193
24508
25043
 	.word	.LC186
24509
25044
 	.word	.LC187
24510
25045
 	.word	1263358532
24511
-	.word	.LANCHOR4
25046
+	.word	.LC198
24512
25047
 	.word	-1067903959
24513
25048
 	.word	.LC188
24514
25049
 	.word	.LC189
..
..
@@ -24516,46 +25051,36 @@
24516
25051
 	.word	1146313043
24517
25052
 	.word	.LC190
24518
25053
 	.word	1112755781
24519
-	.word	.LC191
24520
-	.word	1094995539
24521
-	.word	.LANCHOR4+2048
24522
-	.word	1074031666
24523
-	.word	.LC192
24524
-	.word	1074031676
24525
-	.word	.LC193
24526
-	.word	.LC194
24527
-	.word	1280262987
24528
25054
 	.word	.LC195
24529
25055
 	.word	.LC196
24530
-	.word	1145980246
24531
-	.word	.LC197
24532
-	.word	1074034193
24533
-	.word	.LC198
24534
25056
 	.fnend
24535
25057
 	.size	rknand_sys_storage_ioctl, .-rknand_sys_storage_ioctl
24536
25058
 	.align	2
24537
25059
 	.global	rk_ftl_storage_sys_init
25060
+	.syntax unified
25061
+	.arm
25062
+	.fpu softvfp
24538
25063
 	.type	rk_ftl_storage_sys_init, %function
24539
25064
 rk_ftl_storage_sys_init:
24540
25065
 	.fnstart
24541
25066
 	@ args = 0, pretend = 0, frame = 0
24542
25067
 	@ frame_needed = 0, uses_anonymous_args = 0
24543
-	stmfd	sp!, {r3, r4, r5, r6, r7, lr}
24544
-	.save {r3, r4, r5, r6, r7, lr}
24545
-	mov	r2, #512
24546
-	ldr	r4, .L4061
25068
+	push	{r4, r5, r6, r7, r8, lr}
25069
+	.save {r4, r5, r6, r7, r8, lr}
24547
25070
 	mvn	r3, #0
25071
+	ldr	r4, .L3967
24548
25072
 	mov	r5, #0
24549
-	add	r0, r4, #2048
25073
+	mov	r2, #512
24550
25074
 	ldr	r1, [r4, #2004]
25075
+	add	r0, r4, #2048
24551
25076
 	str	r3, [r4, #2028]
25077
+	strb	r5, [r4, #2020]
24552
25078
 	add	r3, r1, #512
24553
-	str	r3, [r4, #2032]
24554
25079
 	str	r1, [r4, #2044]
25080
+	str	r3, [r4, #2032]
24555
25081
 	add	r3, r1, #1024
24556
25082
 	add	r1, r1, #1536
24557
25083
 	str	r3, [r4, #2564]
24558
-	strb	r5, [r4, #2020]
24559
25084
 	str	r5, [r4, #2024]
24560
25085
 	str	r5, [r4, #2572]
24561
25086
 	str	r1, [r4, #2568]
..
..
@@ -24567,40 +25092,42 @@
24567
25092
 	ldr	r3, [r6, #16]
24568
25093
 	cmp	r7, r5
24569
25094
 	str	r3, [r4, #2040]
24570
-	beq	.L4052
24571
-	mov	r0, r6
25095
+	beq	.L3958
24572
25096
 	mov	r1, #508
25097
+	mov	r0, r6
24573
25098
 	bl	js_hash
24574
25099
 	cmp	r7, r0
24575
-	beq	.L4052
25100
+	beq	.L3958
24576
25101
 	str	r5, [r6, #16]
24577
-	ldr	r0, .L4061+4
25102
+	ldr	r0, .L3967+4
24578
25103
 	str	r5, [r4, #2040]
24579
25104
 	bl	printk
24580
-.L4052:
25105
+.L3958:
24581
25106
 	ldr	r3, [r4, #2040]
24582
25107
 	mov	r0, #2
24583
25108
 	ldr	r1, [r4, #2564]
24584
25109
 	cmp	r3, #0
24585
-	ldrne	r3, .L4061
24586
-	ldrne	r2, .L4061+8
24587
-	strne	r2, [r3, #2036]
25110
+	ldrne	r3, .L3967+8
25111
+	strne	r3, [r4, #2036]
24588
25112
 	bl	StorageSysDataLoad
24589
25113
 	ldr	r1, [r4, #2568]
24590
25114
 	mov	r0, #3
24591
25115
 	bl	StorageSysDataLoad
24592
-	ldmfd	sp!, {r3, r4, r5, r6, r7, lr}
25116
+	pop	{r4, r5, r6, r7, r8, lr}
24593
25117
 	b	rknand_sys_storage_init
24594
-.L4062:
25118
+.L3968:
24595
25119
 	.align	2
24596
-.L4061:
24597
-	.word	.LANCHOR4
25120
+.L3967:
25121
+	.word	.LANCHOR2
24598
25122
 	.word	.LC199
24599
25123
 	.word	-1067903959
24600
25124
 	.fnend
24601
25125
 	.size	rk_ftl_storage_sys_init, .-rk_ftl_storage_sys_init
24602
25126
 	.align	2
24603
25127
 	.global	StorageSysDataDeInit
25128
+	.syntax unified
25129
+	.arm
25130
+	.fpu softvfp
24604
25131
 	.type	StorageSysDataDeInit, %function
24605
25132
 StorageSysDataDeInit:
24606
25133
 	.fnstart
..
..
@@ -24613,269 +25140,269 @@
24613
25140
 	.size	StorageSysDataDeInit, .-StorageSysDataDeInit
24614
25141
 	.align	2
24615
25142
 	.global	rk_ftl_vendor_storage_init
25143
+	.syntax unified
25144
+	.arm
25145
+	.fpu softvfp
24616
25146
 	.type	rk_ftl_vendor_storage_init, %function
24617
25147
 rk_ftl_vendor_storage_init:
24618
25148
 	.fnstart
24619
25149
 	@ args = 0, pretend = 0, frame = 0
24620
25150
 	@ frame_needed = 0, uses_anonymous_args = 0
24621
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
25151
+	push	{r4, r5, r6, r7, r8, r9, r10, lr}
24622
25152
 	.save {r4, r5, r6, r7, r8, r9, r10, lr}
24623
25153
 	mov	r0, #65536
25154
+	ldr	r6, .L3980
24624
25155
 	bl	ftl_malloc
24625
-	ldr	r6, .L4075
24626
25156
 	cmp	r0, #0
24627
25157
 	str	r0, [r6, #2576]
24628
-	beq	.L4070
24629
-	ldr	r9, .L4075+4
24630
-	mov	r8, #0
24631
-	mov	r4, r8
24632
-	mov	r7, r8
24633
-	mov	r10, r6
24634
-.L4068:
24635
-	mov	r0, r7, asl #7
24636
-	mov	r1, #128
25158
+	beq	.L3976
25159
+	ldr	r10, .L3980+4
25160
+	mov	r7, #0
25161
+	ldr	r9, .L3980+8
25162
+	mov	r4, r7
25163
+	mov	r8, r7
25164
+.L3974:
24637
25165
 	ldr	r2, [r6, #2576]
25166
+	mov	r1, #128
25167
+	lsl	r0, r8, #7
24638
25168
 	bl	FlashBootVendorRead
24639
25169
 	cmp	r0, #0
24640
-	bne	.L4066
24641
-	ldr	r3, [r10, #2576]
24642
-	ldr	r0, .L4075+8
24643
-	add	r2, r3, #61440
24644
-	ldr	r1, [r3]
25170
+	bne	.L3972
25171
+	ldr	r1, [r6, #2576]
25172
+	mov	r0, r10
25173
+	add	r2, r1, #61440
25174
+	ldr	r3, [r1, #4]
24645
25175
 	ldr	r2, [r2, #4092]
24646
-	ldr	r3, [r3, #4]
25176
+	ldr	r1, [r1]
24647
25177
 	bl	printk
24648
-	ldr	r5, [r10, #2576]
25178
+	ldr	r5, [r6, #2576]
24649
25179
 	ldr	r3, [r5]
24650
25180
 	cmp	r3, r9
24651
-	bne	.L4067
25181
+	bne	.L3973
24652
25182
 	add	r2, r5, #61440
24653
25183
 	ldr	r3, [r5, #4]
24654
-	ldr	r1, [r2, #4092]
24655
-	cmp	r4, r3
24656
-	movcs	r2, #0
24657
-	movcc	r2, #1
24658
-	cmp	r1, r3
24659
-	movne	r2, #0
25184
+	ldr	r2, [r2, #4092]
25185
+	cmp	r3, r4
25186
+	sub	r2, r2, r3
25187
+	clz	r2, r2
25188
+	lsr	r2, r2, #5
25189
+	movls	r2, #0
24660
25190
 	cmp	r2, #0
24661
-	movne	r8, r7
25191
+	movne	r7, r8
24662
25192
 	movne	r4, r3
24663
-.L4067:
24664
-	cmp	r7, #1
24665
-	movne	r7, #1
24666
-	bne	.L4068
24667
-.L4074:
25193
+.L3973:
25194
+	add	r8, r8, #1
25195
+	cmp	r8, #2
25196
+	bne	.L3974
24668
25197
 	cmp	r4, #0
24669
-	beq	.L4069
24670
-	mov	r0, r8, asl #7
24671
-	mov	r1, #128
25198
+	beq	.L3975
24672
25199
 	mov	r2, r5
25200
+	mov	r1, #128
25201
+	lsl	r0, r7, #7
24673
25202
 	bl	FlashBootVendorRead
24674
25203
 	cmp	r0, #0
24675
-	bne	.L4066
24676
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
24677
-.L4069:
24678
-	mov	r0, r5
24679
-	mov	r1, r4
25204
+	bne	.L3972
25205
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
25206
+.L3975:
24680
25207
 	mov	r2, #65536
25208
+	mov	r1, r4
25209
+	mov	r0, r5
24681
25210
 	bl	memset
24682
-	ldr	r3, .L4075+4
24683
-	str	r7, [r5, #4]
25211
+	mov	r3, #1
25212
+	add	r2, r5, #61440
25213
+	str	r3, [r5, #4]
24684
25214
 	mov	r0, r4
24685
-	str	r3, [r5]
24686
-	add	r3, r5, #61440
24687
-	str	r7, [r3, #4092]
24688
-	ldr	r3, .L4075+12
25215
+	str	r9, [r5]
25216
+	str	r3, [r2, #4092]
25217
+	ldr	r3, .L3980+12
24689
25218
 	strh	r4, [r5, #12]	@ movhi
24690
25219
 	strh	r3, [r5, #14]	@ movhi
24691
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
24692
-.L4066:
25220
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
25221
+.L3972:
24693
25222
 	ldr	r0, [r6, #2576]
24694
25223
 	bl	kfree
24695
25224
 	mov	r3, #0
24696
25225
 	mvn	r0, #0
24697
25226
 	str	r3, [r6, #2576]
24698
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
24699
-.L4070:
25227
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
25228
+.L3976:
24700
25229
 	mvn	r0, #11
24701
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
24702
-.L4076:
25230
+	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
25231
+.L3981:
24703
25232
 	.align	2
24704
-.L4075:
24705
-	.word	.LANCHOR4
24706
-	.word	1380668996
25233
+.L3980:
25234
+	.word	.LANCHOR2
24707
25235
 	.word	.LC200
25236
+	.word	1380668996
24708
25237
 	.word	-1032
24709
25238
 	.fnend
24710
25239
 	.size	rk_ftl_vendor_storage_init, .-rk_ftl_vendor_storage_init
24711
25240
 	.align	2
24712
25241
 	.global	rk_ftl_vendor_read
25242
+	.syntax unified
25243
+	.arm
25244
+	.fpu softvfp
24713
25245
 	.type	rk_ftl_vendor_read, %function
24714
25246
 rk_ftl_vendor_read:
24715
25247
 	.fnstart
24716
25248
 	@ args = 0, pretend = 0, frame = 0
24717
25249
 	@ frame_needed = 0, uses_anonymous_args = 0
24718
-	stmfd	sp!, {r3, r4, r5, lr}
24719
-	.save {r3, r4, r5, lr}
24720
-	ldr	r3, .L4084
25250
+	ldr	r3, .L3992
24721
25251
 	ldr	ip, [r3, #2576]
24722
25252
 	cmp	ip, #0
24723
-	ldrneh	r4, [ip, #10]
24724
-	movne	r3, #0
24725
-	beq	.L4082
24726
-.L4079:
25253
+	beq	.L3987
25254
+	push	{r4, r5, r6, lr}
25255
+	.save {r4, r5, r6, lr}
25256
+	mov	r3, #0
25257
+	ldrh	r4, [ip, #10]
25258
+.L3984:
24727
25259
 	cmp	r3, r4
24728
-	bcs	.L4082
24729
-	add	lr, ip, r3, asl #3
25260
+	bcc	.L3986
25261
+	mvn	r0, #0
25262
+	pop	{r4, r5, r6, pc}
25263
+.L3986:
25264
+	add	lr, ip, r3, lsl #3
24730
25265
 	ldrh	r5, [lr, #16]
24731
25266
 	cmp	r5, r0
24732
-	bne	.L4080
24733
-	ldrh	r3, [lr, #20]
25267
+	bne	.L3985
25268
+	ldrh	r4, [lr, #20]
24734
25269
 	mov	r0, r1
24735
25270
 	ldrh	r1, [lr, #18]
24736
-	mov	r4, r2
24737
-	cmp	r2, r3
25271
+	cmp	r4, r2
25272
+	movcs	r4, r2
24738
25273
 	add	r1, r1, #1024
24739
-	movcs	r4, r3
24740
-	add	r1, ip, r1
24741
25274
 	mov	r2, r4
25275
+	add	r1, ip, r1
24742
25276
 	bl	memcpy
24743
25277
 	mov	r0, r4
24744
-	ldmfd	sp!, {r3, r4, r5, pc}
24745
-.L4080:
25278
+	pop	{r4, r5, r6, pc}
25279
+.L3985:
24746
25280
 	add	r3, r3, #1
24747
-	b	.L4079
24748
-.L4082:
25281
+	b	.L3984
25282
+.L3987:
24749
25283
 	mvn	r0, #0
24750
-	ldmfd	sp!, {r3, r4, r5, pc}
24751
-.L4085:
25284
+	bx	lr
25285
+.L3993:
24752
25286
 	.align	2
24753
-.L4084:
24754
-	.word	.LANCHOR4
25287
+.L3992:
25288
+	.word	.LANCHOR2
24755
25289
 	.fnend
24756
25290
 	.size	rk_ftl_vendor_read, .-rk_ftl_vendor_read
24757
25291
 	.align	2
24758
25292
 	.global	rk_ftl_vendor_write
25293
+	.syntax unified
25294
+	.arm
25295
+	.fpu softvfp
24759
25296
 	.type	rk_ftl_vendor_write, %function
24760
25297
 rk_ftl_vendor_write:
24761
25298
 	.fnstart
24762
25299
 	@ args = 0, pretend = 0, frame = 24
24763
25300
 	@ frame_needed = 0, uses_anonymous_args = 0
24764
-	stmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
25301
+	ldr	r3, .L4015
25302
+	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
24765
25303
 	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
24766
-	mov	r9, r2
24767
-	ldr	r2, .L4109
24768
25304
 	.pad #28
24769
25305
 	sub	sp, sp, #28
24770
-	ldr	r4, [r2, #2576]
25306
+	ldr	r4, [r3, #2576]
24771
25307
 	cmp	r4, #0
24772
-	beq	.L4101
24773
-	mov	r3, r1
24774
-	add	r7, r9, #63
24775
-	ldrh	r1, [r4, #8]
24776
-	bic	r7, r7, #63
25308
+	beq	.L4009
25309
+	mov	r8, r2
24777
25310
 	ldrh	r2, [r4, #10]
24778
-	mov	ip, r0
24779
-	mov	r6, #0
24780
-	str	r1, [sp, #4]
24781
-.L4088:
24782
-	cmp	r6, r2
24783
-	bcs	.L4107
24784
-	add	r5, r4, r6, asl #3
24785
-	ldrh	r1, [r5, #16]
24786
-	cmp	r1, ip
24787
-	bne	.L4089
24788
-	ldrh	r1, [r5, #20]
24789
-	add	fp, r4, #1024
24790
-	add	r1, r1, #63
24791
-	bic	r1, r1, #63
24792
-	str	r1, [sp, #8]
24793
-	cmp	r9, r1
24794
-	bls	.L4090
25311
+	add	r6, r8, #63
25312
+	ldrh	r3, [r4, #8]
25313
+	mov	fp, r1
25314
+	bic	r6, r6, #63
25315
+	mov	r7, #0
25316
+	str	r3, [sp, #4]
25317
+.L3996:
25318
+	cmp	r7, r2
25319
+	bcc	.L4004
24795
25320
 	ldrh	r1, [r4, #14]
24796
-	cmp	r1, r7
24797
-	subcs	r2, r2, #1
24798
-	strcs	r2, [sp, #12]
24799
-	ldrcsh	r8, [r5, #18]
24800
-	bcc	.L4101
24801
-.L4091:
24802
-	ldr	r2, [sp, #12]
24803
-	add	r5, r5, #8
24804
-	cmp	r6, r2
24805
-	bcs	.L4108
24806
-	ldrh	r10, [r5, #20]
24807
-	add	r0, fp, r8
24808
-	ldrh	r2, [r5, #16]
24809
-	add	r6, r6, #1
24810
-	ldrh	r1, [r5, #18]
24811
-	strh	r10, [r5, #12]	@ movhi
24812
-	add	r10, r10, #63
24813
-	bic	r10, r10, #63
24814
-	strh	r2, [r5, #8]	@ movhi
24815
-	strh	r8, [r5, #10]	@ movhi
24816
-	add	r1, fp, r1
24817
-	mov	r2, r10
24818
-	str	r3, [sp, #20]
24819
-	str	ip, [sp, #16]
24820
-	bl	memcpy
24821
-	add	r8, r8, r10
24822
-	ldr	r3, [sp, #20]
24823
-	ldr	ip, [sp, #16]
24824
-	b	.L4091
24825
-.L4108:
24826
-	add	r6, r4, r6, asl #3
24827
-	uxth	r8, r8
24828
-	add	r0, fp, r8
24829
-	mov	r1, r3
24830
-	strh	r8, [r6, #18]	@ movhi
24831
-	mov	r2, r9
24832
-	strh	ip, [r6, #16]	@ movhi
24833
-	uxth	r7, r7
24834
-	strh	r9, [r6, #20]	@ movhi
24835
-	add	r8, r8, r7
24836
-	bl	memcpy
24837
-	ldrh	r5, [r4, #14]
24838
-	strh	r8, [r4, #12]	@ movhi
24839
-	ldr	r3, [sp, #8]
24840
-	add	r5, r3, r5
24841
-	rsb	r7, r7, r5
24842
-	strh	r7, [r4, #14]	@ movhi
24843
-	b	.L4106
24844
-.L4090:
24845
-	ldrh	r0, [r5, #18]
24846
-	mov	r1, r3
24847
-	mov	r2, r9
24848
-	add	r0, fp, r0
24849
-	bl	memcpy
24850
-	strh	r9, [r5, #20]	@ movhi
24851
-	b	.L4106
24852
-.L4089:
24853
-	add	r6, r6, #1
24854
-	b	.L4088
24855
-.L4107:
24856
-	ldrh	r1, [r4, #14]
24857
-	cmp	r1, r7
24858
-	bcc	.L4101
24859
-	add	r2, r4, r2, asl #3
24860
-	uxth	r7, r7
24861
-	rsb	r1, r7, r1
24862
-	strh	ip, [r2, #16]	@ movhi
24863
-	ldrh	r0, [r4, #12]
24864
-	strh	r9, [r2, #20]	@ movhi
24865
-	strh	r0, [r2, #18]	@ movhi
24866
-	add	r0, r7, r0
24867
-	strh	r1, [r4, #14]	@ movhi
24868
-	mov	r1, r3
24869
-	strh	r0, [r4, #12]	@ movhi
24870
-	ldrh	r0, [r2, #18]
24871
-	mov	r2, r9
25321
+	cmp	r6, r1
25322
+	bhi	.L4009
25323
+	add	r3, r4, r2, lsl #3
25324
+	uxth	r6, r6
25325
+	strh	r0, [r3, #16]	@ movhi
25326
+	ldrh	r2, [r4, #12]
25327
+	strh	r8, [r3, #20]	@ movhi
25328
+	strh	r2, [r3, #18]	@ movhi
25329
+	add	r2, r2, r6
25330
+	sub	r6, r1, r6
25331
+	strh	r2, [r4, #12]	@ movhi
25332
+	strh	r6, [r4, #14]	@ movhi
25333
+	mov	r2, r8
25334
+	ldrh	r0, [r3, #18]
25335
+	mov	r1, fp
24872
25336
 	add	r0, r0, #1024
24873
25337
 	add	r0, r4, r0
24874
25338
 	bl	memcpy
24875
25339
 	ldrh	r3, [r4, #10]
24876
25340
 	add	r3, r3, #1
24877
25341
 	strh	r3, [r4, #10]	@ movhi
24878
-.L4106:
25342
+	b	.L4014
25343
+.L4004:
25344
+	add	r5, r4, r7, lsl #3
25345
+	ldrh	r3, [r5, #16]
25346
+	cmp	r3, r0
25347
+	str	r3, [sp, #8]
25348
+	bne	.L3997
25349
+	ldrh	r1, [r5, #20]
25350
+	add	r3, r4, #1024
25351
+	add	r1, r1, #63
25352
+	bic	r1, r1, #63
25353
+	cmp	r8, r1
25354
+	str	r1, [sp, #12]
25355
+	bls	.L3998
25356
+	ldrh	r1, [r4, #14]
25357
+	cmp	r6, r1
25358
+	subls	r2, r2, #1
25359
+	ldrhls	r10, [r5, #18]
25360
+	strls	r2, [sp, #16]
25361
+	bls	.L3999
25362
+.L4009:
25363
+	mvn	r0, #0
25364
+	b	.L3994
25365
+.L4000:
25366
+	ldrh	r9, [r5, #20]
25367
+	add	r0, r3, r10
25368
+	ldrh	r2, [r5, #16]
25369
+	add	r7, r7, #1
25370
+	ldrh	r1, [r5, #18]
25371
+	strh	r9, [r5, #12]	@ movhi
25372
+	add	r9, r9, #63
25373
+	bic	r9, r9, #63
25374
+	strh	r2, [r5, #8]	@ movhi
25375
+	strh	r10, [r5, #10]	@ movhi
25376
+	add	r1, r3, r1
25377
+	mov	r2, r9
25378
+	str	r3, [sp, #20]
25379
+	bl	memcpy
25380
+	ldr	r3, [sp, #20]
25381
+	add	r10, r10, r9
25382
+.L3999:
25383
+	ldr	r2, [sp, #16]
25384
+	add	r5, r5, #8
25385
+	cmp	r7, r2
25386
+	bcc	.L4000
25387
+	ldrh	r2, [sp, #8]
25388
+	add	r7, r4, r7, lsl #3
25389
+	uxth	r5, r10
25390
+	uxtah	r0, r3, r10
25391
+	strh	r8, [r7, #20]	@ movhi
25392
+	strh	r2, [r7, #16]	@ movhi
25393
+	mov	r1, fp
25394
+	strh	r5, [r7, #18]	@ movhi
25395
+	mov	r2, r8
25396
+	bl	memcpy
25397
+	uxth	r3, r6
25398
+	ldrh	r6, [r4, #14]
25399
+	add	r5, r5, r3
25400
+	sub	r6, r6, r3
25401
+	ldr	r3, [sp, #12]
25402
+	strh	r5, [r4, #12]	@ movhi
25403
+	add	r6, r6, r3
25404
+	strh	r6, [r4, #14]	@ movhi
25405
+.L4014:
24879
25406
 	ldr	r3, [r4, #4]
24880
25407
 	add	r2, r4, #61440
24881
25408
 	mov	r1, #128
..
..
@@ -24890,30 +25417,41 @@
24890
25417
 	movhi	r3, #0
24891
25418
 	strh	r3, [r4, #8]	@ movhi
24892
25419
 	ldr	r3, [sp, #4]
24893
-	mov	r0, r3, asl #7
25420
+	lsl	r0, r3, #7
24894
25421
 	bl	FlashBootVendorWrite
24895
25422
 	mov	r0, #0
24896
-	b	.L4087
24897
-.L4101:
24898
-	mvn	r0, #0
24899
-.L4087:
25423
+.L3994:
24900
25424
 	add	sp, sp, #28
24901
25425
 	@ sp needed
24902
-	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
24903
-.L4110:
25426
+	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
25427
+.L3998:
25428
+	ldrh	r0, [r5, #18]
25429
+	mov	r2, r8
25430
+	mov	r1, fp
25431
+	add	r0, r3, r0
25432
+	bl	memcpy
25433
+	strh	r8, [r5, #20]	@ movhi
25434
+	b	.L4014
25435
+.L3997:
25436
+	add	r7, r7, #1
25437
+	b	.L3996
25438
+.L4016:
24904
25439
 	.align	2
24905
-.L4109:
24906
-	.word	.LANCHOR4
25440
+.L4015:
25441
+	.word	.LANCHOR2
24907
25442
 	.fnend
24908
25443
 	.size	rk_ftl_vendor_write, .-rk_ftl_vendor_write
24909
25444
 	.align	2
24910
25445
 	.global	rk_ftl_vendor_storage_ioctl
25446
+	.syntax unified
25447
+	.arm
25448
+	.fpu softvfp
24911
25449
 	.type	rk_ftl_vendor_storage_ioctl, %function
24912
25450
 rk_ftl_vendor_storage_ioctl:
24913
25451
 	.fnstart
24914
25452
 	@ args = 0, pretend = 0, frame = 0
24915
25453
 	@ frame_needed = 0, uses_anonymous_args = 0
24916
-	stmfd	sp!, {r4, r5, r6, lr}
25454
+	push	{r4, r5, r6, lr}
24917
25455
 	.save {r4, r5, r6, lr}
24918
25456
 	mov	r0, #4096
24919
25457
 	mov	r5, r2
..
..
@@ -24921,81 +25459,79 @@
24921
25459
 	bl	ftl_malloc
24922
25460
 	subs	r4, r0, #0
24923
25461
 	mvneq	r5, #0
24924
-	beq	.L4112
24925
-	ldr	r3, .L4128
25462
+	beq	.L4017
25463
+	ldr	r3, .L4033
24926
25464
 	cmp	r6, r3
24927
-	beq	.L4114
25465
+	beq	.L4020
24928
25466
 	add	r3, r3, #1
24929
25467
 	cmp	r6, r3
24930
-	beq	.L4115
24931
-	b	.L4126
24932
-.L4114:
24933
-	mov	r1, r5
25468
+	beq	.L4021
25469
+.L4031:
25470
+	mvn	r5, #13
25471
+	b	.L4019
25472
+.L4020:
24934
25473
 	mov	r2, #8
25474
+	mov	r1, r5
24935
25475
 	bl	rk_copy_from_user
24936
25476
 	cmp	r0, #0
24937
-	bne	.L4126
25477
+	bne	.L4031
24938
25478
 	ldr	r2, [r4]
24939
-	ldr	r3, .L4128+4
25479
+	ldr	r3, .L4033+4
24940
25480
 	cmp	r2, r3
24941
-	beq	.L4117
24942
-.L4118:
25481
+	beq	.L4023
25482
+.L4024:
24943
25483
 	mvn	r5, #0
24944
-	b	.L4113
24945
-.L4117:
24946
-	ldrh	r0, [r4, #4]
24947
-	add	r1, r4, #8
25484
+.L4019:
25485
+	mov	r0, r4
25486
+	bl	kfree
25487
+.L4017:
25488
+	mov	r0, r5
25489
+	pop	{r4, r5, r6, pc}
25490
+.L4023:
24948
25491
 	ldrh	r2, [r4, #6]
25492
+	add	r1, r4, #8
25493
+	ldrh	r0, [r4, #4]
24949
25494
 	bl	rk_ftl_vendor_read
24950
25495
 	cmn	r0, #1
24951
-	beq	.L4118
25496
+	beq	.L4024
24952
25497
 	uxth	r2, r0
24953
25498
 	strh	r0, [r4, #6]	@ movhi
24954
25499
 	mov	r1, r4
24955
25500
 	mov	r0, r5
24956
25501
 	add	r2, r2, #8
24957
25502
 	bl	rk_copy_to_user
24958
-	cmp	r0, #0
24959
-	moveq	r5, #0
24960
-	mvnne	r5, #13
24961
-	b	.L4113
24962
-.L4115:
24963
-	mov	r1, r5
25503
+	subs	r5, r0, #0
25504
+	beq	.L4019
25505
+	b	.L4031
25506
+.L4021:
24964
25507
 	mov	r2, #8
25508
+	mov	r1, r5
24965
25509
 	bl	rk_copy_from_user
24966
25510
 	cmp	r0, #0
24967
-	bne	.L4126
25511
+	bne	.L4031
24968
25512
 	ldr	r2, [r4]
24969
-	ldr	r3, .L4128+4
25513
+	ldr	r3, .L4033+4
24970
25514
 	cmp	r2, r3
24971
-	bne	.L4118
25515
+	bne	.L4024
24972
25516
 	ldrh	r2, [r4, #6]
24973
25517
 	movw	r3, #4087
24974
25518
 	cmp	r2, r3
24975
-	bhi	.L4118
24976
-	mov	r0, r4
24977
-	mov	r1, r5
25519
+	bhi	.L4024
24978
25520
 	add	r2, r2, #8
25521
+	mov	r1, r5
25522
+	mov	r0, r4
24979
25523
 	bl	rk_copy_from_user
24980
25524
 	cmp	r0, #0
24981
-	bne	.L4126
24982
-	ldrh	r0, [r4, #4]
24983
-	add	r1, r4, #8
25525
+	bne	.L4031
24984
25526
 	ldrh	r2, [r4, #6]
25527
+	add	r1, r4, #8
25528
+	ldrh	r0, [r4, #4]
24985
25529
 	bl	rk_ftl_vendor_write
24986
25530
 	mov	r5, r0
24987
-	b	.L4113
24988
-.L4126:
24989
-	mvn	r5, #13
24990
-.L4113:
24991
-	mov	r0, r4
24992
-	bl	kfree
24993
-.L4112:
24994
-	mov	r0, r5
24995
-	ldmfd	sp!, {r4, r5, r6, pc}
24996
-.L4129:
25531
+	b	.L4019
25532
+.L4034:
24997
25533
 	.align	2
24998
-.L4128:
25534
+.L4033:
24999
25535
 	.word	1074034177
25000
25536
 	.word	1448232273
25001
25537
 	.fnend
..
..
@@ -25009,6 +25545,8 @@
25009
25545
 	.global	gSnSectorData
25010
25546
 	.global	gpDrmKeyInfo
25011
25547
 	.global	gpBootConfig
25548
+	.global	ftl_dma32_buffer_size
25549
+	.global	ftl_dma32_buffer
25012
25550
 	.global	gLoaderBootInfo
25013
25551
 	.global	RK29_NANDC1_REG_BASE
25014
25552
 	.global	RK29_NANDC_REG_BASE
..
..
@@ -25244,18 +25782,11 @@
25244
25782
 	.global	IDByte
25245
25783
 	.global	read_retry_cur_offset
25246
25784
 	.section	.rodata
25247
-	.align	2
25248
-.LANCHOR3 = . + 0
25249
-	.type	__func__.20390, %object
25250
-	.size	__func__.20390, 11
25251
-__func__.20390:
25785
+	.set	.LANCHOR3,. + 0
25786
+	.type	__func__.23812, %object
25787
+	.size	__func__.23812, 11
25788
+__func__.23812:
25252
25789
 	.ascii	"FtlMemInit\000"
25253
-.LC0:
25254
-	.byte	60
25255
-	.byte	40
25256
-	.byte	24
25257
-	.byte	16
25258
-	.space	1
25259
25790
 	.type	samsung_14nm_slc_rr, %object
25260
25791
 	.size	samsung_14nm_slc_rr, 26
25261
25792
 samsung_14nm_slc_rr:
..
..
@@ -25285,7 +25816,6 @@
25285
25816
 	.byte	-125
25286
25817
 	.byte	-115
25287
25818
 	.byte	100
25288
-	.space	2
25289
25819
 	.type	samsung_14nm_mlc_rr, %object
25290
25820
 	.size	samsung_14nm_mlc_rr, 104
25291
25821
 samsung_14nm_mlc_rr:
..
..
@@ -25393,452 +25923,33 @@
25393
25923
 	.byte	18
25394
25924
 	.byte	9
25395
25925
 	.byte	8
25396
-	.type	__func__.21169, %object
25397
-	.size	__func__.21169, 17
25398
-__func__.21169:
25926
+	.type	__func__.24591, %object
25927
+	.size	__func__.24591, 17
25928
+__func__.24591:
25399
25929
 	.ascii	"FtlDumpBlockInfo\000"
25400
-	.space	3
25401
-	.type	__func__.21188, %object
25402
-	.size	__func__.21188, 16
25403
-__func__.21188:
25930
+	.type	__func__.24610, %object
25931
+	.size	__func__.24610, 16
25932
+__func__.24610:
25404
25933
 	.ascii	"FtlScanAllBlock\000"
25405
-	.type	__func__.21456, %object
25406
-	.size	__func__.21456, 17
25407
-__func__.21456:
25934
+	.type	__func__.24878, %object
25935
+	.size	__func__.24878, 17
25936
+__func__.24878:
25408
25937
 	.ascii	"ftl_scan_all_ppa\000"
25409
-	.space	3
25410
-	.type	__func__.21137, %object
25411
-	.size	__func__.21137, 12
25412
-__func__.21137:
25938
+	.type	__func__.24559, %object
25939
+	.size	__func__.24559, 12
25940
+__func__.24559:
25413
25941
 	.ascii	"FtlCheckVpc\000"
25414
-	.type	__func__.21436, %object
25415
-	.size	__func__.21436, 21
25416
-__func__.21436:
25942
+	.type	__func__.24858, %object
25943
+	.size	__func__.24858, 21
25944
+__func__.24858:
25417
25945
 	.ascii	"FtlVpcCheckAndModify\000"
25418
-	.space	3
25419
-	.type	__func__.20463, %object
25420
-	.size	__func__.20463, 8
25421
-__func__.20463:
25946
+	.type	__func__.23885, %object
25947
+	.size	__func__.23885, 8
25948
+__func__.23885:
25422
25949
 	.ascii	"FtlInit\000"
25423
-	.section	.rodata.str1.1,"aMS",%progbits,1
25424
-.LC1:
25425
-	.ascii	"FlashEraseBlocks pageAddr error %x\012\000"
25426
-.LC2:
25427
-	.ascii	"phyBlk = 0x%x die = %d block_in_die = 0x%x 0x%8x\012"
25428
-	.ascii	"\000"
25429
-.LC3:
25430
-	.ascii	"FtlFreeSysBlkQueueOut free count = %d\012\000"
25431
-.LC4:
25432
-	.ascii	"FtlFreeSysBlkQueueOut = %x, free count = %d, error\012"
25433
-	.ascii	"\000"
25434
-.LC5:
25435
-	.ascii	"FtlFreeSysBlkQueueOut = %x, free count = %d\012\000"
25436
-.LC6:
25437
-	.ascii	"FLASH INFO:\012\000"
25438
-.LC7:
25439
-	.ascii	"FLASH ID: %x\012\000"
25440
-.LC8:
25441
-	.ascii	"Device Capacity: %d MB\012\000"
25442
-.LC9:
25443
-	.ascii	"FMWAIT: %x %x %x %x\012\000"
25444
-.LC10:
25445
-	.ascii	"FTL INFO:\012\000"
25446
-.LC11:
25447
-	.ascii	"g_MaxLpn = 0x%x\012\000"
25448
-.LC12:
25449
-	.ascii	"g_VaildLpn = 0x%x\012\000"
25450
-.LC13:
25451
-	.ascii	"read_page_count = 0x%x\012\000"
25452
-.LC14:
25453
-	.ascii	"discard_page_count = 0x%x\012\000"
25454
-.LC15:
25455
-	.ascii	"write_page_count = 0x%x\012\000"
25456
-.LC16:
25457
-	.ascii	"cache_write_count = 0x%x\012\000"
25458
-.LC17:
25459
-	.ascii	"l2p_write_count = 0x%x\012\000"
25460
-.LC18:
25461
-	.ascii	"gc_page_count = 0x%x\012\000"
25462
-.LC19:
25463
-	.ascii	"totle_write = %d MB\012\000"
25464
-.LC20:
25465
-	.ascii	"totle_read = %d MB\012\000"
25466
-.LC21:
25467
-	.ascii	"GSV = 0x%x\012\000"
25468
-.LC22:
25469
-	.ascii	"GDV = 0x%x\012\000"
25470
-.LC23:
25471
-	.ascii	"bad blk num = %d %d\012\000"
25472
-.LC24:
25473
-	.ascii	"free_superblocks = 0x%x\012\000"
25474
-.LC25:
25475
-	.ascii	"mlc_EC = 0x%x\012\000"
25476
-.LC26:
25477
-	.ascii	"slc_EC = 0x%x\012\000"
25478
-.LC27:
25479
-	.ascii	"avg_EC = 0x%x\012\000"
25480
-.LC28:
25481
-	.ascii	"sys_EC = 0x%x\012\000"
25482
-.LC29:
25483
-	.ascii	"max_EC = 0x%x\012\000"
25484
-.LC30:
25485
-	.ascii	"min_EC = 0x%x\012\000"
25486
-.LC31:
25487
-	.ascii	"PLT = 0x%x\012\000"
25488
-.LC32:
25489
-	.ascii	"POT = 0x%x\012\000"
25490
-.LC33:
25491
-	.ascii	"MaxSector = 0x%x\012\000"
25492
-.LC34:
25493
-	.ascii	"init_sys_blks_pp = 0x%x\012\000"
25494
-.LC35:
25495
-	.ascii	"sys_blks_pp = 0x%x\012\000"
25496
-.LC36:
25497
-	.ascii	"free sysblock = 0x%x\012\000"
25498
-.LC37:
25499
-	.ascii	"data_blks_pp = 0x%x\012\000"
25500
-.LC38:
25501
-	.ascii	"data_op_blks_pp = 0x%x\012\000"
25502
-.LC39:
25503
-	.ascii	"max_data_blks = 0x%x\012\000"
25504
-.LC40:
25505
-	.ascii	"Sys.id = 0x%x\012\000"
25506
-.LC41:
25507
-	.ascii	"Bbt.id = 0x%x\012\000"
25508
-.LC42:
25509
-	.ascii	"ACT.page = 0x%x\012\000"
25510
-.LC43:
25511
-	.ascii	"ACT.plane = 0x%x\012\000"
25512
-.LC44:
25513
-	.ascii	"ACT.id = 0x%x\012\000"
25514
-.LC45:
25515
-	.ascii	"ACT.mode = 0x%x\012\000"
25516
-.LC46:
25517
-	.ascii	"ACT.a_pages = 0x%x\012\000"
25518
-.LC47:
25519
-	.ascii	"ACT VPC = 0x%x\012\000"
25520
-.LC48:
25521
-	.ascii	"BUF.page = 0x%x\012\000"
25522
-.LC49:
25523
-	.ascii	"BUF.plane = 0x%x\012\000"
25524
-.LC50:
25525
-	.ascii	"BUF.id = 0x%x\012\000"
25526
-.LC51:
25527
-	.ascii	"BUF.mode = 0x%x\012\000"
25528
-.LC52:
25529
-	.ascii	"BUF.a_pages = 0x%x\012\000"
25530
-.LC53:
25531
-	.ascii	"BUF VPC = 0x%x\012\000"
25532
-.LC54:
25533
-	.ascii	"TMP.page = 0x%x\012\000"
25534
-.LC55:
25535
-	.ascii	"TMP.plane = 0x%x\012\000"
25536
-.LC56:
25537
-	.ascii	"TMP.id = 0x%x\012\000"
25538
-.LC57:
25539
-	.ascii	"TMP.mode = 0x%x\012\000"
25540
-.LC58:
25541
-	.ascii	"TMP.a_pages = 0x%x\012\000"
25542
-.LC59:
25543
-	.ascii	"GC.page = 0x%x\012\000"
25544
-.LC60:
25545
-	.ascii	"GC.plane = 0x%x\012\000"
25546
-.LC61:
25547
-	.ascii	"GC.id = 0x%x\012\000"
25548
-.LC62:
25549
-	.ascii	"GC.mode = 0x%x\012\000"
25550
-.LC63:
25551
-	.ascii	"GC.a_pages = 0x%x\012\000"
25552
-.LC64:
25553
-	.ascii	"WR_CHK = 0x%x %x %x %x\012\000"
25554
-.LC65:
25555
-	.ascii	"Read Err = 0x%x\012\000"
25556
-.LC66:
25557
-	.ascii	"Prog Err = 0x%x\012\000"
25558
-.LC67:
25559
-	.ascii	"gc_free_blk_th= 0x%x\012\000"
25560
-.LC68:
25561
-	.ascii	"gc_merge_free_blk_th= 0x%x\012\000"
25562
-.LC69:
25563
-	.ascii	"gc_skip_write_count= 0x%x\012\000"
25564
-.LC70:
25565
-	.ascii	"gc_blk_index= 0x%x\012\000"
25566
-.LC71:
25567
-	.ascii	"free min EC= 0x%x\012\000"
25568
-.LC72:
25569
-	.ascii	"free max EC= 0x%x\012\000"
25570
-.LC73:
25571
-	.ascii	"GC__SB VPC = 0x%x\012\000"
25572
-.LC74:
25573
-	.ascii	"%d. [0x%x]=0x%x 0x%x  0x%x\012\000"
25574
-.LC75:
25575
-	.ascii	"free %d. [0x%x] 0x%x  0x%x\012\000"
25576
-.LC76:
25577
-	.ascii	"%s\012\000"
25578
-.LC77:
25579
-	.ascii	"FTL version: 5.0.63 20200923\000"
25580
-.LC78:
25581
-	.ascii	"swblk %x ,avg = %x max= %x vpc= %x,ec=%x ,max ec=%x"
25582
-	.ascii	"\012\000"
25583
-.LC79:
25584
-	.ascii	"FtlGcRefreshBlock  0x%x\012\000"
25585
-.LC80:
25586
-	.ascii	"FtlGcMarkBadPhyBlk %d 0x%x\012\000"
25587
-.LC81:
25588
-	.ascii	"%s error allocating memory. return -1\012\000"
25589
-.LC82:
25590
-	.ascii	"%s %p:0x%x:\000"
25591
-.LC83:
25592
-	.ascii	"%x \000"
25593
-.LC84:
25594
-	.ascii	"\000"
25595
-.LC85:
25596
-	.ascii	"otp error! %d\000"
25597
-.LC86:
25598
-	.ascii	"rr\000"
25599
-.LC87:
25600
-	.ascii	"%d statReg->V6.mtrans_cnt=%d flReg.V6.page_num=%d\012"
25601
-	.ascii	"\000"
25602
-.LC88:
25603
-	.ascii	"nandc:\000"
25604
-.LC89:
25605
-	.ascii	"%d flReg.d32=%x %x\012\000"
25606
-.LC90:
25607
-	.ascii	"sdr read ok %x ecc=%d\012\000"
25608
-.LC91:
25609
-	.ascii	"sync para %d\012\000"
25610
-.LC92:
25611
-	.ascii	"TOG mode Read error %x %x\012\000"
25612
-.LC93:
25613
-	.ascii	"read retry status %x %x %x\012\000"
25614
-.LC94:
25615
-	.ascii	"micron RR %d row=%x,count %d,status=%d\012\000"
25616
-.LC95:
25617
-	.ascii	"samsung RR %d row=%x,count %d,status=%d\012\000"
25618
-.LC96:
25619
-	.ascii	"ECC:%d\012\000"
25620
-.LC97:
25621
-	.ascii	"No.%d FLASH ID:%x %x %x %x %x %x\012\000"
25622
-.LC98:
25623
-	.ascii	"FlashLoadPhyInfo fail %x!!\012\000"
25624
-.LC99:
25625
-	.ascii	"Read pageadd=%x  ecc=%x err=%x\012\000"
25626
-.LC100:
25627
-	.ascii	"data:\000"
25628
-.LC101:
25629
-	.ascii	"spare:\000"
25630
-.LC102:
25631
-	.ascii	"ReadRetry pageadd=%x ecc=%x err=%x\012\000"
25632
-.LC103:
25633
-	.ascii	"FLFB:%d %d\012\000"
25634
-.LC104:
25635
-	.ascii	"prog error: = %x\012\000"
25636
-.LC105:
25637
-	.ascii	"prog read error: = %x\012\000"
25638
-.LC106:
25639
-	.ascii	"prog read REFRESH: = %x\012\000"
25640
-.LC107:
25641
-	.ascii	"prog read s error: = %x %x %x\012\000"
25642
-.LC108:
25643
-	.ascii	"prog read d error: = %x %x %x\012\000"
25644
-.LC109:
25645
-	.ascii	"id = %x,%x addr= %x,spare= %x %x %x %x data= %x\012"
25646
-	.ascii	"\000"
25647
-.LC110:
25648
-	.ascii	"...%s enter...\012\000"
25649
-.LC111:
25650
-	.ascii	"superBlkID = %x vpc=%x\012\000"
25651
-.LC112:
25652
-	.ascii	"flashmode = %x pagenum = %x %x\012\000"
25653
-.LC113:
25654
-	.ascii	"id = %x,%x addr= %x,spare= %x %x %x %x data=%x %x\012"
25655
-	.ascii	"\000"
25656
-.LC114:
25657
-	.ascii	"blk = %x vpc=%x mode = %x\012\000"
25658
-.LC115:
25659
-	.ascii	"mlc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
25660
-	.ascii	"%x\012\000"
25661
-.LC116:
25662
-	.ascii	"slc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
25663
-	.ascii	"%x\012\000"
25664
-.LC117:
25665
-	.ascii	"ftl_scan_all_ppa blk %x page %x flag: %x\012\000"
25666
-.LC118:
25667
-	.ascii	"ftl_scan_all_ppa blk %x page %x flag: %x .........."
25668
-	.ascii	"..... is bad block\012\000"
25669
-.LC119:
25670
-	.ascii	"addr= %x, status= %d,spare= %x %x %x %x data=%x %x\012"
25671
-	.ascii	"\000"
25672
-.LC120:
25673
-	.ascii	"%s finished\012\000"
25674
-.LC121:
25675
-	.ascii	"FlashMakeFactorBbt %d\012\000"
25676
-.LC122:
25677
-	.ascii	"bad block:%d %d\012\000"
25678
-.LC123:
25679
-	.ascii	"FMFB:%d %d\012\000"
25680
-.LC124:
25681
-	.ascii	"E:bad block:%d\012\000"
25682
-.LC125:
25683
-	.ascii	"FMFB:Save %d %d\012\000"
25684
-.LC126:
25685
-	.ascii	"FtlBbmTblFlush id=%x,page=%x,previd=%x cnt=%d\012\000"
25686
-.LC127:
25687
-	.ascii	"FtlBbmTblFlush error:%x\012\000"
25688
-.LC128:
25689
-	.ascii	"FtlBbmTblFlush error = %x error count = %d\012\000"
25690
-.LC129:
25691
-	.ascii	"FtlGcFreeBadSuperBlk 0x%x\012\000"
25692
-.LC130:
25693
-	.ascii	"decrement_vpc_count %x = %d\012\000"
25694
-.LC131:
25695
-	.ascii	"decrement_vpc_count %x = %d in free list\012\000"
25696
-.LC132:
25697
-	.ascii	"FtlVpcTblFlush error = %x error count = %d\012\000"
25698
-.LC133:
25699
-	.ascii	"page map lost: %x %x\012\000"
25700
-.LC134:
25701
-	.ascii	"FtlMapWritePage error = %x\012\000"
25702
-.LC135:
25703
-	.ascii	"FtlMapWritePage error = %x error count = %d\012\000"
25704
-.LC136:
25705
-	.ascii	"FtlVendorPartRead refresh = %x phyAddr = %x\012\000"
25706
-.LC137:
25707
-	.ascii	"no ect\000"
25708
-.LC138:
25709
-	.ascii	"slc mode\000"
25710
-.LC139:
25711
-	.ascii	"BBT:\000"
25712
-.LC140:
25713
-	.ascii	"region_id = %x phyAddr = %x\012\000"
25714
-.LC141:
25715
-	.ascii	"map_ppn:\000"
25716
-.LC142:
25717
-	.ascii	"load_l2p_region refresh = %x phyAddr = %x\012\000"
25718
-.LC143:
25719
-	.ascii	"FtlCheckVpc2 %x = %x  %x\012\000"
25720
-.LC144:
25721
-	.ascii	"free blk vpc error %x = %x  %x\012\000"
25722
-.LC145:
25723
-	.ascii	"error_flag %x\012\000"
25724
-.LC146:
25725
-	.ascii	"Ftlscanalldata = %x\012\000"
25726
-.LC147:
25727
-	.ascii	"scan lpa = %x ppa= %x\012\000"
25728
-.LC148:
25729
-	.ascii	"lba = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
25730
-	.ascii	"\000"
25731
-.LC149:
25732
-	.ascii	"RSB refresh addr %x\012\000"
25733
-.LC150:
25734
-	.ascii	"spuer block %x vpn is 0\012 \000"
25735
-.LC151:
25736
-	.ascii	"g_recovery_ppa %x ver %x\012 \000"
25737
-.LC152:
25738
-	.ascii	"FtlCheckVpc %x = %x  %x\012\000"
25739
-.LC153:
25740
-	.ascii	"FtlGcScanTempBlk Error ID %x %x!!!!!!! \012\000"
25741
-.LC154:
25742
-	.ascii	"FtlGcScanTempBlkError ID %x %x!!!!!!!\012\000"
25743
-.LC155:
25744
-	.ascii	"GC des block %x done\012\000"
25745
-.LC156:
25746
-	.ascii	"too many bad block  = %d %d\012\000"
25747
-.LC157:
25748
-	.ascii	"%d GC datablk  = %x vpc %x %x\012\000"
25749
-.LC158:
25750
-	.ascii	"SWL %x, FSB = %x vpc= %x,ec=%x th=%x\012\000"
25751
-.LC159:
25752
-	.ascii	"Ftlwrite decrement_vpc_count %x = %d\012\000"
25753
-.LC160:
25754
-	.ascii	"rk_ftl_de_init %x\012\000"
25755
-.LC161:
25756
-	.ascii	"...%s: no bad block mapping table, format device\012"
25757
-	.ascii	"\000"
25758
-.LC162:
25759
-	.ascii	"...%s FtlSysBlkInit error ,format device!\012\000"
25760
-.LC163:
25761
-	.ascii	"FtlInit %x\012\000"
25762
-.LC164:
25763
-	.ascii	"fix power lost blk = %x vpc=%x\012\000"
25764
-.LC165:
25765
-	.ascii	"erase power lost blk = %x vpc=%x\012\000"
25766
-.LC166:
25767
-	.ascii	"FtlWrite: lpa error:%x %x\012\000"
25768
-.LC167:
25769
-	.ascii	"id = %x,%x addr= %x,spare= %x %x %x %x data = %x\012"
25770
-	.ascii	"\000"
25771
-.LC168:
25772
-	.ascii	":\000"
25773
-.LC169:
25774
-	.ascii	"phyBlk = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
25775
-	.ascii	"\000"
25776
-.LC170:
25777
-	.ascii	"Mblk:\000"
25778
-.LC171:
25779
-	.ascii	"L2P:\000"
25780
-.LC172:
25781
-	.ascii	"L2PC:\000"
25782
-.LC173:
25783
-	.ascii	"write_idblock fix data %x %x\012\000"
25784
-.LC174:
25785
-	.ascii	"idblk:\000"
25786
-.LC175:
25787
-	.ascii	"idb reverse %x %x\012\000"
25788
-.LC176:
25789
-	.ascii	"write_idblock totle_sec %x %x %x %x\012\000"
25790
-.LC177:
25791
-	.ascii	"IDBlockWriteData %x %x\012\000"
25792
-.LC178:
25793
-	.ascii	"IDBlockWriteData %x %x ret= %x\012\000"
25794
-.LC179:
25795
-	.ascii	"IdBlockReadData %x %x\012\000"
25796
-.LC180:
25797
-	.ascii	"IdBlockReadData %x %x ret= %x\012\000"
25798
-.LC181:
25799
-	.ascii	"write and check error:%d idb=%x,offset=%x,r=%x,w=%x"
25800
-	.ascii	"\012\000"
25801
-.LC182:
25802
-	.ascii	"write\000"
25803
-.LC183:
25804
-	.ascii	"read\000"
25805
-.LC184:
25806
-	.ascii	"write_idblock error %d\012\000"
25807
-.LC185:
25808
-	.ascii	"wl_lba %p %x %x %x\012\000"
25809
-.LC186:
25810
-	.ascii	"RKNAND_GET_DRM_KEY\012\000"
25811
-.LC187:
25812
-	.ascii	"rk_copy_from_user error\012\000"
25813
-.LC188:
25814
-	.ascii	"RKNAND_STORE_DRM_KEY\012\000"
25815
-.LC189:
25816
-	.ascii	"RKNAND_DIASBLE_SECURE_BOOT\012\000"
25817
-.LC190:
25818
-	.ascii	"RKNAND_ENASBLE_SECURE_BOOT\012\000"
25819
-.LC191:
25820
-	.ascii	"RKNAND_GET_SN_SECTOR\012\000"
25821
-.LC192:
25822
-	.ascii	"RKNAND_LOADER_UNLOCK\012\000"
25823
-.LC193:
25824
-	.ascii	"RKNAND_LOADER_STATUS\012\000"
25825
-.LC194:
25826
-	.ascii	"RKNAND_LOADER_LOCK\012\000"
25827
-.LC195:
25828
-	.ascii	"LockKey not match %d\012\000"
25829
-.LC196:
25830
-	.ascii	"RKNAND_GET_VENDOR_SECTOR\012\000"
25831
-.LC197:
25832
-	.ascii	"RKNAND_STORE_VENDOR_SECTOR\012\000"
25833
-.LC198:
25834
-	.ascii	"return ret = %lx\012\000"
25835
-.LC199:
25836
-	.ascii	"secureBootEn check error\012\000"
25837
-.LC200:
25838
-	.ascii	"\0013vendor storage %x,%x,%x\012\000"
25839
25950
 	.data
25840
25951
 	.align	2
25841
-.LANCHOR1 = . + 0
25952
+	.set	.LANCHOR1,. + 0
25842
25953
 	.type	random_seed, %object
25843
25954
 	.size	random_seed, 256
25844
25955
 random_seed:
..
..
@@ -26018,7 +26129,6 @@
26018
26129
 	.byte	126
26019
26130
 	.byte	124
26020
26131
 	.byte	0
26021
-	.space	3
26022
26132
 	.type	Toshiba15RefValue, %object
26023
26133
 	.size	Toshiba15RefValue, 95
26024
26134
 Toshiba15RefValue:
..
..
@@ -26117,7 +26227,6 @@
26117
26227
 	.byte	116
26118
26228
 	.byte	114
26119
26229
 	.byte	0
26120
-	.space	1
26121
26230
 	.type	ToshibaRefValue, %object
26122
26231
 	.size	ToshibaRefValue, 8
26123
26232
 ToshibaRefValue:
..
..
@@ -28614,9 +28723,16 @@
28614
28723
 	.word	1
28615
28724
 	.bss
28616
28725
 	.align	2
28617
-.LANCHOR0 = . + 0
28618
-.LANCHOR2 = . + 8184
28619
-.LANCHOR4 = . + 16368
28726
+	.set	.LANCHOR0,. + 0
28727
+	.set	.LANCHOR2,. + 8184
28728
+	.type	gNandChipMap, %object
28729
+	.size	gNandChipMap, 32
28730
+gNandChipMap:
28731
+	.space	32
28732
+	.type	p_blk_mode_table, %object
28733
+	.size	p_blk_mode_table, 4
28734
+p_blk_mode_table:
28735
+	.space	4
28620
28736
 	.type	g_slc2KBNand, %object
28621
28737
 	.size	g_slc2KBNand, 1
28622
28738
 g_slc2KBNand:
..
..
@@ -28635,10 +28751,6 @@
28635
28751
 gNandRandomizer:
28636
28752
 	.space	1
28637
28753
 	.space	3
28638
-	.type	gNandChipMap, %object
28639
-	.size	gNandChipMap, 32
28640
-gNandChipMap:
28641
-	.space	32
28642
28754
 	.type	gpNandParaInfo, %object
28643
28755
 	.size	gpNandParaInfo, 4
28644
28756
 gpNandParaInfo:
..
..
@@ -28647,6 +28759,15 @@
28647
28759
 	.size	gNandOptPara, 32
28648
28760
 gNandOptPara:
28649
28761
 	.space	32
28762
+	.type	g_retryMode, %object
28763
+	.size	g_retryMode, 1
28764
+g_retryMode:
28765
+	.space	1
28766
+	.type	g_maxRegNum, %object
28767
+	.size	g_maxRegNum, 1
28768
+g_maxRegNum:
28769
+	.space	1
28770
+	.space	2
28650
28771
 	.type	gpNandc, %object
28651
28772
 	.size	gpNandc, 4
28652
28773
 gpNandc:
..
..
@@ -28704,19 +28825,10 @@
28704
28825
 	.size	FlashWaitBusyScheduleEn, 4
28705
28826
 FlashWaitBusyScheduleEn:
28706
28827
 	.space	4
28707
-	.type	g_retryMode, %object
28708
-	.size	g_retryMode, 1
28709
-g_retryMode:
28710
-	.space	1
28711
-	.type	g_maxRegNum, %object
28712
-	.size	g_maxRegNum, 1
28713
-g_maxRegNum:
28714
-	.space	1
28715
28828
 	.type	gReadRetryInfo, %object
28716
28829
 	.size	gReadRetryInfo, 852
28717
28830
 gReadRetryInfo:
28718
28831
 	.space	852
28719
-	.space	2
28720
28832
 	.type	read_retry_cur_offset, %object
28721
28833
 	.size	read_retry_cur_offset, 4
28722
28834
 read_retry_cur_offset:
..
..
@@ -28838,7 +28950,6 @@
28838
28950
 	.size	c_ftl_nand_planes_per_die, 2
28839
28951
 c_ftl_nand_planes_per_die:
28840
28952
 	.space	2
28841
-	.space	2
28842
28953
 	.type	p_plane_order_table, %object
28843
28954
 	.size	p_plane_order_table, 32
28844
28955
 p_plane_order_table:
..
..
@@ -28890,6 +29001,7 @@
28890
29001
 	.type	c_ftl_nand_reserved_blks, %object
28891
29002
 	.size	c_ftl_nand_reserved_blks, 2
28892
29003
 c_ftl_nand_reserved_blks:
29004
+	.space	2
28893
29005
 	.space	2
28894
29006
 	.type	DeviceCapacity, %object
28895
29007
 	.size	DeviceCapacity, 4
..
..
@@ -29038,10 +29150,6 @@
29038
29150
 	.size	g_VaildLpn, 4
29039
29151
 g_VaildLpn:
29040
29152
 	.space	4
29041
-	.type	p_blk_mode_table, %object
29042
-	.size	p_blk_mode_table, 4
29043
-p_blk_mode_table:
29044
-	.space	4
29045
29153
 	.type	g_totle_read_page_count, %object
29046
29154
 	.size	g_totle_read_page_count, 4
29047
29155
 g_totle_read_page_count:
..
..
@@ -29115,14 +29223,14 @@
29115
29223
 	.size	g_gc_superblock, 48
29116
29224
 g_gc_superblock:
29117
29225
 	.space	48
29118
-	.type	g_all_blk_used_slc_mode, %object
29119
-	.size	g_all_blk_used_slc_mode, 4
29120
-g_all_blk_used_slc_mode:
29121
-	.space	4
29122
29226
 	.type	g_sys_ext_data, %object
29123
29227
 	.size	g_sys_ext_data, 512
29124
29228
 g_sys_ext_data:
29125
29229
 	.space	512
29230
+	.type	g_all_blk_used_slc_mode, %object
29231
+	.size	g_all_blk_used_slc_mode, 4
29232
+g_all_blk_used_slc_mode:
29233
+	.space	4
29126
29234
 	.type	g_gc_free_blk_threshold, %object
29127
29235
 	.size	g_gc_free_blk_threshold, 2
29128
29236
 g_gc_free_blk_threshold:
..
..
@@ -29404,6 +29512,14 @@
29404
29512
 	.size	RK29_NANDC_REG_BASE, 4
29405
29513
 RK29_NANDC_REG_BASE:
29406
29514
 	.space	4
29515
+	.type	ftl_dma32_buffer_size, %object
29516
+	.size	ftl_dma32_buffer_size, 4
29517
+ftl_dma32_buffer_size:
29518
+	.space	4
29519
+	.type	ftl_dma32_buffer, %object
29520
+	.size	ftl_dma32_buffer, 4
29521
+ftl_dma32_buffer:
29522
+	.space	4
29407
29523
 	.type	gFlashPageBuffer0, %object
29408
29524
 	.size	gFlashPageBuffer0, 4
29409
29525
 gFlashPageBuffer0:
..
..
@@ -29465,11 +29581,11 @@
29465
29581
 	.size	gMultiPageReadEn, 1
29466
29582
 gMultiPageReadEn:
29467
29583
 	.space	1
29468
-	.space	2
29469
29584
 	.type	FbbtBlk, %object
29470
29585
 	.size	FbbtBlk, 16
29471
29586
 FbbtBlk:
29472
29587
 	.space	16
29588
+	.space	2
29473
29589
 	.type	req_sys, %object
29474
29590
 	.size	req_sys, 36
29475
29591
 req_sys:
..
..
@@ -29486,11 +29602,6 @@
29486
29602
 	.size	g_ect_tbl_power_up_flush, 2
29487
29603
 g_ect_tbl_power_up_flush:
29488
29604
 	.space	2
29489
-	.space	2
29490
-	.type	check_valid_page_count_table, %object
29491
-	.size	check_valid_page_count_table, 8192
29492
-check_valid_page_count_table:
29493
-	.space	8192
29494
29605
 	.type	g_power_lost_ecc_error_blk, %object
29495
29606
 	.size	g_power_lost_ecc_error_blk, 2
29496
29607
 g_power_lost_ecc_error_blk:
..
..
@@ -29498,6 +29609,7 @@
29498
29609
 	.type	g_power_lost_recovery_flag, %object
29499
29610
 	.size	g_power_lost_recovery_flag, 2
29500
29611
 g_power_lost_recovery_flag:
29612
+	.space	2
29501
29613
 	.space	2
29502
29614
 	.type	g_recovery_page_num, %object
29503
29615
 	.size	g_recovery_page_num, 4
..
..
@@ -29601,6 +29713,10 @@
29601
29713
 	.size	g_vendor, 4
29602
29714
 g_vendor:
29603
29715
 	.space	4
29716
+	.type	check_valid_page_count_table, %object
29717
+	.size	check_valid_page_count_table, 8192
29718
+check_valid_page_count_table:
29719
+	.space	8192
29604
29720
 	.type	g_gc_refresh_block_temp_tbl, %object
29605
29721
 	.size	g_gc_refresh_block_temp_tbl, 34
29606
29722
 g_gc_refresh_block_temp_tbl:
..
..
@@ -29630,3 +29746,419 @@
29630
29746
 	.size	gFlashSdrModeEn, 1
29631
29747
 gFlashSdrModeEn:
29632
29748
 	.space	1
29749
+	.section	.rodata.str1.1,"aMS",%progbits,1
29750
+.LC1:
29751
+	.ascii	"FlashEraseBlocks pageAddr error %x\012\000"
29752
+.LC2:
29753
+	.ascii	"phyBlk = 0x%x die = %d block_in_die = 0x%x 0x%8x\012"
29754
+	.ascii	"\000"
29755
+.LC3:
29756
+	.ascii	"FtlFreeSysBlkQueueOut free count = %d\012\000"
29757
+.LC4:
29758
+	.ascii	"FtlFreeSysBlkQueueOut = %x, free count = %d, error\012"
29759
+	.ascii	"\000"
29760
+.LC5:
29761
+	.ascii	"FtlFreeSysBlkQueueOut = %x, free count = %d\012\000"
29762
+.LC6:
29763
+	.ascii	"FLASH INFO:\012\000"
29764
+.LC7:
29765
+	.ascii	"FLASH ID: %x\012\000"
29766
+.LC8:
29767
+	.ascii	"Device Capacity: %d MB\012\000"
29768
+.LC9:
29769
+	.ascii	"FMWAIT: %x %x %x %x\012\000"
29770
+.LC10:
29771
+	.ascii	"FTL INFO:\012\000"
29772
+.LC11:
29773
+	.ascii	"g_MaxLpn = 0x%x\012\000"
29774
+.LC12:
29775
+	.ascii	"g_VaildLpn = 0x%x\012\000"
29776
+.LC13:
29777
+	.ascii	"read_page_count = 0x%x\012\000"
29778
+.LC14:
29779
+	.ascii	"discard_page_count = 0x%x\012\000"
29780
+.LC15:
29781
+	.ascii	"write_page_count = 0x%x\012\000"
29782
+.LC16:
29783
+	.ascii	"cache_write_count = 0x%x\012\000"
29784
+.LC17:
29785
+	.ascii	"l2p_write_count = 0x%x\012\000"
29786
+.LC18:
29787
+	.ascii	"gc_page_count = 0x%x\012\000"
29788
+.LC19:
29789
+	.ascii	"totle_write = %d MB\012\000"
29790
+.LC20:
29791
+	.ascii	"totle_read = %d MB\012\000"
29792
+.LC21:
29793
+	.ascii	"GSV = 0x%x\012\000"
29794
+.LC22:
29795
+	.ascii	"GDV = 0x%x\012\000"
29796
+.LC23:
29797
+	.ascii	"bad blk num = %d %d\012\000"
29798
+.LC24:
29799
+	.ascii	"free_superblocks = 0x%x\012\000"
29800
+.LC25:
29801
+	.ascii	"mlc_EC = 0x%x\012\000"
29802
+.LC26:
29803
+	.ascii	"slc_EC = 0x%x\012\000"
29804
+.LC27:
29805
+	.ascii	"avg_EC = 0x%x\012\000"
29806
+.LC28:
29807
+	.ascii	"sys_EC = 0x%x\012\000"
29808
+.LC29:
29809
+	.ascii	"max_EC = 0x%x\012\000"
29810
+.LC30:
29811
+	.ascii	"min_EC = 0x%x\012\000"
29812
+.LC31:
29813
+	.ascii	"PLT = 0x%x\012\000"
29814
+.LC32:
29815
+	.ascii	"POT = 0x%x\012\000"
29816
+.LC33:
29817
+	.ascii	"MaxSector = 0x%x\012\000"
29818
+.LC34:
29819
+	.ascii	"init_sys_blks_pp = 0x%x\012\000"
29820
+.LC35:
29821
+	.ascii	"sys_blks_pp = 0x%x\012\000"
29822
+.LC36:
29823
+	.ascii	"free sysblock = 0x%x\012\000"
29824
+.LC37:
29825
+	.ascii	"data_blks_pp = 0x%x\012\000"
29826
+.LC38:
29827
+	.ascii	"data_op_blks_pp = 0x%x\012\000"
29828
+.LC39:
29829
+	.ascii	"max_data_blks = 0x%x\012\000"
29830
+.LC40:
29831
+	.ascii	"Sys.id = 0x%x\012\000"
29832
+.LC41:
29833
+	.ascii	"Bbt.id = 0x%x\012\000"
29834
+.LC42:
29835
+	.ascii	"ACT.page = 0x%x\012\000"
29836
+.LC43:
29837
+	.ascii	"ACT.plane = 0x%x\012\000"
29838
+.LC44:
29839
+	.ascii	"ACT.id = 0x%x\012\000"
29840
+.LC45:
29841
+	.ascii	"ACT.mode = 0x%x\012\000"
29842
+.LC46:
29843
+	.ascii	"ACT.a_pages = 0x%x\012\000"
29844
+.LC47:
29845
+	.ascii	"ACT VPC = 0x%x\012\000"
29846
+.LC48:
29847
+	.ascii	"BUF.page = 0x%x\012\000"
29848
+.LC49:
29849
+	.ascii	"BUF.plane = 0x%x\012\000"
29850
+.LC50:
29851
+	.ascii	"BUF.id = 0x%x\012\000"
29852
+.LC51:
29853
+	.ascii	"BUF.mode = 0x%x\012\000"
29854
+.LC52:
29855
+	.ascii	"BUF.a_pages = 0x%x\012\000"
29856
+.LC53:
29857
+	.ascii	"BUF VPC = 0x%x\012\000"
29858
+.LC54:
29859
+	.ascii	"TMP.page = 0x%x\012\000"
29860
+.LC55:
29861
+	.ascii	"TMP.plane = 0x%x\012\000"
29862
+.LC56:
29863
+	.ascii	"TMP.id = 0x%x\012\000"
29864
+.LC57:
29865
+	.ascii	"TMP.mode = 0x%x\012\000"
29866
+.LC58:
29867
+	.ascii	"TMP.a_pages = 0x%x\012\000"
29868
+.LC59:
29869
+	.ascii	"GC.page = 0x%x\012\000"
29870
+.LC60:
29871
+	.ascii	"GC.plane = 0x%x\012\000"
29872
+.LC61:
29873
+	.ascii	"GC.id = 0x%x\012\000"
29874
+.LC62:
29875
+	.ascii	"GC.mode = 0x%x\012\000"
29876
+.LC63:
29877
+	.ascii	"GC.a_pages = 0x%x\012\000"
29878
+.LC64:
29879
+	.ascii	"WR_CHK = 0x%x %x %x %x\012\000"
29880
+.LC65:
29881
+	.ascii	"Read Err = 0x%x\012\000"
29882
+.LC66:
29883
+	.ascii	"Prog Err = 0x%x\012\000"
29884
+.LC67:
29885
+	.ascii	"gc_free_blk_th= 0x%x\012\000"
29886
+.LC68:
29887
+	.ascii	"gc_merge_free_blk_th= 0x%x\012\000"
29888
+.LC69:
29889
+	.ascii	"gc_skip_write_count= 0x%x\012\000"
29890
+.LC70:
29891
+	.ascii	"gc_blk_index= 0x%x\012\000"
29892
+.LC71:
29893
+	.ascii	"free min EC= 0x%x\012\000"
29894
+.LC72:
29895
+	.ascii	"free max EC= 0x%x\012\000"
29896
+.LC73:
29897
+	.ascii	"GC__SB VPC = 0x%x\012\000"
29898
+.LC74:
29899
+	.ascii	"%d. [0x%x]=0x%x 0x%x  0x%x\012\000"
29900
+.LC75:
29901
+	.ascii	"free %d. [0x%x] 0x%x  0x%x\012\000"
29902
+.LC76:
29903
+	.ascii	"FTL version: 5.0.63 20210616\000"
29904
+.LC77:
29905
+	.ascii	"%s\012\000"
29906
+.LC78:
29907
+	.ascii	"swblk %x ,avg = %x max= %x vpc= %x,ec=%x ,max ec=%x"
29908
+	.ascii	"\012\000"
29909
+.LC79:
29910
+	.ascii	"FtlGcRefreshBlock  0x%x\012\000"
29911
+.LC80:
29912
+	.ascii	"FtlGcMarkBadPhyBlk %d 0x%x\012\000"
29913
+.LC81:
29914
+	.ascii	"%s error allocating memory. return -1\012\000"
29915
+.LC82:
29916
+	.ascii	"%s %p:0x%x:\000"
29917
+.LC83:
29918
+	.ascii	"%x \000"
29919
+.LC84:
29920
+	.ascii	"\000"
29921
+.LC85:
29922
+	.ascii	"otp error! %d\000"
29923
+.LC86:
29924
+	.ascii	"rr\000"
29925
+.LC87:
29926
+	.ascii	"%d statReg->V6.mtrans_cnt=%d flReg.V6.page_num=%d\012"
29927
+	.ascii	"\000"
29928
+.LC88:
29929
+	.ascii	"nandc:\000"
29930
+.LC89:
29931
+	.ascii	"%d flReg.d32=%x %x\012\000"
29932
+.LC90:
29933
+	.ascii	"sdr read ok %x ecc=%d\012\000"
29934
+.LC91:
29935
+	.ascii	"sync para %d\012\000"
29936
+.LC92:
29937
+	.ascii	"TOG mode Read error %x %x\012\000"
29938
+.LC93:
29939
+	.ascii	"read retry status %x %x %x\012\000"
29940
+.LC94:
29941
+	.ascii	"micron RR %d row=%x,count %d,status=%d\012\000"
29942
+.LC95:
29943
+	.ascii	"samsung RR %d row=%x,count %d,status=%d\012\000"
29944
+.LC96:
29945
+	.ascii	"ECC:%d\012\000"
29946
+.LC97:
29947
+	.ascii	"No.%d FLASH ID:%x %x %x %x %x %x\012\000"
29948
+.LC98:
29949
+	.ascii	"FlashLoadPhyInfo fail %x!!\012\000"
29950
+.LC99:
29951
+	.ascii	"Read pageadd=%x  ecc=%x err=%x\012\000"
29952
+.LC100:
29953
+	.ascii	"data:\000"
29954
+.LC101:
29955
+	.ascii	"spare:\000"
29956
+.LC102:
29957
+	.ascii	"ReadRetry pageadd=%x ecc=%x err=%x\012\000"
29958
+.LC103:
29959
+	.ascii	"FLFB:%d %d\012\000"
29960
+.LC104:
29961
+	.ascii	"prog error: = %x\012\000"
29962
+.LC105:
29963
+	.ascii	"prog read error: = %x\012\000"
29964
+.LC106:
29965
+	.ascii	"prog read REFRESH: = %x\012\000"
29966
+.LC107:
29967
+	.ascii	"prog read s error: = %x %x %x\012\000"
29968
+.LC108:
29969
+	.ascii	"prog read d error: = %x %x %x\012\000"
29970
+.LC109:
29971
+	.ascii	"id = %x,%x addr= %x,spare= %x %x %x %x data= %x\012"
29972
+	.ascii	"\000"
29973
+.LC110:
29974
+	.ascii	"...%s enter...\012\000"
29975
+.LC111:
29976
+	.ascii	"superBlkID = %x vpc=%x\012\000"
29977
+.LC112:
29978
+	.ascii	"flashmode = %x pagenum = %x %x\012\000"
29979
+.LC113:
29980
+	.ascii	"id = %x,%x addr= %x,spare= %x %x %x %x data=%x %x\012"
29981
+	.ascii	"\000"
29982
+.LC114:
29983
+	.ascii	"blk = %x vpc=%x mode = %x\012\000"
29984
+.LC115:
29985
+	.ascii	"mlc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
29986
+	.ascii	"%x\012\000"
29987
+.LC116:
29988
+	.ascii	"slc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
29989
+	.ascii	"%x\012\000"
29990
+.LC117:
29991
+	.ascii	"ftl_scan_all_ppa blk %x page %x flag: %x\012\000"
29992
+.LC118:
29993
+	.ascii	"ftl_scan_all_ppa blk %x page %x flag: %x .........."
29994
+	.ascii	"..... is bad block\012\000"
29995
+.LC119:
29996
+	.ascii	"addr= %x, status= %d,spare= %x %x %x %x data=%x %x\012"
29997
+	.ascii	"\000"
29998
+.LC120:
29999
+	.ascii	"%s finished\012\000"
30000
+.LC121:
30001
+	.ascii	"FlashMakeFactorBbt %d\012\000"
30002
+.LC122:
30003
+	.ascii	"bad block:%d %d\012\000"
30004
+.LC123:
30005
+	.ascii	"FMFB:%d %d\012\000"
30006
+.LC124:
30007
+	.ascii	"E:bad block:%d\012\000"
30008
+.LC125:
30009
+	.ascii	"FMFB:Save %d %d\012\000"
30010
+.LC126:
30011
+	.ascii	"FtlBbmTblFlush id=%x,page=%x,previd=%x cnt=%d\012\000"
30012
+.LC127:
30013
+	.ascii	"FtlBbmTblFlush error:%x\012\000"
30014
+.LC128:
30015
+	.ascii	"FtlBbmTblFlush error = %x error count = %d\012\000"
30016
+.LC129:
30017
+	.ascii	"FtlGcFreeBadSuperBlk 0x%x\012\000"
30018
+.LC130:
30019
+	.ascii	"decrement_vpc_count %x = %d\012\000"
30020
+.LC131:
30021
+	.ascii	"decrement_vpc_count %x = %d in free list\012\000"
30022
+.LC132:
30023
+	.ascii	"FtlVpcTblFlush error = %x error count = %d\012\000"
30024
+.LC133:
30025
+	.ascii	"page map lost: %x %x\012\000"
30026
+.LC134:
30027
+	.ascii	"FtlMapWritePage error = %x\012\000"
30028
+.LC135:
30029
+	.ascii	"FtlMapWritePage error = %x error count = %d\012\000"
30030
+.LC136:
30031
+	.ascii	"FtlVendorPartRead refresh = %x phyAddr = %x\012\000"
30032
+.LC137:
30033
+	.ascii	"no ect\000"
30034
+.LC138:
30035
+	.ascii	"slc mode\000"
30036
+.LC139:
30037
+	.ascii	"BBT:\000"
30038
+.LC140:
30039
+	.ascii	"region_id = %x phyAddr = %x\012\000"
30040
+.LC141:
30041
+	.ascii	"map_ppn:\000"
30042
+.LC142:
30043
+	.ascii	"load_l2p_region refresh = %x phyAddr = %x\012\000"
30044
+.LC143:
30045
+	.ascii	"FtlCheckVpc2 %x = %x  %x\012\000"
30046
+.LC144:
30047
+	.ascii	"free blk vpc error %x = %x  %x\012\000"
30048
+.LC145:
30049
+	.ascii	"error_flag %x\012\000"
30050
+.LC146:
30051
+	.ascii	"Ftlscanalldata = %x\012\000"
30052
+.LC147:
30053
+	.ascii	"scan lpa = %x ppa= %x\012\000"
30054
+.LC148:
30055
+	.ascii	"lba = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
30056
+	.ascii	"\000"
30057
+.LC149:
30058
+	.ascii	"RSB refresh addr %x\012\000"
30059
+.LC150:
30060
+	.ascii	"spuer block %x vpn is 0\012 \000"
30061
+.LC151:
30062
+	.ascii	"g_recovery_ppa %x ver %x\012 \000"
30063
+.LC152:
30064
+	.ascii	"FtlCheckVpc %x = %x  %x\012\000"
30065
+.LC153:
30066
+	.ascii	"FtlGcScanTempBlk Error ID %x %x!!!!!!! \012\000"
30067
+.LC154:
30068
+	.ascii	"FtlGcScanTempBlkError ID %x %x!!!!!!!\012\000"
30069
+.LC155:
30070
+	.ascii	"GC des block %x done\012\000"
30071
+.LC156:
30072
+	.ascii	"too many bad block  = %d %d\012\000"
30073
+.LC157:
30074
+	.ascii	"%d GC datablk  = %x vpc %x %x\012\000"
30075
+.LC158:
30076
+	.ascii	"SWL %x, FSB = %x vpc= %x,ec=%x th=%x\012\000"
30077
+.LC159:
30078
+	.ascii	"Ftlwrite decrement_vpc_count %x = %d\012\000"
30079
+.LC160:
30080
+	.ascii	"rk_ftl_de_init %x\012\000"
30081
+.LC161:
30082
+	.ascii	"...%s: no bad block mapping table, format device\012"
30083
+	.ascii	"\000"
30084
+.LC162:
30085
+	.ascii	"...%s FtlSysBlkInit error ,format device!\012\000"
30086
+.LC163:
30087
+	.ascii	"FtlInit %x\012\000"
30088
+.LC164:
30089
+	.ascii	"fix power lost blk = %x vpc=%x\012\000"
30090
+.LC165:
30091
+	.ascii	"erase power lost blk = %x vpc=%x\012\000"
30092
+.LC166:
30093
+	.ascii	"FtlWrite: lpa error:%x %x\012\000"
30094
+.LC167:
30095
+	.ascii	"id = %x,%x addr= %x,spare= %x %x %x %x data = %x\012"
30096
+	.ascii	"\000"
30097
+.LC168:
30098
+	.ascii	":\000"
30099
+.LC169:
30100
+	.ascii	"phyBlk = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
30101
+	.ascii	"\000"
30102
+.LC170:
30103
+	.ascii	"Mblk:\000"
30104
+.LC171:
30105
+	.ascii	"L2P:\000"
30106
+.LC172:
30107
+	.ascii	"L2PC:\000"
30108
+.LC173:
30109
+	.ascii	"write_idblock fix data %x %x\012\000"
30110
+.LC174:
30111
+	.ascii	"idblk:\000"
30112
+.LC175:
30113
+	.ascii	"idb reverse %x %x\012\000"
30114
+.LC176:
30115
+	.ascii	"write_idblock totle_sec %x %x %x %x\012\000"
30116
+.LC177:
30117
+	.ascii	"IDBlockWriteData %x %x\012\000"
30118
+.LC178:
30119
+	.ascii	"IDBlockWriteData %x %x ret= %x\012\000"
30120
+.LC179:
30121
+	.ascii	"IdBlockReadData %x %x\012\000"
30122
+.LC180:
30123
+	.ascii	"IdBlockReadData %x %x ret= %x\012\000"
30124
+.LC181:
30125
+	.ascii	"write and check error:%d idb=%x,offset=%x,r=%x,w=%x"
30126
+	.ascii	"\012\000"
30127
+.LC182:
30128
+	.ascii	"write\000"
30129
+.LC183:
30130
+	.ascii	"read\000"
30131
+.LC184:
30132
+	.ascii	"write_idblock error %d\012\000"
30133
+.LC185:
30134
+	.ascii	"wl_lba %p %x %x %x\012\000"
30135
+.LC186:
30136
+	.ascii	"RKNAND_GET_DRM_KEY\012\000"
30137
+.LC187:
30138
+	.ascii	"rk_copy_from_user error\012\000"
30139
+.LC188:
30140
+	.ascii	"RKNAND_STORE_DRM_KEY\012\000"
30141
+.LC189:
30142
+	.ascii	"RKNAND_DIASBLE_SECURE_BOOT\012\000"
30143
+.LC190:
30144
+	.ascii	"RKNAND_ENASBLE_SECURE_BOOT\012\000"
30145
+.LC191:
30146
+	.ascii	"RKNAND_GET_SN_SECTOR\012\000"
30147
+.LC192:
30148
+	.ascii	"RKNAND_LOADER_UNLOCK\012\000"
30149
+.LC193:
30150
+	.ascii	"RKNAND_LOADER_STATUS\012\000"
30151
+.LC194:
30152
+	.ascii	"RKNAND_LOADER_LOCK\012\000"
30153
+.LC195:
30154
+	.ascii	"LockKey not match %d\012\000"
30155
+.LC196:
30156
+	.ascii	"RKNAND_GET_VENDOR_SECTOR\012\000"
30157
+.LC197:
30158
+	.ascii	"RKNAND_STORE_VENDOR_SECTOR\012\000"
30159
+.LC198:
30160
+	.ascii	"return ret = %lx\012\000"
30161
+.LC199:
30162
+	.ascii	"secureBootEn check error\012\000"
30163
+.LC200:
30164
+	.ascii	"\0013vendor storage %x,%x,%x\012\000"