forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/pwm/pwm-mxs.c
....@@ -9,7 +9,6 @@
99 #include <linux/kernel.h>
1010 #include <linux/module.h>
1111 #include <linux/of.h>
12
-#include <linux/of_address.h>
1312 #include <linux/platform_device.h>
1413 #include <linux/pwm.h>
1514 #include <linux/slab.h>
....@@ -25,12 +24,16 @@
2524 #define  PERIOD_PERIOD(p)	((p) & 0xffff)
2625 #define  PERIOD_PERIOD_MAX	0x10000
2726 #define  PERIOD_ACTIVE_HIGH	(3 << 16)
27
+#define  PERIOD_ACTIVE_LOW	(2 << 16)
28
+#define  PERIOD_INACTIVE_HIGH	(3 << 18)
2829 #define  PERIOD_INACTIVE_LOW	(2 << 18)
30
+#define  PERIOD_POLARITY_NORMAL	(PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW)
31
+#define  PERIOD_POLARITY_INVERSE	(PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH)
2932 #define  PERIOD_CDIV(div)	(((div) & 0x7) << 20)
3033 #define  PERIOD_CDIV_MAX	8
3134 
32
-static const unsigned int cdiv[PERIOD_CDIV_MAX] = {
33
-	1, 2, 4, 8, 16, 64, 256, 1024
35
+static const u8 cdiv_shift[PERIOD_CDIV_MAX] = {
36
+	0, 1, 2, 3, 4, 6, 8, 10
3437 };
3538 
3639 struct mxs_pwm_chip {
....@@ -41,19 +44,34 @@
4144 
4245 #define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
4346 
44
-static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
45
-			  int duty_ns, int period_ns)
47
+static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
48
+			 const struct pwm_state *state)
4649 {
4750 	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
4851 	int ret, div = 0;
4952 	unsigned int period_cycles, duty_cycles;
5053 	unsigned long rate;
5154 	unsigned long long c;
55
+	unsigned int pol_bits;
56
+
57
+	/*
58
+	 * If the PWM channel is disabled, make sure to turn on the
59
+	 * clock before calling clk_get_rate() and writing to the
60
+	 * registers. Otherwise, just keep it enabled.
61
+	 */
62
+	if (!pwm_is_enabled(pwm)) {
63
+		ret = clk_prepare_enable(mxs->clk);
64
+		if (ret)
65
+			return ret;
66
+	}
67
+
68
+	if (!state->enabled && pwm_is_enabled(pwm))
69
+		writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
5270 
5371 	rate = clk_get_rate(mxs->clk);
5472 	while (1) {
55
-		c = rate / cdiv[div];
56
-		c = c * period_ns;
73
+		c = rate >> cdiv_shift[div];
74
+		c = c * state->period;
5775 		do_div(c, 1000000000);
5876 		if (c < PERIOD_PERIOD_MAX)
5977 			break;
....@@ -63,62 +81,40 @@
6381 	}
6482 
6583 	period_cycles = c;
66
-	c *= duty_ns;
67
-	do_div(c, period_ns);
84
+	c *= state->duty_cycle;
85
+	do_div(c, state->period);
6886 	duty_cycles = c;
6987 
7088 	/*
71
-	 * If the PWM channel is disabled, make sure to turn on the clock
72
-	 * before writing the register. Otherwise, keep it enabled.
89
+	 * The data sheet the says registers must be written to in
90
+	 * this order (ACTIVEn, then PERIODn). Also, the new settings
91
+	 * only take effect at the beginning of a new period, avoiding
92
+	 * glitches.
7393 	 */
74
-	if (!pwm_is_enabled(pwm)) {
75
-		ret = clk_prepare_enable(mxs->clk);
76
-		if (ret)
77
-			return ret;
78
-	}
7994 
95
+	pol_bits = state->polarity == PWM_POLARITY_NORMAL ?
96
+		PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE;
8097 	writel(duty_cycles << 16,
81
-			mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
82
-	writel(PERIOD_PERIOD(period_cycles) | PERIOD_ACTIVE_HIGH |
83
-	       PERIOD_INACTIVE_LOW | PERIOD_CDIV(div),
84
-			mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
98
+	       mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
99
+	writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div),
100
+	       mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
85101 
86
-	/*
87
-	 * If the PWM is not enabled, turn the clock off again to save power.
88
-	 */
89
-	if (!pwm_is_enabled(pwm))
102
+	if (state->enabled) {
103
+		if (!pwm_is_enabled(pwm)) {
104
+			/*
105
+			 * The clock was enabled above. Just enable
106
+			 * the channel in the control register.
107
+			 */
108
+			writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
109
+		}
110
+	} else {
90111 		clk_disable_unprepare(mxs->clk);
91
-
112
+	}
92113 	return 0;
93
-}
94
-
95
-static int mxs_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
96
-{
97
-	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
98
-	int ret;
99
-
100
-	ret = clk_prepare_enable(mxs->clk);
101
-	if (ret)
102
-		return ret;
103
-
104
-	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
105
-
106
-	return 0;
107
-}
108
-
109
-static void mxs_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
110
-{
111
-	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
112
-
113
-	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
114
-
115
-	clk_disable_unprepare(mxs->clk);
116114 }
117115 
118116 static const struct pwm_ops mxs_pwm_ops = {
119
-	.config = mxs_pwm_config,
120
-	.enable = mxs_pwm_enable,
121
-	.disable = mxs_pwm_disable,
117
+	.apply = mxs_pwm_apply,
122118 	.owner = THIS_MODULE,
123119 };
124120 
....@@ -126,15 +122,13 @@
126122 {
127123 	struct device_node *np = pdev->dev.of_node;
128124 	struct mxs_pwm_chip *mxs;
129
-	struct resource *res;
130125 	int ret;
131126 
132127 	mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
133128 	if (!mxs)
134129 		return -ENOMEM;
135130 
136
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
137
-	mxs->base = devm_ioremap_resource(&pdev->dev, res);
131
+	mxs->base = devm_platform_ioremap_resource(pdev, 0);
138132 	if (IS_ERR(mxs->base))
139133 		return PTR_ERR(mxs->base);
140134 
....@@ -144,6 +138,8 @@
144138 
145139 	mxs->chip.dev = &pdev->dev;
146140 	mxs->chip.ops = &mxs_pwm_ops;
141
+	mxs->chip.of_xlate = of_pwm_xlate_with_flags;
142
+	mxs->chip.of_pwm_n_cells = 3;
147143 	mxs->chip.base = -1;
148144 
149145 	ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
....@@ -151,6 +147,11 @@
151147 		dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
152148 		return ret;
153149 	}
150
+
151
+	/* FIXME: Only do this if the PWM isn't already running */
152
+	ret = stmp_reset_block(mxs->base);
153
+	if (ret)
154
+		return dev_err_probe(&pdev->dev, ret, "failed to reset PWM\n");
154155 
155156 	ret = pwmchip_add(&mxs->chip);
156157 	if (ret < 0) {
....@@ -160,15 +161,7 @@
160161 
161162 	platform_set_drvdata(pdev, mxs);
162163 
163
-	ret = stmp_reset_block(mxs->base);
164
-	if (ret)
165
-		goto pwm_remove;
166
-
167164 	return 0;
168
-
169
-pwm_remove:
170
-	pwmchip_remove(&mxs->chip);
171
-	return ret;
172165 }
173166 
174167 static int mxs_pwm_remove(struct platform_device *pdev)