~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,34 +1,9 @@
	1	+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
1	2	/*
2		- * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
3		- * Copyright (c) 2016 Vadim Pasternak <vadimp@mellanox.com>
	3	+ * Mellanox platform driver
4	4	*
5		- * Redistribution and use in source and binary forms, with or without
6		- * modification, are permitted provided that the following conditions are met:
7		- *
8		- * 1. Redistributions of source code must retain the above copyright
9		- * notice, this list of conditions and the following disclaimer.
10		- * 2. Redistributions in binary form must reproduce the above copyright
11		- * notice, this list of conditions and the following disclaimer in the
12		- * documentation and/or other materials provided with the distribution.
13		- * 3. Neither the names of the copyright holders nor the names of its
14		- * contributors may be used to endorse or promote products derived from
15		- * this software without specific prior written permission.
16		- *
17		- * Alternatively, this software may be distributed under the terms of the
18		- * GNU General Public License ("GPL") version 2 as published by the Free
19		- * Software Foundation.
20		- *
21		- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22		- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23		- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24		- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25		- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26		- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27		- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28		- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29		- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30		- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31		- * POSSIBILITY OF SUCH DAMAGE.
	5	+ * Copyright (C) 2016-2018 Mellanox Technologies
	6	+ * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
32	7	*/
33	8
34	9	#include <linux/device.h>
..	..	@@ -49,12 +24,23 @@
49	24	#define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
50	25	#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
51	26	#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
	27	+#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
	28	+#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
	29	+#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04
	30	+#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06
	31	+#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08
	32	+#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a
52	33	#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
	34	+#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
	35	+#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
53	36	#define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
54	37	#define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
55	38	#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
56	39	#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
57	40	#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
	41	+#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a
	42	+#define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b
	43	+#define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e
58	44	#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
59	45	#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
60	46	#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
..	..	@@ -64,6 +50,10 @@
64	50	#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
65	51	#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
66	52	#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
	53	+#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42
	54	+#define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43
	55	+#define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44
	56	+#define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45
67	57	#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
68	58	#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51
69	59	#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52
..	..	@@ -76,6 +66,21 @@
76	66	#define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
77	67	#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
78	68	#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
	69	+#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
	70	+#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8
	71	+#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9
	72	+#define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb
	73	+#define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd
	74	+#define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce
	75	+#define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf
	76	+#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1
	77	+#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2
	78	+#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3
	79	+#define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde
	80	+#define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf
	81	+#define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0
	82	+#define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1
	83	+#define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2
79	84	#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
80	85	#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
81	86	#define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5
..	..	@@ -89,9 +94,17 @@
89	94	#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
90	95	#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
91	96	#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
	97	+#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
	98	+#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
	99	+#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
	100	+#define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8
	101	+#define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9
	102	+#define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb
	103	+#define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc
92	104	#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
93	105	#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
94	106	#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
	107	+#define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc
95	108
96	109	#define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL
97	110	#define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
..	..	@@ -99,6 +112,9 @@
99	112	MLXPLAT_CPLD_LPC_PIO_OFFSET)
100	113	#define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
101	114	MLXPLAT_CPLD_LPC_I2C_CH2_OFF) \| \
	115	+ MLXPLAT_CPLD_LPC_PIO_OFFSET)
	116	+#define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
	117	+ MLXPLAT_CPLD_LPC_I2C_CH3_OFF) \| \
102	118	MLXPLAT_CPLD_LPC_PIO_OFFSET)
103	119
104	120	/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
..	..	@@ -111,20 +127,34 @@
111	127	MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
112	128	#define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01
113	129	#define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
	130	+#define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
114	131	#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
	132	+#define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6)
115	133	#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
116	134	#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
	135	+#define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0)
	136	+#define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0)
117	137	#define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
118	138	#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0)
119	139	#define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0)
120	140	#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
121	141	#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
	142	+#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
	143	+#define MLXPLAT_CPLD_I2C_CAP_BIT 0x04
	144	+#define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT)
	145	+
	146	+/* Masks for aggregation for comex carriers */
	147	+#define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1)
	148	+#define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF \| \
	149	+ MLXPLAT_CPLD_AGGR_MASK_CARRIER)
	150	+#define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1
122	151
123	152	/* Default I2C parent bus number */
124	153	#define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1
125	154
126	155	/* Maximum number of possible physical buses equipped on system */
127	156	#define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16
	157	+#define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24
128	158
129	159	/* Number of channels in group */
130	160	#define MLXPLAT_CPLD_GRP_CHNL_NUM 8
..	..	@@ -132,9 +162,10 @@
132	162	/* Start channel numbers */
133	163	#define MLXPLAT_CPLD_CH1 2
134	164	#define MLXPLAT_CPLD_CH2 10
	165	+#define MLXPLAT_CPLD_CH3 18
135	166
136	167	/* Number of LPC attached MUX platform devices */
137		-#define MLXPLAT_CPLD_LPC_MUX_DEVS 2
	168	+#define MLXPLAT_CPLD_LPC_MUX_DEVS 3
138	169
139	170	/* Hotplug devices adapter numbers */
140	171	#define MLXPLAT_CPLD_NR_NONE -1
..	..	@@ -145,6 +176,20 @@
145	176	#define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
146	177	#define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14
147	178
	179	+/* Masks and default values for watchdogs */
	180	+#define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)
	181	+#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))
	182	+
	183	+#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)
	184	+#define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0
	185	+#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
	186	+#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
	187	+#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
	188	+#define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6))
	189	+#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30
	190	+#define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600
	191	+#define MLXPLAT_CPLD_WD_MAX_DEVS 2
	192	+
148	193	/* mlxplat_priv - platform private data
149	194	* @pdev_i2c - i2c controller platform device
150	195	* @pdev_mux - array of mux platform devices
..	..	@@ -152,6 +197,8 @@
152	197	* @pdev_led - led platform devices
153	198	* @pdev_io_regs - register access platform devices
154	199	* @pdev_fan - FAN platform devices
	200	+ * @pdev_wd - array of watchdog platform devices
	201	+ * @regmap: device register map
155	202	*/
156	203	struct mlxplat_priv {
157	204	struct platform_device *pdev_i2c;
..	..	@@ -160,6 +207,8 @@
160	207	struct platform_device *pdev_led;
161	208	struct platform_device *pdev_io_regs;
162	209	struct platform_device *pdev_fan;
	210	+ struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS];
	211	+ void *regmap;
163	212	};
164	213
165	214	/* Regions for LPC I2C controller and LPC base register space */
..	..	@@ -171,6 +220,30 @@
171	220	MLXPLAT_CPLD_LPC_IO_RANGE,
172	221	"mlxplat_cpld_lpc_regs",
173	222	IORESOURCE_IO),
	223	+};
	224	+
	225	+/* Platform i2c next generation systems data */
	226	+static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = {
	227	+ {
	228	+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
	229	+ .mask = MLXPLAT_CPLD_I2C_CAP_MASK,
	230	+ .bit = MLXPLAT_CPLD_I2C_CAP_BIT,
	231	+ },
	232	+};
	233	+
	234	+static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = {
	235	+ {
	236	+ .data = mlxplat_mlxcpld_i2c_ng_items_data,
	237	+ },
	238	+};
	239	+
	240	+/* Platform next generation systems i2c data */
	241	+static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = {
	242	+ .items = mlxplat_mlxcpld_i2c_ng_items,
	243	+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
	244	+ .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
	245	+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET,
	246	+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C,
174	247	};
175	248
176	249	/* Platform default channels */
..	..	@@ -191,7 +264,7 @@
191	264	static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 };
192	265
193	266	/* Platform mux data */
194		-static struct i2c_mux_reg_platform_data mlxplat_mux_data[] = {
	267	+static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = {
195	268	{
196	269	.parent = 1,
197	270	.base_nr = MLXPLAT_CPLD_CH1,
..	..	@@ -211,6 +284,40 @@
211	284
212	285	};
213	286
	287	+/* Platform mux configuration variables */
	288	+static int mlxplat_max_adap_num;
	289	+static int mlxplat_mux_num;
	290	+static struct i2c_mux_reg_platform_data *mlxplat_mux_data;
	291	+
	292	+/* Platform extended mux data */
	293	+static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = {
	294	+ {
	295	+ .parent = 1,
	296	+ .base_nr = MLXPLAT_CPLD_CH1,
	297	+ .write_only = 1,
	298	+ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
	299	+ .reg_size = 1,
	300	+ .idle_in_use = 1,
	301	+ },
	302	+ {
	303	+ .parent = 1,
	304	+ .base_nr = MLXPLAT_CPLD_CH2,
	305	+ .write_only = 1,
	306	+ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3,
	307	+ .reg_size = 1,
	308	+ .idle_in_use = 1,
	309	+ },
	310	+ {
	311	+ .parent = 1,
	312	+ .base_nr = MLXPLAT_CPLD_CH3,
	313	+ .write_only = 1,
	314	+ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
	315	+ .reg_size = 1,
	316	+ .idle_in_use = 1,
	317	+ },
	318	+
	319	+};
	320	+
214	321	/* Platform hotplug devices */
215	322	static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
216	323	{
..	..	@@ -218,6 +325,15 @@
218	325	},
219	326	{
220	327	I2C_BOARD_INFO("dps460", 0x58),
	328	+ },
	329	+};
	330	+
	331	+static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = {
	332	+ {
	333	+ I2C_BOARD_INFO("dps460", 0x5b),
	334	+ },
	335	+ {
	336	+ I2C_BOARD_INFO("dps460", 0x5a),
221	337	},
222	338	};
223	339
..	..	@@ -233,6 +349,22 @@
233	349	},
234	350	{
235	351	I2C_BOARD_INFO("24c32", 0x50),
	352	+ },
	353	+};
	354	+
	355	+/* Platform hotplug comex carrier system family data */
	356	+static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = {
	357	+ {
	358	+ .label = "psu1",
	359	+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
	360	+ .mask = BIT(0),
	361	+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
	362	+ },
	363	+ {
	364	+ .label = "psu2",
	365	+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
	366	+ .mask = BIT(1),
	367	+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
236	368	},
237	369	};
238	370
..	..	@@ -348,6 +480,45 @@
348	480	},
349	481	};
350	482
	483	+static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = {
	484	+ {
	485	+ .data = mlxplat_mlxcpld_comex_psu_items_data,
	486	+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
	487	+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
	488	+ .mask = MLXPLAT_CPLD_PSU_MASK,
	489	+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data),
	490	+ .inversed = 1,
	491	+ .health = false,
	492	+ },
	493	+ {
	494	+ .data = mlxplat_mlxcpld_default_pwr_items_data,
	495	+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
	496	+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
	497	+ .mask = MLXPLAT_CPLD_PWR_MASK,
	498	+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data),
	499	+ .inversed = 0,
	500	+ .health = false,
	501	+ },
	502	+ {
	503	+ .data = mlxplat_mlxcpld_default_fan_items_data,
	504	+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
	505	+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
	506	+ .mask = MLXPLAT_CPLD_FAN_MASK,
	507	+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data),
	508	+ .inversed = 1,
	509	+ .health = false,
	510	+ },
	511	+ {
	512	+ .data = mlxplat_mlxcpld_default_asic_items_data,
	513	+ .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
	514	+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
	515	+ .mask = MLXPLAT_CPLD_ASIC_MASK,
	516	+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
	517	+ .inversed = 0,
	518	+ .health = true,
	519	+ },
	520	+};
	521	+
351	522	static
352	523	struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
353	524	.items = mlxplat_mlxcpld_default_items,
..	..	@@ -356,6 +527,16 @@
356	527	.mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
357	528	.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
358	529	.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
	530	+};
	531	+
	532	+static
	533	+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = {
	534	+ .items = mlxplat_mlxcpld_comex_items,
	535	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items),
	536	+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
	537	+ .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF,
	538	+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET,
	539	+ .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK,
359	540	};
360	541
361	542	static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
..	..	@@ -582,36 +763,48 @@
582	763	.label = "fan1",
583	764	.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
584	765	.mask = BIT(0),
	766	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	767	+ .bit = BIT(0),
585	768	.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
586	769	},
587	770	{
588	771	.label = "fan2",
589	772	.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
590	773	.mask = BIT(1),
	774	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	775	+ .bit = BIT(1),
591	776	.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
592	777	},
593	778	{
594	779	.label = "fan3",
595	780	.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
596	781	.mask = BIT(2),
	782	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	783	+ .bit = BIT(2),
597	784	.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
598	785	},
599	786	{
600	787	.label = "fan4",
601	788	.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
602	789	.mask = BIT(3),
	790	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	791	+ .bit = BIT(3),
603	792	.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
604	793	},
605	794	{
606	795	.label = "fan5",
607	796	.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
608	797	.mask = BIT(4),
	798	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	799	+ .bit = BIT(4),
609	800	.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
610	801	},
611	802	{
612	803	.label = "fan6",
613	804	.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
614	805	.mask = BIT(5),
	806	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	807	+ .bit = BIT(5),
615	808	.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
616	809	},
617	810	};
..	..	@@ -660,7 +853,117 @@
660	853	.items = mlxplat_mlxcpld_default_ng_items,
661	854	.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items),
662	855	.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
663		- .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
	856	+ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF \| MLXPLAT_CPLD_AGGR_MASK_COMEX,
	857	+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
	858	+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
	859	+};
	860	+
	861	+/* Platform hotplug extended system family data */
	862	+static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = {
	863	+ {
	864	+ .label = "psu1",
	865	+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
	866	+ .mask = BIT(0),
	867	+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
	868	+ },
	869	+ {
	870	+ .label = "psu2",
	871	+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
	872	+ .mask = BIT(1),
	873	+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
	874	+ },
	875	+ {
	876	+ .label = "psu3",
	877	+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
	878	+ .mask = BIT(2),
	879	+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
	880	+ },
	881	+ {
	882	+ .label = "psu4",
	883	+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
	884	+ .mask = BIT(3),
	885	+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
	886	+ },
	887	+};
	888	+
	889	+static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = {
	890	+ {
	891	+ .label = "pwr1",
	892	+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
	893	+ .mask = BIT(0),
	894	+ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
	895	+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
	896	+ },
	897	+ {
	898	+ .label = "pwr2",
	899	+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
	900	+ .mask = BIT(1),
	901	+ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
	902	+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
	903	+ },
	904	+ {
	905	+ .label = "pwr3",
	906	+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
	907	+ .mask = BIT(2),
	908	+ .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0],
	909	+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
	910	+ },
	911	+ {
	912	+ .label = "pwr4",
	913	+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
	914	+ .mask = BIT(3),
	915	+ .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1],
	916	+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
	917	+ },
	918	+};
	919	+
	920	+static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
	921	+ {
	922	+ .data = mlxplat_mlxcpld_ext_psu_items_data,
	923	+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
	924	+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
	925	+ .mask = MLXPLAT_CPLD_PSU_EXT_MASK,
	926	+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
	927	+ .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),
	928	+ .inversed = 1,
	929	+ .health = false,
	930	+ },
	931	+ {
	932	+ .data = mlxplat_mlxcpld_ext_pwr_items_data,
	933	+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
	934	+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
	935	+ .mask = MLXPLAT_CPLD_PWR_EXT_MASK,
	936	+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
	937	+ .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),
	938	+ .inversed = 0,
	939	+ .health = false,
	940	+ },
	941	+ {
	942	+ .data = mlxplat_mlxcpld_default_ng_fan_items_data,
	943	+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
	944	+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
	945	+ .mask = MLXPLAT_CPLD_FAN_NG_MASK,
	946	+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
	947	+ .inversed = 1,
	948	+ .health = false,
	949	+ },
	950	+ {
	951	+ .data = mlxplat_mlxcpld_default_asic_items_data,
	952	+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
	953	+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
	954	+ .mask = MLXPLAT_CPLD_ASIC_MASK,
	955	+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
	956	+ .inversed = 0,
	957	+ .health = true,
	958	+ },
	959	+};
	960	+
	961	+static
	962	+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
	963	+ .items = mlxplat_mlxcpld_ext_items,
	964	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items),
	965	+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
	966	+ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF \| MLXPLAT_CPLD_AGGR_MASK_COMEX,
664	967	.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
665	968	.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
666	969	};
..	..	@@ -814,9 +1117,127 @@
814	1117	.label = "fan1:green",
815	1118	.reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
816	1119	.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
	1120	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1121	+ .bit = BIT(0),
817	1122	},
818	1123	{
819	1124	.label = "fan1:orange",
	1125	+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
	1126	+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
	1127	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1128	+ .bit = BIT(0),
	1129	+ },
	1130	+ {
	1131	+ .label = "fan2:green",
	1132	+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
	1133	+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
	1134	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1135	+ .bit = BIT(1),
	1136	+ },
	1137	+ {
	1138	+ .label = "fan2:orange",
	1139	+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
	1140	+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
	1141	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1142	+ .bit = BIT(1),
	1143	+ },
	1144	+ {
	1145	+ .label = "fan3:green",
	1146	+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
	1147	+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
	1148	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1149	+ .bit = BIT(2),
	1150	+ },
	1151	+ {
	1152	+ .label = "fan3:orange",
	1153	+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
	1154	+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
	1155	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1156	+ .bit = BIT(2),
	1157	+ },
	1158	+ {
	1159	+ .label = "fan4:green",
	1160	+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
	1161	+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
	1162	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1163	+ .bit = BIT(3),
	1164	+ },
	1165	+ {
	1166	+ .label = "fan4:orange",
	1167	+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
	1168	+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
	1169	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1170	+ .bit = BIT(3),
	1171	+ },
	1172	+ {
	1173	+ .label = "fan5:green",
	1174	+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
	1175	+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
	1176	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1177	+ .bit = BIT(4),
	1178	+ },
	1179	+ {
	1180	+ .label = "fan5:orange",
	1181	+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
	1182	+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
	1183	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1184	+ .bit = BIT(4),
	1185	+ },
	1186	+ {
	1187	+ .label = "fan6:green",
	1188	+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
	1189	+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
	1190	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1191	+ .bit = BIT(5),
	1192	+ },
	1193	+ {
	1194	+ .label = "fan6:orange",
	1195	+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
	1196	+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
	1197	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1198	+ .bit = BIT(5),
	1199	+ },
	1200	+ {
	1201	+ .label = "uid:blue",
	1202	+ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
	1203	+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
	1204	+ },
	1205	+};
	1206	+
	1207	+static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
	1208	+ .data = mlxplat_mlxcpld_default_ng_led_data,
	1209	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
	1210	+};
	1211	+
	1212	+/* Platform led for Comex based 100GbE systems */
	1213	+static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = {
	1214	+ {
	1215	+ .label = "status:green",
	1216	+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
	1217	+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
	1218	+ },
	1219	+ {
	1220	+ .label = "status:red",
	1221	+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
	1222	+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
	1223	+ },
	1224	+ {
	1225	+ .label = "psu:green",
	1226	+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
	1227	+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
	1228	+ },
	1229	+ {
	1230	+ .label = "psu:red",
	1231	+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
	1232	+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
	1233	+ },
	1234	+ {
	1235	+ .label = "fan1:green",
	1236	+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
	1237	+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
	1238	+ },
	1239	+ {
	1240	+ .label = "fan1:red",
820	1241	.reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
821	1242	.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
822	1243	},
..	..	@@ -826,7 +1247,7 @@
826	1247	.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
827	1248	},
828	1249	{
829		- .label = "fan2:orange",
	1250	+ .label = "fan2:red",
830	1251	.reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
831	1252	.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
832	1253	},
..	..	@@ -836,7 +1257,7 @@
836	1257	.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
837	1258	},
838	1259	{
839		- .label = "fan3:orange",
	1260	+ .label = "fan3:red",
840	1261	.reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
841	1262	.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
842	1263	},
..	..	@@ -846,35 +1267,20 @@
846	1267	.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
847	1268	},
848	1269	{
849		- .label = "fan4:orange",
	1270	+ .label = "fan4:red",
850	1271	.reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
851	1272	.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
852	1273	},
853	1274	{
854		- .label = "fan5:green",
855		- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
	1275	+ .label = "uid:blue",
	1276	+ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
856	1277	.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
857		- },
858		- {
859		- .label = "fan5:orange",
860		- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
861		- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
862		- },
863		- {
864		- .label = "fan6:green",
865		- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
866		- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
867		- },
868		- {
869		- .label = "fan6:orange",
870		- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
871		- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
872	1278	},
873	1279	};
874	1280
875		-static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
876		- .data = mlxplat_mlxcpld_default_ng_led_data,
877		- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
	1281	+static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = {
	1282	+ .data = mlxplat_mlxcpld_comex_100G_led_data,
	1283	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data),
878	1284	};
879	1285
880	1286	/* Platform register access default */
..	..	@@ -888,6 +1294,32 @@
888	1294	{
889	1295	.label = "cpld2_version",
890	1296	.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
	1297	+ .bit = GENMASK(7, 0),
	1298	+ .mode = 0444,
	1299	+ },
	1300	+ {
	1301	+ .label = "cpld1_pn",
	1302	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
	1303	+ .bit = GENMASK(15, 0),
	1304	+ .mode = 0444,
	1305	+ .regnum = 2,
	1306	+ },
	1307	+ {
	1308	+ .label = "cpld2_pn",
	1309	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
	1310	+ .bit = GENMASK(15, 0),
	1311	+ .mode = 0444,
	1312	+ .regnum = 2,
	1313	+ },
	1314	+ {
	1315	+ .label = "cpld1_version_min",
	1316	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
	1317	+ .bit = GENMASK(7, 0),
	1318	+ .mode = 0444,
	1319	+ },
	1320	+ {
	1321	+ .label = "cpld2_version_min",
	1322	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
891	1323	.bit = GENMASK(7, 0),
892	1324	.mode = 0444,
893	1325	},
..	..	@@ -998,6 +1430,32 @@
998	1430	.mode = 0444,
999	1431	},
1000	1432	{
	1433	+ .label = "cpld1_pn",
	1434	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
	1435	+ .bit = GENMASK(15, 0),
	1436	+ .mode = 0444,
	1437	+ .regnum = 2,
	1438	+ },
	1439	+ {
	1440	+ .label = "cpld2_pn",
	1441	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
	1442	+ .bit = GENMASK(15, 0),
	1443	+ .mode = 0444,
	1444	+ .regnum = 2,
	1445	+ },
	1446	+ {
	1447	+ .label = "cpld1_version_min",
	1448	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
	1449	+ .bit = GENMASK(7, 0),
	1450	+ .mode = 0444,
	1451	+ },
	1452	+ {
	1453	+ .label = "cpld2_version_min",
	1454	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
	1455	+ .bit = GENMASK(7, 0),
	1456	+ .mode = 0444,
	1457	+ },
	1458	+ {
1001	1459	.label = "reset_long_pb",
1002	1460	.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1003	1461	.mask = GENMASK(7, 0) & ~BIT(0),
..	..	@@ -1040,6 +1498,12 @@
1040	1498	.mode = 0444,
1041	1499	},
1042	1500	{
	1501	+ .label = "reset_sff_wd",
	1502	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
	1503	+ .mask = GENMASK(7, 0) & ~BIT(6),
	1504	+ .mode = 0444,
	1505	+ },
	1506	+ {
1043	1507	.label = "psu1_on",
1044	1508	.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
1045	1509	.mask = GENMASK(7, 0) & ~BIT(0),
..	..	@@ -1064,6 +1528,12 @@
1064	1528	.mode = 0200,
1065	1529	},
1066	1530	{
	1531	+ .label = "select_iio",
	1532	+ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
	1533	+ .mask = GENMASK(7, 0) & ~BIT(6),
	1534	+ .mode = 0644,
	1535	+ },
	1536	+ {
1067	1537	.label = "asic_health",
1068	1538	.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1069	1539	.mask = MLXPLAT_CPLD_ASIC_MASK,
..	..	@@ -1077,6 +1547,273 @@
1077	1547	.counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
1078	1548	};
1079	1549
	1550	+/* Platform register access for next generation systems families data */
	1551	+static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
	1552	+ {
	1553	+ .label = "cpld1_version",
	1554	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
	1555	+ .bit = GENMASK(7, 0),
	1556	+ .mode = 0444,
	1557	+ },
	1558	+ {
	1559	+ .label = "cpld2_version",
	1560	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
	1561	+ .bit = GENMASK(7, 0),
	1562	+ .mode = 0444,
	1563	+ },
	1564	+ {
	1565	+ .label = "cpld3_version",
	1566	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
	1567	+ .bit = GENMASK(7, 0),
	1568	+ .mode = 0444,
	1569	+ },
	1570	+ {
	1571	+ .label = "cpld4_version",
	1572	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
	1573	+ .bit = GENMASK(7, 0),
	1574	+ .mode = 0444,
	1575	+ },
	1576	+ {
	1577	+ .label = "cpld1_pn",
	1578	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
	1579	+ .bit = GENMASK(15, 0),
	1580	+ .mode = 0444,
	1581	+ .regnum = 2,
	1582	+ },
	1583	+ {
	1584	+ .label = "cpld2_pn",
	1585	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
	1586	+ .bit = GENMASK(15, 0),
	1587	+ .mode = 0444,
	1588	+ .regnum = 2,
	1589	+ },
	1590	+ {
	1591	+ .label = "cpld3_pn",
	1592	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
	1593	+ .bit = GENMASK(15, 0),
	1594	+ .mode = 0444,
	1595	+ .regnum = 2,
	1596	+ },
	1597	+ {
	1598	+ .label = "cpld4_pn",
	1599	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
	1600	+ .bit = GENMASK(15, 0),
	1601	+ .mode = 0444,
	1602	+ .regnum = 2,
	1603	+ },
	1604	+ {
	1605	+ .label = "cpld1_version_min",
	1606	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
	1607	+ .bit = GENMASK(7, 0),
	1608	+ .mode = 0444,
	1609	+ },
	1610	+ {
	1611	+ .label = "cpld2_version_min",
	1612	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
	1613	+ .bit = GENMASK(7, 0),
	1614	+ .mode = 0444,
	1615	+ },
	1616	+ {
	1617	+ .label = "cpld3_version_min",
	1618	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
	1619	+ .bit = GENMASK(7, 0),
	1620	+ .mode = 0444,
	1621	+ },
	1622	+ {
	1623	+ .label = "cpld4_version_min",
	1624	+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
	1625	+ .bit = GENMASK(7, 0),
	1626	+ .mode = 0444,
	1627	+ },
	1628	+ {
	1629	+ .label = "reset_long_pb",
	1630	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	1631	+ .mask = GENMASK(7, 0) & ~BIT(0),
	1632	+ .mode = 0444,
	1633	+ },
	1634	+ {
	1635	+ .label = "reset_short_pb",
	1636	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	1637	+ .mask = GENMASK(7, 0) & ~BIT(1),
	1638	+ .mode = 0444,
	1639	+ },
	1640	+ {
	1641	+ .label = "reset_aux_pwr_or_ref",
	1642	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	1643	+ .mask = GENMASK(7, 0) & ~BIT(2),
	1644	+ .mode = 0444,
	1645	+ },
	1646	+ {
	1647	+ .label = "reset_from_comex",
	1648	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	1649	+ .mask = GENMASK(7, 0) & ~BIT(4),
	1650	+ .mode = 0444,
	1651	+ },
	1652	+ {
	1653	+ .label = "reset_from_asic",
	1654	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	1655	+ .mask = GENMASK(7, 0) & ~BIT(5),
	1656	+ .mode = 0444,
	1657	+ },
	1658	+ {
	1659	+ .label = "reset_swb_wd",
	1660	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	1661	+ .mask = GENMASK(7, 0) & ~BIT(6),
	1662	+ .mode = 0444,
	1663	+ },
	1664	+ {
	1665	+ .label = "reset_asic_thermal",
	1666	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	1667	+ .mask = GENMASK(7, 0) & ~BIT(7),
	1668	+ .mode = 0444,
	1669	+ },
	1670	+ {
	1671	+ .label = "reset_comex_pwr_fail",
	1672	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
	1673	+ .mask = GENMASK(7, 0) & ~BIT(3),
	1674	+ .mode = 0444,
	1675	+ },
	1676	+ {
	1677	+ .label = "reset_platform",
	1678	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
	1679	+ .mask = GENMASK(7, 0) & ~BIT(4),
	1680	+ .mode = 0444,
	1681	+ },
	1682	+ {
	1683	+ .label = "reset_soc",
	1684	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
	1685	+ .mask = GENMASK(7, 0) & ~BIT(5),
	1686	+ .mode = 0444,
	1687	+ },
	1688	+ {
	1689	+ .label = "reset_comex_wd",
	1690	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
	1691	+ .mask = GENMASK(7, 0) & ~BIT(6),
	1692	+ .mode = 0444,
	1693	+ },
	1694	+ {
	1695	+ .label = "reset_voltmon_upgrade_fail",
	1696	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
	1697	+ .mask = GENMASK(7, 0) & ~BIT(0),
	1698	+ .mode = 0444,
	1699	+ },
	1700	+ {
	1701	+ .label = "reset_system",
	1702	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
	1703	+ .mask = GENMASK(7, 0) & ~BIT(1),
	1704	+ .mode = 0444,
	1705	+ },
	1706	+ {
	1707	+ .label = "reset_sw_pwr_off",
	1708	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
	1709	+ .mask = GENMASK(7, 0) & ~BIT(2),
	1710	+ .mode = 0444,
	1711	+ },
	1712	+ {
	1713	+ .label = "reset_comex_thermal",
	1714	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
	1715	+ .mask = GENMASK(7, 0) & ~BIT(3),
	1716	+ .mode = 0444,
	1717	+ },
	1718	+ {
	1719	+ .label = "reset_reload_bios",
	1720	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
	1721	+ .mask = GENMASK(7, 0) & ~BIT(5),
	1722	+ .mode = 0444,
	1723	+ },
	1724	+ {
	1725	+ .label = "reset_ac_pwr_fail",
	1726	+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
	1727	+ .mask = GENMASK(7, 0) & ~BIT(6),
	1728	+ .mode = 0444,
	1729	+ },
	1730	+ {
	1731	+ .label = "psu1_on",
	1732	+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
	1733	+ .mask = GENMASK(7, 0) & ~BIT(0),
	1734	+ .mode = 0200,
	1735	+ },
	1736	+ {
	1737	+ .label = "psu2_on",
	1738	+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
	1739	+ .mask = GENMASK(7, 0) & ~BIT(1),
	1740	+ .mode = 0200,
	1741	+ },
	1742	+ {
	1743	+ .label = "pwr_cycle",
	1744	+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
	1745	+ .mask = GENMASK(7, 0) & ~BIT(2),
	1746	+ .mode = 0200,
	1747	+ },
	1748	+ {
	1749	+ .label = "pwr_down",
	1750	+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
	1751	+ .mask = GENMASK(7, 0) & ~BIT(3),
	1752	+ .mode = 0200,
	1753	+ },
	1754	+ {
	1755	+ .label = "jtag_enable",
	1756	+ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
	1757	+ .mask = GENMASK(7, 0) & ~BIT(4),
	1758	+ .mode = 0644,
	1759	+ },
	1760	+ {
	1761	+ .label = "asic_health",
	1762	+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
	1763	+ .mask = MLXPLAT_CPLD_ASIC_MASK,
	1764	+ .bit = 1,
	1765	+ .mode = 0444,
	1766	+ },
	1767	+ {
	1768	+ .label = "fan_dir",
	1769	+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
	1770	+ .bit = GENMASK(7, 0),
	1771	+ .mode = 0444,
	1772	+ },
	1773	+ {
	1774	+ .label = "voltreg_update_status",
	1775	+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
	1776	+ .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
	1777	+ .bit = 5,
	1778	+ .mode = 0444,
	1779	+ },
	1780	+ {
	1781	+ .label = "vpd_wp",
	1782	+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
	1783	+ .mask = GENMASK(7, 0) & ~BIT(3),
	1784	+ .mode = 0644,
	1785	+ },
	1786	+ {
	1787	+ .label = "pcie_asic_reset_dis",
	1788	+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
	1789	+ .mask = GENMASK(7, 0) & ~BIT(4),
	1790	+ .mode = 0644,
	1791	+ },
	1792	+ {
	1793	+ .label = "config1",
	1794	+ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
	1795	+ .bit = GENMASK(7, 0),
	1796	+ .mode = 0444,
	1797	+ },
	1798	+ {
	1799	+ .label = "config2",
	1800	+ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
	1801	+ .bit = GENMASK(7, 0),
	1802	+ .mode = 0444,
	1803	+ },
	1804	+ {
	1805	+ .label = "ufm_version",
	1806	+ .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
	1807	+ .bit = GENMASK(7, 0),
	1808	+ .mode = 0444,
	1809	+ },
	1810	+};
	1811	+
	1812	+static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
	1813	+ .data = mlxplat_mlxcpld_default_ng_regs_io_data,
	1814	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data),
	1815	+};
	1816	+
1080	1817	/* Platform FAN default */
1081	1818	static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
1082	1819	{
..	..	@@ -1087,67 +1824,329 @@
1087	1824	.label = "tacho1",
1088	1825	.reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
1089	1826	.mask = GENMASK(7, 0),
	1827	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
	1828	+ .bit = BIT(0),
	1829	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
	1830	+
1090	1831	},
1091	1832	{
1092	1833	.label = "tacho2",
1093	1834	.reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
1094	1835	.mask = GENMASK(7, 0),
	1836	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
	1837	+ .bit = BIT(1),
	1838	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1095	1839	},
1096	1840	{
1097	1841	.label = "tacho3",
1098	1842	.reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
1099	1843	.mask = GENMASK(7, 0),
	1844	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
	1845	+ .bit = BIT(2),
	1846	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1100	1847	},
1101	1848	{
1102	1849	.label = "tacho4",
1103	1850	.reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
1104	1851	.mask = GENMASK(7, 0),
	1852	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
	1853	+ .bit = BIT(3),
	1854	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1105	1855	},
1106	1856	{
1107	1857	.label = "tacho5",
1108	1858	.reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
1109	1859	.mask = GENMASK(7, 0),
	1860	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
	1861	+ .bit = BIT(4),
	1862	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1110	1863	},
1111	1864	{
1112	1865	.label = "tacho6",
1113	1866	.reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
1114	1867	.mask = GENMASK(7, 0),
	1868	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
	1869	+ .bit = BIT(5),
	1870	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1115	1871	},
1116	1872	{
1117	1873	.label = "tacho7",
1118	1874	.reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
1119	1875	.mask = GENMASK(7, 0),
	1876	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
	1877	+ .bit = BIT(6),
	1878	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1120	1879	},
1121	1880	{
1122	1881	.label = "tacho8",
1123	1882	.reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
1124	1883	.mask = GENMASK(7, 0),
	1884	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
	1885	+ .bit = BIT(7),
	1886	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1125	1887	},
1126	1888	{
1127	1889	.label = "tacho9",
1128	1890	.reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
1129	1891	.mask = GENMASK(7, 0),
	1892	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
	1893	+ .bit = BIT(0),
	1894	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1130	1895	},
1131	1896	{
1132	1897	.label = "tacho10",
1133	1898	.reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
1134	1899	.mask = GENMASK(7, 0),
	1900	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
	1901	+ .bit = BIT(1),
	1902	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1135	1903	},
1136	1904	{
1137	1905	.label = "tacho11",
1138	1906	.reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
1139	1907	.mask = GENMASK(7, 0),
	1908	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
	1909	+ .bit = BIT(2),
	1910	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1140	1911	},
1141	1912	{
1142	1913	.label = "tacho12",
1143	1914	.reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
1144	1915	.mask = GENMASK(7, 0),
	1916	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
	1917	+ .bit = BIT(3),
	1918	+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
	1919	+ },
	1920	+ {
	1921	+ .label = "conf",
	1922	+ .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
1145	1923	},
1146	1924	};
1147	1925
1148	1926	static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
1149	1927	.data = mlxplat_mlxcpld_default_fan_data,
1150	1928	.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
	1929	+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
	1930	+};
	1931	+
	1932	+/* Watchdog type1: hardware implementation version1
	1933	+ * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems).
	1934	+ */
	1935	+static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = {
	1936	+ {
	1937	+ .label = "action",
	1938	+ .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET,
	1939	+ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
	1940	+ .bit = 0,
	1941	+ },
	1942	+ {
	1943	+ .label = "timeout",
	1944	+ .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET,
	1945	+ .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
	1946	+ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
	1947	+ },
	1948	+ {
	1949	+ .label = "ping",
	1950	+ .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
	1951	+ .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
	1952	+ .bit = 0,
	1953	+ },
	1954	+ {
	1955	+ .label = "reset",
	1956	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	1957	+ .mask = GENMASK(7, 0) & ~BIT(6),
	1958	+ .bit = 6,
	1959	+ },
	1960	+};
	1961	+
	1962	+static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = {
	1963	+ {
	1964	+ .label = "action",
	1965	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
	1966	+ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
	1967	+ .bit = 4,
	1968	+ },
	1969	+ {
	1970	+ .label = "timeout",
	1971	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
	1972	+ .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
	1973	+ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
	1974	+ },
	1975	+ {
	1976	+ .label = "ping",
	1977	+ .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
	1978	+ .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
	1979	+ .bit = 1,
	1980	+ },
	1981	+};
	1982	+
	1983	+static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = {
	1984	+ {
	1985	+ .data = mlxplat_mlxcpld_wd_main_regs_type1,
	1986	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1),
	1987	+ .version = MLX_WDT_TYPE1,
	1988	+ .identity = "mlx-wdt-main",
	1989	+ },
	1990	+ {
	1991	+ .data = mlxplat_mlxcpld_wd_aux_regs_type1,
	1992	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1),
	1993	+ .version = MLX_WDT_TYPE1,
	1994	+ .identity = "mlx-wdt-aux",
	1995	+ },
	1996	+};
	1997	+
	1998	+/* Watchdog type2: hardware implementation version 2
	1999	+ * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140).
	2000	+ */
	2001	+static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = {
	2002	+ {
	2003	+ .label = "action",
	2004	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
	2005	+ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
	2006	+ .bit = 0,
	2007	+ },
	2008	+ {
	2009	+ .label = "timeout",
	2010	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
	2011	+ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
	2012	+ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
	2013	+ },
	2014	+ {
	2015	+ .label = "timeleft",
	2016	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET,
	2017	+ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
	2018	+ },
	2019	+ {
	2020	+ .label = "ping",
	2021	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
	2022	+ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
	2023	+ .bit = 0,
	2024	+ },
	2025	+ {
	2026	+ .label = "reset",
	2027	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	2028	+ .mask = GENMASK(7, 0) & ~BIT(6),
	2029	+ .bit = 6,
	2030	+ },
	2031	+};
	2032	+
	2033	+static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = {
	2034	+ {
	2035	+ .label = "action",
	2036	+ .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
	2037	+ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
	2038	+ .bit = 4,
	2039	+ },
	2040	+ {
	2041	+ .label = "timeout",
	2042	+ .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
	2043	+ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
	2044	+ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
	2045	+ },
	2046	+ {
	2047	+ .label = "timeleft",
	2048	+ .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET,
	2049	+ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
	2050	+ },
	2051	+ {
	2052	+ .label = "ping",
	2053	+ .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
	2054	+ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
	2055	+ .bit = 4,
	2056	+ },
	2057	+};
	2058	+
	2059	+static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = {
	2060	+ {
	2061	+ .data = mlxplat_mlxcpld_wd_main_regs_type2,
	2062	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2),
	2063	+ .version = MLX_WDT_TYPE2,
	2064	+ .identity = "mlx-wdt-main",
	2065	+ },
	2066	+ {
	2067	+ .data = mlxplat_mlxcpld_wd_aux_regs_type2,
	2068	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2),
	2069	+ .version = MLX_WDT_TYPE2,
	2070	+ .identity = "mlx-wdt-aux",
	2071	+ },
	2072	+};
	2073	+
	2074	+/* Watchdog type3: hardware implementation version 3
	2075	+ * Can be on all systems. It's differentiated by WD capability bit.
	2076	+ * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140)
	2077	+ * still have only one main watchdog.
	2078	+ */
	2079	+static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = {
	2080	+ {
	2081	+ .label = "action",
	2082	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
	2083	+ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
	2084	+ .bit = 0,
	2085	+ },
	2086	+ {
	2087	+ .label = "timeout",
	2088	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
	2089	+ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
	2090	+ .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
	2091	+ },
	2092	+ {
	2093	+ .label = "timeleft",
	2094	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
	2095	+ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
	2096	+ },
	2097	+ {
	2098	+ .label = "ping",
	2099	+ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
	2100	+ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
	2101	+ .bit = 0,
	2102	+ },
	2103	+ {
	2104	+ .label = "reset",
	2105	+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
	2106	+ .mask = GENMASK(7, 0) & ~BIT(6),
	2107	+ .bit = 6,
	2108	+ },
	2109	+};
	2110	+
	2111	+static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = {
	2112	+ {
	2113	+ .label = "action",
	2114	+ .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
	2115	+ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
	2116	+ .bit = 4,
	2117	+ },
	2118	+ {
	2119	+ .label = "timeout",
	2120	+ .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
	2121	+ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
	2122	+ .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
	2123	+ },
	2124	+ {
	2125	+ .label = "timeleft",
	2126	+ .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
	2127	+ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
	2128	+ },
	2129	+ {
	2130	+ .label = "ping",
	2131	+ .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
	2132	+ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
	2133	+ .bit = 4,
	2134	+ },
	2135	+};
	2136	+
	2137	+static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = {
	2138	+ {
	2139	+ .data = mlxplat_mlxcpld_wd_main_regs_type3,
	2140	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3),
	2141	+ .version = MLX_WDT_TYPE3,
	2142	+ .identity = "mlx-wdt-main",
	2143	+ },
	2144	+ {
	2145	+ .data = mlxplat_mlxcpld_wd_aux_regs_type3,
	2146	+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3),
	2147	+ .version = MLX_WDT_TYPE3,
	2148	+ .identity = "mlx-wdt-aux",
	2149	+ },
1151	2150	};
1152	2151
1153	2152	static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
..	..	@@ -1158,12 +2157,15 @@
1158	2157	case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
1159	2158	case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
1160	2159	case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
	2160	+ case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
1161	2161	case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
1162	2162	case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
1163	2163	case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
1164	2164	case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
1165	2165	case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
1166	2166	case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
	2167	+ case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
	2168	+ case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
1167	2169	case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
1168	2170	case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
1169	2171	case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
..	..	@@ -1172,6 +2174,16 @@
1172	2174	case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
1173	2175	case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
1174	2176	case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
	2177	+ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
	2178	+ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
	2179	+ case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
	2180	+ case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
	2181	+ case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
	2182	+ case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
	2183	+ case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
	2184	+ case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
	2185	+ case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
	2186	+ case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
1175	2187	case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
1176	2188	case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
1177	2189	return true;
..	..	@@ -1184,12 +2196,23 @@
1184	2196	switch (reg) {
1185	2197	case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
1186	2198	case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
	2199	+ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
	2200	+ case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
	2201	+ case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
	2202	+ case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
	2203	+ case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
	2204	+ case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
1187	2205	case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
	2206	+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
	2207	+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
1188	2208	case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
1189	2209	case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
1190	2210	case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
1191	2211	case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
1192	2212	case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
	2213	+ case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
	2214	+ case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
	2215	+ case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
1193	2216	case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
1194	2217	case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
1195	2218	case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
..	..	@@ -1198,6 +2221,10 @@
1198	2221	case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
1199	2222	case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
1200	2223	case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
	2224	+ case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
	2225	+ case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
	2226	+ case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
	2227	+ case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
1201	2228	case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
1202	2229	case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
1203	2230	case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
..	..	@@ -1210,6 +2237,20 @@
1210	2237	case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
1211	2238	case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
1212	2239	case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
	2240	+ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
	2241	+ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
	2242	+ case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
	2243	+ case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
	2244	+ case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
	2245	+ case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
	2246	+ case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
	2247	+ case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
	2248	+ case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
	2249	+ case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
	2250	+ case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
	2251	+ case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
	2252	+ case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
	2253	+ case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
1213	2254	case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
1214	2255	case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
1215	2256	case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
..	..	@@ -1224,6 +2265,14 @@
1224	2265	case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
1225	2266	case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
1226	2267	case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
	2268	+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
	2269	+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
	2270	+ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
	2271	+ case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
	2272	+ case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:
	2273	+ case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:
	2274	+ case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
	2275	+ case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
1227	2276	return true;
1228	2277	}
1229	2278	return false;
..	..	@@ -1234,18 +2283,33 @@
1234	2283	switch (reg) {
1235	2284	case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
1236	2285	case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
	2286	+ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
	2287	+ case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
	2288	+ case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
	2289	+ case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
	2290	+ case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
	2291	+ case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
1237	2292	case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
	2293	+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
	2294	+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
1238	2295	case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
1239	2296	case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
1240	2297	case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
1241	2298	case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
1242	2299	case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
	2300	+ case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
	2301	+ case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
	2302	+ case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
1243	2303	case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
1244	2304	case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
1245	2305	case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
1246	2306	case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
1247	2307	case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
1248	2308	case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
	2309	+ case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
	2310	+ case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
	2311	+ case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
	2312	+ case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
1249	2313	case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
1250	2314	case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
1251	2315	case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
..	..	@@ -1258,6 +2322,14 @@
1258	2322	case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
1259	2323	case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
1260	2324	case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
	2325	+ case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
	2326	+ case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
	2327	+ case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
	2328	+ case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
	2329	+ case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
	2330	+ case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
	2331	+ case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
	2332	+ case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
1261	2333	case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
1262	2334	case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
1263	2335	case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
..	..	@@ -1272,6 +2344,14 @@
1272	2344	case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
1273	2345	case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
1274	2346	case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
	2347	+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
	2348	+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
	2349	+ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
	2350	+ case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
	2351	+ case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:
	2352	+ case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:
	2353	+ case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
	2354	+ case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
1275	2355	return true;
1276	2356	}
1277	2357	return false;
..	..	@@ -1281,6 +2361,25 @@
1281	2361	{ MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
1282	2362	{ MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
1283	2363	{ MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
	2364	+ { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
	2365	+};
	2366	+
	2367	+static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = {
	2368	+ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
	2369	+ { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
	2370	+};
	2371	+
	2372	+static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = {
	2373	+ { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET,
	2374	+ MLXPLAT_CPLD_LOW_AGGRCX_MASK },
	2375	+ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
	2376	+};
	2377	+
	2378	+static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = {
	2379	+ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
	2380	+ { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 },
	2381	+ { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 },
	2382	+ { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
1284	2383	};
1285	2384
1286	2385	struct mlxplat_mlxcpld_regmap_context {
..	..	@@ -1321,21 +2420,70 @@
1321	2420	.reg_write = mlxplat_mlxcpld_reg_write,
1322	2421	};
1323	2422
	2423	+static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = {
	2424	+ .reg_bits = 8,
	2425	+ .val_bits = 8,
	2426	+ .max_register = 255,
	2427	+ .cache_type = REGCACHE_FLAT,
	2428	+ .writeable_reg = mlxplat_mlxcpld_writeable_reg,
	2429	+ .readable_reg = mlxplat_mlxcpld_readable_reg,
	2430	+ .volatile_reg = mlxplat_mlxcpld_volatile_reg,
	2431	+ .reg_defaults = mlxplat_mlxcpld_regmap_ng,
	2432	+ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng),
	2433	+ .reg_read = mlxplat_mlxcpld_reg_read,
	2434	+ .reg_write = mlxplat_mlxcpld_reg_write,
	2435	+};
	2436	+
	2437	+static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = {
	2438	+ .reg_bits = 8,
	2439	+ .val_bits = 8,
	2440	+ .max_register = 255,
	2441	+ .cache_type = REGCACHE_FLAT,
	2442	+ .writeable_reg = mlxplat_mlxcpld_writeable_reg,
	2443	+ .readable_reg = mlxplat_mlxcpld_readable_reg,
	2444	+ .volatile_reg = mlxplat_mlxcpld_volatile_reg,
	2445	+ .reg_defaults = mlxplat_mlxcpld_regmap_comex_default,
	2446	+ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default),
	2447	+ .reg_read = mlxplat_mlxcpld_reg_read,
	2448	+ .reg_write = mlxplat_mlxcpld_reg_write,
	2449	+};
	2450	+
	2451	+static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = {
	2452	+ .reg_bits = 8,
	2453	+ .val_bits = 8,
	2454	+ .max_register = 255,
	2455	+ .cache_type = REGCACHE_FLAT,
	2456	+ .writeable_reg = mlxplat_mlxcpld_writeable_reg,
	2457	+ .readable_reg = mlxplat_mlxcpld_readable_reg,
	2458	+ .volatile_reg = mlxplat_mlxcpld_volatile_reg,
	2459	+ .reg_defaults = mlxplat_mlxcpld_regmap_ng400,
	2460	+ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400),
	2461	+ .reg_read = mlxplat_mlxcpld_reg_read,
	2462	+ .reg_write = mlxplat_mlxcpld_reg_write,
	2463	+};
	2464	+
1324	2465	static struct resource mlxplat_mlxcpld_resources[] = {
1325	2466	[0] = DEFINE_RES_IRQ_NAMED(17, "mlxreg-hotplug"),
1326	2467	};
1327	2468
1328	2469	static struct platform_device *mlxplat_dev;
	2470	+static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c;
1329	2471	static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
1330	2472	static struct mlxreg_core_platform_data *mlxplat_led;
1331	2473	static struct mlxreg_core_platform_data *mlxplat_regs_io;
1332	2474	static struct mlxreg_core_platform_data *mlxplat_fan;
	2475	+static struct mlxreg_core_platform_data
	2476	+ *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS];
	2477	+static const struct regmap_config *mlxplat_regmap_config;
1333	2478
1334	2479	static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
1335	2480	{
1336	2481	int i;
1337	2482
1338		- for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
	2483	+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
	2484	+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
	2485	+ mlxplat_mux_data = mlxplat_default_mux_data;
	2486	+ for (i = 0; i < mlxplat_mux_num; i++) {
1339	2487	mlxplat_mux_data[i].values = mlxplat_default_channels[i];
1340	2488	mlxplat_mux_data[i].n_values =
1341	2489	ARRAY_SIZE(mlxplat_default_channels[i]);
..	..	@@ -1345,15 +2493,19 @@
1345	2493	mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
1346	2494	mlxplat_led = &mlxplat_default_led_data;
1347	2495	mlxplat_regs_io = &mlxplat_default_regs_io_data;
	2496	+ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
1348	2497
1349	2498	return 1;
1350		-};
	2499	+}
1351	2500
1352	2501	static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)
1353	2502	{
1354	2503	int i;
1355	2504
1356		- for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
	2505	+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
	2506	+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
	2507	+ mlxplat_mux_data = mlxplat_default_mux_data;
	2508	+ for (i = 0; i < mlxplat_mux_num; i++) {
1357	2509	mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
1358	2510	mlxplat_mux_data[i].n_values =
1359	2511	ARRAY_SIZE(mlxplat_msn21xx_channels);
..	..	@@ -1363,15 +2515,19 @@
1363	2515	mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
1364	2516	mlxplat_led = &mlxplat_msn21xx_led_data;
1365	2517	mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
	2518	+ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
1366	2519
1367	2520	return 1;
1368		-};
	2521	+}
1369	2522
1370	2523	static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi)
1371	2524	{
1372	2525	int i;
1373	2526
1374		- for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
	2527	+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
	2528	+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
	2529	+ mlxplat_mux_data = mlxplat_default_mux_data;
	2530	+ for (i = 0; i < mlxplat_mux_num; i++) {
1375	2531	mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
1376	2532	mlxplat_mux_data[i].n_values =
1377	2533	ARRAY_SIZE(mlxplat_msn21xx_channels);
..	..	@@ -1381,15 +2537,19 @@
1381	2537	mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
1382	2538	mlxplat_led = &mlxplat_default_led_data;
1383	2539	mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
	2540	+ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
1384	2541
1385	2542	return 1;
1386		-};
	2543	+}
1387	2544
1388	2545	static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi)
1389	2546	{
1390	2547	int i;
1391	2548
1392		- for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
	2549	+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
	2550	+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
	2551	+ mlxplat_mux_data = mlxplat_default_mux_data;
	2552	+ for (i = 0; i < mlxplat_mux_num; i++) {
1393	2553	mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
1394	2554	mlxplat_mux_data[i].n_values =
1395	2555	ARRAY_SIZE(mlxplat_msn21xx_channels);
..	..	@@ -1399,15 +2559,19 @@
1399	2559	mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
1400	2560	mlxplat_led = &mlxplat_msn21xx_led_data;
1401	2561	mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
	2562	+ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
1402	2563
1403	2564	return 1;
1404		-};
	2565	+}
1405	2566
1406	2567	static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi)
1407	2568	{
1408	2569	int i;
1409	2570
1410		- for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
	2571	+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
	2572	+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
	2573	+ mlxplat_mux_data = mlxplat_default_mux_data;
	2574	+ for (i = 0; i < mlxplat_mux_num; i++) {
1411	2575	mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
1412	2576	mlxplat_mux_data[i].n_values =
1413	2577	ARRAY_SIZE(mlxplat_msn21xx_channels);
..	..	@@ -1416,12 +2580,115 @@
1416	2580	mlxplat_hotplug->deferred_nr =
1417	2581	mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
1418	2582	mlxplat_led = &mlxplat_default_ng_led_data;
	2583	+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
1419	2584	mlxplat_fan = &mlxplat_default_fan_data;
	2585	+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
	2586	+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
	2587	+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
	2588	+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng;
1420	2589
1421	2590	return 1;
1422		-};
	2591	+}
	2592	+
	2593	+static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi)
	2594	+{
	2595	+ int i;
	2596	+
	2597	+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
	2598	+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data);
	2599	+ mlxplat_mux_data = mlxplat_extended_mux_data;
	2600	+ for (i = 0; i < mlxplat_mux_num; i++) {
	2601	+ mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
	2602	+ mlxplat_mux_data[i].n_values =
	2603	+ ARRAY_SIZE(mlxplat_msn21xx_channels);
	2604	+ }
	2605	+ mlxplat_hotplug = &mlxplat_mlxcpld_comex_data;
	2606	+ mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
	2607	+ mlxplat_led = &mlxplat_comex_100G_led_data;
	2608	+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
	2609	+ mlxplat_fan = &mlxplat_default_fan_data;
	2610	+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
	2611	+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
	2612	+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex;
	2613	+
	2614	+ return 1;
	2615	+}
	2616	+
	2617	+static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi)
	2618	+{
	2619	+ int i;
	2620	+
	2621	+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
	2622	+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
	2623	+ mlxplat_mux_data = mlxplat_default_mux_data;
	2624	+ for (i = 0; i < mlxplat_mux_num; i++) {
	2625	+ mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
	2626	+ mlxplat_mux_data[i].n_values =
	2627	+ ARRAY_SIZE(mlxplat_msn21xx_channels);
	2628	+ }
	2629	+ mlxplat_hotplug = &mlxplat_mlxcpld_ext_data;
	2630	+ mlxplat_hotplug->deferred_nr =
	2631	+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
	2632	+ mlxplat_led = &mlxplat_default_ng_led_data;
	2633	+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
	2634	+ mlxplat_fan = &mlxplat_default_fan_data;
	2635	+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
	2636	+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
	2637	+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
	2638	+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
	2639	+
	2640	+ return 1;
	2641	+}
1423	2642
1424	2643	static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
	2644	+ {
	2645	+ .callback = mlxplat_dmi_default_matched,
	2646	+ .matches = {
	2647	+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
	2648	+ },
	2649	+ },
	2650	+ {
	2651	+ .callback = mlxplat_dmi_msn21xx_matched,
	2652	+ .matches = {
	2653	+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"),
	2654	+ },
	2655	+ },
	2656	+ {
	2657	+ .callback = mlxplat_dmi_msn274x_matched,
	2658	+ .matches = {
	2659	+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"),
	2660	+ },
	2661	+ },
	2662	+ {
	2663	+ .callback = mlxplat_dmi_msn201x_matched,
	2664	+ .matches = {
	2665	+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"),
	2666	+ },
	2667	+ },
	2668	+ {
	2669	+ .callback = mlxplat_dmi_qmb7xx_matched,
	2670	+ .matches = {
	2671	+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
	2672	+ },
	2673	+ },
	2674	+ {
	2675	+ .callback = mlxplat_dmi_qmb7xx_matched,
	2676	+ .matches = {
	2677	+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"),
	2678	+ },
	2679	+ },
	2680	+ {
	2681	+ .callback = mlxplat_dmi_comex_matched,
	2682	+ .matches = {
	2683	+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"),
	2684	+ },
	2685	+ },
	2686	+ {
	2687	+ .callback = mlxplat_dmi_ng400_matched,
	2688	+ .matches = {
	2689	+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"),
	2690	+ },
	2691	+ },
1425	2692	{
1426	2693	.callback = mlxplat_dmi_msn274x_matched,
1427	2694	.matches = {
..	..	@@ -1475,51 +2742,28 @@
1475	2742	.callback = mlxplat_dmi_qmb7xx_matched,
1476	2743	.matches = {
1477	2744	DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
1478		- DMI_MATCH(DMI_PRODUCT_NAME, "QMB7"),
	2745	+ DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"),
1479	2746	},
1480	2747	},
1481	2748	{
1482	2749	.callback = mlxplat_dmi_qmb7xx_matched,
1483	2750	.matches = {
1484	2751	DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
1485		- DMI_MATCH(DMI_PRODUCT_NAME, "SN37"),
	2752	+ DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"),
1486	2753	},
1487	2754	},
1488	2755	{
1489	2756	.callback = mlxplat_dmi_qmb7xx_matched,
1490	2757	.matches = {
1491	2758	DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
1492		- DMI_MATCH(DMI_PRODUCT_NAME, "SN34"),
1493		- },
1494		- },
1495		- {
1496		- .callback = mlxplat_dmi_default_matched,
1497		- .matches = {
1498		- DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
1499		- },
1500		- },
1501		- {
1502		- .callback = mlxplat_dmi_msn21xx_matched,
1503		- .matches = {
1504		- DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"),
1505		- },
1506		- },
1507		- {
1508		- .callback = mlxplat_dmi_msn274x_matched,
1509		- .matches = {
1510		- DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"),
1511		- },
1512		- },
1513		- {
1514		- .callback = mlxplat_dmi_msn201x_matched,
1515		- .matches = {
1516		- DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"),
	2759	+ DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"),
1517	2760	},
1518	2761	},
1519	2762	{
1520	2763	.callback = mlxplat_dmi_qmb7xx_matched,
1521	2764	.matches = {
1522		- DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
	2765	+ DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
	2766	+ DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"),
1523	2767	},
1524	2768	},
1525	2769	{ }
..	..	@@ -1535,7 +2779,7 @@
1535	2779	/* Scan adapters from expected id to verify it is free. */
1536	2780	*nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR;
1537	2781	for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i <
1538		- MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; i++) {
	2782	+ mlxplat_max_adap_num; i++) {
1539	2783	search_adap = i2c_get_adapter(i);
1540	2784	if (search_adap) {
1541	2785	i2c_put_adapter(search_adap);
..	..	@@ -1549,17 +2793,38 @@
1549	2793	}
1550	2794
1551	2795	/* Return with error if free id for adapter is not found. */
1552		- if (i == MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM)
	2796	+ if (i == mlxplat_max_adap_num)
1553	2797	return -ENODEV;
1554	2798
1555	2799	/* Shift adapter ids, since expected parent adapter is not free. */
1556	2800	*nr = i;
1557		- for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
	2801	+ for (i = 0; i < mlxplat_mux_num; i++) {
1558	2802	shift = *nr - mlxplat_mux_data[i].parent;
1559	2803	mlxplat_mux_data[i].parent = *nr;
1560	2804	mlxplat_mux_data[i].base_nr += shift;
1561	2805	if (shift > 0)
1562	2806	mlxplat_hotplug->shift_nr = shift;
	2807	+ }
	2808	+
	2809	+ return 0;
	2810	+}
	2811	+
	2812	+static int mlxplat_mlxcpld_check_wd_capability(void *regmap)
	2813	+{
	2814	+ u32 regval;
	2815	+ int i, rc;
	2816	+
	2817	+ rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
	2818	+ &regval);
	2819	+ if (rc)
	2820	+ return rc;
	2821	+
	2822	+ if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) {
	2823	+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) {
	2824	+ if (mlxplat_wd_data[i])
	2825	+ mlxplat_wd_data[i] =
	2826	+ &mlxplat_mlxcpld_wd_set_type3[i];
	2827	+ }
1563	2828	}
1564	2829
1565	2830	return 0;
..	..	@@ -1588,19 +2853,42 @@
1588	2853	}
1589	2854	platform_set_drvdata(mlxplat_dev, priv);
1590	2855
	2856	+ mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev,
	2857	+ mlxplat_lpc_resources[1].start, 1);
	2858	+ if (!mlxplat_mlxcpld_regmap_ctx.base) {
	2859	+ err = -ENOMEM;
	2860	+ goto fail_alloc;
	2861	+ }
	2862	+
	2863	+ if (!mlxplat_regmap_config)
	2864	+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config;
	2865	+
	2866	+ priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL,
	2867	+ &mlxplat_mlxcpld_regmap_ctx,
	2868	+ mlxplat_regmap_config);
	2869	+ if (IS_ERR(priv->regmap)) {
	2870	+ err = PTR_ERR(priv->regmap);
	2871	+ goto fail_alloc;
	2872	+ }
	2873	+
1591	2874	err = mlxplat_mlxcpld_verify_bus_topology(&nr);
1592	2875	if (nr < 0)
1593	2876	goto fail_alloc;
1594	2877
1595		- nr = (nr == MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM) ? -1 : nr;
1596		- priv->pdev_i2c = platform_device_register_simple("i2c_mlxcpld", nr,
1597		- NULL, 0);
	2878	+ nr = (nr == mlxplat_max_adap_num) ? -1 : nr;
	2879	+ if (mlxplat_i2c)
	2880	+ mlxplat_i2c->regmap = priv->regmap;
	2881	+ priv->pdev_i2c = platform_device_register_resndata(
	2882	+ &mlxplat_dev->dev, "i2c_mlxcpld",
	2883	+ nr, mlxplat_mlxcpld_resources,
	2884	+ ARRAY_SIZE(mlxplat_mlxcpld_resources),
	2885	+ mlxplat_i2c, sizeof(*mlxplat_i2c));
1598	2886	if (IS_ERR(priv->pdev_i2c)) {
1599	2887	err = PTR_ERR(priv->pdev_i2c);
1600	2888	goto fail_alloc;
1601	2889	}
1602	2890
1603		- for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
	2891	+ for (i = 0; i < mlxplat_mux_num; i++) {
1604	2892	priv->pdev_mux[i] = platform_device_register_resndata(
1605	2893	&priv->pdev_i2c->dev,
1606	2894	"i2c-mux-reg", i, NULL,
..	..	@@ -1612,21 +2900,8 @@
1612	2900	}
1613	2901	}
1614	2902
1615		- mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev,
1616		- mlxplat_lpc_resources[1].start, 1);
1617		- if (!mlxplat_mlxcpld_regmap_ctx.base) {
1618		- err = -ENOMEM;
1619		- goto fail_platform_mux_register;
1620		- }
1621		-
1622		- mlxplat_hotplug->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL,
1623		- &mlxplat_mlxcpld_regmap_ctx,
1624		- &mlxplat_mlxcpld_regmap_config);
1625		- if (IS_ERR(mlxplat_hotplug->regmap)) {
1626		- err = PTR_ERR(mlxplat_hotplug->regmap);
1627		- goto fail_platform_mux_register;
1628		- }
1629		-
	2903	+ /* Add hotplug driver */
	2904	+ mlxplat_hotplug->regmap = priv->regmap;
1630	2905	priv->pdev_hotplug = platform_device_register_resndata(
1631	2906	&mlxplat_dev->dev, "mlxreg-hotplug",
1632	2907	PLATFORM_DEVID_NONE,
..	..	@@ -1639,16 +2914,16 @@
1639	2914	}
1640	2915
1641	2916	/* Set default registers. */
1642		- for (j = 0; j < mlxplat_mlxcpld_regmap_config.num_reg_defaults; j++) {
1643		- err = regmap_write(mlxplat_hotplug->regmap,
1644		- mlxplat_mlxcpld_regmap_default[j].reg,
1645		- mlxplat_mlxcpld_regmap_default[j].def);
	2917	+ for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) {
	2918	+ err = regmap_write(priv->regmap,
	2919	+ mlxplat_regmap_config->reg_defaults[j].reg,
	2920	+ mlxplat_regmap_config->reg_defaults[j].def);
1646	2921	if (err)
1647	2922	goto fail_platform_mux_register;
1648	2923	}
1649	2924
1650	2925	/* Add LED driver. */
1651		- mlxplat_led->regmap = mlxplat_hotplug->regmap;
	2926	+ mlxplat_led->regmap = priv->regmap;
1652	2927	priv->pdev_led = platform_device_register_resndata(
1653	2928	&mlxplat_dev->dev, "leds-mlxreg",
1654	2929	PLATFORM_DEVID_NONE, NULL, 0,
..	..	@@ -1660,7 +2935,7 @@
1660	2935
1661	2936	/* Add registers io access driver. */
1662	2937	if (mlxplat_regs_io) {
1663		- mlxplat_regs_io->regmap = mlxplat_hotplug->regmap;
	2938	+ mlxplat_regs_io->regmap = priv->regmap;
1664	2939	priv->pdev_io_regs = platform_device_register_resndata(
1665	2940	&mlxplat_dev->dev, "mlxreg-io",
1666	2941	PLATFORM_DEVID_NONE, NULL, 0,
..	..	@@ -1674,7 +2949,7 @@
1674	2949
1675	2950	/* Add FAN driver. */
1676	2951	if (mlxplat_fan) {
1677		- mlxplat_fan->regmap = mlxplat_hotplug->regmap;
	2952	+ mlxplat_fan->regmap = priv->regmap;
1678	2953	priv->pdev_fan = platform_device_register_resndata(
1679	2954	&mlxplat_dev->dev, "mlxreg-fan",
1680	2955	PLATFORM_DEVID_NONE, NULL, 0,
..	..	@@ -1686,15 +2961,36 @@
1686	2961	}
1687	2962	}
1688	2963
1689		- /* Sync registers with hardware. */
1690		- regcache_mark_dirty(mlxplat_hotplug->regmap);
1691		- err = regcache_sync(mlxplat_hotplug->regmap);
	2964	+ /* Add WD drivers. */
	2965	+ err = mlxplat_mlxcpld_check_wd_capability(priv->regmap);
1692	2966	if (err)
1693		- goto fail_platform_fan_register;
	2967	+ goto fail_platform_wd_register;
	2968	+ for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) {
	2969	+ if (mlxplat_wd_data[j]) {
	2970	+ mlxplat_wd_data[j]->regmap = priv->regmap;
	2971	+ priv->pdev_wd[j] = platform_device_register_resndata(
	2972	+ &mlxplat_dev->dev, "mlx-wdt",
	2973	+ j, NULL, 0,
	2974	+ mlxplat_wd_data[j],
	2975	+ sizeof(*mlxplat_wd_data[j]));
	2976	+ if (IS_ERR(priv->pdev_wd[j])) {
	2977	+ err = PTR_ERR(priv->pdev_wd[j]);
	2978	+ goto fail_platform_wd_register;
	2979	+ }
	2980	+ }
	2981	+ }
	2982	+
	2983	+ /* Sync registers with hardware. */
	2984	+ regcache_mark_dirty(priv->regmap);
	2985	+ err = regcache_sync(priv->regmap);
	2986	+ if (err)
	2987	+ goto fail_platform_wd_register;
1694	2988
1695	2989	return 0;
1696	2990
1697		-fail_platform_fan_register:
	2991	+fail_platform_wd_register:
	2992	+ while (--j >= 0)
	2993	+ platform_device_unregister(priv->pdev_wd[j]);
1698	2994	if (mlxplat_fan)
1699	2995	platform_device_unregister(priv->pdev_fan);
1700	2996	fail_platform_io_regs_register:
..	..	@@ -1720,6 +3016,8 @@
1720	3016	struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
1721	3017	int i;
1722	3018
	3019	+ for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--)
	3020	+ platform_device_unregister(priv->pdev_wd[i]);
1723	3021	if (priv->pdev_fan)
1724	3022	platform_device_unregister(priv->pdev_fan);
1725	3023	if (priv->pdev_io_regs)
..	..	@@ -1727,7 +3025,7 @@
1727	3025	platform_device_unregister(priv->pdev_led);
1728	3026	platform_device_unregister(priv->pdev_hotplug);
1729	3027
1730		- for (i = ARRAY_SIZE(mlxplat_mux_data) - 1; i >= 0 ; i--)
	3028	+ for (i = mlxplat_mux_num - 1; i >= 0 ; i--)
1731	3029	platform_device_unregister(priv->pdev_mux[i]);
1732	3030
1733	3031	platform_device_unregister(priv->pdev_i2c);