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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/platform/x86/intel_scu_ipc.c
....@@ -1,13 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
2
- * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
3
+ * Driver for the Intel SCU IPC mechanism
34  *
45  * (C) Copyright 2008-2010,2015 Intel Corporation
56  * Author: Sreedhara DS (sreedhara.ds@intel.com)
6
- *
7
- * This program is free software; you can redistribute it and/or
8
- * modify it under the terms of the GNU General Public License
9
- * as published by the Free Software Foundation; version 2
10
- * of the License.
117  *
128  * SCU running in ARC processor communicates with other entity running in IA
139  * core through IPC mechanism which in turn messaging between IA core ad SCU.
....@@ -16,23 +12,21 @@
1612  * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
1713  * along with other APIs.
1814  */
15
+
1916 #include <linux/delay.h>
17
+#include <linux/device.h>
2018 #include <linux/errno.h>
2119 #include <linux/init.h>
22
-#include <linux/device.h>
23
-#include <linux/pm.h>
24
-#include <linux/pci.h>
2520 #include <linux/interrupt.h>
26
-#include <linux/sfi.h>
27
-#include <asm/intel-mid.h>
21
+#include <linux/io.h>
22
+#include <linux/iopoll.h>
23
+#include <linux/module.h>
24
+#include <linux/slab.h>
25
+
2826 #include <asm/intel_scu_ipc.h>
2927 
3028 /* IPC defines the following message types */
31
-#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
32
-#define IPCMSG_BATTERY        0xEF /* Coulomb Counter Accumulator */
33
-#define IPCMSG_FW_UPDATE      0xFE /* Firmware update */
34
-#define IPCMSG_PCNTRL         0xFF /* Power controller unit read/write */
35
-#define IPCMSG_FW_REVISION    0xF4 /* Get firmware revision */
29
+#define IPCMSG_PCNTRL         0xff /* Power controller unit read/write */
3630 
3731 /* Command id associated with message IPCMSG_PCNTRL */
3832 #define IPC_CMD_PCNTRL_W      0 /* Register write */
....@@ -60,57 +54,133 @@
6054 #define IPC_RWBUF_SIZE    20		/* IPC Read buffer Size */
6155 #define IPC_IOC	          0x100		/* IPC command register IOC bit */
6256 
63
-#define PCI_DEVICE_ID_LINCROFT		0x082a
64
-#define PCI_DEVICE_ID_PENWELL		0x080e
65
-#define PCI_DEVICE_ID_CLOVERVIEW	0x08ea
66
-#define PCI_DEVICE_ID_TANGIER		0x11a0
67
-
68
-/* intel scu ipc driver data */
69
-struct intel_scu_ipc_pdata_t {
70
-	u32 i2c_base;
71
-	u32 i2c_len;
72
-};
73
-
74
-static const struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
75
-	.i2c_base = 0xff12b000,
76
-	.i2c_len = 0x10,
77
-};
78
-
79
-/* Penwell and Cloverview */
80
-static const struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
81
-	.i2c_base = 0xff12b000,
82
-	.i2c_len = 0x10,
83
-};
84
-
85
-static const struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
86
-	.i2c_base  = 0xff00d000,
87
-	.i2c_len = 0x10,
88
-};
89
-
9057 struct intel_scu_ipc_dev {
91
-	struct device *dev;
58
+	struct device dev;
59
+	struct resource mem;
60
+	struct module *owner;
61
+	int irq;
9262 	void __iomem *ipc_base;
93
-	void __iomem *i2c_base;
9463 	struct completion cmd_complete;
95
-	u8 irq_mode;
9664 };
97
-
98
-static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */
9965 
10066 #define IPC_STATUS		0x04
10167 #define IPC_STATUS_IRQ		BIT(2)
68
+#define IPC_STATUS_ERR		BIT(1)
69
+#define IPC_STATUS_BUSY		BIT(0)
10270 
10371 /*
104
- * IPC Read Buffer (Read Only):
105
- * 16 byte buffer for receiving data from SCU, if IPC command
106
- * processing results in response data
72
+ * IPC Write/Read Buffers:
73
+ * 16 byte buffer for sending and receiving data to and from SCU.
10774  */
75
+#define IPC_WRITE_BUFFER	0x80
10876 #define IPC_READ_BUFFER		0x90
10977 
110
-#define IPC_I2C_CNTRL_ADDR	0
111
-#define I2C_DATA_ADDR		0x04
78
+/* Timeout in jiffies */
79
+#define IPC_TIMEOUT		(3 * HZ)
11280 
81
+static struct intel_scu_ipc_dev *ipcdev; /* Only one for now */
11382 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
83
+
84
+static struct class intel_scu_ipc_class = {
85
+	.name = "intel_scu_ipc",
86
+	.owner = THIS_MODULE,
87
+};
88
+
89
+/**
90
+ * intel_scu_ipc_dev_get() - Get SCU IPC instance
91
+ *
92
+ * The recommended new API takes SCU IPC instance as parameter and this
93
+ * function can be called by driver to get the instance. This also makes
94
+ * sure the driver providing the IPC functionality cannot be unloaded
95
+ * while the caller has the instance.
96
+ *
97
+ * Call intel_scu_ipc_dev_put() to release the instance.
98
+ *
99
+ * Returns %NULL if SCU IPC is not currently available.
100
+ */
101
+struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void)
102
+{
103
+	struct intel_scu_ipc_dev *scu = NULL;
104
+
105
+	mutex_lock(&ipclock);
106
+	if (ipcdev) {
107
+		get_device(&ipcdev->dev);
108
+		/*
109
+		 * Prevent the IPC provider from being unloaded while it
110
+		 * is being used.
111
+		 */
112
+		if (!try_module_get(ipcdev->owner))
113
+			put_device(&ipcdev->dev);
114
+		else
115
+			scu = ipcdev;
116
+	}
117
+
118
+	mutex_unlock(&ipclock);
119
+	return scu;
120
+}
121
+EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_get);
122
+
123
+/**
124
+ * intel_scu_ipc_dev_put() - Put SCU IPC instance
125
+ * @scu: SCU IPC instance
126
+ *
127
+ * This function releases the SCU IPC instance retrieved from
128
+ * intel_scu_ipc_dev_get() and allows the driver providing IPC to be
129
+ * unloaded.
130
+ */
131
+void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu)
132
+{
133
+	if (scu) {
134
+		module_put(scu->owner);
135
+		put_device(&scu->dev);
136
+	}
137
+}
138
+EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_put);
139
+
140
+struct intel_scu_ipc_devres {
141
+	struct intel_scu_ipc_dev *scu;
142
+};
143
+
144
+static void devm_intel_scu_ipc_dev_release(struct device *dev, void *res)
145
+{
146
+	struct intel_scu_ipc_devres *dr = res;
147
+	struct intel_scu_ipc_dev *scu = dr->scu;
148
+
149
+	intel_scu_ipc_dev_put(scu);
150
+}
151
+
152
+/**
153
+ * devm_intel_scu_ipc_dev_get() - Allocate managed SCU IPC device
154
+ * @dev: Device requesting the SCU IPC device
155
+ *
156
+ * The recommended new API takes SCU IPC instance as parameter and this
157
+ * function can be called by driver to get the instance. This also makes
158
+ * sure the driver providing the IPC functionality cannot be unloaded
159
+ * while the caller has the instance.
160
+ *
161
+ * Returns %NULL if SCU IPC is not currently available.
162
+ */
163
+struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev)
164
+{
165
+	struct intel_scu_ipc_devres *dr;
166
+	struct intel_scu_ipc_dev *scu;
167
+
168
+	dr = devres_alloc(devm_intel_scu_ipc_dev_release, sizeof(*dr), GFP_KERNEL);
169
+	if (!dr)
170
+		return NULL;
171
+
172
+	scu = intel_scu_ipc_dev_get();
173
+	if (!scu) {
174
+		devres_free(dr);
175
+		return NULL;
176
+	}
177
+
178
+	dr->scu = scu;
179
+	devres_add(dev, dr);
180
+
181
+	return scu;
182
+}
183
+EXPORT_SYMBOL_GPL(devm_intel_scu_ipc_dev_get);
114184 
115185 /*
116186  * Send ipc command
....@@ -133,7 +203,7 @@
133203  */
134204 static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
135205 {
136
-	writel(data, scu->ipc_base + 0x80 + offset);
206
+	writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset);
137207 }
138208 
139209 /*
....@@ -145,7 +215,7 @@
145215  */
146216 static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
147217 {
148
-	return __raw_readl(scu->ipc_base + 0x04);
218
+	return __raw_readl(scu->ipc_base + IPC_STATUS);
149219 }
150220 
151221 /* Read ipc byte data */
....@@ -163,24 +233,15 @@
163233 /* Wait till scu status is busy */
164234 static inline int busy_loop(struct intel_scu_ipc_dev *scu)
165235 {
166
-	u32 status = ipc_read_status(scu);
167
-	u32 loop_count = 100000;
236
+	u8 status;
237
+	int err;
168238 
169
-	/* break if scu doesn't reset busy bit after huge retry */
170
-	while ((status & BIT(0)) && --loop_count) {
171
-		udelay(1); /* scu processing time is in few u secods */
172
-		status = ipc_read_status(scu);
173
-	}
239
+	err = readx_poll_timeout(ipc_read_status, scu, status, !(status & IPC_STATUS_BUSY),
240
+				 100, jiffies_to_usecs(IPC_TIMEOUT));
241
+	if (err)
242
+		return err;
174243 
175
-	if (status & BIT(0)) {
176
-		dev_err(scu->dev, "IPC timed out");
177
-		return -ETIMEDOUT;
178
-	}
179
-
180
-	if (status & BIT(1))
181
-		return -EIO;
182
-
183
-	return 0;
244
+	return (status & IPC_STATUS_ERR) ? -EIO : 0;
184245 }
185246 
186247 /* Wait till ipc ioc interrupt is received or timeout in 10 HZ */
....@@ -188,13 +249,13 @@
188249 {
189250 	int status;
190251 
191
-	if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
192
-		dev_err(scu->dev, "IPC timed out\n");
193
-		return -ETIMEDOUT;
194
-	}
252
+	wait_for_completion_timeout(&scu->cmd_complete, IPC_TIMEOUT);
195253 
196254 	status = ipc_read_status(scu);
197
-	if (status & BIT(1))
255
+	if (status & IPC_STATUS_BUSY)
256
+		return -ETIMEDOUT;
257
+
258
+	if (status & IPC_STATUS_ERR)
198259 		return -EIO;
199260 
200261 	return 0;
....@@ -202,13 +263,31 @@
202263 
203264 static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
204265 {
205
-	return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
266
+	return scu->irq > 0 ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
267
+}
268
+
269
+static struct intel_scu_ipc_dev *intel_scu_ipc_get(struct intel_scu_ipc_dev *scu)
270
+{
271
+	u8 status;
272
+
273
+	if (!scu)
274
+		scu = ipcdev;
275
+	if (!scu)
276
+		return ERR_PTR(-ENODEV);
277
+
278
+	status = ipc_read_status(scu);
279
+	if (status & IPC_STATUS_BUSY) {
280
+		dev_dbg(&scu->dev, "device is busy\n");
281
+		return ERR_PTR(-EBUSY);
282
+	}
283
+
284
+	return scu;
206285 }
207286 
208287 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
209
-static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
288
+static int pwr_reg_rdwr(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
289
+			u32 count, u32 op, u32 id)
210290 {
211
-	struct intel_scu_ipc_dev *scu = &ipcdev;
212291 	int nc;
213292 	u32 offset = 0;
214293 	int err;
....@@ -218,10 +297,10 @@
218297 	memset(cbuf, 0, sizeof(cbuf));
219298 
220299 	mutex_lock(&ipclock);
221
-
222
-	if (scu->dev == NULL) {
300
+	scu = intel_scu_ipc_get(scu);
301
+	if (IS_ERR(scu)) {
223302 		mutex_unlock(&ipclock);
224
-		return -ENODEV;
303
+		return PTR_ERR(scu);
225304 	}
226305 
227306 	for (nc = 0; nc < count; nc++, offset += 2) {
....@@ -258,345 +337,198 @@
258337 }
259338 
260339 /**
261
- *	intel_scu_ipc_ioread8		-	read a word via the SCU
262
- *	@addr: register on SCU
263
- *	@data: return pointer for read byte
340
+ * intel_scu_ipc_dev_ioread8() - Read a byte via the SCU
341
+ * @scu: Optional SCU IPC instance
342
+ * @addr: Register on SCU
343
+ * @data: Return pointer for read byte
264344  *
265
- *	Read a single register. Returns 0 on success or an error code. All
266
- *	locking between SCU accesses is handled for the caller.
345
+ * Read a single register. Returns %0 on success or an error code. All
346
+ * locking between SCU accesses is handled for the caller.
267347  *
268
- *	This function may sleep.
348
+ * This function may sleep.
269349  */
270
-int intel_scu_ipc_ioread8(u16 addr, u8 *data)
350
+int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr, u8 *data)
271351 {
272
-	return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
352
+	return pwr_reg_rdwr(scu, &addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
273353 }
274
-EXPORT_SYMBOL(intel_scu_ipc_ioread8);
354
+EXPORT_SYMBOL(intel_scu_ipc_dev_ioread8);
275355 
276356 /**
277
- *	intel_scu_ipc_ioread16		-	read a word via the SCU
278
- *	@addr: register on SCU
279
- *	@data: return pointer for read word
357
+ * intel_scu_ipc_dev_iowrite8() - Write a byte via the SCU
358
+ * @scu: Optional SCU IPC instance
359
+ * @addr: Register on SCU
360
+ * @data: Byte to write
280361  *
281
- *	Read a register pair. Returns 0 on success or an error code. All
282
- *	locking between SCU accesses is handled for the caller.
362
+ * Write a single register. Returns %0 on success or an error code. All
363
+ * locking between SCU accesses is handled for the caller.
283364  *
284
- *	This function may sleep.
365
+ * This function may sleep.
285366  */
286
-int intel_scu_ipc_ioread16(u16 addr, u16 *data)
367
+int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr, u8 data)
287368 {
288
-	u16 x[2] = {addr, addr + 1};
289
-	return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
369
+	return pwr_reg_rdwr(scu, &addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
290370 }
291
-EXPORT_SYMBOL(intel_scu_ipc_ioread16);
371
+EXPORT_SYMBOL(intel_scu_ipc_dev_iowrite8);
292372 
293373 /**
294
- *	intel_scu_ipc_ioread32		-	read a dword via the SCU
295
- *	@addr: register on SCU
296
- *	@data: return pointer for read dword
374
+ * intel_scu_ipc_dev_readv() - Read a set of registers
375
+ * @scu: Optional SCU IPC instance
376
+ * @addr: Register list
377
+ * @data: Bytes to return
378
+ * @len: Length of array
297379  *
298
- *	Read four registers. Returns 0 on success or an error code. All
299
- *	locking between SCU accesses is handled for the caller.
380
+ * Read registers. Returns %0 on success or an error code. All locking
381
+ * between SCU accesses is handled for the caller.
300382  *
301
- *	This function may sleep.
383
+ * The largest array length permitted by the hardware is 5 items.
384
+ *
385
+ * This function may sleep.
302386  */
303
-int intel_scu_ipc_ioread32(u16 addr, u32 *data)
387
+int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
388
+			    size_t len)
304389 {
305
-	u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
306
-	return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
390
+	return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
307391 }
308
-EXPORT_SYMBOL(intel_scu_ipc_ioread32);
392
+EXPORT_SYMBOL(intel_scu_ipc_dev_readv);
309393 
310394 /**
311
- *	intel_scu_ipc_iowrite8		-	write a byte via the SCU
312
- *	@addr: register on SCU
313
- *	@data: byte to write
395
+ * intel_scu_ipc_dev_writev() - Write a set of registers
396
+ * @scu: Optional SCU IPC instance
397
+ * @addr: Register list
398
+ * @data: Bytes to write
399
+ * @len: Length of array
314400  *
315
- *	Write a single register. Returns 0 on success or an error code. All
316
- *	locking between SCU accesses is handled for the caller.
401
+ * Write registers. Returns %0 on success or an error code. All locking
402
+ * between SCU accesses is handled for the caller.
317403  *
318
- *	This function may sleep.
404
+ * The largest array length permitted by the hardware is 5 items.
405
+ *
406
+ * This function may sleep.
319407  */
320
-int intel_scu_ipc_iowrite8(u16 addr, u8 data)
408
+int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
409
+			     size_t len)
321410 {
322
-	return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
411
+	return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
323412 }
324
-EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
413
+EXPORT_SYMBOL(intel_scu_ipc_dev_writev);
325414 
326415 /**
327
- *	intel_scu_ipc_iowrite16		-	write a word via the SCU
328
- *	@addr: register on SCU
329
- *	@data: word to write
416
+ * intel_scu_ipc_dev_update() - Update a register
417
+ * @scu: Optional SCU IPC instance
418
+ * @addr: Register address
419
+ * @data: Bits to update
420
+ * @mask: Mask of bits to update
330421  *
331
- *	Write two registers. Returns 0 on success or an error code. All
332
- *	locking between SCU accesses is handled for the caller.
422
+ * Read-modify-write power control unit register. The first data argument
423
+ * must be register value and second is mask value mask is a bitmap that
424
+ * indicates which bits to update. %0 = masked. Don't modify this bit, %1 =
425
+ * modify this bit. returns %0 on success or an error code.
333426  *
334
- *	This function may sleep.
427
+ * This function may sleep. Locking between SCU accesses is handled
428
+ * for the caller.
335429  */
336
-int intel_scu_ipc_iowrite16(u16 addr, u16 data)
430
+int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr, u8 data,
431
+			     u8 mask)
337432 {
338
-	u16 x[2] = {addr, addr + 1};
339
-	return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
433
+	u8 tmp[2] = { data, mask };
434
+	return pwr_reg_rdwr(scu, &addr, tmp, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
340435 }
341
-EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
436
+EXPORT_SYMBOL(intel_scu_ipc_dev_update);
342437 
343438 /**
344
- *	intel_scu_ipc_iowrite32		-	write a dword via the SCU
345
- *	@addr: register on SCU
346
- *	@data: dword to write
439
+ * intel_scu_ipc_dev_simple_command() - Send a simple command
440
+ * @scu: Optional SCU IPC instance
441
+ * @cmd: Command
442
+ * @sub: Sub type
347443  *
348
- *	Write four registers. Returns 0 on success or an error code. All
349
- *	locking between SCU accesses is handled for the caller.
444
+ * Issue a simple command to the SCU. Do not use this interface if you must
445
+ * then access data as any data values may be overwritten by another SCU
446
+ * access by the time this function returns.
350447  *
351
- *	This function may sleep.
448
+ * This function may sleep. Locking for SCU accesses is handled for the
449
+ * caller.
352450  */
353
-int intel_scu_ipc_iowrite32(u16 addr, u32 data)
451
+int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,
452
+				     int sub)
354453 {
355
-	u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
356
-	return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
357
-}
358
-EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
359
-
360
-/**
361
- *	intel_scu_ipc_readvv		-	read a set of registers
362
- *	@addr: register list
363
- *	@data: bytes to return
364
- *	@len: length of array
365
- *
366
- *	Read registers. Returns 0 on success or an error code. All
367
- *	locking between SCU accesses is handled for the caller.
368
- *
369
- *	The largest array length permitted by the hardware is 5 items.
370
- *
371
- *	This function may sleep.
372
- */
373
-int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
374
-{
375
-	return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
376
-}
377
-EXPORT_SYMBOL(intel_scu_ipc_readv);
378
-
379
-/**
380
- *	intel_scu_ipc_writev		-	write a set of registers
381
- *	@addr: register list
382
- *	@data: bytes to write
383
- *	@len: length of array
384
- *
385
- *	Write registers. Returns 0 on success or an error code. All
386
- *	locking between SCU accesses is handled for the caller.
387
- *
388
- *	The largest array length permitted by the hardware is 5 items.
389
- *
390
- *	This function may sleep.
391
- *
392
- */
393
-int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
394
-{
395
-	return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
396
-}
397
-EXPORT_SYMBOL(intel_scu_ipc_writev);
398
-
399
-/**
400
- *	intel_scu_ipc_update_register	-	r/m/w a register
401
- *	@addr: register address
402
- *	@bits: bits to update
403
- *	@mask: mask of bits to update
404
- *
405
- *	Read-modify-write power control unit register. The first data argument
406
- *	must be register value and second is mask value
407
- *	mask is a bitmap that indicates which bits to update.
408
- *	0 = masked. Don't modify this bit, 1 = modify this bit.
409
- *	returns 0 on success or an error code.
410
- *
411
- *	This function may sleep. Locking between SCU accesses is handled
412
- *	for the caller.
413
- */
414
-int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
415
-{
416
-	u8 data[2] = { bits, mask };
417
-	return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
418
-}
419
-EXPORT_SYMBOL(intel_scu_ipc_update_register);
420
-
421
-/**
422
- *	intel_scu_ipc_simple_command	-	send a simple command
423
- *	@cmd: command
424
- *	@sub: sub type
425
- *
426
- *	Issue a simple command to the SCU. Do not use this interface if
427
- *	you must then access data as any data values may be overwritten
428
- *	by another SCU access by the time this function returns.
429
- *
430
- *	This function may sleep. Locking for SCU accesses is handled for
431
- *	the caller.
432
- */
433
-int intel_scu_ipc_simple_command(int cmd, int sub)
434
-{
435
-	struct intel_scu_ipc_dev *scu = &ipcdev;
454
+	u32 cmdval;
436455 	int err;
437456 
438457 	mutex_lock(&ipclock);
439
-	if (scu->dev == NULL) {
458
+	scu = intel_scu_ipc_get(scu);
459
+	if (IS_ERR(scu)) {
440460 		mutex_unlock(&ipclock);
441
-		return -ENODEV;
461
+		return PTR_ERR(scu);
442462 	}
443
-	ipc_command(scu, sub << 12 | cmd);
463
+
464
+	cmdval = sub << 12 | cmd;
465
+	ipc_command(scu, cmdval);
444466 	err = intel_scu_ipc_check_status(scu);
445467 	mutex_unlock(&ipclock);
468
+	if (err)
469
+		dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
446470 	return err;
447471 }
448
-EXPORT_SYMBOL(intel_scu_ipc_simple_command);
472
+EXPORT_SYMBOL(intel_scu_ipc_dev_simple_command);
449473 
450474 /**
451
- *	intel_scu_ipc_command	-	command with data
452
- *	@cmd: command
453
- *	@sub: sub type
454
- *	@in: input data
455
- *	@inlen: input length in dwords
456
- *	@out: output data
457
- *	@outlein: output length in dwords
475
+ * intel_scu_ipc_command_with_size() - Command with data
476
+ * @scu: Optional SCU IPC instance
477
+ * @cmd: Command
478
+ * @sub: Sub type
479
+ * @in: Input data
480
+ * @inlen: Input length in bytes
481
+ * @size: Input size written to the IPC command register in whatever
482
+ *	  units (dword, byte) the particular firmware requires. Normally
483
+ *	  should be the same as @inlen.
484
+ * @out: Output data
485
+ * @outlen: Output length in bytes
458486  *
459
- *	Issue a command to the SCU which involves data transfers. Do the
460
- *	data copies under the lock but leave it for the caller to interpret
487
+ * Issue a command to the SCU which involves data transfers. Do the
488
+ * data copies under the lock but leave it for the caller to interpret.
461489  */
462
-int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
463
-			  u32 *out, int outlen)
490
+int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,
491
+					int sub, const void *in, size_t inlen,
492
+					size_t size, void *out, size_t outlen)
464493 {
465
-	struct intel_scu_ipc_dev *scu = &ipcdev;
494
+	size_t outbuflen = DIV_ROUND_UP(outlen, sizeof(u32));
495
+	size_t inbuflen = DIV_ROUND_UP(inlen, sizeof(u32));
496
+	u32 cmdval, inbuf[4] = {};
466497 	int i, err;
467498 
468
-	mutex_lock(&ipclock);
469
-	if (scu->dev == NULL) {
470
-		mutex_unlock(&ipclock);
471
-		return -ENODEV;
472
-	}
473
-
474
-	for (i = 0; i < inlen; i++)
475
-		ipc_data_writel(scu, *in++, 4 * i);
476
-
477
-	ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
478
-	err = intel_scu_ipc_check_status(scu);
479
-
480
-	if (!err) {
481
-		for (i = 0; i < outlen; i++)
482
-			*out++ = ipc_data_readl(scu, 4 * i);
483
-	}
484
-
485
-	mutex_unlock(&ipclock);
486
-	return err;
487
-}
488
-EXPORT_SYMBOL(intel_scu_ipc_command);
489
-
490
-#define IPC_SPTR		0x08
491
-#define IPC_DPTR		0x0C
492
-
493
-/**
494
- * intel_scu_ipc_raw_command() - IPC command with data and pointers
495
- * @cmd:	IPC command code.
496
- * @sub:	IPC command sub type.
497
- * @in:		input data of this IPC command.
498
- * @inlen:	input data length in dwords.
499
- * @out:	output data of this IPC command.
500
- * @outlen:	output data length in dwords.
501
- * @sptr:	data writing to SPTR register.
502
- * @dptr:	data writing to DPTR register.
503
- *
504
- * Send an IPC command to SCU with input/output data and source/dest pointers.
505
- *
506
- * Return:	an IPC error code or 0 on success.
507
- */
508
-int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,
509
-			      u32 *out, int outlen, u32 dptr, u32 sptr)
510
-{
511
-	struct intel_scu_ipc_dev *scu = &ipcdev;
512
-	int inbuflen = DIV_ROUND_UP(inlen, 4);
513
-	u32 inbuf[4];
514
-	int i, err;
515
-
516
-	/* Up to 16 bytes */
517
-	if (inbuflen > 4)
499
+	if (inbuflen > 4 || outbuflen > 4)
518500 		return -EINVAL;
519501 
520502 	mutex_lock(&ipclock);
521
-	if (scu->dev == NULL) {
503
+	scu = intel_scu_ipc_get(scu);
504
+	if (IS_ERR(scu)) {
522505 		mutex_unlock(&ipclock);
523
-		return -ENODEV;
506
+		return PTR_ERR(scu);
524507 	}
525508 
526
-	writel(dptr, scu->ipc_base + IPC_DPTR);
527
-	writel(sptr, scu->ipc_base + IPC_SPTR);
528
-
529
-	/*
530
-	 * SRAM controller doesn't support 8-bit writes, it only
531
-	 * supports 32-bit writes, so we have to copy input data into
532
-	 * the temporary buffer, and SCU FW will use the inlen to
533
-	 * determine the actual input data length in the temporary
534
-	 * buffer.
535
-	 */
536509 	memcpy(inbuf, in, inlen);
537
-
538510 	for (i = 0; i < inbuflen; i++)
539511 		ipc_data_writel(scu, inbuf[i], 4 * i);
540512 
541
-	ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
513
+	cmdval = (size << 16) | (sub << 12) | cmd;
514
+	ipc_command(scu, cmdval);
542515 	err = intel_scu_ipc_check_status(scu);
516
+
543517 	if (!err) {
544
-		for (i = 0; i < outlen; i++)
545
-			*out++ = ipc_data_readl(scu, 4 * i);
518
+		u32 outbuf[4] = {};
519
+
520
+		for (i = 0; i < outbuflen; i++)
521
+			outbuf[i] = ipc_data_readl(scu, 4 * i);
522
+
523
+		memcpy(out, outbuf, outlen);
546524 	}
547525 
548526 	mutex_unlock(&ipclock);
527
+	if (err)
528
+		dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
549529 	return err;
550530 }
551
-EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);
552
-
553
-/* I2C commands */
554
-#define IPC_I2C_WRITE 1 /* I2C Write command */
555
-#define IPC_I2C_READ  2 /* I2C Read command */
556
-
557
-/**
558
- *	intel_scu_ipc_i2c_cntrl		-	I2C read/write operations
559
- *	@addr: I2C address + command bits
560
- *	@data: data to read/write
561
- *
562
- *	Perform an an I2C read/write operation via the SCU. All locking is
563
- *	handled for the caller. This function may sleep.
564
- *
565
- *	Returns an error code or 0 on success.
566
- *
567
- *	This has to be in the IPC driver for the locking.
568
- */
569
-int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
570
-{
571
-	struct intel_scu_ipc_dev *scu = &ipcdev;
572
-	u32 cmd = 0;
573
-
574
-	mutex_lock(&ipclock);
575
-	if (scu->dev == NULL) {
576
-		mutex_unlock(&ipclock);
577
-		return -ENODEV;
578
-	}
579
-	cmd = (addr >> 24) & 0xFF;
580
-	if (cmd == IPC_I2C_READ) {
581
-		writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
582
-		/* Write not getting updated without delay */
583
-		usleep_range(1000, 2000);
584
-		*data = readl(scu->i2c_base + I2C_DATA_ADDR);
585
-	} else if (cmd == IPC_I2C_WRITE) {
586
-		writel(*data, scu->i2c_base + I2C_DATA_ADDR);
587
-		usleep_range(1000, 2000);
588
-		writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
589
-	} else {
590
-		dev_err(scu->dev,
591
-			"intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
592
-
593
-		mutex_unlock(&ipclock);
594
-		return -EIO;
595
-	}
596
-	mutex_unlock(&ipclock);
597
-	return 0;
598
-}
599
-EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
531
+EXPORT_SYMBOL(intel_scu_ipc_dev_command_with_size);
600532 
601533 /*
602534  * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
....@@ -616,73 +548,179 @@
616548 	return IRQ_HANDLED;
617549 }
618550 
619
-/**
620
- *	ipc_probe	-	probe an Intel SCU IPC
621
- *	@pdev: the PCI device matching
622
- *	@id: entry in the match table
623
- *
624
- *	Enable and install an intel SCU IPC. This appears in the PCI space
625
- *	but uses some hard coded addresses as well.
626
- */
627
-static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
551
+static void intel_scu_ipc_release(struct device *dev)
628552 {
629
-	int err;
630
-	struct intel_scu_ipc_dev *scu = &ipcdev;
631
-	struct intel_scu_ipc_pdata_t *pdata;
553
+	struct intel_scu_ipc_dev *scu;
632554 
633
-	if (scu->dev)		/* We support only one SCU */
634
-		return -EBUSY;
635
-
636
-	pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
637
-	if (!pdata)
638
-		return -ENODEV;
639
-
640
-	err = pcim_enable_device(pdev);
641
-	if (err)
642
-		return err;
643
-
644
-	err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
645
-	if (err)
646
-		return err;
647
-
648
-	init_completion(&scu->cmd_complete);
649
-
650
-	scu->ipc_base = pcim_iomap_table(pdev)[0];
651
-
652
-	scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
653
-	if (!scu->i2c_base)
654
-		return -ENOMEM;
655
-
656
-	err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc",
657
-			       scu);
658
-	if (err)
659
-		return err;
660
-
661
-	/* Assign device at last */
662
-	scu->dev = &pdev->dev;
663
-
664
-	intel_scu_devices_create();
665
-
666
-	pci_set_drvdata(pdev, scu);
667
-	return 0;
555
+	scu = container_of(dev, struct intel_scu_ipc_dev, dev);
556
+	if (scu->irq > 0)
557
+		free_irq(scu->irq, scu);
558
+	iounmap(scu->ipc_base);
559
+	release_mem_region(scu->mem.start, resource_size(&scu->mem));
560
+	kfree(scu);
668561 }
669562 
670
-#define SCU_DEVICE(id, pdata)	{PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&pdata}
563
+/**
564
+ * __intel_scu_ipc_register() - Register SCU IPC device
565
+ * @parent: Parent device
566
+ * @scu_data: Data used to configure SCU IPC
567
+ * @owner: Module registering the SCU IPC device
568
+ *
569
+ * Call this function to register SCU IPC mechanism under @parent.
570
+ * Returns pointer to the new SCU IPC device or ERR_PTR() in case of
571
+ * failure. The caller may use the returned instance if it needs to do
572
+ * SCU IPC calls itself.
573
+ */
574
+struct intel_scu_ipc_dev *
575
+__intel_scu_ipc_register(struct device *parent,
576
+			 const struct intel_scu_ipc_data *scu_data,
577
+			 struct module *owner)
578
+{
579
+	int err;
580
+	struct intel_scu_ipc_dev *scu;
581
+	void __iomem *ipc_base;
671582 
672
-static const struct pci_device_id pci_ids[] = {
673
-	SCU_DEVICE(PCI_DEVICE_ID_LINCROFT,	intel_scu_ipc_lincroft_pdata),
674
-	SCU_DEVICE(PCI_DEVICE_ID_PENWELL,	intel_scu_ipc_penwell_pdata),
675
-	SCU_DEVICE(PCI_DEVICE_ID_CLOVERVIEW,	intel_scu_ipc_penwell_pdata),
676
-	SCU_DEVICE(PCI_DEVICE_ID_TANGIER,	intel_scu_ipc_tangier_pdata),
677
-	{}
678
-};
583
+	mutex_lock(&ipclock);
584
+	/* We support only one IPC */
585
+	if (ipcdev) {
586
+		err = -EBUSY;
587
+		goto err_unlock;
588
+	}
679589 
680
-static struct pci_driver ipc_driver = {
681
-	.driver = {
682
-		.suppress_bind_attrs = true,
683
-	},
684
-	.name = "intel_scu_ipc",
685
-	.id_table = pci_ids,
686
-	.probe = ipc_probe,
687
-};
688
-builtin_pci_driver(ipc_driver);
590
+	scu = kzalloc(sizeof(*scu), GFP_KERNEL);
591
+	if (!scu) {
592
+		err = -ENOMEM;
593
+		goto err_unlock;
594
+	}
595
+
596
+	scu->owner = owner;
597
+	scu->dev.parent = parent;
598
+	scu->dev.class = &intel_scu_ipc_class;
599
+	scu->dev.release = intel_scu_ipc_release;
600
+
601
+	if (!request_mem_region(scu_data->mem.start, resource_size(&scu_data->mem),
602
+				"intel_scu_ipc")) {
603
+		err = -EBUSY;
604
+		goto err_free;
605
+	}
606
+
607
+	ipc_base = ioremap(scu_data->mem.start, resource_size(&scu_data->mem));
608
+	if (!ipc_base) {
609
+		err = -ENOMEM;
610
+		goto err_release;
611
+	}
612
+
613
+	scu->ipc_base = ipc_base;
614
+	scu->mem = scu_data->mem;
615
+	scu->irq = scu_data->irq;
616
+	init_completion(&scu->cmd_complete);
617
+
618
+	if (scu->irq > 0) {
619
+		err = request_irq(scu->irq, ioc, 0, "intel_scu_ipc", scu);
620
+		if (err)
621
+			goto err_unmap;
622
+	}
623
+
624
+	/*
625
+	 * After this point intel_scu_ipc_release() takes care of
626
+	 * releasing the SCU IPC resources once refcount drops to zero.
627
+	 */
628
+	dev_set_name(&scu->dev, "intel_scu_ipc");
629
+	err = device_register(&scu->dev);
630
+	if (err) {
631
+		put_device(&scu->dev);
632
+		goto err_unlock;
633
+	}
634
+
635
+	/* Assign device at last */
636
+	ipcdev = scu;
637
+	mutex_unlock(&ipclock);
638
+
639
+	return scu;
640
+
641
+err_unmap:
642
+	iounmap(ipc_base);
643
+err_release:
644
+	release_mem_region(scu_data->mem.start, resource_size(&scu_data->mem));
645
+err_free:
646
+	kfree(scu);
647
+err_unlock:
648
+	mutex_unlock(&ipclock);
649
+
650
+	return ERR_PTR(err);
651
+}
652
+EXPORT_SYMBOL_GPL(__intel_scu_ipc_register);
653
+
654
+/**
655
+ * intel_scu_ipc_unregister() - Unregister SCU IPC
656
+ * @scu: SCU IPC handle
657
+ *
658
+ * This unregisters the SCU IPC device and releases the acquired
659
+ * resources once the refcount goes to zero.
660
+ */
661
+void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu)
662
+{
663
+	mutex_lock(&ipclock);
664
+	if (!WARN_ON(!ipcdev)) {
665
+		ipcdev = NULL;
666
+		device_unregister(&scu->dev);
667
+	}
668
+	mutex_unlock(&ipclock);
669
+}
670
+EXPORT_SYMBOL_GPL(intel_scu_ipc_unregister);
671
+
672
+static void devm_intel_scu_ipc_unregister(struct device *dev, void *res)
673
+{
674
+	struct intel_scu_ipc_devres *dr = res;
675
+	struct intel_scu_ipc_dev *scu = dr->scu;
676
+
677
+	intel_scu_ipc_unregister(scu);
678
+}
679
+
680
+/**
681
+ * __devm_intel_scu_ipc_register() - Register managed SCU IPC device
682
+ * @parent: Parent device
683
+ * @scu_data: Data used to configure SCU IPC
684
+ * @owner: Module registering the SCU IPC device
685
+ *
686
+ * Call this function to register managed SCU IPC mechanism under
687
+ * @parent. Returns pointer to the new SCU IPC device or ERR_PTR() in
688
+ * case of failure. The caller may use the returned instance if it needs
689
+ * to do SCU IPC calls itself.
690
+ */
691
+struct intel_scu_ipc_dev *
692
+__devm_intel_scu_ipc_register(struct device *parent,
693
+			      const struct intel_scu_ipc_data *scu_data,
694
+			      struct module *owner)
695
+{
696
+	struct intel_scu_ipc_devres *dr;
697
+	struct intel_scu_ipc_dev *scu;
698
+
699
+	dr = devres_alloc(devm_intel_scu_ipc_unregister, sizeof(*dr), GFP_KERNEL);
700
+	if (!dr)
701
+		return NULL;
702
+
703
+	scu = __intel_scu_ipc_register(parent, scu_data, owner);
704
+	if (IS_ERR(scu)) {
705
+		devres_free(dr);
706
+		return scu;
707
+	}
708
+
709
+	dr->scu = scu;
710
+	devres_add(parent, dr);
711
+
712
+	return scu;
713
+}
714
+EXPORT_SYMBOL_GPL(__devm_intel_scu_ipc_register);
715
+
716
+static int __init intel_scu_ipc_init(void)
717
+{
718
+	return class_register(&intel_scu_ipc_class);
719
+}
720
+subsys_initcall(intel_scu_ipc_init);
721
+
722
+static void __exit intel_scu_ipc_exit(void)
723
+{
724
+	class_unregister(&intel_scu_ipc_class);
725
+}
726
+module_exit(intel_scu_ipc_exit);