add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/platform/x86/intel_atomisp2_pm.c
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@@ -1,8 +1,8 @@
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 // SPDX-License-Identifier: GPL-2.0
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 /*
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- * Dummy driver for Intel's Image Signal Processor found on Bay and Cherry
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- * Trail devices. The sole purpose of this driver is to allow the ISP to
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- * be put in D3.
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+ * Dummy driver for Intel's Image Signal Processor found on Bay Trail
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+ * and Cherry Trail devices. The sole purpose of this driver is to allow
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+ * the ISP to be put in D3.
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  *
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  * Copyright (C) 2018 Hans de Goede <hdegoede@redhat.com>
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  *
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@@ -36,8 +36,7 @@
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 static int isp_set_power(struct pci_dev *dev, bool enable)
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 {
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 	unsigned long timeout;
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-	u32 val = enable ? ISPSSPM0_IUNIT_POWER_ON :
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-		ISPSSPM0_IUNIT_POWER_OFF;
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+	u32 val = enable ? ISPSSPM0_IUNIT_POWER_ON : ISPSSPM0_IUNIT_POWER_OFF;
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 	/* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
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 	iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM0,
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@@ -45,29 +44,25 @@
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 	/*
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 	 * There should be no IUNIT access while power-down is
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-	 * in progress HW sighting: 4567865
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+	 * in progress. HW sighting: 4567865.
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 	 * Wait up to 50 ms for the IUNIT to shut down.
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 	 * And we do the same for power on.
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 	 */
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 	timeout = jiffies + msecs_to_jiffies(50);
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-	while (1) {
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+	do {
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 		u32 tmp;
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 		/* Wait until ISPSSPM0 bit[25:24] shows the right value */
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 		iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM0, &tmp);
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 		tmp = (tmp & ISPSSPM0_ISPSSS_MASK) >> ISPSSPM0_ISPSSS_OFFSET;
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 		if (tmp == val)
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-			break;
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+			return 0;
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-		if (time_after(jiffies, timeout)) {
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-			dev_err(&dev->dev, "IUNIT power-%s timeout.\n",
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-				enable ? "on" : "off");
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-			return -EBUSY;
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-		}
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 		usleep_range(1000, 2000);
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-	}
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+	} while (time_before(jiffies, timeout));
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-	return 0;
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+	dev_err(&dev->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
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+	return -EBUSY;
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 }
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 static int isp_probe(struct pci_dev *dev, const struct pci_device_id *id)