~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,7 @@
8	8	*/
9	9	#include <linux/clk.h>
10	10	#include <linux/gpio/driver.h>
	11	+#include <linux/hwspinlock.h>
11	12	#include <linux/io.h>
12	13	#include <linux/irq.h>
13	14	#include <linux/mfd/syscon.h>
..	..	@@ -43,6 +44,18 @@
43	44	#define STM32_GPIO_AFRL 0x20
44	45	#define STM32_GPIO_AFRH 0x24
45	46
	47	+/* custom bitfield to backup pin status */
	48	+#define STM32_GPIO_BKP_MODE_SHIFT 0
	49	+#define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
	50	+#define STM32_GPIO_BKP_ALT_SHIFT 2
	51	+#define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
	52	+#define STM32_GPIO_BKP_SPEED_SHIFT 6
	53	+#define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
	54	+#define STM32_GPIO_BKP_PUPD_SHIFT 8
	55	+#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
	56	+#define STM32_GPIO_BKP_TYPE 10
	57	+#define STM32_GPIO_BKP_VAL 11
	58	+
46	59	#define STM32_GPIO_PINS_PER_BANK 16
47	60	#define STM32_GPIO_IRQ_LINE 16
48	61
..	..	@@ -50,6 +63,8 @@
50	63
51	64	#define gpio_range_to_bank(chip) \
52	65	container_of(chip, struct stm32_gpio_bank, range)
	66	+
	67	+#define HWSPNLCK_TIMEOUT 1000 /* usec */
53	68
54	69	static const char * const stm32_gpio_functions[] = {
55	70	"gpio", "af0", "af1",
..	..	@@ -69,6 +84,7 @@
69	84	struct stm32_gpio_bank {
70	85	void __iomem *base;
71	86	struct clk *clk;
	87	+ struct reset_control *rstc;
72	88	spinlock_t lock;
73	89	struct gpio_chip gpio_chip;
74	90	struct pinctrl_gpio_range range;
..	..	@@ -76,6 +92,8 @@
76	92	struct irq_domain *domain;
77	93	u32 bank_nr;
78	94	u32 bank_ioport_nr;
	95	+ u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
	96	+ u8 irq_type[STM32_GPIO_PINS_PER_BANK];
79	97	};
80	98
81	99	struct stm32_pinctrl {
..	..	@@ -91,6 +109,12 @@
91	109	struct irq_domain *domain;
92	110	struct regmap *regmap;
93	111	struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
	112	+ struct hwspinlock *hwlock;
	113	+ struct stm32_desc_pin *pins;
	114	+ u32 npins;
	115	+ u32 pkg;
	116	+ u16 irqmux_map;
	117	+ spinlock_t irqmux_lock;
94	118	};
95	119
96	120	static inline int stm32_gpio_pin(int gpio)
..	..	@@ -126,11 +150,50 @@
126	150	return 0;
127	151	}
128	152
	153	+static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
	154	+ u32 offset, u32 value)
	155	+{
	156	+ bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
	157	+ bank->pin_backup[offset] \|= value << STM32_GPIO_BKP_VAL;
	158	+}
	159	+
	160	+static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
	161	+ u32 mode, u32 alt)
	162	+{
	163	+ bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK \|
	164	+ STM32_GPIO_BKP_ALT_MASK);
	165	+ bank->pin_backup[offset] \|= mode << STM32_GPIO_BKP_MODE_SHIFT;
	166	+ bank->pin_backup[offset] \|= alt << STM32_GPIO_BKP_ALT_SHIFT;
	167	+}
	168	+
	169	+static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
	170	+ u32 drive)
	171	+{
	172	+ bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
	173	+ bank->pin_backup[offset] \|= drive << STM32_GPIO_BKP_TYPE;
	174	+}
	175	+
	176	+static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
	177	+ u32 speed)
	178	+{
	179	+ bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
	180	+ bank->pin_backup[offset] \|= speed << STM32_GPIO_BKP_SPEED_SHIFT;
	181	+}
	182	+
	183	+static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
	184	+ u32 bias)
	185	+{
	186	+ bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
	187	+ bank->pin_backup[offset] \|= bias << STM32_GPIO_BKP_PUPD_SHIFT;
	188	+}
	189	+
129	190	/* GPIO functions */
130	191
131	192	static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
132	193	unsigned offset, int value)
133	194	{
	195	+ stm32_gpio_backup_value(bank, offset, value);
	196	+
134	197	if (!value)
135	198	offset += STM32_GPIO_PINS_PER_BANK;
136	199
..	..	@@ -162,6 +225,13 @@
162	225	pinctrl_gpio_free(chip->base + offset);
163	226	}
164	227
	228	+static int stm32_gpio_get_noclk(struct gpio_chip *chip, unsigned int offset)
	229	+{
	230	+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
	231	+
	232	+ return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
	233	+}
	234	+
165	235	static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
166	236	{
167	237	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
..	..	@@ -169,7 +239,7 @@
169	239
170	240	clk_enable(bank->clk);
171	241
172		- ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
	242	+ ret = stm32_gpio_get_noclk(chip, offset);
173	243
174	244	clk_disable(bank->clk);
175	245
..	..	@@ -222,9 +292,9 @@
222	292
223	293	stm32_pmx_get_mode(bank, pin, &mode, &alt);
224	294	if ((alt == 0) && (mode == 0))
225		- ret = 1;
	295	+ ret = GPIO_LINE_DIRECTION_IN;
226	296	else if ((alt == 0) && (mode == 1))
227		- ret = 0;
	297	+ ret = GPIO_LINE_DIRECTION_OUT;
228	298	else
229	299	ret = -EINVAL;
230	300
..	..	@@ -240,12 +310,62 @@
240	310	.direction_output = stm32_gpio_direction_output,
241	311	.to_irq = stm32_gpio_to_irq,
242	312	.get_direction = stm32_gpio_get_direction,
	313	+ .set_config = gpiochip_generic_config,
	314	+};
	315	+
	316	+static void stm32_gpio_irq_trigger(struct irq_data *d)
	317	+{
	318	+ struct stm32_gpio_bank *bank = d->domain->host_data;
	319	+ int level;
	320	+
	321	+ /* Do not access the GPIO if this is not LEVEL triggered IRQ. */
	322	+ if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
	323	+ return;
	324	+
	325	+ /* If level interrupt type then retrig */
	326	+ level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq);
	327	+ if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) \|\|
	328	+ (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
	329	+ irq_chip_retrigger_hierarchy(d);
	330	+}
	331	+
	332	+static void stm32_gpio_irq_eoi(struct irq_data *d)
	333	+{
	334	+ irq_chip_eoi_parent(d);
	335	+ stm32_gpio_irq_trigger(d);
	336	+};
	337	+
	338	+static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
	339	+{
	340	+ struct stm32_gpio_bank *bank = d->domain->host_data;
	341	+ u32 parent_type;
	342	+
	343	+ switch (type) {
	344	+ case IRQ_TYPE_EDGE_RISING:
	345	+ case IRQ_TYPE_EDGE_FALLING:
	346	+ case IRQ_TYPE_EDGE_BOTH:
	347	+ parent_type = type;
	348	+ break;
	349	+ case IRQ_TYPE_LEVEL_HIGH:
	350	+ parent_type = IRQ_TYPE_EDGE_RISING;
	351	+ break;
	352	+ case IRQ_TYPE_LEVEL_LOW:
	353	+ parent_type = IRQ_TYPE_EDGE_FALLING;
	354	+ break;
	355	+ default:
	356	+ return -EINVAL;
	357	+ }
	358	+
	359	+ bank->irq_type[d->hwirq] = type;
	360	+
	361	+ return irq_chip_set_type_parent(d, parent_type);
243	362	};
244	363
245	364	static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
246	365	{
247	366	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
248	367	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
	368	+ unsigned long flags;
249	369	int ret;
250	370
251	371	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
..	..	@@ -259,6 +379,10 @@
259	379	return ret;
260	380	}
261	381
	382	+ flags = irqd_get_trigger_type(irq_data);
	383	+ if (flags & IRQ_TYPE_LEVEL_MASK)
	384	+ clk_enable(bank->clk);
	385	+
262	386	return 0;
263	387	}
264	388
..	..	@@ -266,16 +390,25 @@
266	390	{
267	391	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
268	392
	393	+ if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK)
	394	+ clk_disable(bank->clk);
	395	+
269	396	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
	397	+}
	398	+
	399	+static void stm32_gpio_irq_unmask(struct irq_data *d)
	400	+{
	401	+ irq_chip_unmask_parent(d);
	402	+ stm32_gpio_irq_trigger(d);
270	403	}
271	404
272	405	static struct irq_chip stm32_gpio_irq_chip = {
273	406	.name = "stm32gpio",
274		- .irq_eoi = irq_chip_eoi_parent,
	407	+ .irq_eoi = stm32_gpio_irq_eoi,
275	408	.irq_ack = irq_chip_ack_parent,
276	409	.irq_mask = irq_chip_mask_parent,
277		- .irq_unmask = irq_chip_unmask_parent,
278		- .irq_set_type = irq_chip_set_type_parent,
	410	+ .irq_unmask = stm32_gpio_irq_unmask,
	411	+ .irq_set_type = stm32_gpio_set_type,
279	412	.irq_set_wake = irq_chip_set_wake_parent,
280	413	.irq_request_resources = stm32_gpio_irq_request_resources,
281	414	.irq_release_resources = stm32_gpio_irq_release_resources,
..	..	@@ -300,9 +433,55 @@
300	433	{
301	434	struct stm32_gpio_bank *bank = d->host_data;
302	435	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
	436	+ unsigned long flags;
	437	+ int ret = 0;
	438	+
	439	+ /*
	440	+ * gpio irq mux is shared between several banks, a lock has to be done
	441	+ * to avoid overriding.
	442	+ */
	443	+ spin_lock_irqsave(&pctl->irqmux_lock, flags);
	444	+
	445	+ if (pctl->hwlock) {
	446	+ ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
	447	+ HWSPNLCK_TIMEOUT);
	448	+ if (ret) {
	449	+ dev_err(pctl->dev, "Can't get hwspinlock\n");
	450	+ goto unlock;
	451	+ }
	452	+ }
	453	+
	454	+ if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
	455	+ dev_err(pctl->dev, "irq line %ld already requested.\n",
	456	+ irq_data->hwirq);
	457	+ ret = -EBUSY;
	458	+ if (pctl->hwlock)
	459	+ hwspin_unlock_in_atomic(pctl->hwlock);
	460	+ goto unlock;
	461	+ } else {
	462	+ pctl->irqmux_map \|= BIT(irq_data->hwirq);
	463	+ }
303	464
304	465	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
305		- return 0;
	466	+
	467	+ if (pctl->hwlock)
	468	+ hwspin_unlock_in_atomic(pctl->hwlock);
	469	+
	470	+unlock:
	471	+ spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
	472	+ return ret;
	473	+}
	474	+
	475	+static void stm32_gpio_domain_deactivate(struct irq_domain *d,
	476	+ struct irq_data *irq_data)
	477	+{
	478	+ struct stm32_gpio_bank *bank = d->host_data;
	479	+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
	480	+ unsigned long flags;
	481	+
	482	+ spin_lock_irqsave(&pctl->irqmux_lock, flags);
	483	+ pctl->irqmux_map &= ~BIT(irq_data->hwirq);
	484	+ spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
306	485	}
307	486
308	487	static int stm32_gpio_domain_alloc(struct irq_domain *d,
..	..	@@ -331,6 +510,7 @@
331	510	.alloc = stm32_gpio_domain_alloc,
332	511	.free = irq_domain_free_irqs_common,
333	512	.activate = stm32_gpio_domain_activate,
	513	+ .deactivate = stm32_gpio_domain_deactivate,
334	514	};
335	515
336	516	/* Pinctrl functions */
..	..	@@ -354,8 +534,8 @@
354	534	{
355	535	int i;
356	536
357		- for (i = 0; i < pctl->match_data->npins; i++) {
358		- const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
	537	+ for (i = 0; i < pctl->npins; i++) {
	538	+ const struct stm32_desc_pin *pin = pctl->pins + i;
359	539	const struct stm32_desc_function *func = pin->functions;
360	540
361	541	if (pin->pin.number != pin_num)
..	..	@@ -416,8 +596,8 @@
416	596
417	597	pins = of_find_property(node, "pinmux", NULL);
418	598	if (!pins) {
419		- dev_err(pctl->dev, "missing pins property in node %s .\n",
420		- node->name);
	599	+ dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
	600	+ node);
421	601	return -EINVAL;
422	602	}
423	603
..	..	@@ -509,6 +689,7 @@
509	689	&reserved_maps, num_maps);
510	690	if (ret < 0) {
511	691	pinctrl_utils_free_map(pctldev, map, num_maps);
	692	+ of_node_put(np);
512	693	return ret;
513	694	}
514	695	}
..	..	@@ -579,16 +760,27 @@
579	760	return 0;
580	761	}
581	762
582		-static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
583		- int pin, u32 mode, u32 alt)
	763	+static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
	764	+ int pin, u32 mode, u32 alt)
584	765	{
	766	+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
585	767	u32 val;
586	768	int alt_shift = (pin % 8) * 4;
587	769	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
588	770	unsigned long flags;
	771	+ int err = 0;
589	772
590	773	clk_enable(bank->clk);
591	774	spin_lock_irqsave(&bank->lock, flags);
	775	+
	776	+ if (pctl->hwlock) {
	777	+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
	778	+ HWSPNLCK_TIMEOUT);
	779	+ if (err) {
	780	+ dev_err(pctl->dev, "Can't get hwspinlock\n");
	781	+ goto unlock;
	782	+ }
	783	+ }
592	784
593	785	val = readl_relaxed(bank->base + alt_offset);
594	786	val &= ~GENMASK(alt_shift + 3, alt_shift);
..	..	@@ -600,8 +792,16 @@
600	792	val \|= mode << (pin * 2);
601	793	writel_relaxed(val, bank->base + STM32_GPIO_MODER);
602	794
	795	+ if (pctl->hwlock)
	796	+ hwspin_unlock_in_atomic(pctl->hwlock);
	797	+
	798	+ stm32_gpio_backup_mode(bank, pin, mode, alt);
	799	+
	800	+unlock:
603	801	spin_unlock_irqrestore(&bank->lock, flags);
604	802	clk_disable(bank->clk);
	803	+
	804	+ return err;
605	805	}
606	806
607	807	void stm32_pmx_get_mode(struct stm32_gpio_bank bank, int pin, u32 mode,
..	..	@@ -658,9 +858,7 @@
658	858	mode = stm32_gpio_get_mode(function);
659	859	alt = stm32_gpio_get_alt(function);
660	860
661		- stm32_pmx_set_mode(bank, pin, mode, alt);
662		-
663		- return 0;
	861	+ return stm32_pmx_set_mode(bank, pin, mode, alt);
664	862	}
665	863
666	864	static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
..	..	@@ -670,9 +868,7 @@
670	868	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
671	869	int pin = stm32_gpio_pin(gpio);
672	870
673		- stm32_pmx_set_mode(bank, pin, !input, 0);
674		-
675		- return 0;
	871	+ return stm32_pmx_set_mode(bank, pin, !input, 0);
676	872	}
677	873
678	874	static const struct pinmux_ops stm32_pmx_ops = {
..	..	@@ -686,22 +882,41 @@
686	882
687	883	/* Pinconf functions */
688	884
689		-static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
690		- unsigned offset, u32 drive)
	885	+static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
	886	+ unsigned offset, u32 drive)
691	887	{
	888	+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
692	889	unsigned long flags;
693	890	u32 val;
	891	+ int err = 0;
694	892
695	893	clk_enable(bank->clk);
696	894	spin_lock_irqsave(&bank->lock, flags);
	895	+
	896	+ if (pctl->hwlock) {
	897	+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
	898	+ HWSPNLCK_TIMEOUT);
	899	+ if (err) {
	900	+ dev_err(pctl->dev, "Can't get hwspinlock\n");
	901	+ goto unlock;
	902	+ }
	903	+ }
697	904
698	905	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
699	906	val &= ~BIT(offset);
700	907	val \|= drive << offset;
701	908	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
702	909
	910	+ if (pctl->hwlock)
	911	+ hwspin_unlock_in_atomic(pctl->hwlock);
	912	+
	913	+ stm32_gpio_backup_driving(bank, offset, drive);
	914	+
	915	+unlock:
703	916	spin_unlock_irqrestore(&bank->lock, flags);
704	917	clk_disable(bank->clk);
	918	+
	919	+ return err;
705	920	}
706	921
707	922	static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
..	..	@@ -722,22 +937,41 @@
722	937	return (val >> offset);
723	938	}
724	939
725		-static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
726		- unsigned offset, u32 speed)
	940	+static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
	941	+ unsigned offset, u32 speed)
727	942	{
	943	+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
728	944	unsigned long flags;
729	945	u32 val;
	946	+ int err = 0;
730	947
731	948	clk_enable(bank->clk);
732	949	spin_lock_irqsave(&bank->lock, flags);
	950	+
	951	+ if (pctl->hwlock) {
	952	+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
	953	+ HWSPNLCK_TIMEOUT);
	954	+ if (err) {
	955	+ dev_err(pctl->dev, "Can't get hwspinlock\n");
	956	+ goto unlock;
	957	+ }
	958	+ }
733	959
734	960	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
735	961	val &= ~GENMASK(offset * 2 + 1, offset * 2);
736	962	val \|= speed << (offset * 2);
737	963	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
738	964
	965	+ if (pctl->hwlock)
	966	+ hwspin_unlock_in_atomic(pctl->hwlock);
	967	+
	968	+ stm32_gpio_backup_speed(bank, offset, speed);
	969	+
	970	+unlock:
739	971	spin_unlock_irqrestore(&bank->lock, flags);
740	972	clk_disable(bank->clk);
	973	+
	974	+ return err;
741	975	}
742	976
743	977	static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
..	..	@@ -758,22 +992,41 @@
758	992	return (val >> (offset * 2));
759	993	}
760	994
761		-static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
762		- unsigned offset, u32 bias)
	995	+static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
	996	+ unsigned offset, u32 bias)
763	997	{
	998	+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
764	999	unsigned long flags;
765	1000	u32 val;
	1001	+ int err = 0;
766	1002
767	1003	clk_enable(bank->clk);
768	1004	spin_lock_irqsave(&bank->lock, flags);
	1005	+
	1006	+ if (pctl->hwlock) {
	1007	+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
	1008	+ HWSPNLCK_TIMEOUT);
	1009	+ if (err) {
	1010	+ dev_err(pctl->dev, "Can't get hwspinlock\n");
	1011	+ goto unlock;
	1012	+ }
	1013	+ }
769	1014
770	1015	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
771	1016	val &= ~GENMASK(offset * 2 + 1, offset * 2);
772	1017	val \|= bias << (offset * 2);
773	1018	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
774	1019
	1020	+ if (pctl->hwlock)
	1021	+ hwspin_unlock_in_atomic(pctl->hwlock);
	1022	+
	1023	+ stm32_gpio_backup_bias(bank, offset, bias);
	1024	+
	1025	+unlock:
775	1026	spin_unlock_irqrestore(&bank->lock, flags);
776	1027	clk_disable(bank->clk);
	1028	+
	1029	+ return err;
777	1030	}
778	1031
779	1032	static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
..	..	@@ -825,7 +1078,7 @@
825	1078	struct stm32_gpio_bank *bank;
826	1079	int offset, ret = 0;
827	1080
828		- range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
	1081	+ range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
829	1082	if (!range) {
830	1083	dev_err(pctl->dev, "No gpio range defined.\n");
831	1084	return -EINVAL;
..	..	@@ -836,29 +1089,29 @@
836	1089
837	1090	switch (param) {
838	1091	case PIN_CONFIG_DRIVE_PUSH_PULL:
839		- stm32_pconf_set_driving(bank, offset, 0);
	1092	+ ret = stm32_pconf_set_driving(bank, offset, 0);
840	1093	break;
841	1094	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
842		- stm32_pconf_set_driving(bank, offset, 1);
	1095	+ ret = stm32_pconf_set_driving(bank, offset, 1);
843	1096	break;
844	1097	case PIN_CONFIG_SLEW_RATE:
845		- stm32_pconf_set_speed(bank, offset, arg);
	1098	+ ret = stm32_pconf_set_speed(bank, offset, arg);
846	1099	break;
847	1100	case PIN_CONFIG_BIAS_DISABLE:
848		- stm32_pconf_set_bias(bank, offset, 0);
	1101	+ ret = stm32_pconf_set_bias(bank, offset, 0);
849	1102	break;
850	1103	case PIN_CONFIG_BIAS_PULL_UP:
851		- stm32_pconf_set_bias(bank, offset, 1);
	1104	+ ret = stm32_pconf_set_bias(bank, offset, 1);
852	1105	break;
853	1106	case PIN_CONFIG_BIAS_PULL_DOWN:
854		- stm32_pconf_set_bias(bank, offset, 2);
	1107	+ ret = stm32_pconf_set_bias(bank, offset, 2);
855	1108	break;
856	1109	case PIN_CONFIG_OUTPUT:
857	1110	__stm32_gpio_set(bank, offset, arg);
858	1111	ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
859	1112	break;
860	1113	default:
861		- ret = -EINVAL;
	1114	+ ret = -ENOTSUPP;
862	1115	}
863	1116
864	1117	return ret;
..	..	@@ -883,13 +1136,31 @@
883	1136	int i, ret;
884	1137
885	1138	for (i = 0; i < num_configs; i++) {
	1139	+ mutex_lock(&pctldev->mutex);
886	1140	ret = stm32_pconf_parse_conf(pctldev, g->pin,
887	1141	pinconf_to_config_param(configs[i]),
888	1142	pinconf_to_config_argument(configs[i]));
	1143	+ mutex_unlock(&pctldev->mutex);
889	1144	if (ret < 0)
890	1145	return ret;
891	1146
892	1147	g->config = configs[i];
	1148	+ }
	1149	+
	1150	+ return 0;
	1151	+}
	1152	+
	1153	+static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
	1154	+ unsigned long *configs, unsigned int num_configs)
	1155	+{
	1156	+ int i, ret;
	1157	+
	1158	+ for (i = 0; i < num_configs; i++) {
	1159	+ ret = stm32_pconf_parse_conf(pctldev, pin,
	1160	+ pinconf_to_config_param(configs[i]),
	1161	+ pinconf_to_config_argument(configs[i]));
	1162	+ if (ret < 0)
	1163	+ return ret;
893	1164	}
894	1165
895	1166	return 0;
..	..	@@ -960,10 +1231,10 @@
960	1231	}
961	1232	}
962	1233
963		-
964	1234	static const struct pinconf_ops stm32_pconf_ops = {
965	1235	.pin_config_group_get = stm32_pconf_group_get,
966	1236	.pin_config_group_set = stm32_pconf_group_set,
	1237	+ .pin_config_set = stm32_pconf_set,
967	1238	.pin_config_dbg_show = stm32_pconf_dbg_show,
968	1239	};
969	1240
..	..	@@ -976,13 +1247,11 @@
976	1247	struct of_phandle_args args;
977	1248	struct device *dev = pctl->dev;
978	1249	struct resource res;
979		- struct reset_control *rstc;
980	1250	int npins = STM32_GPIO_PINS_PER_BANK;
981	1251	int bank_nr, err, i = 0;
982	1252
983		- rstc = of_reset_control_get_exclusive(np, NULL);
984		- if (!IS_ERR(rstc))
985		- reset_control_deassert(rstc);
	1253	+ if (!IS_ERR(bank->rstc))
	1254	+ reset_control_deassert(bank->rstc);
986	1255
987	1256	if (of_address_to_resource(np, 0, &res))
988	1257	return -ENODEV;
..	..	@@ -990,12 +1259,6 @@
990	1259	bank->base = devm_ioremap_resource(dev, &res);
991	1260	if (IS_ERR(bank->base))
992	1261	return PTR_ERR(bank->base);
993		-
994		- bank->clk = of_clk_get_by_name(np, NULL);
995		- if (IS_ERR(bank->clk)) {
996		- dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
997		- return PTR_ERR(bank->clk);
998		- }
999	1262
1000	1263	err = clk_prepare(bank->clk);
1001	1264	if (err) {
..	..	@@ -1040,15 +1303,17 @@
1040	1303	bank->bank_ioport_nr = bank_ioport_nr;
1041	1304	spin_lock_init(&bank->lock);
1042	1305
1043		- /* create irq hierarchical domain */
1044		- bank->fwnode = of_node_to_fwnode(np);
	1306	+ if (pctl->domain) {
	1307	+ /* create irq hierarchical domain */
	1308	+ bank->fwnode = of_node_to_fwnode(np);
1045	1309
1046		- bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1047		- STM32_GPIO_IRQ_LINE, bank->fwnode,
1048		- &stm32_gpio_domain_ops, bank);
	1310	+ bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
	1311	+ bank->fwnode, &stm32_gpio_domain_ops,
	1312	+ bank);
1049	1313
1050		- if (!bank->domain)
1051		- return -ENODEV;
	1314	+ if (!bank->domain)
	1315	+ return -ENODEV;
	1316	+ }
1052	1317
1053	1318	err = gpiochip_add_data(&bank->gpio_chip, bank);
1054	1319	if (err) {
..	..	@@ -1060,22 +1325,35 @@
1060	1325	return 0;
1061	1326	}
1062	1327
	1328	+static struct irq_domain stm32_pctrl_get_irq_domain(struct device_node np)
	1329	+{
	1330	+ struct device_node *parent;
	1331	+ struct irq_domain *domain;
	1332	+
	1333	+ if (!of_find_property(np, "interrupt-parent", NULL))
	1334	+ return NULL;
	1335	+
	1336	+ parent = of_irq_find_parent(np);
	1337	+ if (!parent)
	1338	+ return ERR_PTR(-ENXIO);
	1339	+
	1340	+ domain = irq_find_host(parent);
	1341	+ of_node_put(parent);
	1342	+ if (!domain)
	1343	+ /* domain not registered yet */
	1344	+ return ERR_PTR(-EPROBE_DEFER);
	1345	+
	1346	+ return domain;
	1347	+}
	1348	+
1063	1349	static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1064	1350	struct stm32_pinctrl *pctl)
1065	1351	{
1066		- struct device_node np = pdev->dev.of_node, parent;
	1352	+ struct device_node *np = pdev->dev.of_node;
1067	1353	struct device *dev = &pdev->dev;
1068	1354	struct regmap *rm;
1069	1355	int offset, ret, i;
1070	1356	int mask, mask_width;
1071		-
1072		- parent = of_irq_find_parent(np);
1073		- if (!parent)
1074		- return -ENXIO;
1075		-
1076		- pctl->domain = irq_find_host(parent);
1077		- if (!pctl->domain)
1078		- return -ENXIO;
1079	1357
1080	1358	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1081	1359	if (IS_ERR(pctl->regmap))
..	..	@@ -1116,7 +1394,7 @@
1116	1394	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1117	1395	int i;
1118	1396
1119		- pctl->ngroups = pctl->match_data->npins;
	1397	+ pctl->ngroups = pctl->npins;
1120	1398
1121	1399	/* Allocate groups */
1122	1400	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
..	..	@@ -1130,17 +1408,48 @@
1130	1408	if (!pctl->grp_names)
1131	1409	return -ENOMEM;
1132	1410
1133		- for (i = 0; i < pctl->match_data->npins; i++) {
1134		- const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
	1411	+ for (i = 0; i < pctl->npins; i++) {
	1412	+ const struct stm32_desc_pin *pin = pctl->pins + i;
1135	1413	struct stm32_pinctrl_group *group = pctl->groups + i;
1136	1414
1137	1415	group->name = pin->pin.name;
1138	1416	group->pin = pin->pin.number;
1139		-
1140	1417	pctl->grp_names[i] = pin->pin.name;
1141	1418	}
1142	1419
1143	1420	return 0;
	1421	+}
	1422	+
	1423	+static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
	1424	+ struct stm32_desc_pin *pins)
	1425	+{
	1426	+ const struct stm32_desc_pin *p;
	1427	+ int i, nb_pins_available = 0;
	1428	+
	1429	+ for (i = 0; i < pctl->match_data->npins; i++) {
	1430	+ p = pctl->match_data->pins + i;
	1431	+ if (pctl->pkg && !(pctl->pkg & p->pkg))
	1432	+ continue;
	1433	+ pins->pin = p->pin;
	1434	+ pins->functions = p->functions;
	1435	+ pins++;
	1436	+ nb_pins_available++;
	1437	+ }
	1438	+
	1439	+ pctl->npins = nb_pins_available;
	1440	+
	1441	+ return 0;
	1442	+}
	1443	+
	1444	+static void stm32_pctl_get_package(struct device_node *np,
	1445	+ struct stm32_pinctrl *pctl)
	1446	+{
	1447	+ if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
	1448	+ pctl->pkg = 0;
	1449	+ dev_warn(pctl->dev, "No package detected, use default one\n");
	1450	+ } else {
	1451	+ dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
	1452	+ }
1144	1453	}
1145	1454
1146	1455	int stm32_pctl_probe(struct platform_device *pdev)
..	..	@@ -1151,7 +1460,7 @@
1151	1460	struct device *dev = &pdev->dev;
1152	1461	struct stm32_pinctrl *pctl;
1153	1462	struct pinctrl_pin_desc *pins;
1154		- int i, ret, banks = 0;
	1463	+ int i, ret, hwlock_id, banks = 0;
1155	1464
1156	1465	if (!np)
1157	1466	return -EINVAL;
..	..	@@ -1171,32 +1480,64 @@
1171	1480
1172	1481	platform_set_drvdata(pdev, pctl);
1173	1482
	1483	+ /* check for IRQ controller (may require deferred probe) */
	1484	+ pctl->domain = stm32_pctrl_get_irq_domain(np);
	1485	+ if (IS_ERR(pctl->domain))
	1486	+ return PTR_ERR(pctl->domain);
	1487	+ if (!pctl->domain)
	1488	+ dev_warn(dev, "pinctrl without interrupt support\n");
	1489	+
	1490	+ /* hwspinlock is optional */
	1491	+ hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
	1492	+ if (hwlock_id < 0) {
	1493	+ if (hwlock_id == -EPROBE_DEFER)
	1494	+ return hwlock_id;
	1495	+ } else {
	1496	+ pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
	1497	+ }
	1498	+
	1499	+ spin_lock_init(&pctl->irqmux_lock);
	1500	+
1174	1501	pctl->dev = dev;
1175	1502	pctl->match_data = match->data;
	1503	+
	1504	+ /* get package information */
	1505	+ stm32_pctl_get_package(np, pctl);
	1506	+
	1507	+ pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
	1508	+ sizeof(*pctl->pins), GFP_KERNEL);
	1509	+ if (!pctl->pins)
	1510	+ return -ENOMEM;
	1511	+
	1512	+ ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
	1513	+ if (ret)
	1514	+ return ret;
	1515	+
1176	1516	ret = stm32_pctrl_build_state(pdev);
1177	1517	if (ret) {
1178	1518	dev_err(dev, "build state failed: %d\n", ret);
1179	1519	return -EINVAL;
1180	1520	}
1181	1521
1182		- if (of_find_property(np, "interrupt-parent", NULL)) {
	1522	+ if (pctl->domain) {
1183	1523	ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1184	1524	if (ret)
1185	1525	return ret;
1186	1526	}
1187	1527
1188		- pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
	1528	+ pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1189	1529	GFP_KERNEL);
1190	1530	if (!pins)
1191	1531	return -ENOMEM;
1192	1532
1193		- for (i = 0; i < pctl->match_data->npins; i++)
1194		- pins[i] = pctl->match_data->pins[i].pin;
	1533	+ for (i = 0; i < pctl->npins; i++)
	1534	+ pins[i] = pctl->pins[i].pin;
1195	1535
1196	1536	pctl->pctl_desc.name = dev_name(&pdev->dev);
1197	1537	pctl->pctl_desc.owner = THIS_MODULE;
1198	1538	pctl->pctl_desc.pins = pins;
1199		- pctl->pctl_desc.npins = pctl->match_data->npins;
	1539	+ pctl->pctl_desc.npins = pctl->npins;
	1540	+ pctl->pctl_desc.link_consumers = true;
1200	1541	pctl->pctl_desc.confops = &stm32_pconf_ops;
1201	1542	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1202	1543	pctl->pctl_desc.pmxops = &stm32_pmx_ops;
..	..	@@ -1223,11 +1564,35 @@
1223	1564	if (!pctl->banks)
1224	1565	return -ENOMEM;
1225	1566
	1567	+ i = 0;
	1568	+ for_each_available_child_of_node(np, child) {
	1569	+ struct stm32_gpio_bank *bank = &pctl->banks[i];
	1570	+
	1571	+ if (of_property_read_bool(child, "gpio-controller")) {
	1572	+ bank->rstc = of_reset_control_get_exclusive(child,
	1573	+ NULL);
	1574	+ if (PTR_ERR(bank->rstc) == -EPROBE_DEFER)
	1575	+ return -EPROBE_DEFER;
	1576	+
	1577	+ bank->clk = of_clk_get_by_name(child, NULL);
	1578	+ if (IS_ERR(bank->clk)) {
	1579	+ if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
	1580	+ dev_err(dev,
	1581	+ "failed to get clk (%ld)\n",
	1582	+ PTR_ERR(bank->clk));
	1583	+ return PTR_ERR(bank->clk);
	1584	+ }
	1585	+ i++;
	1586	+ }
	1587	+ }
	1588	+
1226	1589	for_each_available_child_of_node(np, child) {
1227	1590	if (of_property_read_bool(child, "gpio-controller")) {
1228	1591	ret = stm32_gpiolib_register_bank(pctl, child);
1229		- if (ret)
	1592	+ if (ret) {
	1593	+ of_node_put(child);
1230	1594	return ret;
	1595	+ }
1231	1596
1232	1597	pctl->nbanks++;
1233	1598	}
..	..	@@ -1238,3 +1603,74 @@
1238	1603	return 0;
1239	1604	}
1240	1605
	1606	+static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
	1607	+ struct stm32_pinctrl *pctl, u32 pin)
	1608	+{
	1609	+ const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
	1610	+ u32 val, alt, mode, offset = stm32_gpio_pin(pin);
	1611	+ struct pinctrl_gpio_range *range;
	1612	+ struct stm32_gpio_bank *bank;
	1613	+ bool pin_is_irq;
	1614	+ int ret;
	1615	+
	1616	+ range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
	1617	+ if (!range)
	1618	+ return 0;
	1619	+
	1620	+ pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
	1621	+
	1622	+ if (!desc \|\| (!pin_is_irq && !desc->gpio_owner))
	1623	+ return 0;
	1624	+
	1625	+ bank = gpiochip_get_data(range->gc);
	1626	+
	1627	+ alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
	1628	+ alt >>= STM32_GPIO_BKP_ALT_SHIFT;
	1629	+ mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
	1630	+ mode >>= STM32_GPIO_BKP_MODE_SHIFT;
	1631	+
	1632	+ ret = stm32_pmx_set_mode(bank, offset, mode, alt);
	1633	+ if (ret)
	1634	+ return ret;
	1635	+
	1636	+ if (mode == 1) {
	1637	+ val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
	1638	+ val = val >> STM32_GPIO_BKP_VAL;
	1639	+ __stm32_gpio_set(bank, offset, val);
	1640	+ }
	1641	+
	1642	+ val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
	1643	+ val >>= STM32_GPIO_BKP_TYPE;
	1644	+ ret = stm32_pconf_set_driving(bank, offset, val);
	1645	+ if (ret)
	1646	+ return ret;
	1647	+
	1648	+ val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
	1649	+ val >>= STM32_GPIO_BKP_SPEED_SHIFT;
	1650	+ ret = stm32_pconf_set_speed(bank, offset, val);
	1651	+ if (ret)
	1652	+ return ret;
	1653	+
	1654	+ val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
	1655	+ val >>= STM32_GPIO_BKP_PUPD_SHIFT;
	1656	+ ret = stm32_pconf_set_bias(bank, offset, val);
	1657	+ if (ret)
	1658	+ return ret;
	1659	+
	1660	+ if (pin_is_irq)
	1661	+ regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
	1662	+
	1663	+ return 0;
	1664	+}
	1665	+
	1666	+int __maybe_unused stm32_pinctrl_resume(struct device *dev)
	1667	+{
	1668	+ struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
	1669	+ struct stm32_pinctrl_group *g = pctl->groups;
	1670	+ int i;
	1671	+
	1672	+ for (i = 0; i < pctl->ngroups; i++, g++)
	1673	+ stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
	1674	+
	1675	+ return 0;
	1676	+}