add new system file

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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/pinctrl/pinctrl-amd.c
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@@ -126,6 +126,14 @@
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 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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+
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+	/* Use special handling for Pin0 debounce */
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+	if (offset == 0) {
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+		pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
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+		if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
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+			debounce = 0;
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+	}
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+
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 	pin_reg = readl(gpio_dev->base + offset * 4);
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 	if (debounce) {
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@@ -181,18 +189,6 @@
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 	return ret;
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 }
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-static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
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-			       unsigned long config)
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-{
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-	u32 debounce;
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-
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-	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
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-		return -ENOTSUPP;
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-
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-	debounce = pinconf_to_config_argument(config);
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-	return amd_gpio_set_debounce(gc, offset, debounce);
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-}
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-
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 #ifdef CONFIG_DEBUG_FS
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 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
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 {
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@@ -215,6 +211,7 @@
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 	char *output_value;
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 	char *output_enable;
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+	seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
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 	for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
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 		seq_printf(s, "GPIO bank%d\t", bank);
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@@ -656,7 +653,7 @@
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 		break;
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 	default:
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-		dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
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+		dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
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 			param);
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 		return -ENOTSUPP;
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 	}
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@@ -667,7 +664,7 @@
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 }
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 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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-				unsigned long *configs, unsigned num_configs)
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+			   unsigned long *configs, unsigned int num_configs)
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 {
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 	int i;
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 	u32 arg;
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@@ -709,7 +706,7 @@
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 			break;
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 		default:
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-			dev_err(&gpio_dev->pdev->dev,
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+			dev_dbg(&gpio_dev->pdev->dev,
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 				"Invalid config param %04x\n", param);
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 			ret = -ENOTSUPP;
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 		}
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@@ -757,6 +754,20 @@
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 	return 0;
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 }
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+static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
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+			       unsigned long config)
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+{
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+	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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+
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+	if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
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+		u32 debounce = pinconf_to_config_argument(config);
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+
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+		return amd_gpio_set_debounce(gc, pin, debounce);
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+	}
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+
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+	return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
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+}
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+
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 static const struct pinconf_ops amd_pinconf_ops = {
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 	.pin_config_get		= amd_pinconf_get,
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 	.pin_config_set		= amd_pinconf_set,
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@@ -784,9 +795,9 @@
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 		raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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-		pin_reg = readl(gpio_dev->base + i * 4);
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+		pin_reg = readl(gpio_dev->base + pin * 4);
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 		pin_reg &= ~mask;
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-		writel(pin_reg, gpio_dev->base + i * 4);
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+		writel(pin_reg, gpio_dev->base + pin * 4);
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 		raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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 	}