forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/phy/qualcomm/phy-qcom-qmp.c
....@@ -35,7 +35,7 @@
3535 #define PLL_READY_GATE_EN			BIT(3)
3636 /* QPHY_PCS_STATUS bit */
3737 #define PHYSTATUS				BIT(6)
38
-/* QPHY_COM_PCS_READY_STATUS bit */
38
+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
3939 #define PCS_READY				BIT(0)
4040 
4141 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
....@@ -72,6 +72,9 @@
7272 
7373 #define MAX_PROP_NAME				32
7474 
75
+/* Define the assumed distance between lanes for underspecified device trees. */
76
+#define QMP_PHY_LEGACY_LANE_STRIDE		0x400
77
+
7578 struct qmp_phy_init_tbl {
7679 	unsigned int offset;
7780 	unsigned int val;
....@@ -79,20 +82,34 @@
7982 	 * register part of layout ?
8083 	 * if yes, then offset gives index in the reg-layout
8184 	 */
82
-	int in_layout;
85
+	bool in_layout;
86
+	/*
87
+	 * mask of lanes for which this register is written
88
+	 * for cases when second lane needs different values
89
+	 */
90
+	u8 lane_mask;
8391 };
8492 
8593 #define QMP_PHY_INIT_CFG(o, v)		\
8694 	{				\
8795 		.offset = o,		\
8896 		.val = v,		\
97
+		.lane_mask = 0xff,	\
8998 	}
9099 
91100 #define QMP_PHY_INIT_CFG_L(o, v)	\
92101 	{				\
93102 		.offset = o,		\
94103 		.val = v,		\
95
-		.in_layout = 1,		\
104
+		.in_layout = true,	\
105
+		.lane_mask = 0xff,	\
106
+	}
107
+
108
+#define QMP_PHY_INIT_CFG_LANE(o, v, l)	\
109
+	{				\
110
+		.offset = o,		\
111
+		.val = v,		\
112
+		.lane_mask = l,		\
96113 	}
97114 
98115 /* set of registers with offsets different per-PHY */
....@@ -112,12 +129,21 @@
112129 	QPHY_SW_RESET,
113130 	QPHY_START_CTRL,
114131 	QPHY_PCS_READY_STATUS,
132
+	QPHY_PCS_STATUS,
115133 	QPHY_PCS_AUTONOMOUS_MODE_CTRL,
116134 	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
117135 	QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
136
+	QPHY_PCS_POWER_DOWN_CONTROL,
137
+	/* Keep last to ensure regs_layout arrays are properly initialized */
138
+	QPHY_LAYOUT_SIZE
118139 };
119140 
120
-static const unsigned int pciephy_regs_layout[] = {
141
+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
142
+	[QPHY_START_CTRL]		= 0x00,
143
+	[QPHY_PCS_READY_STATUS]		= 0x168,
144
+};
145
+
146
+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
121147 	[QPHY_COM_SW_RESET]		= 0x400,
122148 	[QPHY_COM_POWER_DOWN_CONTROL]	= 0x404,
123149 	[QPHY_COM_START_CONTROL]	= 0x408,
....@@ -130,10 +156,10 @@
130156 	[QPHY_FLL_MAN_CODE]		= 0xd4,
131157 	[QPHY_SW_RESET]			= 0x00,
132158 	[QPHY_START_CTRL]		= 0x08,
133
-	[QPHY_PCS_READY_STATUS]		= 0x174,
159
+	[QPHY_PCS_STATUS]		= 0x174,
134160 };
135161 
136
-static const unsigned int usb3phy_regs_layout[] = {
162
+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
137163 	[QPHY_FLL_CNTRL1]		= 0xc0,
138164 	[QPHY_FLL_CNTRL2]		= 0xc4,
139165 	[QPHY_FLL_CNT_VAL_L]		= 0xc8,
....@@ -141,19 +167,135 @@
141167 	[QPHY_FLL_MAN_CODE]		= 0xd0,
142168 	[QPHY_SW_RESET]			= 0x00,
143169 	[QPHY_START_CTRL]		= 0x08,
144
-	[QPHY_PCS_READY_STATUS]		= 0x17c,
170
+	[QPHY_PCS_STATUS]		= 0x17c,
145171 	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= 0x0d4,
146172 	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
147173 	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
148174 };
149175 
150
-static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
176
+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
151177 	[QPHY_SW_RESET]			= 0x00,
152178 	[QPHY_START_CTRL]		= 0x08,
153
-	[QPHY_PCS_READY_STATUS]		= 0x174,
179
+	[QPHY_PCS_STATUS]		= 0x174,
154180 	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= 0x0d8,
155181 	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
156182 	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
183
+};
184
+
185
+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
186
+	[QPHY_SW_RESET]			= 0x00,
187
+	[QPHY_START_CTRL]		= 0x08,
188
+	[QPHY_PCS_STATUS]		= 0x174,
189
+};
190
+
191
+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
192
+	[QPHY_SW_RESET]			= 0x00,
193
+	[QPHY_START_CTRL]		= 0x08,
194
+	[QPHY_PCS_STATUS]		= 0x2ac,
195
+};
196
+
197
+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
198
+	[QPHY_SW_RESET]			= 0x00,
199
+	[QPHY_START_CTRL]		= 0x44,
200
+	[QPHY_PCS_STATUS]		= 0x14,
201
+	[QPHY_PCS_POWER_DOWN_CONTROL]	= 0x40,
202
+	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= 0x308,
203
+	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
204
+};
205
+
206
+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
207
+	[QPHY_SW_RESET]			= 0x00,
208
+	[QPHY_START_CTRL]		= 0x44,
209
+	[QPHY_PCS_STATUS]		= 0x14,
210
+	[QPHY_PCS_POWER_DOWN_CONTROL]	= 0x40,
211
+	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= 0x608,
212
+	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
213
+};
214
+
215
+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
216
+	[QPHY_START_CTRL]		= 0x00,
217
+	[QPHY_PCS_READY_STATUS]		= 0x160,
218
+};
219
+
220
+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
221
+	[QPHY_START_CTRL]		= QPHY_V4_PCS_UFS_PHY_START,
222
+	[QPHY_PCS_READY_STATUS]		= QPHY_V4_PCS_UFS_READY_STATUS,
223
+	[QPHY_SW_RESET]			= QPHY_V4_PCS_UFS_SW_RESET,
224
+};
225
+
226
+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
227
+	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
228
+	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
229
+	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
230
+	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
231
+	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
232
+	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
233
+	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
234
+	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
235
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
236
+	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
237
+	/* PLL and Loop filter settings */
238
+	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
239
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
240
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
241
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
242
+	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
243
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
244
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
245
+	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
246
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
247
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
248
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
249
+	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
250
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
251
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
252
+	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
253
+	/* SSC settings */
254
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
255
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
256
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
257
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
258
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
259
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
260
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
261
+};
262
+
263
+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
264
+	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
265
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
266
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
267
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
268
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
269
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
270
+	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
271
+	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
272
+	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
273
+};
274
+
275
+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
276
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
277
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
278
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
279
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
280
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
281
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
282
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
283
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
284
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
285
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
286
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
287
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
288
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
289
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
290
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
291
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
292
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
293
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
294
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
295
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
296
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
297
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
298
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
157299 };
158300 
159301 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
....@@ -232,6 +374,157 @@
232374 	QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
233375 	QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
234376 	QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
377
+};
378
+
379
+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
380
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
381
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
382
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
383
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
384
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
385
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
386
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
387
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
388
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
389
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
390
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
391
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
392
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
393
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
394
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
395
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
396
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
397
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
398
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
399
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
400
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
401
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
402
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
403
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
404
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
405
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
406
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
407
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
408
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
409
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
410
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
411
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
412
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
413
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
414
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
415
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
416
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
417
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
418
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
419
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
420
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
421
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
422
+};
423
+
424
+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
425
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
426
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
427
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
428
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
429
+};
430
+
431
+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
432
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
433
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
434
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
435
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
436
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
437
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
438
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
439
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
440
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
441
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
442
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
443
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
444
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
445
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
446
+};
447
+
448
+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
449
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
450
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
451
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
452
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
453
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
454
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
455
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
456
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
457
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
458
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
459
+};
460
+
461
+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
462
+	QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
463
+	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
464
+	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
465
+	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
466
+	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
467
+	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
468
+	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
469
+	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
470
+	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
471
+	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
472
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
473
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
474
+	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
475
+	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
476
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
477
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
478
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
479
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
480
+	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
481
+	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
482
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
483
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
484
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
485
+	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
486
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
487
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
488
+	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
489
+	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
490
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
491
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
492
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
493
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
494
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
495
+	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
496
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
497
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
498
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
499
+	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
500
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
501
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
502
+	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
503
+	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
504
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
505
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
506
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
507
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
508
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
509
+};
510
+
511
+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
512
+	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
513
+	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
514
+};
515
+
516
+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
517
+	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
518
+	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
519
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
520
+	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
521
+	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
522
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
523
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
524
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
525
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
526
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
527
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
235528 };
236529 
237530 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
....@@ -383,6 +676,229 @@
383676 	QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
384677 };
385678 
679
+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
680
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
681
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
682
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
683
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
684
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
685
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
686
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
687
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
688
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
689
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
690
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
691
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
692
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
693
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
694
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
695
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
696
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
697
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
698
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
699
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
700
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
701
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
702
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
703
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
704
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
705
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
706
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
707
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
708
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
709
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
710
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
711
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
712
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
713
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
714
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
715
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
716
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
717
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
718
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
719
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
720
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
721
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
722
+};
723
+
724
+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
725
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
726
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
727
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
728
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
729
+};
730
+
731
+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
732
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
733
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
734
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
735
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
736
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
737
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
738
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
739
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
740
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
741
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
742
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
743
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
744
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
745
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
746
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
747
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
748
+};
749
+
750
+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
751
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
752
+
753
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
754
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
755
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
756
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
757
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
758
+
759
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
760
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
761
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
762
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
763
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
764
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
765
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
766
+
767
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
768
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
769
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
770
+
771
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
772
+};
773
+
774
+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
775
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
776
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
777
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
778
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
779
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
780
+};
781
+
782
+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
783
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
784
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
785
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
786
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
787
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
788
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
789
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
790
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
791
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
792
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
793
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
794
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
795
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
796
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
797
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
798
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
799
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
800
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
801
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
802
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
803
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
804
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
805
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
806
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
807
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
808
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
809
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
810
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
811
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
812
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
813
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
814
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
815
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
816
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
817
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
818
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
819
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
820
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
821
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
822
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
823
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
824
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
825
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
826
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
827
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
828
+};
829
+
830
+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
831
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
832
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
833
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
834
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
835
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
836
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
837
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
838
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
839
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
840
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
841
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
842
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
843
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
844
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
845
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
846
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
847
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
848
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
849
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
850
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
851
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
852
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
853
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
854
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
855
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
856
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
857
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
858
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
859
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
860
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
861
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
862
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
863
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
864
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
865
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
866
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
867
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
868
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
869
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
870
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
871
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
872
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
873
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
874
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
875
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
876
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
877
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
878
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
879
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
880
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
881
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
882
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
883
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
884
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
885
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
886
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
887
+};
888
+
889
+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
890
+};
891
+
892
+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
893
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
894
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
895
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
896
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
897
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
898
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
899
+	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
900
+};
901
+
386902 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
387903 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
388904 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
....@@ -428,6 +944,88 @@
428944 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
429945 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
430946 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
947
+};
948
+
949
+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
950
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
951
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
952
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
953
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
954
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
955
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
956
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
957
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
958
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
959
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
960
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
961
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
962
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
963
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
964
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
965
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
966
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
967
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
968
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
969
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
970
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
971
+};
972
+
973
+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
974
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
975
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
976
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
977
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
978
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
979
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
980
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
981
+};
982
+
983
+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
984
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
985
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
986
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
987
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
988
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
989
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
990
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
991
+};
992
+
993
+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
994
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
995
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
996
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
997
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
998
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
999
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
1000
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1001
+};
1002
+
1003
+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
1004
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
1005
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1006
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1007
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1008
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
1009
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
1010
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
1011
+};
1012
+
1013
+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
1014
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1015
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
1016
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1017
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
1018
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
1019
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
1020
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
1021
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1022
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
1023
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
1024
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
1025
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
1026
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
1027
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1028
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
4311029 };
4321030 
4331031 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
....@@ -600,6 +1198,631 @@
6001198 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
6011199 };
6021200 
1201
+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1202
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1203
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1204
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1205
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1206
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1207
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1208
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1209
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1210
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1211
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1212
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1213
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1214
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1215
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1216
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1217
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1218
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1219
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1220
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1221
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1222
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1223
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1224
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1225
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1226
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1227
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1228
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1229
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1230
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1231
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1232
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1233
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1234
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1235
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1236
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1237
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1238
+
1239
+	/* Rate B */
1240
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1241
+};
1242
+
1243
+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1244
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1245
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1246
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1247
+};
1248
+
1249
+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1250
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1251
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1252
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1253
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1254
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1255
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1256
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1257
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1258
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1259
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1260
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1261
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1262
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1263
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1264
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1265
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1266
+};
1267
+
1268
+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1269
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1270
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1271
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1272
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1273
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1274
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1275
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1276
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1277
+};
1278
+
1279
+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1280
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1281
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1282
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1283
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1284
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1285
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1286
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1287
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1288
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1289
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1290
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1291
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1292
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1293
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1294
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1295
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1296
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1297
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1298
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1299
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1300
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1301
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1302
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1303
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1304
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1305
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1306
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1307
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1308
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1309
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1310
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1311
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1312
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1313
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1314
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1315
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1316
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1317
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1318
+};
1319
+
1320
+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1321
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1322
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1323
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1324
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1325
+};
1326
+
1327
+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1328
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1329
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1330
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1331
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1332
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1333
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1334
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1335
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1336
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1337
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1338
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1339
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1340
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1341
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1342
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1343
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1344
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1345
+};
1346
+
1347
+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1348
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1349
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1350
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1351
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1352
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1353
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1354
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1355
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1356
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1357
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1358
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1359
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1360
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1361
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1362
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1363
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1364
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1365
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1366
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1367
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1368
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1369
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1370
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1371
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1372
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1373
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1374
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1375
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1376
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1377
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1378
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1379
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1380
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1381
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1382
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1383
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1384
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1385
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1386
+};
1387
+
1388
+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1389
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1390
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1391
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1392
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1393
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1394
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1395
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1396
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1397
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1398
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1399
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1400
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1401
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1402
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1403
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1404
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1405
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1406
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1407
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1408
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1409
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1410
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1411
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1412
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1413
+
1414
+	/* Rate B */
1415
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1416
+};
1417
+
1418
+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1419
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1420
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1421
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1422
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1423
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1424
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1425
+};
1426
+
1427
+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1428
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1429
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1430
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1431
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1432
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1433
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1434
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1435
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1436
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1437
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1438
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1439
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1440
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1441
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1442
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1443
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1444
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1445
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1446
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1447
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1448
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1449
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1450
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1451
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1452
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1453
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1454
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1455
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1456
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1457
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1458
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1459
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1460
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1461
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1462
+
1463
+};
1464
+
1465
+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1466
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1467
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1468
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1469
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1470
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1471
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1472
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1473
+};
1474
+
1475
+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1476
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1477
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1478
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1479
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1480
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1481
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1482
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1483
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1484
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1485
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1486
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1487
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1488
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1489
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1490
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1491
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1492
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1493
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1494
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1495
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1496
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1497
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1498
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1499
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1500
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1501
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1502
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1503
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1504
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1505
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1506
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1507
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1508
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1509
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1510
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1511
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1512
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1513
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1514
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1515
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1516
+};
1517
+
1518
+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1519
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1520
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1521
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1522
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1523
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1524
+};
1525
+
1526
+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1527
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1528
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1529
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1530
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1531
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1532
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1533
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1534
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1535
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1536
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1537
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1538
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1539
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1540
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1541
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1542
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1543
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1544
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1545
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1546
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1547
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1548
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1549
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1550
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1551
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1552
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1553
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1554
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1555
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1556
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1557
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1558
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1559
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1560
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1561
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1562
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1563
+};
1564
+
1565
+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1566
+	/* Lock Det settings */
1567
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1568
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1569
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1570
+
1571
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1572
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1573
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1574
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1575
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1576
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1577
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1578
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1579
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1580
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1581
+};
1582
+
1583
+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1584
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1585
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1586
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1587
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1588
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1589
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1590
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1591
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1592
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1593
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1594
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1595
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1596
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1597
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1598
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1599
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1600
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1601
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1602
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1603
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1604
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1605
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1606
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1607
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1608
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1609
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1610
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1611
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1612
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1613
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1614
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1615
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1616
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1617
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1618
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1619
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1620
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1621
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1622
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1623
+	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1624
+};
1625
+
1626
+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1627
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1628
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1629
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1630
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1631
+};
1632
+
1633
+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1634
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1635
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1636
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1637
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1638
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1639
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1640
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1641
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1642
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1643
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1644
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1645
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1646
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1647
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1648
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1649
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1650
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1651
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1652
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1653
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1654
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1655
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1656
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1657
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1658
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1659
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1660
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1661
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1662
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1663
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1664
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1665
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1666
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1667
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1668
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1669
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1670
+};
1671
+
1672
+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1673
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1674
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1675
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1676
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1677
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1678
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1679
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1680
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1681
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1682
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1683
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1684
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1685
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1686
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1687
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1688
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1689
+};
1690
+
1691
+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1692
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1693
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1694
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1695
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1696
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1697
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1698
+	QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1699
+	QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1700
+};
1701
+
1702
+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1703
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1704
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1705
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1706
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1707
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1708
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1709
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1710
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1711
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1712
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1713
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1714
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1715
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1716
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1717
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1718
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1719
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1720
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1721
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1722
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1723
+	QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1724
+	QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1725
+	QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1726
+	QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1727
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1728
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1729
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1730
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1731
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1732
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1733
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1734
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1735
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1736
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1737
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1738
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1739
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1740
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1741
+};
1742
+
1743
+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1744
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1745
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1746
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1747
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1748
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1749
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1750
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1751
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1752
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1753
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1754
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1755
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1756
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1757
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1758
+};
1759
+
1760
+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
1761
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1762
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1763
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
1764
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1765
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1766
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1767
+};
1768
+
1769
+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
1770
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1771
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
1772
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
1773
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
1774
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1775
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1776
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1777
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1778
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1779
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1780
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1781
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1782
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1783
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1784
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1785
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1786
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1787
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1788
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1789
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
1790
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1791
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1792
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1793
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1794
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1795
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1796
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1797
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1798
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1799
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1800
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1801
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1802
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1803
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1804
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1805
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1806
+};
1807
+
1808
+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
1809
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1810
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1811
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1812
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1813
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1814
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1815
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1816
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1817
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1818
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1819
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1820
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1821
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1822
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1823
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1824
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1825
+};
6031826 
6041827 /* struct qmp_phy_cfg - per-PHY initialization config */
6051828 struct qmp_phy_cfg {
....@@ -617,6 +1840,18 @@
6171840 	int rx_tbl_num;
6181841 	const struct qmp_phy_init_tbl *pcs_tbl;
6191842 	int pcs_tbl_num;
1843
+	const struct qmp_phy_init_tbl *pcs_misc_tbl;
1844
+	int pcs_misc_tbl_num;
1845
+
1846
+	/* Init sequence for DP PHY block link rates */
1847
+	const struct qmp_phy_init_tbl *serdes_tbl_rbr;
1848
+	int serdes_tbl_rbr_num;
1849
+	const struct qmp_phy_init_tbl *serdes_tbl_hbr;
1850
+	int serdes_tbl_hbr_num;
1851
+	const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
1852
+	int serdes_tbl_hbr2_num;
1853
+	const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
1854
+	int serdes_tbl_hbr3_num;
6201855 
6211856 	/* clock ids to be requested */
6221857 	const char * const *clk_list;
....@@ -633,7 +1868,6 @@
6331868 
6341869 	unsigned int start_ctrl;
6351870 	unsigned int pwrdn_ctrl;
636
-	unsigned int mask_pcs_ready;
6371871 	unsigned int mask_com_pcs_ready;
6381872 
6391873 	/* true, if PHY has a separate PHY_COM control block */
....@@ -648,70 +1882,91 @@
6481882 
6491883 	/* true, if PHY has a separate DP_COM control block */
6501884 	bool has_phy_dp_com_ctrl;
651
-	/* Register offset of secondary tx/rx lanes for USB DP combo PHY */
652
-	unsigned int tx_b_lane_offset;
653
-	unsigned int rx_b_lane_offset;
1885
+	/* true, if PHY has secondary tx/rx lanes to be configured */
1886
+	bool is_dual_lane_phy;
1887
+
1888
+	/* true, if PCS block has no separate SW_RESET register */
1889
+	bool no_pcs_sw_reset;
1890
+};
1891
+
1892
+struct qmp_phy_combo_cfg {
1893
+	const struct qmp_phy_cfg *usb_cfg;
1894
+	const struct qmp_phy_cfg *dp_cfg;
6541895 };
6551896 
6561897 /**
6571898  * struct qmp_phy - per-lane phy descriptor
6581899  *
6591900  * @phy: generic phy
1901
+ * @cfg: phy specific configuration
1902
+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
6601903  * @tx: iomapped memory space for lane's tx
6611904  * @rx: iomapped memory space for lane's rx
6621905  * @pcs: iomapped memory space for lane's pcs
1906
+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
1907
+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
6631908  * @pcs_misc: iomapped memory space for lane's pcs_misc
6641909  * @pipe_clk: pipe lock
6651910  * @index: lane index
6661911  * @qmp: QMP phy to which this lane belongs
6671912  * @lane_rst: lane's reset controller
1913
+ * @mode: current PHY mode
6681914  */
6691915 struct qmp_phy {
6701916 	struct phy *phy;
1917
+	const struct qmp_phy_cfg *cfg;
1918
+	void __iomem *serdes;
6711919 	void __iomem *tx;
6721920 	void __iomem *rx;
6731921 	void __iomem *pcs;
1922
+	void __iomem *tx2;
1923
+	void __iomem *rx2;
6741924 	void __iomem *pcs_misc;
6751925 	struct clk *pipe_clk;
6761926 	unsigned int index;
6771927 	struct qcom_qmp *qmp;
6781928 	struct reset_control *lane_rst;
1929
+	enum phy_mode mode;
1930
+	unsigned int dp_aux_cfg;
1931
+	struct phy_configure_opts_dp dp_opts;
1932
+	struct qmp_phy_dp_clks *dp_clks;
1933
+};
1934
+
1935
+struct qmp_phy_dp_clks {
1936
+	struct qmp_phy *qphy;
1937
+	struct clk_hw dp_link_hw;
1938
+	struct clk_hw dp_pixel_hw;
6791939 };
6801940 
6811941 /**
6821942  * struct qcom_qmp - structure holding QMP phy block attributes
6831943  *
6841944  * @dev: device
685
- * @serdes: iomapped memory space for phy's serdes
6861945  * @dp_com: iomapped memory space for phy's dp_com control block
6871946  *
6881947  * @clks: array of clocks required by phy
6891948  * @resets: array of resets required by phy
6901949  * @vregs: regulator supplies bulk data
6911950  *
692
- * @cfg: phy specific configuration
6931951  * @phys: array of per-lane phy descriptors
6941952  * @phy_mutex: mutex lock for PHY common block initialization
6951953  * @init_count: phy common block initialization count
696
- * @phy_initialized: indicate if PHY has been initialized
697
- * @mode: current PHY mode
1954
+ * @ufs_reset: optional UFS PHY reset handle
6981955  */
6991956 struct qcom_qmp {
7001957 	struct device *dev;
701
-	void __iomem *serdes;
7021958 	void __iomem *dp_com;
7031959 
7041960 	struct clk_bulk_data *clks;
7051961 	struct reset_control **resets;
7061962 	struct regulator_bulk_data *vregs;
7071963 
708
-	const struct qmp_phy_cfg *cfg;
7091964 	struct qmp_phy **phys;
7101965 
7111966 	struct mutex phy_mutex;
7121967 	int init_count;
713
-	bool phy_initialized;
714
-	enum phy_mode mode;
1968
+
1969
+	struct reset_control *ufs_reset;
7151970 };
7161971 
7171972 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
....@@ -743,8 +1998,29 @@
7431998 	"aux", "cfg_ahb", "ref",
7441999 };
7452000 
2001
+static const char * const msm8996_ufs_phy_clk_l[] = {
2002
+	"ref",
2003
+};
2004
+
7462005 static const char * const qmp_v3_phy_clk_l[] = {
7472006 	"aux", "cfg_ahb", "ref", "com_aux",
2007
+};
2008
+
2009
+static const char * const sdm845_pciephy_clk_l[] = {
2010
+	"aux", "cfg_ahb", "ref", "refgen",
2011
+};
2012
+
2013
+static const char * const qmp_v4_phy_clk_l[] = {
2014
+	"aux", "ref_clk_src", "ref", "com_aux",
2015
+};
2016
+
2017
+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
2018
+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
2019
+	"aux", "ref_clk_src", "com_aux"
2020
+};
2021
+
2022
+static const char * const sdm845_ufs_phy_clk_l[] = {
2023
+	"ref", "ref_aux",
7482024 };
7492025 
7502026 /* list of resets */
....@@ -756,9 +2032,41 @@
7562032 	"phy", "common",
7572033 };
7582034 
2035
+static const char * const sc7180_usb3phy_reset_l[] = {
2036
+	"phy",
2037
+};
2038
+
2039
+static const char * const sdm845_pciephy_reset_l[] = {
2040
+	"phy",
2041
+};
2042
+
7592043 /* list of regulators */
760
-static const char * const msm8996_phy_vreg_l[] = {
2044
+static const char * const qmp_phy_vreg_l[] = {
7612045 	"vdda-phy", "vdda-pll",
2046
+};
2047
+
2048
+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
2049
+	.type			= PHY_TYPE_USB3,
2050
+	.nlanes			= 1,
2051
+
2052
+	.serdes_tbl		= ipq8074_usb3_serdes_tbl,
2053
+	.serdes_tbl_num		= ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
2054
+	.tx_tbl			= msm8996_usb3_tx_tbl,
2055
+	.tx_tbl_num		= ARRAY_SIZE(msm8996_usb3_tx_tbl),
2056
+	.rx_tbl			= ipq8074_usb3_rx_tbl,
2057
+	.rx_tbl_num		= ARRAY_SIZE(ipq8074_usb3_rx_tbl),
2058
+	.pcs_tbl		= ipq8074_usb3_pcs_tbl,
2059
+	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
2060
+	.clk_list		= msm8996_phy_clk_l,
2061
+	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
2062
+	.reset_list		= msm8996_usb3phy_reset_l,
2063
+	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
2064
+	.vreg_list		= qmp_phy_vreg_l,
2065
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2066
+	.regs			= usb3phy_regs_layout,
2067
+
2068
+	.start_ctrl		= SERDES_START | PCS_START,
2069
+	.pwrdn_ctrl		= SW_PWRDN,
7622070 };
7632071 
7642072 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
....@@ -777,8 +2085,8 @@
7772085 	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
7782086 	.reset_list		= msm8996_pciephy_reset_l,
7792087 	.num_resets		= ARRAY_SIZE(msm8996_pciephy_reset_l),
780
-	.vreg_list		= msm8996_phy_vreg_l,
781
-	.num_vregs		= ARRAY_SIZE(msm8996_phy_vreg_l),
2088
+	.vreg_list		= qmp_phy_vreg_l,
2089
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
7822090 	.regs			= pciephy_regs_layout,
7832091 
7842092 	.start_ctrl		= PCS_START | PLL_READY_GATE_EN,
....@@ -790,6 +2098,31 @@
7902098 	.has_pwrdn_delay	= true,
7912099 	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
7922100 	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
2101
+};
2102
+
2103
+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
2104
+	.type			= PHY_TYPE_UFS,
2105
+	.nlanes			= 1,
2106
+
2107
+	.serdes_tbl		= msm8996_ufs_serdes_tbl,
2108
+	.serdes_tbl_num		= ARRAY_SIZE(msm8996_ufs_serdes_tbl),
2109
+	.tx_tbl			= msm8996_ufs_tx_tbl,
2110
+	.tx_tbl_num		= ARRAY_SIZE(msm8996_ufs_tx_tbl),
2111
+	.rx_tbl			= msm8996_ufs_rx_tbl,
2112
+	.rx_tbl_num		= ARRAY_SIZE(msm8996_ufs_rx_tbl),
2113
+
2114
+	.clk_list		= msm8996_ufs_phy_clk_l,
2115
+	.num_clks		= ARRAY_SIZE(msm8996_ufs_phy_clk_l),
2116
+
2117
+	.vreg_list		= qmp_phy_vreg_l,
2118
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2119
+
2120
+	.regs			= msm8996_ufsphy_regs_layout,
2121
+
2122
+	.start_ctrl		= SERDES_START,
2123
+	.pwrdn_ctrl		= SW_PWRDN,
2124
+
2125
+	.no_pcs_sw_reset	= true,
7932126 };
7942127 
7952128 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
....@@ -808,13 +2141,12 @@
8082141 	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
8092142 	.reset_list		= msm8996_usb3phy_reset_l,
8102143 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
811
-	.vreg_list		= msm8996_phy_vreg_l,
812
-	.num_vregs		= ARRAY_SIZE(msm8996_phy_vreg_l),
2144
+	.vreg_list		= qmp_phy_vreg_l,
2145
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
8132146 	.regs			= usb3phy_regs_layout,
8142147 
8152148 	.start_ctrl		= SERDES_START | PCS_START,
8162149 	.pwrdn_ctrl		= SW_PWRDN,
817
-	.mask_pcs_ready		= PHYSTATUS,
8182150 };
8192151 
8202152 static const char * const ipq8074_pciephy_clk_l[] = {
....@@ -847,10 +2179,67 @@
8472179 
8482180 	.start_ctrl		= SERDES_START | PCS_START,
8492181 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
850
-	.mask_pcs_ready		= PHYSTATUS,
8512182 
8522183 	.has_phy_com_ctrl	= false,
8532184 	.has_lane_rst		= false,
2185
+	.has_pwrdn_delay	= true,
2186
+	.pwrdn_delay_min	= 995,		/* us */
2187
+	.pwrdn_delay_max	= 1005,		/* us */
2188
+};
2189
+
2190
+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
2191
+	.type = PHY_TYPE_PCIE,
2192
+	.nlanes = 1,
2193
+
2194
+	.serdes_tbl		= sdm845_qmp_pcie_serdes_tbl,
2195
+	.serdes_tbl_num		= ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
2196
+	.tx_tbl			= sdm845_qmp_pcie_tx_tbl,
2197
+	.tx_tbl_num		= ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
2198
+	.rx_tbl			= sdm845_qmp_pcie_rx_tbl,
2199
+	.rx_tbl_num		= ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
2200
+	.pcs_tbl		= sdm845_qmp_pcie_pcs_tbl,
2201
+	.pcs_tbl_num		= ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
2202
+	.pcs_misc_tbl		= sdm845_qmp_pcie_pcs_misc_tbl,
2203
+	.pcs_misc_tbl_num	= ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
2204
+	.clk_list		= sdm845_pciephy_clk_l,
2205
+	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),
2206
+	.reset_list		= sdm845_pciephy_reset_l,
2207
+	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
2208
+	.vreg_list		= qmp_phy_vreg_l,
2209
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2210
+	.regs			= sdm845_qmp_pciephy_regs_layout,
2211
+
2212
+	.start_ctrl		= PCS_START | SERDES_START,
2213
+	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
2214
+
2215
+	.has_pwrdn_delay	= true,
2216
+	.pwrdn_delay_min	= 995,		/* us */
2217
+	.pwrdn_delay_max	= 1005,		/* us */
2218
+};
2219
+
2220
+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
2221
+	.type = PHY_TYPE_PCIE,
2222
+	.nlanes = 1,
2223
+
2224
+	.serdes_tbl		= sdm845_qhp_pcie_serdes_tbl,
2225
+	.serdes_tbl_num		= ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
2226
+	.tx_tbl			= sdm845_qhp_pcie_tx_tbl,
2227
+	.tx_tbl_num		= ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
2228
+	.rx_tbl			= sdm845_qhp_pcie_rx_tbl,
2229
+	.rx_tbl_num		= ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
2230
+	.pcs_tbl		= sdm845_qhp_pcie_pcs_tbl,
2231
+	.pcs_tbl_num		= ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
2232
+	.clk_list		= sdm845_pciephy_clk_l,
2233
+	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),
2234
+	.reset_list		= sdm845_pciephy_reset_l,
2235
+	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
2236
+	.vreg_list		= qmp_phy_vreg_l,
2237
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2238
+	.regs			= sdm845_qhp_pciephy_regs_layout,
2239
+
2240
+	.start_ctrl		= PCS_START | SERDES_START,
2241
+	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
2242
+
8542243 	.has_pwrdn_delay	= true,
8552244 	.pwrdn_delay_min	= 995,		/* us */
8562245 	.pwrdn_delay_max	= 1005,		/* us */
....@@ -872,21 +2261,85 @@
8722261 	.num_clks		= ARRAY_SIZE(qmp_v3_phy_clk_l),
8732262 	.reset_list		= msm8996_usb3phy_reset_l,
8742263 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
875
-	.vreg_list		= msm8996_phy_vreg_l,
876
-	.num_vregs		= ARRAY_SIZE(msm8996_phy_vreg_l),
2264
+	.vreg_list		= qmp_phy_vreg_l,
2265
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
8772266 	.regs			= qmp_v3_usb3phy_regs_layout,
8782267 
8792268 	.start_ctrl		= SERDES_START | PCS_START,
8802269 	.pwrdn_ctrl		= SW_PWRDN,
881
-	.mask_pcs_ready		= PHYSTATUS,
8822270 
8832271 	.has_pwrdn_delay	= true,
8842272 	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
8852273 	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
8862274 
8872275 	.has_phy_dp_com_ctrl	= true,
888
-	.tx_b_lane_offset	= 0x400,
889
-	.rx_b_lane_offset	= 0x400,
2276
+	.is_dual_lane_phy	= true,
2277
+};
2278
+
2279
+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
2280
+	.type			= PHY_TYPE_USB3,
2281
+	.nlanes			= 1,
2282
+
2283
+	.serdes_tbl		= qmp_v3_usb3_serdes_tbl,
2284
+	.serdes_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2285
+	.tx_tbl			= qmp_v3_usb3_tx_tbl,
2286
+	.tx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2287
+	.rx_tbl			= qmp_v3_usb3_rx_tbl,
2288
+	.rx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
2289
+	.pcs_tbl		= qmp_v3_usb3_pcs_tbl,
2290
+	.pcs_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
2291
+	.clk_list		= qmp_v3_phy_clk_l,
2292
+	.num_clks		= ARRAY_SIZE(qmp_v3_phy_clk_l),
2293
+	.reset_list		= sc7180_usb3phy_reset_l,
2294
+	.num_resets		= ARRAY_SIZE(sc7180_usb3phy_reset_l),
2295
+	.vreg_list		= qmp_phy_vreg_l,
2296
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2297
+	.regs			= qmp_v3_usb3phy_regs_layout,
2298
+
2299
+	.start_ctrl		= SERDES_START | PCS_START,
2300
+	.pwrdn_ctrl		= SW_PWRDN,
2301
+
2302
+	.has_pwrdn_delay	= true,
2303
+	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
2304
+	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
2305
+
2306
+	.has_phy_dp_com_ctrl	= true,
2307
+	.is_dual_lane_phy	= true,
2308
+};
2309
+
2310
+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
2311
+	.type			= PHY_TYPE_DP,
2312
+	.nlanes			= 1,
2313
+
2314
+	.serdes_tbl		= qmp_v3_dp_serdes_tbl,
2315
+	.serdes_tbl_num		= ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
2316
+	.tx_tbl			= qmp_v3_dp_tx_tbl,
2317
+	.tx_tbl_num		= ARRAY_SIZE(qmp_v3_dp_tx_tbl),
2318
+
2319
+	.serdes_tbl_rbr		= qmp_v3_dp_serdes_tbl_rbr,
2320
+	.serdes_tbl_rbr_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
2321
+	.serdes_tbl_hbr		= qmp_v3_dp_serdes_tbl_hbr,
2322
+	.serdes_tbl_hbr_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
2323
+	.serdes_tbl_hbr2	= qmp_v3_dp_serdes_tbl_hbr2,
2324
+	.serdes_tbl_hbr2_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
2325
+	.serdes_tbl_hbr3	= qmp_v3_dp_serdes_tbl_hbr3,
2326
+	.serdes_tbl_hbr3_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
2327
+
2328
+	.clk_list		= qmp_v3_phy_clk_l,
2329
+	.num_clks		= ARRAY_SIZE(qmp_v3_phy_clk_l),
2330
+	.reset_list		= sc7180_usb3phy_reset_l,
2331
+	.num_resets		= ARRAY_SIZE(sc7180_usb3phy_reset_l),
2332
+	.vreg_list		= qmp_phy_vreg_l,
2333
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2334
+	.regs			= qmp_v3_usb3phy_regs_layout,
2335
+
2336
+	.has_phy_dp_com_ctrl	= true,
2337
+	.is_dual_lane_phy	= true,
2338
+};
2339
+
2340
+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
2341
+	.usb_cfg		= &sc7180_usb3phy_cfg,
2342
+	.dp_cfg			= &sc7180_dpphy_cfg,
8902343 };
8912344 
8922345 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
....@@ -905,23 +2358,240 @@
9052358 	.num_clks		= ARRAY_SIZE(qmp_v3_phy_clk_l),
9062359 	.reset_list		= msm8996_usb3phy_reset_l,
9072360 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
908
-	.vreg_list		= msm8996_phy_vreg_l,
909
-	.num_vregs		= ARRAY_SIZE(msm8996_phy_vreg_l),
2361
+	.vreg_list		= qmp_phy_vreg_l,
2362
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
9102363 	.regs			= qmp_v3_usb3phy_regs_layout,
9112364 
9122365 	.start_ctrl		= SERDES_START | PCS_START,
9132366 	.pwrdn_ctrl		= SW_PWRDN,
914
-	.mask_pcs_ready		= PHYSTATUS,
9152367 
9162368 	.has_pwrdn_delay	= true,
9172369 	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
9182370 	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
9192371 };
9202372 
921
-static void qcom_qmp_phy_configure(void __iomem *base,
922
-				   const unsigned int *regs,
923
-				   const struct qmp_phy_init_tbl tbl[],
924
-				   int num)
2373
+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
2374
+	.type			= PHY_TYPE_UFS,
2375
+	.nlanes			= 2,
2376
+
2377
+	.serdes_tbl		= sdm845_ufsphy_serdes_tbl,
2378
+	.serdes_tbl_num		= ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
2379
+	.tx_tbl			= sdm845_ufsphy_tx_tbl,
2380
+	.tx_tbl_num		= ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
2381
+	.rx_tbl			= sdm845_ufsphy_rx_tbl,
2382
+	.rx_tbl_num		= ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
2383
+	.pcs_tbl		= sdm845_ufsphy_pcs_tbl,
2384
+	.pcs_tbl_num		= ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
2385
+	.clk_list		= sdm845_ufs_phy_clk_l,
2386
+	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
2387
+	.vreg_list		= qmp_phy_vreg_l,
2388
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2389
+	.regs			= sdm845_ufsphy_regs_layout,
2390
+
2391
+	.start_ctrl		= SERDES_START,
2392
+	.pwrdn_ctrl		= SW_PWRDN,
2393
+
2394
+	.is_dual_lane_phy	= true,
2395
+	.no_pcs_sw_reset	= true,
2396
+};
2397
+
2398
+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
2399
+	.type			= PHY_TYPE_PCIE,
2400
+	.nlanes			= 1,
2401
+
2402
+	.serdes_tbl		= msm8998_pcie_serdes_tbl,
2403
+	.serdes_tbl_num		= ARRAY_SIZE(msm8998_pcie_serdes_tbl),
2404
+	.tx_tbl			= msm8998_pcie_tx_tbl,
2405
+	.tx_tbl_num		= ARRAY_SIZE(msm8998_pcie_tx_tbl),
2406
+	.rx_tbl			= msm8998_pcie_rx_tbl,
2407
+	.rx_tbl_num		= ARRAY_SIZE(msm8998_pcie_rx_tbl),
2408
+	.pcs_tbl		= msm8998_pcie_pcs_tbl,
2409
+	.pcs_tbl_num		= ARRAY_SIZE(msm8998_pcie_pcs_tbl),
2410
+	.clk_list		= msm8996_phy_clk_l,
2411
+	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
2412
+	.reset_list		= ipq8074_pciephy_reset_l,
2413
+	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),
2414
+	.vreg_list		= qmp_phy_vreg_l,
2415
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2416
+	.regs			= pciephy_regs_layout,
2417
+
2418
+	.start_ctrl             = SERDES_START | PCS_START,
2419
+	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
2420
+};
2421
+
2422
+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
2423
+	.type                   = PHY_TYPE_USB3,
2424
+	.nlanes                 = 1,
2425
+
2426
+	.serdes_tbl             = msm8998_usb3_serdes_tbl,
2427
+	.serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
2428
+	.tx_tbl                 = msm8998_usb3_tx_tbl,
2429
+	.tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
2430
+	.rx_tbl                 = msm8998_usb3_rx_tbl,
2431
+	.rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
2432
+	.pcs_tbl                = msm8998_usb3_pcs_tbl,
2433
+	.pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
2434
+	.clk_list               = msm8996_phy_clk_l,
2435
+	.num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2436
+	.reset_list             = msm8996_usb3phy_reset_l,
2437
+	.num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2438
+	.vreg_list              = qmp_phy_vreg_l,
2439
+	.num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2440
+	.regs                   = qmp_v3_usb3phy_regs_layout,
2441
+
2442
+	.start_ctrl             = SERDES_START | PCS_START,
2443
+	.pwrdn_ctrl             = SW_PWRDN,
2444
+
2445
+	.is_dual_lane_phy       = true,
2446
+};
2447
+
2448
+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
2449
+	.type			= PHY_TYPE_UFS,
2450
+	.nlanes			= 2,
2451
+
2452
+	.serdes_tbl		= sm8150_ufsphy_serdes_tbl,
2453
+	.serdes_tbl_num		= ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
2454
+	.tx_tbl			= sm8150_ufsphy_tx_tbl,
2455
+	.tx_tbl_num		= ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
2456
+	.rx_tbl			= sm8150_ufsphy_rx_tbl,
2457
+	.rx_tbl_num		= ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
2458
+	.pcs_tbl		= sm8150_ufsphy_pcs_tbl,
2459
+	.pcs_tbl_num		= ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
2460
+	.clk_list		= sdm845_ufs_phy_clk_l,
2461
+	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
2462
+	.vreg_list		= qmp_phy_vreg_l,
2463
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2464
+	.regs			= sm8150_ufsphy_regs_layout,
2465
+
2466
+	.start_ctrl		= SERDES_START,
2467
+	.pwrdn_ctrl		= SW_PWRDN,
2468
+
2469
+	.is_dual_lane_phy	= true,
2470
+};
2471
+
2472
+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
2473
+	.type			= PHY_TYPE_USB3,
2474
+	.nlanes			= 1,
2475
+
2476
+	.serdes_tbl		= sm8150_usb3_serdes_tbl,
2477
+	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2478
+	.tx_tbl			= sm8150_usb3_tx_tbl,
2479
+	.tx_tbl_num		= ARRAY_SIZE(sm8150_usb3_tx_tbl),
2480
+	.rx_tbl			= sm8150_usb3_rx_tbl,
2481
+	.rx_tbl_num		= ARRAY_SIZE(sm8150_usb3_rx_tbl),
2482
+	.pcs_tbl		= sm8150_usb3_pcs_tbl,
2483
+	.pcs_tbl_num		= ARRAY_SIZE(sm8150_usb3_pcs_tbl),
2484
+	.clk_list		= qmp_v4_phy_clk_l,
2485
+	.num_clks		= ARRAY_SIZE(qmp_v4_phy_clk_l),
2486
+	.reset_list		= msm8996_usb3phy_reset_l,
2487
+	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
2488
+	.vreg_list		= qmp_phy_vreg_l,
2489
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2490
+	.regs			= qmp_v4_usb3phy_regs_layout,
2491
+
2492
+	.start_ctrl		= SERDES_START | PCS_START,
2493
+	.pwrdn_ctrl		= SW_PWRDN,
2494
+
2495
+	.has_pwrdn_delay	= true,
2496
+	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
2497
+	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
2498
+
2499
+	.has_phy_dp_com_ctrl	= true,
2500
+	.is_dual_lane_phy	= true,
2501
+};
2502
+
2503
+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
2504
+	.type			= PHY_TYPE_USB3,
2505
+	.nlanes			= 1,
2506
+
2507
+	.serdes_tbl		= sm8150_usb3_uniphy_serdes_tbl,
2508
+	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
2509
+	.tx_tbl			= sm8150_usb3_uniphy_tx_tbl,
2510
+	.tx_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
2511
+	.rx_tbl			= sm8150_usb3_uniphy_rx_tbl,
2512
+	.rx_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
2513
+	.pcs_tbl		= sm8150_usb3_uniphy_pcs_tbl,
2514
+	.pcs_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
2515
+	.clk_list		= qmp_v4_phy_clk_l,
2516
+	.num_clks		= ARRAY_SIZE(qmp_v4_phy_clk_l),
2517
+	.reset_list		= msm8996_usb3phy_reset_l,
2518
+	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
2519
+	.vreg_list		= qmp_phy_vreg_l,
2520
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2521
+	.regs			= qmp_v4_usb3_uniphy_regs_layout,
2522
+
2523
+	.start_ctrl		= SERDES_START | PCS_START,
2524
+	.pwrdn_ctrl		= SW_PWRDN,
2525
+
2526
+	.has_pwrdn_delay	= true,
2527
+	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
2528
+	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
2529
+};
2530
+
2531
+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
2532
+	.type			= PHY_TYPE_USB3,
2533
+	.nlanes			= 1,
2534
+
2535
+	.serdes_tbl		= sm8150_usb3_serdes_tbl,
2536
+	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2537
+	.tx_tbl			= sm8250_usb3_tx_tbl,
2538
+	.tx_tbl_num		= ARRAY_SIZE(sm8250_usb3_tx_tbl),
2539
+	.rx_tbl			= sm8250_usb3_rx_tbl,
2540
+	.rx_tbl_num		= ARRAY_SIZE(sm8250_usb3_rx_tbl),
2541
+	.pcs_tbl		= sm8250_usb3_pcs_tbl,
2542
+	.pcs_tbl_num		= ARRAY_SIZE(sm8250_usb3_pcs_tbl),
2543
+	.clk_list		= qmp_v4_sm8250_usbphy_clk_l,
2544
+	.num_clks		= ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
2545
+	.reset_list		= msm8996_usb3phy_reset_l,
2546
+	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
2547
+	.vreg_list		= qmp_phy_vreg_l,
2548
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2549
+	.regs			= qmp_v4_usb3phy_regs_layout,
2550
+
2551
+	.start_ctrl		= SERDES_START | PCS_START,
2552
+	.pwrdn_ctrl		= SW_PWRDN,
2553
+
2554
+	.has_pwrdn_delay	= true,
2555
+	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
2556
+	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
2557
+
2558
+	.has_phy_dp_com_ctrl	= true,
2559
+	.is_dual_lane_phy	= true,
2560
+};
2561
+
2562
+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
2563
+	.type			= PHY_TYPE_USB3,
2564
+	.nlanes			= 1,
2565
+
2566
+	.serdes_tbl		= sm8150_usb3_uniphy_serdes_tbl,
2567
+	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
2568
+	.tx_tbl			= sm8250_usb3_uniphy_tx_tbl,
2569
+	.tx_tbl_num		= ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
2570
+	.rx_tbl			= sm8250_usb3_uniphy_rx_tbl,
2571
+	.rx_tbl_num		= ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
2572
+	.pcs_tbl		= sm8250_usb3_uniphy_pcs_tbl,
2573
+	.pcs_tbl_num		= ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
2574
+	.clk_list		= qmp_v4_phy_clk_l,
2575
+	.num_clks		= ARRAY_SIZE(qmp_v4_phy_clk_l),
2576
+	.reset_list		= msm8996_usb3phy_reset_l,
2577
+	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
2578
+	.vreg_list		= qmp_phy_vreg_l,
2579
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
2580
+	.regs			= qmp_v4_usb3_uniphy_regs_layout,
2581
+
2582
+	.start_ctrl		= SERDES_START | PCS_START,
2583
+	.pwrdn_ctrl		= SW_PWRDN,
2584
+
2585
+	.has_pwrdn_delay	= true,
2586
+	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
2587
+	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
2588
+};
2589
+
2590
+static void qcom_qmp_phy_configure_lane(void __iomem *base,
2591
+					const unsigned int *regs,
2592
+					const struct qmp_phy_init_tbl tbl[],
2593
+					int num,
2594
+					u8 lane_mask)
9252595 {
9262596 	int i;
9272597 	const struct qmp_phy_init_tbl *t = tbl;
....@@ -930,6 +2600,9 @@
9302600 		return;
9312601 
9322602 	for (i = 0; i < num; i++, t++) {
2603
+		if (!(t->lane_mask & lane_mask))
2604
+			continue;
2605
+
9332606 		if (t->in_layout)
9342607 			writel(t->val, base + regs[t->offset]);
9352608 		else
....@@ -937,10 +2610,309 @@
9372610 	}
9382611 }
9392612 
940
-static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
2613
+static void qcom_qmp_phy_configure(void __iomem *base,
2614
+				   const unsigned int *regs,
2615
+				   const struct qmp_phy_init_tbl tbl[],
2616
+				   int num)
9412617 {
942
-	const struct qmp_phy_cfg *cfg = qmp->cfg;
943
-	void __iomem *serdes = qmp->serdes;
2618
+	qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
2619
+}
2620
+
2621
+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
2622
+{
2623
+	struct qcom_qmp *qmp = qphy->qmp;
2624
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
2625
+	void __iomem *serdes = qphy->serdes;
2626
+	const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
2627
+	const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
2628
+	int serdes_tbl_num = cfg->serdes_tbl_num;
2629
+	int ret;
2630
+
2631
+	qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
2632
+
2633
+	if (cfg->type == PHY_TYPE_DP) {
2634
+		switch (dp_opts->link_rate) {
2635
+		case 1620:
2636
+			qcom_qmp_phy_configure(serdes, cfg->regs,
2637
+					       cfg->serdes_tbl_rbr,
2638
+					       cfg->serdes_tbl_rbr_num);
2639
+			break;
2640
+		case 2700:
2641
+			qcom_qmp_phy_configure(serdes, cfg->regs,
2642
+					       cfg->serdes_tbl_hbr,
2643
+					       cfg->serdes_tbl_hbr_num);
2644
+			break;
2645
+		case 5400:
2646
+			qcom_qmp_phy_configure(serdes, cfg->regs,
2647
+					       cfg->serdes_tbl_hbr2,
2648
+					       cfg->serdes_tbl_hbr2_num);
2649
+			break;
2650
+		case 8100:
2651
+			qcom_qmp_phy_configure(serdes, cfg->regs,
2652
+					       cfg->serdes_tbl_hbr3,
2653
+					       cfg->serdes_tbl_hbr3_num);
2654
+			break;
2655
+		default:
2656
+			/* Other link rates aren't supported */
2657
+			return -EINVAL;
2658
+		}
2659
+	}
2660
+
2661
+
2662
+	if (cfg->has_phy_com_ctrl) {
2663
+		void __iomem *status;
2664
+		unsigned int mask, val;
2665
+
2666
+		qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
2667
+		qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
2668
+			     SERDES_START | PCS_START);
2669
+
2670
+		status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
2671
+		mask = cfg->mask_com_pcs_ready;
2672
+
2673
+		ret = readl_poll_timeout(status, val, (val & mask), 10,
2674
+					 PHY_INIT_COMPLETE_TIMEOUT);
2675
+		if (ret) {
2676
+			dev_err(qmp->dev,
2677
+				"phy common block init timed-out\n");
2678
+			return ret;
2679
+		}
2680
+	}
2681
+
2682
+	return 0;
2683
+}
2684
+
2685
+static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy)
2686
+{
2687
+	writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2688
+	       DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2689
+	       qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2690
+
2691
+	/* Turn on BIAS current for PHY/PLL */
2692
+	writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
2693
+	       QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
2694
+	       qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
2695
+
2696
+	writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2697
+
2698
+	writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2699
+	       DP_PHY_PD_CTL_LANE_0_1_PWRDN |
2700
+	       DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
2701
+	       DP_PHY_PD_CTL_DP_CLAMP_EN,
2702
+	       qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2703
+
2704
+	writel(QSERDES_V3_COM_BIAS_EN |
2705
+	       QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
2706
+	       QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
2707
+	       QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
2708
+	       qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
2709
+
2710
+	writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
2711
+	writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
2712
+	writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
2713
+	writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
2714
+	writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
2715
+	writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
2716
+	writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
2717
+	writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
2718
+	writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
2719
+	writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
2720
+	qphy->dp_aux_cfg = 0;
2721
+
2722
+	writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2723
+	       PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2724
+	       PHY_AUX_REQ_ERR_MASK,
2725
+	       qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
2726
+}
2727
+
2728
+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
2729
+	{ 0x00, 0x0c, 0x14, 0x19 },
2730
+	{ 0x00, 0x0b, 0x12, 0xff },
2731
+	{ 0x00, 0x0b, 0xff, 0xff },
2732
+	{ 0x04, 0xff, 0xff, 0xff }
2733
+};
2734
+
2735
+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
2736
+	{ 0x08, 0x0f, 0x16, 0x1f },
2737
+	{ 0x11, 0x1e, 0x1f, 0xff },
2738
+	{ 0x19, 0x1f, 0xff, 0xff },
2739
+	{ 0x1f, 0xff, 0xff, 0xff }
2740
+};
2741
+
2742
+static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy)
2743
+{
2744
+	const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
2745
+	unsigned int v_level = 0, p_level = 0;
2746
+	u32 bias_en, drvr_en;
2747
+	u8 voltage_swing_cfg, pre_emphasis_cfg;
2748
+	int i;
2749
+
2750
+	for (i = 0; i < dp_opts->lanes; i++) {
2751
+		v_level = max(v_level, dp_opts->voltage[i]);
2752
+		p_level = max(p_level, dp_opts->pre[i]);
2753
+	}
2754
+
2755
+	if (dp_opts->lanes == 1) {
2756
+		bias_en = 0x3e;
2757
+		drvr_en = 0x13;
2758
+	} else {
2759
+		bias_en = 0x3f;
2760
+		drvr_en = 0x10;
2761
+	}
2762
+
2763
+	voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
2764
+	pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
2765
+
2766
+	/* TODO: Move check to config check */
2767
+	if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
2768
+		return;
2769
+
2770
+	/* Enable MUX to use Cursor values from these registers */
2771
+	voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
2772
+	pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
2773
+
2774
+	writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL);
2775
+	writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL);
2776
+	writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL);
2777
+	writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL);
2778
+
2779
+	writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2780
+	writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2781
+	writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2782
+	writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2783
+}
2784
+
2785
+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
2786
+{
2787
+	const struct phy_configure_opts_dp *dp_opts = &opts->dp;
2788
+	struct qmp_phy *qphy = phy_get_drvdata(phy);
2789
+
2790
+	memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
2791
+	if (qphy->dp_opts.set_voltages) {
2792
+		qcom_qmp_phy_configure_dp_tx(qphy);
2793
+		qphy->dp_opts.set_voltages = 0;
2794
+	}
2795
+
2796
+	return 0;
2797
+}
2798
+
2799
+static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy)
2800
+{
2801
+	const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
2802
+	const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
2803
+	u32 val, phy_vco_div, status;
2804
+	unsigned long pixel_freq;
2805
+
2806
+	val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2807
+	      DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
2808
+
2809
+	/*
2810
+	 * TODO: Assume orientation is CC1 for now and two lanes, need to
2811
+	 * use type-c connector to understand orientation and lanes.
2812
+	 *
2813
+	 * Otherwise val changes to be like below if this code understood
2814
+	 * the orientation of the type-c cable.
2815
+	 *
2816
+	 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
2817
+	 *	val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
2818
+	 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
2819
+	 *	val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
2820
+	 * if (orientation == ORIENTATION_CC2)
2821
+	 *	writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
2822
+	 */
2823
+	val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
2824
+	writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2825
+
2826
+	writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
2827
+	writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
2828
+	writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
2829
+
2830
+	switch (dp_opts->link_rate) {
2831
+	case 1620:
2832
+		phy_vco_div = 0x1;
2833
+		pixel_freq = 1620000000UL / 2;
2834
+		break;
2835
+	case 2700:
2836
+		phy_vco_div = 0x1;
2837
+		pixel_freq = 2700000000UL / 2;
2838
+		break;
2839
+	case 5400:
2840
+		phy_vco_div = 0x2;
2841
+		pixel_freq = 5400000000UL / 4;
2842
+		break;
2843
+	case 8100:
2844
+		phy_vco_div = 0x0;
2845
+		pixel_freq = 8100000000UL / 6;
2846
+		break;
2847
+	default:
2848
+		/* Other link rates aren't supported */
2849
+		return -EINVAL;
2850
+	}
2851
+	writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
2852
+
2853
+	clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
2854
+	clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
2855
+
2856
+	writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
2857
+	writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2858
+	writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2859
+	writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2860
+	writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2861
+
2862
+	writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
2863
+
2864
+	if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
2865
+			status,
2866
+			((status & BIT(0)) > 0),
2867
+			500,
2868
+			10000))
2869
+		return -ETIMEDOUT;
2870
+
2871
+	writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2872
+
2873
+	if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
2874
+			status,
2875
+			((status & BIT(1)) > 0),
2876
+			500,
2877
+			10000))
2878
+		return -ETIMEDOUT;
2879
+
2880
+	writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2881
+	udelay(2000);
2882
+	writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2883
+
2884
+	return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
2885
+			status,
2886
+			((status & BIT(1)) > 0),
2887
+			500,
2888
+			10000);
2889
+}
2890
+
2891
+/*
2892
+ * We need to calibrate the aux setting here as many times
2893
+ * as the caller tries
2894
+ */
2895
+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
2896
+{
2897
+	struct qmp_phy *qphy = phy_get_drvdata(phy);
2898
+	const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
2899
+	u8 val;
2900
+
2901
+	qphy->dp_aux_cfg++;
2902
+	qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2903
+	val = cfg1_settings[qphy->dp_aux_cfg];
2904
+
2905
+	writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
2906
+
2907
+	return 0;
2908
+}
2909
+
2910
+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
2911
+{
2912
+	struct qcom_qmp *qmp = qphy->qmp;
2913
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
2914
+	void __iomem *serdes = qphy->serdes;
2915
+	void __iomem *pcs = qphy->pcs;
9442916 	void __iomem *dp_com = qmp->dp_com;
9452917 	int ret, i;
9462918 
....@@ -970,7 +2942,7 @@
9702942 		ret = reset_control_deassert(qmp->resets[i]);
9712943 		if (ret) {
9722944 			dev_err(qmp->dev, "%s reset deassert failed\n",
973
-				qmp->cfg->reset_list[i]);
2945
+				qphy->cfg->reset_list[i]);
9742946 			goto err_rst;
9752947 		}
9762948 	}
....@@ -981,10 +2953,6 @@
9812953 		goto err_rst;
9822954 	}
9832955 
984
-	if (cfg->has_phy_com_ctrl)
985
-		qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
986
-			     SW_PWRDN);
987
-
9882956 	if (cfg->has_phy_dp_com_ctrl) {
9892957 		qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
9902958 			     SW_PWRDN);
....@@ -993,6 +2961,9 @@
9932961 			     SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
9942962 			     SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
9952963 
2964
+		/* Default type-c orientation, i.e CC1 */
2965
+		qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
2966
+
9962967 		qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
9972968 			     USB3_MODE | DP_MODE);
9982969 
....@@ -1000,38 +2971,28 @@
10002971 		qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
10012972 			     SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
10022973 			     SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2974
+
2975
+		qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2976
+		qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
10032977 	}
10042978 
1005
-	/* Serdes configuration */
1006
-	qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
1007
-			       cfg->serdes_tbl_num);
1008
-
10092979 	if (cfg->has_phy_com_ctrl) {
1010
-		void __iomem *status;
1011
-		unsigned int mask, val;
1012
-
1013
-		qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
1014
-		qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1015
-			     SERDES_START | PCS_START);
1016
-
1017
-		status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
1018
-		mask = cfg->mask_com_pcs_ready;
1019
-
1020
-		ret = readl_poll_timeout(status, val, (val & mask), 10,
1021
-					 PHY_INIT_COMPLETE_TIMEOUT);
1022
-		if (ret) {
1023
-			dev_err(qmp->dev,
1024
-				"phy common block init timed-out\n");
1025
-			goto err_com_init;
1026
-		}
2980
+		qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
2981
+			     SW_PWRDN);
2982
+	} else {
2983
+		if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
2984
+			qphy_setbits(pcs,
2985
+					cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2986
+					cfg->pwrdn_ctrl);
2987
+		else
2988
+			qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
2989
+					cfg->pwrdn_ctrl);
10272990 	}
10282991 
10292992 	mutex_unlock(&qmp->phy_mutex);
10302993 
10312994 	return 0;
10322995 
1033
-err_com_init:
1034
-	clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
10352996 err_rst:
10362997 	while (++i < cfg->num_resets)
10372998 		reset_control_assert(qmp->resets[i]);
....@@ -1043,10 +3004,11 @@
10433004 	return ret;
10443005 }
10453006 
1046
-static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
3007
+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
10473008 {
1048
-	const struct qmp_phy_cfg *cfg = qmp->cfg;
1049
-	void __iomem *serdes = qmp->serdes;
3009
+	struct qcom_qmp *qmp = qphy->qmp;
3010
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
3011
+	void __iomem *serdes = qphy->serdes;
10503012 	int i = cfg->num_resets;
10513013 
10523014 	mutex_lock(&qmp->phy_mutex);
....@@ -1055,6 +3017,7 @@
10553017 		return 0;
10563018 	}
10573019 
3020
+	reset_control_assert(qmp->ufs_reset);
10583021 	if (cfg->has_phy_com_ctrl) {
10593022 		qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
10603023 			     SERDES_START | PCS_START);
....@@ -1076,25 +3039,65 @@
10763039 	return 0;
10773040 }
10783041 
1079
-/* PHY Initialization */
10803042 static int qcom_qmp_phy_init(struct phy *phy)
10813043 {
10823044 	struct qmp_phy *qphy = phy_get_drvdata(phy);
10833045 	struct qcom_qmp *qmp = qphy->qmp;
1084
-	const struct qmp_phy_cfg *cfg = qmp->cfg;
3046
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
3047
+	int ret;
3048
+	dev_vdbg(qmp->dev, "Initializing QMP phy\n");
3049
+
3050
+	if (cfg->no_pcs_sw_reset) {
3051
+		/*
3052
+		 * Get UFS reset, which is delayed until now to avoid a
3053
+		 * circular dependency where UFS needs its PHY, but the PHY
3054
+		 * needs this UFS reset.
3055
+		 */
3056
+		if (!qmp->ufs_reset) {
3057
+			qmp->ufs_reset =
3058
+				devm_reset_control_get_exclusive(qmp->dev,
3059
+								 "ufsphy");
3060
+
3061
+			if (IS_ERR(qmp->ufs_reset)) {
3062
+				ret = PTR_ERR(qmp->ufs_reset);
3063
+				dev_err(qmp->dev,
3064
+					"failed to get UFS reset: %d\n",
3065
+					ret);
3066
+
3067
+				qmp->ufs_reset = NULL;
3068
+				return ret;
3069
+			}
3070
+		}
3071
+
3072
+		ret = reset_control_assert(qmp->ufs_reset);
3073
+		if (ret)
3074
+			return ret;
3075
+	}
3076
+
3077
+	ret = qcom_qmp_phy_com_init(qphy);
3078
+	if (ret)
3079
+		return ret;
3080
+
3081
+	if (cfg->type == PHY_TYPE_DP)
3082
+		qcom_qmp_phy_dp_aux_init(qphy);
3083
+
3084
+	return 0;
3085
+}
3086
+
3087
+static int qcom_qmp_phy_power_on(struct phy *phy)
3088
+{
3089
+	struct qmp_phy *qphy = phy_get_drvdata(phy);
3090
+	struct qcom_qmp *qmp = qphy->qmp;
3091
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
10853092 	void __iomem *tx = qphy->tx;
10863093 	void __iomem *rx = qphy->rx;
10873094 	void __iomem *pcs = qphy->pcs;
1088
-	void __iomem *dp_com = qmp->dp_com;
3095
+	void __iomem *pcs_misc = qphy->pcs_misc;
10893096 	void __iomem *status;
1090
-	unsigned int mask, val;
3097
+	unsigned int mask, val, ready;
10913098 	int ret;
10923099 
1093
-	dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1094
-
1095
-	ret = qcom_qmp_phy_com_init(qmp);
1096
-	if (ret)
1097
-		return ret;
3100
+	qcom_qmp_phy_serdes_init(qphy);
10983101 
10993102 	if (cfg->has_lane_rst) {
11003103 		ret = reset_control_deassert(qphy->lane_rst);
....@@ -1112,48 +3115,72 @@
11123115 	}
11133116 
11143117 	/* Tx, Rx, and PCS configurations */
1115
-	qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
3118
+	qcom_qmp_phy_configure_lane(tx, cfg->regs,
3119
+				    cfg->tx_tbl, cfg->tx_tbl_num, 1);
11163120 	/* Configuration for other LANE for USB-DP combo PHY */
1117
-	if (cfg->has_phy_dp_com_ctrl)
1118
-		qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs,
1119
-				       cfg->tx_tbl, cfg->tx_tbl_num);
3121
+	if (cfg->is_dual_lane_phy)
3122
+		qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
3123
+					    cfg->tx_tbl, cfg->tx_tbl_num, 2);
11203124 
1121
-	qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
1122
-	if (cfg->has_phy_dp_com_ctrl)
1123
-		qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs,
1124
-				       cfg->rx_tbl, cfg->rx_tbl_num);
3125
+	/* Configure special DP tx tunings */
3126
+	if (cfg->type == PHY_TYPE_DP)
3127
+		qcom_qmp_phy_configure_dp_tx(qphy);
11253128 
1126
-	qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
3129
+	qcom_qmp_phy_configure_lane(rx, cfg->regs,
3130
+				    cfg->rx_tbl, cfg->rx_tbl_num, 1);
3131
+
3132
+	if (cfg->is_dual_lane_phy)
3133
+		qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
3134
+					    cfg->rx_tbl, cfg->rx_tbl_num, 2);
3135
+
3136
+	/* Configure link rate, swing, etc. */
3137
+	if (cfg->type == PHY_TYPE_DP)
3138
+		qcom_qmp_phy_configure_dp_phy(qphy);
3139
+	else
3140
+		qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
3141
+
3142
+	ret = reset_control_deassert(qmp->ufs_reset);
3143
+	if (ret)
3144
+		goto err_pcs_ready;
3145
+
3146
+	qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
3147
+			       cfg->pcs_misc_tbl_num);
11273148 
11283149 	/*
11293150 	 * Pull out PHY from POWER DOWN state.
11303151 	 * This is active low enable signal to power-down PHY.
11313152 	 */
1132
-	qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
3153
+	if(cfg->type == PHY_TYPE_PCIE)
3154
+		qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
11333155 
11343156 	if (cfg->has_pwrdn_delay)
11353157 		usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
11363158 
1137
-	/* Pull PHY out of reset state */
1138
-	qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1139
-	if (cfg->has_phy_dp_com_ctrl)
1140
-		qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
3159
+	if (cfg->type != PHY_TYPE_DP) {
3160
+		/* Pull PHY out of reset state */
3161
+		if (!cfg->no_pcs_sw_reset)
3162
+			qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3163
+		/* start SerDes and Phy-Coding-Sublayer */
3164
+		qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
11413165 
1142
-	/* start SerDes and Phy-Coding-Sublayer */
1143
-	qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3166
+		if (cfg->type == PHY_TYPE_UFS) {
3167
+			status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
3168
+			mask = PCS_READY;
3169
+			ready = PCS_READY;
3170
+		} else {
3171
+			status = pcs + cfg->regs[QPHY_PCS_STATUS];
3172
+			mask = PHYSTATUS;
3173
+			ready = 0;
3174
+		}
11443175 
1145
-	status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1146
-	mask = cfg->mask_pcs_ready;
1147
-
1148
-	ret = readl_poll_timeout(status, val, !(val & mask), 1,
1149
-				 PHY_INIT_COMPLETE_TIMEOUT);
1150
-	if (ret) {
1151
-		dev_err(qmp->dev, "phy initialization timed-out\n");
1152
-		goto err_pcs_ready;
3176
+		ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
3177
+					 PHY_INIT_COMPLETE_TIMEOUT);
3178
+		if (ret) {
3179
+			dev_err(qmp->dev, "phy initialization timed-out\n");
3180
+			goto err_pcs_ready;
3181
+		}
11533182 	}
1154
-	qmp->phy_initialized = true;
1155
-
1156
-	return ret;
3183
+	return 0;
11573184 
11583185 err_pcs_ready:
11593186 	clk_disable_unprepare(qphy->pipe_clk);
....@@ -1161,58 +3188,97 @@
11613188 	if (cfg->has_lane_rst)
11623189 		reset_control_assert(qphy->lane_rst);
11633190 err_lane_rst:
1164
-	qcom_qmp_phy_com_exit(qmp);
1165
-
11663191 	return ret;
3192
+}
3193
+
3194
+static int qcom_qmp_phy_power_off(struct phy *phy)
3195
+{
3196
+	struct qmp_phy *qphy = phy_get_drvdata(phy);
3197
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
3198
+
3199
+	clk_disable_unprepare(qphy->pipe_clk);
3200
+
3201
+	if (cfg->type == PHY_TYPE_DP) {
3202
+		/* Assert DP PHY power down */
3203
+		writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3204
+	} else {
3205
+		/* PHY reset */
3206
+		if (!cfg->no_pcs_sw_reset)
3207
+			qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3208
+
3209
+		/* stop SerDes and Phy-Coding-Sublayer */
3210
+		qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3211
+
3212
+		/* Put PHY into POWER DOWN state: active low */
3213
+		if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
3214
+			qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3215
+				     cfg->pwrdn_ctrl);
3216
+		} else {
3217
+			qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
3218
+					cfg->pwrdn_ctrl);
3219
+		}
3220
+	}
3221
+
3222
+	return 0;
11673223 }
11683224 
11693225 static int qcom_qmp_phy_exit(struct phy *phy)
11703226 {
11713227 	struct qmp_phy *qphy = phy_get_drvdata(phy);
1172
-	struct qcom_qmp *qmp = qphy->qmp;
1173
-	const struct qmp_phy_cfg *cfg = qmp->cfg;
1174
-
1175
-	clk_disable_unprepare(qphy->pipe_clk);
1176
-
1177
-	/* PHY reset */
1178
-	qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1179
-
1180
-	/* stop SerDes and Phy-Coding-Sublayer */
1181
-	qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1182
-
1183
-	/* Put PHY into POWER DOWN state: active low */
1184
-	qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
3228
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
11853229 
11863230 	if (cfg->has_lane_rst)
11873231 		reset_control_assert(qphy->lane_rst);
11883232 
1189
-	qcom_qmp_phy_com_exit(qmp);
1190
-
1191
-	qmp->phy_initialized = false;
3233
+	qcom_qmp_phy_com_exit(qphy);
11923234 
11933235 	return 0;
11943236 }
11953237 
1196
-static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode)
3238
+static int qcom_qmp_phy_enable(struct phy *phy)
3239
+{
3240
+	int ret;
3241
+
3242
+	ret = qcom_qmp_phy_init(phy);
3243
+	if (ret)
3244
+		return ret;
3245
+
3246
+	ret = qcom_qmp_phy_power_on(phy);
3247
+	if (ret)
3248
+		qcom_qmp_phy_exit(phy);
3249
+
3250
+	return ret;
3251
+}
3252
+
3253
+static int qcom_qmp_phy_disable(struct phy *phy)
3254
+{
3255
+	int ret;
3256
+
3257
+	ret = qcom_qmp_phy_power_off(phy);
3258
+	if (ret)
3259
+		return ret;
3260
+	return qcom_qmp_phy_exit(phy);
3261
+}
3262
+
3263
+static int qcom_qmp_phy_set_mode(struct phy *phy,
3264
+				 enum phy_mode mode, int submode)
11973265 {
11983266 	struct qmp_phy *qphy = phy_get_drvdata(phy);
1199
-	struct qcom_qmp *qmp = qphy->qmp;
12003267 
1201
-	qmp->mode = mode;
3268
+	qphy->mode = mode;
12023269 
12033270 	return 0;
12043271 }
12053272 
12063273 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
12073274 {
1208
-	struct qcom_qmp *qmp = qphy->qmp;
1209
-	const struct qmp_phy_cfg *cfg = qmp->cfg;
3275
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
12103276 	void __iomem *pcs = qphy->pcs;
12113277 	void __iomem *pcs_misc = qphy->pcs_misc;
12123278 	u32 intr_mask;
12133279 
1214
-	if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1215
-	    qmp->mode == PHY_MODE_USB_DEVICE_SS)
3280
+	if (qphy->mode == PHY_MODE_USB_HOST_SS ||
3281
+	    qphy->mode == PHY_MODE_USB_DEVICE_SS)
12163282 		intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
12173283 	else
12183284 		intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
....@@ -1235,8 +3301,7 @@
12353301 
12363302 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
12373303 {
1238
-	struct qcom_qmp *qmp = qphy->qmp;
1239
-	const struct qmp_phy_cfg *cfg = qmp->cfg;
3304
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
12403305 	void __iomem *pcs = qphy->pcs;
12413306 	void __iomem *pcs_misc = qphy->pcs_misc;
12423307 
....@@ -1256,15 +3321,15 @@
12563321 {
12573322 	struct qcom_qmp *qmp = dev_get_drvdata(dev);
12583323 	struct qmp_phy *qphy = qmp->phys[0];
1259
-	const struct qmp_phy_cfg *cfg = qmp->cfg;
3324
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
12603325 
1261
-	dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
3326
+	dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
12623327 
1263
-	/* Supported only for USB3 PHY */
3328
+	/* Supported only for USB3 PHY and luckily USB3 is the first phy */
12643329 	if (cfg->type != PHY_TYPE_USB3)
12653330 		return 0;
12663331 
1267
-	if (!qmp->phy_initialized) {
3332
+	if (!qmp->init_count) {
12683333 		dev_vdbg(dev, "PHY not initialized, bailing out\n");
12693334 		return 0;
12703335 	}
....@@ -1281,16 +3346,16 @@
12813346 {
12823347 	struct qcom_qmp *qmp = dev_get_drvdata(dev);
12833348 	struct qmp_phy *qphy = qmp->phys[0];
1284
-	const struct qmp_phy_cfg *cfg = qmp->cfg;
3349
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
12853350 	int ret = 0;
12863351 
1287
-	dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
3352
+	dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
12883353 
1289
-	/* Supported only for USB3 PHY */
3354
+	/* Supported only for USB3 PHY and luckily USB3 is the first phy */
12903355 	if (cfg->type != PHY_TYPE_USB3)
12913356 		return 0;
12923357 
1293
-	if (!qmp->phy_initialized) {
3358
+	if (!qmp->init_count) {
12943359 		dev_vdbg(dev, "PHY not initialized, bailing out\n");
12953360 		return 0;
12963361 	}
....@@ -1313,10 +3378,10 @@
13133378 	return 0;
13143379 }
13153380 
1316
-static int qcom_qmp_phy_vreg_init(struct device *dev)
3381
+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
13173382 {
13183383 	struct qcom_qmp *qmp = dev_get_drvdata(dev);
1319
-	int num = qmp->cfg->num_vregs;
3384
+	int num = cfg->num_vregs;
13203385 	int i;
13213386 
13223387 	qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
....@@ -1324,24 +3389,24 @@
13243389 		return -ENOMEM;
13253390 
13263391 	for (i = 0; i < num; i++)
1327
-		qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
3392
+		qmp->vregs[i].supply = cfg->vreg_list[i];
13283393 
13293394 	return devm_regulator_bulk_get(dev, num, qmp->vregs);
13303395 }
13313396 
1332
-static int qcom_qmp_phy_reset_init(struct device *dev)
3397
+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
13333398 {
13343399 	struct qcom_qmp *qmp = dev_get_drvdata(dev);
13353400 	int i;
13363401 
1337
-	qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
3402
+	qmp->resets = devm_kcalloc(dev, cfg->num_resets,
13383403 				   sizeof(*qmp->resets), GFP_KERNEL);
13393404 	if (!qmp->resets)
13403405 		return -ENOMEM;
13413406 
1342
-	for (i = 0; i < qmp->cfg->num_resets; i++) {
3407
+	for (i = 0; i < cfg->num_resets; i++) {
13433408 		struct reset_control *rst;
1344
-		const char *name = qmp->cfg->reset_list[i];
3409
+		const char *name = cfg->reset_list[i];
13453410 
13463411 		rst = devm_reset_control_get(dev, name);
13473412 		if (IS_ERR(rst)) {
....@@ -1354,10 +3419,10 @@
13543419 	return 0;
13553420 }
13563421 
1357
-static int qcom_qmp_phy_clk_init(struct device *dev)
3422
+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
13583423 {
13593424 	struct qcom_qmp *qmp = dev_get_drvdata(dev);
1360
-	int num = qmp->cfg->num_clks;
3425
+	int num = cfg->num_clks;
13613426 	int i;
13623427 
13633428 	qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
....@@ -1365,9 +3430,14 @@
13653430 		return -ENOMEM;
13663431 
13673432 	for (i = 0; i < num; i++)
1368
-		qmp->clks[i].id = qmp->cfg->clk_list[i];
3433
+		qmp->clks[i].id = cfg->clk_list[i];
13693434 
13703435 	return devm_clk_bulk_get(dev, num, qmp->clks);
3436
+}
3437
+
3438
+static void phy_clk_release_provider(void *res)
3439
+{
3440
+	of_clk_del_provider(res);
13713441 }
13723442 
13733443 /*
....@@ -1394,15 +3464,9 @@
13943464 	struct clk_init_data init = { };
13953465 	int ret;
13963466 
1397
-	if ((qmp->cfg->type != PHY_TYPE_USB3) &&
1398
-	    (qmp->cfg->type != PHY_TYPE_PCIE)) {
1399
-		/* not all phys register pipe clocks, so return success */
1400
-		return 0;
1401
-	}
1402
-
14033467 	ret = of_property_read_string(np, "clock-output-names", &init.name);
14043468 	if (ret) {
1405
-		dev_err(qmp->dev, "%s: No clock-output-names\n", np->name);
3469
+		dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
14063470 		return ret;
14073471 	}
14083472 
....@@ -1416,22 +3480,256 @@
14163480 	fixed->fixed_rate = 125000000;
14173481 	fixed->hw.init = &init;
14183482 
1419
-	return devm_clk_hw_register(qmp->dev, &fixed->hw);
3483
+	ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
3484
+	if (ret)
3485
+		return ret;
3486
+
3487
+	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
3488
+	if (ret)
3489
+		return ret;
3490
+
3491
+	/*
3492
+	 * Roll a devm action because the clock provider is the child node, but
3493
+	 * the child node is not actually a device.
3494
+	 */
3495
+	ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
3496
+	if (ret)
3497
+		phy_clk_release_provider(np);
3498
+
3499
+	return ret;
3500
+}
3501
+
3502
+/*
3503
+ * Display Port PLL driver block diagram for branch clocks
3504
+ *
3505
+ *              +------------------------------+
3506
+ *              |         DP_VCO_CLK           |
3507
+ *              |                              |
3508
+ *              |    +-------------------+     |
3509
+ *              |    |   (DP PLL/VCO)    |     |
3510
+ *              |    +---------+---------+     |
3511
+ *              |              v               |
3512
+ *              |   +----------+-----------+   |
3513
+ *              |   | hsclk_divsel_clk_src |   |
3514
+ *              |   +----------+-----------+   |
3515
+ *              +------------------------------+
3516
+ *                              |
3517
+ *          +---------<---------v------------>----------+
3518
+ *          |                                           |
3519
+ * +--------v----------------+                          |
3520
+ * |    dp_phy_pll_link_clk  |                          |
3521
+ * |     link_clk            |                          |
3522
+ * +--------+----------------+                          |
3523
+ *          |                                           |
3524
+ *          |                                           |
3525
+ *          v                                           v
3526
+ * Input to DISPCC block                                |
3527
+ * for link clk, crypto clk                             |
3528
+ * and interface clock                                  |
3529
+ *                                                      |
3530
+ *                                                      |
3531
+ *      +--------<------------+-----------------+---<---+
3532
+ *      |                     |                 |
3533
+ * +----v---------+  +--------v-----+  +--------v------+
3534
+ * | vco_divided  |  | vco_divided  |  | vco_divided   |
3535
+ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
3536
+ * |              |  |              |  |               |
3537
+ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
3538
+ * +-------+------+  +-----+--------+  +--------+------+
3539
+ *         |                 |                  |
3540
+ *         v---->----------v-------------<------v
3541
+ *                         |
3542
+ *              +----------+-----------------+
3543
+ *              |   dp_phy_pll_vco_div_clk   |
3544
+ *              +---------+------------------+
3545
+ *                        |
3546
+ *                        v
3547
+ *              Input to DISPCC block
3548
+ *              for DP pixel clock
3549
+ *
3550
+ */
3551
+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
3552
+						struct clk_rate_request *req)
3553
+{
3554
+	switch (req->rate) {
3555
+	case 1620000000UL / 2:
3556
+	case 2700000000UL / 2:
3557
+	/* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
3558
+		return 0;
3559
+	default:
3560
+		return -EINVAL;
3561
+	}
3562
+}
3563
+
3564
+static unsigned long
3565
+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3566
+{
3567
+	const struct qmp_phy_dp_clks *dp_clks;
3568
+	const struct qmp_phy *qphy;
3569
+	const struct phy_configure_opts_dp *dp_opts;
3570
+
3571
+	dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
3572
+	qphy = dp_clks->qphy;
3573
+	dp_opts = &qphy->dp_opts;
3574
+
3575
+	switch (dp_opts->link_rate) {
3576
+	case 1620:
3577
+		return 1620000000UL / 2;
3578
+	case 2700:
3579
+		return 2700000000UL / 2;
3580
+	case 5400:
3581
+		return 5400000000UL / 4;
3582
+	case 8100:
3583
+		return 8100000000UL / 6;
3584
+	default:
3585
+		return 0;
3586
+	}
3587
+}
3588
+
3589
+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
3590
+	.determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
3591
+	.recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
3592
+};
3593
+
3594
+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
3595
+					       struct clk_rate_request *req)
3596
+{
3597
+	switch (req->rate) {
3598
+	case 162000000:
3599
+	case 270000000:
3600
+	case 540000000:
3601
+	case 810000000:
3602
+		return 0;
3603
+	default:
3604
+		return -EINVAL;
3605
+	}
3606
+}
3607
+
3608
+static unsigned long
3609
+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3610
+{
3611
+	const struct qmp_phy_dp_clks *dp_clks;
3612
+	const struct qmp_phy *qphy;
3613
+	const struct phy_configure_opts_dp *dp_opts;
3614
+
3615
+	dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
3616
+	qphy = dp_clks->qphy;
3617
+	dp_opts = &qphy->dp_opts;
3618
+
3619
+	switch (dp_opts->link_rate) {
3620
+	case 1620:
3621
+	case 2700:
3622
+	case 5400:
3623
+	case 8100:
3624
+		return dp_opts->link_rate * 100000;
3625
+	default:
3626
+		return 0;
3627
+	}
3628
+}
3629
+
3630
+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
3631
+	.determine_rate = qcom_qmp_dp_link_clk_determine_rate,
3632
+	.recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
3633
+};
3634
+
3635
+static struct clk_hw *
3636
+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
3637
+{
3638
+	struct qmp_phy_dp_clks *dp_clks = data;
3639
+	unsigned int idx = clkspec->args[0];
3640
+
3641
+	if (idx >= 2) {
3642
+		pr_err("%s: invalid index %u\n", __func__, idx);
3643
+		return ERR_PTR(-EINVAL);
3644
+	}
3645
+
3646
+	if (idx == 0)
3647
+		return &dp_clks->dp_link_hw;
3648
+
3649
+	return &dp_clks->dp_pixel_hw;
3650
+}
3651
+
3652
+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
3653
+				struct device_node *np)
3654
+{
3655
+	struct clk_init_data init = { };
3656
+	struct qmp_phy_dp_clks *dp_clks;
3657
+	int ret;
3658
+
3659
+	dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
3660
+	if (!dp_clks)
3661
+		return -ENOMEM;
3662
+
3663
+	dp_clks->qphy = qphy;
3664
+	qphy->dp_clks = dp_clks;
3665
+
3666
+	init.ops = &qcom_qmp_dp_link_clk_ops;
3667
+	init.name = "qmp_dp_phy_pll_link_clk";
3668
+	dp_clks->dp_link_hw.init = &init;
3669
+	ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
3670
+	if (ret)
3671
+		return ret;
3672
+
3673
+	init.ops = &qcom_qmp_dp_pixel_clk_ops;
3674
+	init.name = "qmp_dp_phy_pll_vco_div_clk";
3675
+	dp_clks->dp_pixel_hw.init = &init;
3676
+	ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
3677
+	if (ret)
3678
+		return ret;
3679
+
3680
+	ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
3681
+	if (ret)
3682
+		return ret;
3683
+
3684
+	/*
3685
+	 * Roll a devm action because the clock provider is the child node, but
3686
+	 * the child node is not actually a device.
3687
+	 */
3688
+	ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
3689
+	if (ret)
3690
+		phy_clk_release_provider(np);
3691
+
3692
+	return ret;
14203693 }
14213694 
14223695 static const struct phy_ops qcom_qmp_phy_gen_ops = {
3696
+	.init		= qcom_qmp_phy_enable,
3697
+	.exit		= qcom_qmp_phy_disable,
3698
+	.set_mode	= qcom_qmp_phy_set_mode,
3699
+	.owner		= THIS_MODULE,
3700
+};
3701
+
3702
+static const struct phy_ops qcom_qmp_phy_dp_ops = {
14233703 	.init		= qcom_qmp_phy_init,
3704
+	.configure	= qcom_qmp_dp_phy_configure,
3705
+	.power_on	= qcom_qmp_phy_power_on,
3706
+	.calibrate	= qcom_qmp_dp_phy_calibrate,
3707
+	.power_off	= qcom_qmp_phy_power_off,
14243708 	.exit		= qcom_qmp_phy_exit,
14253709 	.set_mode	= qcom_qmp_phy_set_mode,
14263710 	.owner		= THIS_MODULE,
14273711 };
14283712 
3713
+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
3714
+	.power_on	= qcom_qmp_phy_enable,
3715
+	.power_off	= qcom_qmp_phy_disable,
3716
+	.set_mode	= qcom_qmp_phy_set_mode,
3717
+	.owner		= THIS_MODULE,
3718
+};
3719
+
3720
+static void qcom_qmp_reset_control_put(void *data)
3721
+{
3722
+	reset_control_put(data);
3723
+}
3724
+
14293725 static
1430
-int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
3726
+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
3727
+			void __iomem *serdes, const struct qmp_phy_cfg *cfg)
14313728 {
14323729 	struct qcom_qmp *qmp = dev_get_drvdata(dev);
14333730 	struct phy *generic_phy;
14343731 	struct qmp_phy *qphy;
3732
+	const struct phy_ops *ops;
14353733 	char prop_name[MAX_PROP_NAME];
14363734 	int ret;
14373735 
....@@ -1439,10 +3737,13 @@
14393737 	if (!qphy)
14403738 		return -ENOMEM;
14413739 
3740
+	qphy->cfg = cfg;
3741
+	qphy->serdes = serdes;
14423742 	/*
14433743 	 * Get memory resources for each phy lane:
1444
-	 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; and
1445
-	 * pcs_misc (optional) -> 3.
3744
+	 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
3745
+	 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
3746
+	 * For single lane PHYs: pcs_misc (optional) -> 3.
14463747 	 */
14473748 	qphy->tx = of_iomap(np, 0);
14483749 	if (!qphy->tx)
....@@ -1456,7 +3757,32 @@
14563757 	if (!qphy->pcs)
14573758 		return -ENOMEM;
14583759 
1459
-	qphy->pcs_misc = of_iomap(np, 3);
3760
+	/*
3761
+	 * If this is a dual-lane PHY, then there should be registers for the
3762
+	 * second lane. Some old device trees did not specify this, so fall
3763
+	 * back to old legacy behavior of assuming they can be reached at an
3764
+	 * offset from the first lane.
3765
+	 */
3766
+	if (cfg->is_dual_lane_phy) {
3767
+		qphy->tx2 = of_iomap(np, 3);
3768
+		qphy->rx2 = of_iomap(np, 4);
3769
+		if (!qphy->tx2 || !qphy->rx2) {
3770
+			dev_warn(dev,
3771
+				 "Underspecified device tree, falling back to legacy register regions\n");
3772
+
3773
+			/* In the old version, pcs_misc is at index 3. */
3774
+			qphy->pcs_misc = qphy->tx2;
3775
+			qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
3776
+			qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
3777
+
3778
+		} else {
3779
+			qphy->pcs_misc = of_iomap(np, 5);
3780
+		}
3781
+
3782
+	} else {
3783
+		qphy->pcs_misc = of_iomap(np, 3);
3784
+	}
3785
+
14603786 	if (!qphy->pcs_misc)
14613787 		dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
14623788 
....@@ -1468,10 +3794,10 @@
14683794 	 * all phys that don't need this.
14693795 	 */
14703796 	snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
1471
-	qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
3797
+	qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
14723798 	if (IS_ERR(qphy->pipe_clk)) {
1473
-		if (qmp->cfg->type == PHY_TYPE_PCIE ||
1474
-		    qmp->cfg->type == PHY_TYPE_USB3) {
3799
+		if (cfg->type == PHY_TYPE_PCIE ||
3800
+		    cfg->type == PHY_TYPE_USB3) {
14753801 			ret = PTR_ERR(qphy->pipe_clk);
14763802 			if (ret != -EPROBE_DEFER)
14773803 				dev_err(dev,
....@@ -1483,16 +3809,27 @@
14833809 	}
14843810 
14853811 	/* Get lane reset, if any */
1486
-	if (qmp->cfg->has_lane_rst) {
3812
+	if (cfg->has_lane_rst) {
14873813 		snprintf(prop_name, sizeof(prop_name), "lane%d", id);
14883814 		qphy->lane_rst = of_reset_control_get(np, prop_name);
14893815 		if (IS_ERR(qphy->lane_rst)) {
14903816 			dev_err(dev, "failed to get lane%d reset\n", id);
14913817 			return PTR_ERR(qphy->lane_rst);
14923818 		}
3819
+		ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
3820
+					       qphy->lane_rst);
3821
+		if (ret)
3822
+			return ret;
14933823 	}
14943824 
1495
-	generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops);
3825
+	if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
3826
+		ops = &qcom_qmp_pcie_ufs_ops;
3827
+	else if (cfg->type == PHY_TYPE_DP)
3828
+		ops = &qcom_qmp_phy_dp_ops;
3829
+	else
3830
+		ops = &qcom_qmp_phy_gen_ops;
3831
+
3832
+	generic_phy = devm_phy_create(dev, np, ops);
14963833 	if (IS_ERR(generic_phy)) {
14973834 		ret = PTR_ERR(generic_phy);
14983835 		dev_err(dev, "failed to create qphy %d\n", ret);
....@@ -1510,24 +3847,80 @@
15103847 
15113848 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
15123849 	{
3850
+		.compatible = "qcom,ipq8074-qmp-usb3-phy",
3851
+		.data = &ipq8074_usb3phy_cfg,
3852
+	}, {
15133853 		.compatible = "qcom,msm8996-qmp-pcie-phy",
15143854 		.data = &msm8996_pciephy_cfg,
3855
+	}, {
3856
+		.compatible = "qcom,msm8996-qmp-ufs-phy",
3857
+		.data = &msm8996_ufs_cfg,
15153858 	}, {
15163859 		.compatible = "qcom,msm8996-qmp-usb3-phy",
15173860 		.data = &msm8996_usb3phy_cfg,
15183861 	}, {
3862
+		.compatible = "qcom,msm8998-qmp-pcie-phy",
3863
+		.data = &msm8998_pciephy_cfg,
3864
+	}, {
3865
+		.compatible = "qcom,msm8998-qmp-ufs-phy",
3866
+		.data = &sdm845_ufsphy_cfg,
3867
+	}, {
15193868 		.compatible = "qcom,ipq8074-qmp-pcie-phy",
15203869 		.data = &ipq8074_pciephy_cfg,
3870
+	}, {
3871
+		.compatible = "qcom,sc7180-qmp-usb3-phy",
3872
+		.data = &sc7180_usb3phy_cfg,
3873
+	}, {
3874
+		.compatible = "qcom,sc7180-qmp-usb3-dp-phy",
3875
+		/* It's a combo phy */
3876
+	}, {
3877
+		.compatible = "qcom,sdm845-qhp-pcie-phy",
3878
+		.data = &sdm845_qhp_pciephy_cfg,
3879
+	}, {
3880
+		.compatible = "qcom,sdm845-qmp-pcie-phy",
3881
+		.data = &sdm845_qmp_pciephy_cfg,
15213882 	}, {
15223883 		.compatible = "qcom,sdm845-qmp-usb3-phy",
15233884 		.data = &qmp_v3_usb3phy_cfg,
15243885 	}, {
15253886 		.compatible = "qcom,sdm845-qmp-usb3-uni-phy",
15263887 		.data = &qmp_v3_usb3_uniphy_cfg,
3888
+	}, {
3889
+		.compatible = "qcom,sdm845-qmp-ufs-phy",
3890
+		.data = &sdm845_ufsphy_cfg,
3891
+	}, {
3892
+		.compatible = "qcom,msm8998-qmp-usb3-phy",
3893
+		.data = &msm8998_usb3phy_cfg,
3894
+	}, {
3895
+		.compatible = "qcom,sm8150-qmp-ufs-phy",
3896
+		.data = &sm8150_ufsphy_cfg,
3897
+	}, {
3898
+		.compatible = "qcom,sm8250-qmp-ufs-phy",
3899
+		.data = &sm8150_ufsphy_cfg,
3900
+	}, {
3901
+		.compatible = "qcom,sm8150-qmp-usb3-phy",
3902
+		.data = &sm8150_usb3phy_cfg,
3903
+	}, {
3904
+		.compatible = "qcom,sm8150-qmp-usb3-uni-phy",
3905
+		.data = &sm8150_usb3_uniphy_cfg,
3906
+	}, {
3907
+		.compatible = "qcom,sm8250-qmp-usb3-phy",
3908
+		.data = &sm8250_usb3phy_cfg,
3909
+	}, {
3910
+		.compatible = "qcom,sm8250-qmp-usb3-uni-phy",
3911
+		.data = &sm8250_usb3_uniphy_cfg,
15273912 	},
15283913 	{ },
15293914 };
15303915 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
3916
+
3917
+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
3918
+	{
3919
+		.compatible = "qcom,sc7180-qmp-usb3-dp-phy",
3920
+		.data = &sc7180_usb3dpphy_cfg,
3921
+	},
3922
+	{ }
3923
+};
15313924 
15323925 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
15333926 	SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
....@@ -1538,11 +3931,16 @@
15383931 {
15393932 	struct qcom_qmp *qmp;
15403933 	struct device *dev = &pdev->dev;
1541
-	struct resource *res;
15423934 	struct device_node *child;
15433935 	struct phy_provider *phy_provider;
1544
-	void __iomem *base;
1545
-	int num, id;
3936
+	void __iomem *serdes;
3937
+	void __iomem *usb_serdes;
3938
+	void __iomem *dp_serdes = NULL;
3939
+	const struct qmp_phy_combo_cfg *combo_cfg = NULL;
3940
+	const struct qmp_phy_cfg *cfg = NULL;
3941
+	const struct qmp_phy_cfg *usb_cfg = NULL;
3942
+	const struct qmp_phy_cfg *dp_cfg = NULL;
3943
+	int num, id, expected_phys;
15463944 	int ret;
15473945 
15483946 	qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
....@@ -1553,55 +3951,73 @@
15533951 	dev_set_drvdata(dev, qmp);
15543952 
15553953 	/* Get the specific init parameters of QMP phy */
1556
-	qmp->cfg = of_device_get_match_data(dev);
1557
-	if (!qmp->cfg)
1558
-		return -EINVAL;
3954
+	cfg = of_device_get_match_data(dev);
3955
+	if (!cfg) {
3956
+		const struct of_device_id *match;
15593957 
1560
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1561
-	base = devm_ioremap_resource(dev, res);
1562
-	if (IS_ERR(base))
1563
-		return PTR_ERR(base);
3958
+		match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
3959
+		if (!match)
3960
+			return -EINVAL;
3961
+
3962
+		combo_cfg = match->data;
3963
+		if (!combo_cfg)
3964
+			return -EINVAL;
3965
+
3966
+		usb_cfg = combo_cfg->usb_cfg;
3967
+		cfg = usb_cfg; /* Setup clks and regulators */
3968
+	}
15643969 
15653970 	/* per PHY serdes; usually located at base address */
1566
-	qmp->serdes = base;
3971
+	usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
3972
+	if (IS_ERR(serdes))
3973
+		return PTR_ERR(serdes);
15673974 
15683975 	/* per PHY dp_com; if PHY has dp_com control block */
1569
-	if (qmp->cfg->has_phy_dp_com_ctrl) {
1570
-		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1571
-						   "dp_com");
1572
-		base = devm_ioremap_resource(dev, res);
1573
-		if (IS_ERR(base))
1574
-			return PTR_ERR(base);
3976
+	if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
3977
+		qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
3978
+		if (IS_ERR(qmp->dp_com))
3979
+			return PTR_ERR(qmp->dp_com);
3980
+	}
15753981 
1576
-		qmp->dp_com = base;
3982
+	if (combo_cfg) {
3983
+		/* Only two serdes for combo PHY */
3984
+		dp_serdes = devm_platform_ioremap_resource(pdev, 2);
3985
+		if (IS_ERR(dp_serdes))
3986
+			return PTR_ERR(dp_serdes);
3987
+
3988
+		dp_cfg = combo_cfg->dp_cfg;
3989
+		expected_phys = 2;
3990
+	} else {
3991
+		expected_phys = cfg->nlanes;
15773992 	}
15783993 
15793994 	mutex_init(&qmp->phy_mutex);
15803995 
1581
-	ret = qcom_qmp_phy_clk_init(dev);
3996
+	ret = qcom_qmp_phy_clk_init(dev, cfg);
15823997 	if (ret)
15833998 		return ret;
15843999 
1585
-	ret = qcom_qmp_phy_reset_init(dev);
4000
+	ret = qcom_qmp_phy_reset_init(dev, cfg);
15864001 	if (ret)
15874002 		return ret;
15884003 
1589
-	ret = qcom_qmp_phy_vreg_init(dev);
4004
+	ret = qcom_qmp_phy_vreg_init(dev, cfg);
15904005 	if (ret) {
1591
-		dev_err(dev, "failed to get regulator supplies\n");
4006
+		if (ret != -EPROBE_DEFER)
4007
+			dev_err(dev, "failed to get regulator supplies: %d\n",
4008
+				ret);
15924009 		return ret;
15934010 	}
15944011 
15954012 	num = of_get_available_child_count(dev->of_node);
15964013 	/* do we have a rogue child node ? */
1597
-	if (num > qmp->cfg->nlanes)
4014
+	if (num > expected_phys)
15984015 		return -EINVAL;
15994016 
16004017 	qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
16014018 	if (!qmp->phys)
16024019 		return -ENOMEM;
16034020 
1604
-	id = 0;
16054021 	pm_runtime_set_active(dev);
16064022 	pm_runtime_enable(dev);
16074023 	/*
....@@ -1610,26 +4026,42 @@
16104026 	 */
16114027 	pm_runtime_forbid(dev);
16124028 
4029
+	id = 0;
16134030 	for_each_available_child_of_node(dev->of_node, child) {
4031
+		if (of_node_name_eq(child, "dp-phy")) {
4032
+			cfg = dp_cfg;
4033
+			serdes = dp_serdes;
4034
+		} else if (of_node_name_eq(child, "usb3-phy")) {
4035
+			cfg = usb_cfg;
4036
+			serdes = usb_serdes;
4037
+		}
4038
+
16144039 		/* Create per-lane phy */
1615
-		ret = qcom_qmp_phy_create(dev, child, id);
4040
+		ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
16164041 		if (ret) {
16174042 			dev_err(dev, "failed to create lane%d phy, %d\n",
16184043 				id, ret);
1619
-			pm_runtime_disable(dev);
1620
-			return ret;
4044
+			goto err_node_put;
16214045 		}
16224046 
16234047 		/*
16244048 		 * Register the pipe clock provided by phy.
16254049 		 * See function description to see details of this pipe clock.
16264050 		 */
1627
-		ret = phy_pipe_clk_register(qmp, child);
1628
-		if (ret) {
1629
-			dev_err(qmp->dev,
1630
-				"failed to register pipe clock source\n");
1631
-			pm_runtime_disable(dev);
1632
-			return ret;
4051
+		if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
4052
+			ret = phy_pipe_clk_register(qmp, child);
4053
+			if (ret) {
4054
+				dev_err(qmp->dev,
4055
+					"failed to register pipe clock source\n");
4056
+				goto err_node_put;
4057
+			}
4058
+		} else if (cfg->type == PHY_TYPE_DP) {
4059
+			ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
4060
+			if (ret) {
4061
+				dev_err(qmp->dev,
4062
+					"failed to register DP clock source\n");
4063
+				goto err_node_put;
4064
+			}
16334065 		}
16344066 		id++;
16354067 	}
....@@ -1641,6 +4073,11 @@
16414073 		pm_runtime_disable(dev);
16424074 
16434075 	return PTR_ERR_OR_ZERO(phy_provider);
4076
+
4077
+err_node_put:
4078
+	pm_runtime_disable(dev);
4079
+	of_node_put(child);
4080
+	return ret;
16444081 }
16454082 
16464083 static struct platform_driver qcom_qmp_phy_driver = {