add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/perf/Kconfig
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+# SPDX-License-Identifier: GPL-2.0-only
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 #
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 # Performance Monitor Drivers
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 #
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 	  PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
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 	  interconnect.
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+config ARM_CMN
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+	tristate "Arm CMN-600 PMU support"
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+	depends on ARM64 || (COMPILE_TEST && 64BIT)
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+	help
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+	  Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
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+	  Network interconnect.
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+
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 config ARM_PMU
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 	depends on ARM || ARM64
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 	bool "ARM PMU framework"
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 	depends on ARM_PMU && ACPI
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 	def_bool y
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+config ARM_SMMU_V3_PMU
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+	 tristate "ARM SMMUv3 Performance Monitors Extension"
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+	 depends on ARM64 && ACPI && ARM_SMMU_V3
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+	   help
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+	   Provides support for the ARM SMMUv3 Performance Monitor Counter
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+	   Groups (PMCG), which provide monitoring of transactions passing
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+	   through the SMMU and allow the resulting information to be filtered
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+	   based on the Stream ID of the corresponding master.
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+
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 config ARM_DSU_PMU
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 	tristate "ARM DynamIQ Shared Unit (DSU) PMU"
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 	depends on ARM64
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 	  system, control logic. The PMU allows counting various events related
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 	  to DSU.
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-config HISI_PMU
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-       bool "HiSilicon SoC PMU"
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-       depends on ARM64 && ACPI
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-       help
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-         Support for HiSilicon SoC uncore performance monitoring
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-         unit (PMU), such as: L3C, HHA and DDRC.
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+config FSL_IMX8_DDR_PMU
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+	tristate "Freescale i.MX8 DDR perf monitor"
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+	depends on ARCH_MXC
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+	  help
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+	  Provides support for the DDR performance monitor in i.MX8, which
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+	  can give information about memory throughput and other related
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+	  events.
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 config QCOM_L2_PMU
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 	bool "Qualcomm Technologies L2-cache PMU"
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 	depends on ARCH_QCOM && ARM64 && ACPI
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+	select QCOM_KRYO_L2_ACCESSORS
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 	  help
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 	  Provides support for the L2 cache performance monitor unit (PMU)
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 	  in Qualcomm Technologies processors.
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 	   Adds the L3 cache PMU into the perf events subsystem for
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 	   monitoring L3 cache events.
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+config THUNDERX2_PMU
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+	tristate "Cavium ThunderX2 SoC PMU UNCORE"
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+	depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
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+	default m
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+	help
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+	   Provides support for ThunderX2 UNCORE events.
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+	   The SoC has PMU support in its L3 cache controller (L3C) and
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+	   in the DDR4 Memory Controller (DMC).
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+
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 config XGENE_PMU
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         depends on ARCH_XGENE
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         bool "APM X-Gene SoC PMU"
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 	  Extension, which provides periodic sampling of operations in
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 	  the CPU pipeline and reports this via the perf AUX interface.
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+source "drivers/perf/hisilicon/Kconfig"
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+
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 endmenu