forked from ~ljy/RK356X_SDK_RELEASE

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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/pci/probe.c
....@@ -7,6 +7,7 @@
77 #include <linux/delay.h>
88 #include <linux/init.h>
99 #include <linux/pci.h>
10
+#include <linux/msi.h>
1011 #include <linux/of_device.h>
1112 #include <linux/of_pci.h>
1213 #include <linux/pci_hotplug.h>
....@@ -64,11 +65,6 @@
6465 	return &r->res;
6566 }
6667 
67
-static int find_anything(struct device *dev, void *data)
68
-{
69
-	return 1;
70
-}
71
-
7268 /*
7369  * Some device drivers need know if PCI is initiated.
7470  * Basically, we think PCI is not initiated when there
....@@ -79,7 +75,7 @@
7975 	struct device *dev;
8076 	int no_devices;
8177 
82
-	dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
78
+	dev = bus_find_next_device(&pci_bus_type, NULL);
8379 	no_devices = (dev == NULL);
8480 	put_device(dev);
8581 	return no_devices;
....@@ -121,13 +117,13 @@
121117 	 * Get the lowest of them to find the decode size, and from that
122118 	 * the extent.
123119 	 */
124
-	size = (size & ~(size-1)) - 1;
120
+	size = size & ~(size-1);
125121 
126122 	/*
127123 	 * base == maxbase can be valid only if the BAR has already been
128124 	 * programmed with all 1s.
129125 	 */
130
-	if (base == maxbase && ((base | size) & mask) != mask)
126
+	if (base == maxbase && ((base | (size - 1)) & mask) != mask)
131127 		return 0;
132128 
133129 	return size;
....@@ -278,7 +274,7 @@
278274 			/* Above 32-bit boundary; try to reallocate */
279275 			res->flags |= IORESOURCE_UNSET;
280276 			res->start = 0;
281
-			res->end = sz64;
277
+			res->end = sz64 - 1;
282278 			pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
283279 				 pos, (unsigned long long)l64);
284280 			goto out;
....@@ -286,7 +282,7 @@
286282 	}
287283 
288284 	region.start = l64;
289
-	region.end = l64 + sz64;
285
+	region.end = l64 + sz64 - 1;
290286 
291287 	pcibios_bus_to_resource(dev->bus, res, &region);
292288 	pcibios_resource_to_bus(dev->bus, &inverted_region, res);
....@@ -317,7 +313,7 @@
317313 	res->flags = 0;
318314 out:
319315 	if (res->flags)
320
-		pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res);
316
+		pci_info(dev, "reg 0x%x: %pR\n", pos, res);
321317 
322318 	return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
323319 }
....@@ -345,6 +341,57 @@
345341 		res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
346342 				IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
347343 		__pci_read_base(dev, pci_bar_mem32, res, rom);
344
+	}
345
+}
346
+
347
+static void pci_read_bridge_windows(struct pci_dev *bridge)
348
+{
349
+	u16 io;
350
+	u32 pmem, tmp;
351
+
352
+	pci_read_config_word(bridge, PCI_IO_BASE, &io);
353
+	if (!io) {
354
+		pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
355
+		pci_read_config_word(bridge, PCI_IO_BASE, &io);
356
+		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
357
+	}
358
+	if (io)
359
+		bridge->io_window = 1;
360
+
361
+	/*
362
+	 * DECchip 21050 pass 2 errata: the bridge may miss an address
363
+	 * disconnect boundary by one PCI data phase.  Workaround: do not
364
+	 * use prefetching on this device.
365
+	 */
366
+	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
367
+		return;
368
+
369
+	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
370
+	if (!pmem) {
371
+		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
372
+					       0xffe0fff0);
373
+		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374
+		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
375
+	}
376
+	if (!pmem)
377
+		return;
378
+
379
+	bridge->pref_window = 1;
380
+
381
+	if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
382
+
383
+		/*
384
+		 * Bridge claims to have a 64-bit prefetchable memory
385
+		 * window; verify that the upper bits are actually
386
+		 * writable.
387
+		 */
388
+		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
389
+		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
390
+				       0xffffffff);
391
+		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
392
+		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
393
+		if (tmp)
394
+			bridge->pref_64_window = 1;
348395 	}
349396 }
350397 
....@@ -384,7 +431,7 @@
384431 		region.start = base;
385432 		region.end = limit + io_granularity - 1;
386433 		pcibios_bus_to_resource(dev->bus, res, &region);
387
-		pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
434
+		pci_info(dev, "  bridge window %pR\n", res);
388435 	}
389436 }
390437 
....@@ -406,7 +453,7 @@
406453 		region.start = base;
407454 		region.end = limit + 0xfffff;
408455 		pcibios_bus_to_resource(dev->bus, res, &region);
409
-		pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
456
+		pci_info(dev, "  bridge window %pR\n", res);
410457 	}
411458 }
412459 
....@@ -459,7 +506,7 @@
459506 		region.start = base;
460507 		region.end = limit + 0xfffff;
461508 		pcibios_bus_to_resource(dev->bus, res, &region);
462
-		pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
509
+		pci_info(dev, "  bridge window %pR\n", res);
463510 	}
464511 }
465512 
....@@ -489,8 +536,7 @@
489536 			if (res && res->flags) {
490537 				pci_bus_add_resource(child, res,
491538 						     PCI_SUBTRACTIVE_DECODE);
492
-				pci_printk(KERN_DEBUG, dev,
493
-					   "  bridge window %pR (subtractive decode)\n",
539
+				pci_info(dev, "  bridge window %pR (subtractive decode)\n",
494540 					   res);
495541 			}
496542 		}
....@@ -519,7 +565,7 @@
519565 	return b;
520566 }
521567 
522
-static void devm_pci_release_host_bridge_dev(struct device *dev)
568
+static void pci_release_host_bridge_dev(struct device *dev)
523569 {
524570 	struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
525571 
....@@ -527,17 +573,14 @@
527573 		bridge->release_fn(bridge);
528574 
529575 	pci_free_resource_list(&bridge->windows);
530
-}
531
-
532
-static void pci_release_host_bridge_dev(struct device *dev)
533
-{
534
-	devm_pci_release_host_bridge_dev(dev);
535
-	kfree(to_pci_host_bridge(dev));
576
+	pci_free_resource_list(&bridge->dma_ranges);
577
+	kfree(bridge);
536578 }
537579 
538580 static void pci_init_host_bridge(struct pci_host_bridge *bridge)
539581 {
540582 	INIT_LIST_HEAD(&bridge->windows);
583
+	INIT_LIST_HEAD(&bridge->dma_ranges);
541584 
542585 	/*
543586 	 * We assume we can manage these PCIe features.  Some systems may
....@@ -550,6 +593,9 @@
550593 	bridge->native_shpc_hotplug = 1;
551594 	bridge->native_pme = 1;
552595 	bridge->native_ltr = 1;
596
+	bridge->native_dpc = 1;
597
+
598
+	device_initialize(&bridge->dev);
553599 }
554600 
555601 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
....@@ -567,17 +613,31 @@
567613 }
568614 EXPORT_SYMBOL(pci_alloc_host_bridge);
569615 
616
+static void devm_pci_alloc_host_bridge_release(void *data)
617
+{
618
+	pci_free_host_bridge(data);
619
+}
620
+
570621 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
571622 						   size_t priv)
572623 {
624
+	int ret;
573625 	struct pci_host_bridge *bridge;
574626 
575
-	bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
627
+	bridge = pci_alloc_host_bridge(priv);
576628 	if (!bridge)
577629 		return NULL;
578630 
579
-	pci_init_host_bridge(bridge);
580
-	bridge->dev.release = devm_pci_release_host_bridge_dev;
631
+	bridge->dev.parent = dev;
632
+
633
+	ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
634
+				       bridge);
635
+	if (ret)
636
+		return NULL;
637
+
638
+	ret = devm_of_pci_bridge_init(dev, bridge);
639
+	if (ret)
640
+		return NULL;
581641 
582642 	return bridge;
583643 }
....@@ -585,12 +645,11 @@
585645 
586646 void pci_free_host_bridge(struct pci_host_bridge *bridge)
587647 {
588
-	pci_free_resource_list(&bridge->windows);
589
-
590
-	kfree(bridge);
648
+	put_device(&bridge->dev);
591649 }
592650 EXPORT_SYMBOL(pci_free_host_bridge);
593651 
652
+/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
594653 static const unsigned char pcix_bus_speed[] = {
595654 	PCI_SPEED_UNKNOWN,		/* 0 */
596655 	PCI_SPEED_66MHz_PCIX,		/* 1 */
....@@ -610,13 +669,14 @@
610669 	PCI_SPEED_133MHz_PCIX_533	/* F */
611670 };
612671 
672
+/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
613673 const unsigned char pcie_link_speed[] = {
614674 	PCI_SPEED_UNKNOWN,		/* 0 */
615675 	PCIE_SPEED_2_5GT,		/* 1 */
616676 	PCIE_SPEED_5_0GT,		/* 2 */
617677 	PCIE_SPEED_8_0GT,		/* 3 */
618678 	PCIE_SPEED_16_0GT,		/* 4 */
619
-	PCI_SPEED_UNKNOWN,		/* 5 */
679
+	PCIE_SPEED_32_0GT,		/* 5 */
620680 	PCI_SPEED_UNKNOWN,		/* 6 */
621681 	PCI_SPEED_UNKNOWN,		/* 7 */
622682 	PCI_SPEED_UNKNOWN,		/* 8 */
....@@ -628,6 +688,44 @@
628688 	PCI_SPEED_UNKNOWN,		/* E */
629689 	PCI_SPEED_UNKNOWN		/* F */
630690 };
691
+EXPORT_SYMBOL_GPL(pcie_link_speed);
692
+
693
+const char *pci_speed_string(enum pci_bus_speed speed)
694
+{
695
+	/* Indexed by the pci_bus_speed enum */
696
+	static const char *speed_strings[] = {
697
+	    "33 MHz PCI",		/* 0x00 */
698
+	    "66 MHz PCI",		/* 0x01 */
699
+	    "66 MHz PCI-X",		/* 0x02 */
700
+	    "100 MHz PCI-X",		/* 0x03 */
701
+	    "133 MHz PCI-X",		/* 0x04 */
702
+	    NULL,			/* 0x05 */
703
+	    NULL,			/* 0x06 */
704
+	    NULL,			/* 0x07 */
705
+	    NULL,			/* 0x08 */
706
+	    "66 MHz PCI-X 266",		/* 0x09 */
707
+	    "100 MHz PCI-X 266",	/* 0x0a */
708
+	    "133 MHz PCI-X 266",	/* 0x0b */
709
+	    "Unknown AGP",		/* 0x0c */
710
+	    "1x AGP",			/* 0x0d */
711
+	    "2x AGP",			/* 0x0e */
712
+	    "4x AGP",			/* 0x0f */
713
+	    "8x AGP",			/* 0x10 */
714
+	    "66 MHz PCI-X 533",		/* 0x11 */
715
+	    "100 MHz PCI-X 533",	/* 0x12 */
716
+	    "133 MHz PCI-X 533",	/* 0x13 */
717
+	    "2.5 GT/s PCIe",		/* 0x14 */
718
+	    "5.0 GT/s PCIe",		/* 0x15 */
719
+	    "8.0 GT/s PCIe",		/* 0x16 */
720
+	    "16.0 GT/s PCIe",		/* 0x17 */
721
+	    "32.0 GT/s PCIe",		/* 0x18 */
722
+	};
723
+
724
+	if (speed < ARRAY_SIZE(speed_strings))
725
+		return speed_strings[speed];
726
+	return "Unknown";
727
+}
728
+EXPORT_SYMBOL_GPL(pci_speed_string);
631729 
632730 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
633731 {
....@@ -718,6 +816,7 @@
718816 
719817 		pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
720818 		bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
819
+		bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
721820 
722821 		pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
723822 		pcie_update_link_speed(bus, linksta);
....@@ -817,7 +916,7 @@
817916 	if (err)
818917 		goto free;
819918 
820
-	err = device_register(&bridge->dev);
919
+	err = device_add(&bridge->dev);
821920 	if (err) {
822921 		put_device(&bridge->dev);
823922 		goto free;
....@@ -842,6 +941,12 @@
842941 
843942 	pcibios_add_bus(bus);
844943 
944
+	if (bus->ops->add_bus) {
945
+		err = bus->ops->add_bus(bus);
946
+		if (WARN_ON(err < 0))
947
+			dev_err(&bus->dev, "failed to add bus: %d\n", err);
948
+	}
949
+
845950 	/* Create legacy_io and legacy_mem files for this bus */
846951 	pci_create_legacy_files(bus);
847952 
....@@ -849,6 +954,9 @@
849954 		dev_info(parent, "PCI host bridge to bus %s\n", name);
850955 	else
851956 		pr_info("PCI host bridge to bus %s\n", name);
957
+
958
+	if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
959
+		dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
852960 
853961 	/* Add initial resources to the bus */
854962 	resource_list_for_each_entry_safe(window, n, &resources) {
....@@ -884,7 +992,7 @@
884992 
885993 unregister:
886994 	put_device(&bridge->dev);
887
-	device_unregister(&bridge->dev);
995
+	device_del(&bridge->dev);
888996 
889997 free:
890998 	kfree(bus);
....@@ -934,6 +1042,7 @@
9341042 					   struct pci_dev *bridge, int busnr)
9351043 {
9361044 	struct pci_bus *child;
1045
+	struct pci_host_bridge *host;
9371046 	int i;
9381047 	int ret;
9391048 
....@@ -943,10 +1052,15 @@
9431052 		return NULL;
9441053 
9451054 	child->parent = parent;
946
-	child->ops = parent->ops;
9471055 	child->msi = parent->msi;
9481056 	child->sysdata = parent->sysdata;
9491057 	child->bus_flags = parent->bus_flags;
1058
+
1059
+	host = pci_find_host_bridge(parent);
1060
+	if (host->child_ops)
1061
+		child->ops = host->child_ops;
1062
+	else
1063
+		child->ops = parent->ops;
9501064 
9511065 	/*
9521066 	 * Initialize some portions of the bus device, but don't register
....@@ -1035,6 +1149,42 @@
10351149 
10361150 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
10371151 					      unsigned int available_buses);
1152
+/**
1153
+ * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1154
+ * numbers from EA capability.
1155
+ * @dev: Bridge
1156
+ * @sec: updated with secondary bus number from EA
1157
+ * @sub: updated with subordinate bus number from EA
1158
+ *
1159
+ * If @dev is a bridge with EA capability that specifies valid secondary
1160
+ * and subordinate bus numbers, return true with the bus numbers in @sec
1161
+ * and @sub.  Otherwise return false.
1162
+ */
1163
+static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1164
+{
1165
+	int ea, offset;
1166
+	u32 dw;
1167
+	u8 ea_sec, ea_sub;
1168
+
1169
+	if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1170
+		return false;
1171
+
1172
+	/* find PCI EA capability in list */
1173
+	ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1174
+	if (!ea)
1175
+		return false;
1176
+
1177
+	offset = ea + PCI_EA_FIRST_ENT;
1178
+	pci_read_config_dword(dev, offset, &dw);
1179
+	ea_sec =  dw & PCI_EA_SEC_BUS_MASK;
1180
+	ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1181
+	if (ea_sec  == 0 || ea_sub < ea_sec)
1182
+		return false;
1183
+
1184
+	*sec = ea_sec;
1185
+	*sub = ea_sub;
1186
+	return true;
1187
+}
10381188 
10391189 /*
10401190  * pci_scan_bridge_extend() - Scan buses behind a bridge
....@@ -1069,6 +1219,9 @@
10691219 	u16 bctl;
10701220 	u8 primary, secondary, subordinate;
10711221 	int broken = 0;
1222
+	bool fixed_buses;
1223
+	u8 fixed_sec, fixed_sub;
1224
+	int next_busnr;
10721225 
10731226 	/*
10741227 	 * Make sure the bridge is powered on to be able to access config
....@@ -1168,17 +1321,24 @@
11681321 		/* Clear errors */
11691322 		pci_write_config_word(dev, PCI_STATUS, 0xffff);
11701323 
1324
+		/* Read bus numbers from EA Capability (if present) */
1325
+		fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1326
+		if (fixed_buses)
1327
+			next_busnr = fixed_sec;
1328
+		else
1329
+			next_busnr = max + 1;
1330
+
11711331 		/*
11721332 		 * Prevent assigning a bus number that already exists.
11731333 		 * This can happen when a bridge is hot-plugged, so in this
11741334 		 * case we only re-scan this bus.
11751335 		 */
1176
-		child = pci_find_bus(pci_domain_nr(bus), max+1);
1336
+		child = pci_find_bus(pci_domain_nr(bus), next_busnr);
11771337 		if (!child) {
1178
-			child = pci_add_new_bus(bus, dev, max+1);
1338
+			child = pci_add_new_bus(bus, dev, next_busnr);
11791339 			if (!child)
11801340 				goto out;
1181
-			pci_bus_insert_busn_res(child, max+1,
1341
+			pci_bus_insert_busn_res(child, next_busnr,
11821342 						bus->busn_res.end);
11831343 		}
11841344 		max++;
....@@ -1239,7 +1399,13 @@
12391399 			max += i;
12401400 		}
12411401 
1242
-		/* Set subordinate bus number to its real value */
1402
+		/*
1403
+		 * Set subordinate bus number to its real value.
1404
+		 * If fixed subordinate bus number exists from EA
1405
+		 * capability then use it.
1406
+		 */
1407
+		if (fixed_buses)
1408
+			max = fixed_sub;
12431409 		pci_bus_update_busn_res_end(child, max);
12441410 		pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
12451411 	}
....@@ -1333,26 +1499,38 @@
13331499 	pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
13341500 	pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
13351501 
1502
+	parent = pci_upstream_bridge(pdev);
1503
+	if (!parent)
1504
+		return;
1505
+
13361506 	/*
1337
-	 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1338
-	 * of a Link.  No PCIe component has two Links.  Two Links are
1339
-	 * connected by a Switch that has a Port on each Link and internal
1340
-	 * logic to connect the two Ports.
1507
+	 * Some systems do not identify their upstream/downstream ports
1508
+	 * correctly so detect impossible configurations here and correct
1509
+	 * the port type accordingly.
13411510 	 */
13421511 	type = pci_pcie_type(pdev);
1343
-	if (type == PCI_EXP_TYPE_ROOT_PORT ||
1344
-	    type == PCI_EXP_TYPE_PCIE_BRIDGE)
1345
-		pdev->has_secondary_link = 1;
1346
-	else if (type == PCI_EXP_TYPE_UPSTREAM ||
1347
-		 type == PCI_EXP_TYPE_DOWNSTREAM) {
1348
-		parent = pci_upstream_bridge(pdev);
1349
-
1512
+	if (type == PCI_EXP_TYPE_DOWNSTREAM) {
13501513 		/*
1351
-		 * Usually there's an upstream device (Root Port or Switch
1352
-		 * Downstream Port), but we can't assume one exists.
1514
+		 * If pdev claims to be downstream port but the parent
1515
+		 * device is also downstream port assume pdev is actually
1516
+		 * upstream port.
13531517 		 */
1354
-		if (parent && !parent->has_secondary_link)
1355
-			pdev->has_secondary_link = 1;
1518
+		if (pcie_downstream_port(parent)) {
1519
+			pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1520
+			pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1521
+			pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1522
+		}
1523
+	} else if (type == PCI_EXP_TYPE_UPSTREAM) {
1524
+		/*
1525
+		 * If pdev claims to be upstream port but the parent
1526
+		 * device is also upstream port assume pdev is actually
1527
+		 * downstream port.
1528
+		 */
1529
+		if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1530
+			pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1531
+			pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1532
+			pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1533
+		}
13561534 	}
13571535 }
13581536 
....@@ -1381,6 +1559,19 @@
13811559 			return;
13821560 		}
13831561 	}
1562
+}
1563
+
1564
+static void set_pcie_untrusted(struct pci_dev *dev)
1565
+{
1566
+	struct pci_dev *parent;
1567
+
1568
+	/*
1569
+	 * If the upstream bridge is untrusted we treat this device
1570
+	 * untrusted as well.
1571
+	 */
1572
+	parent = pci_upstream_bridge(dev);
1573
+	if (parent && (parent->untrusted || parent->external_facing))
1574
+		dev->untrusted = true;
13841575 }
13851576 
13861577 /**
....@@ -1449,6 +1640,21 @@
14491640 	int pos;
14501641 	u32 status;
14511642 	u16 class;
1643
+
1644
+#ifdef CONFIG_PCI_IOV
1645
+	/*
1646
+	 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1647
+	 * implement a PCIe capability and therefore must implement extended
1648
+	 * config space.  We can skip the NO_EXTCFG test below and the
1649
+	 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1650
+	 * the fact that the SR-IOV capability on the PF resides in extended
1651
+	 * config space and must be accessible and non-aliased to have enabled
1652
+	 * support for this VF.  This is a micro performance optimization for
1653
+	 * systems supporting many VFs.
1654
+	 */
1655
+	if (dev->is_virtfn)
1656
+		return PCI_CFG_SPACE_EXP_SIZE;
1657
+#endif
14521658 
14531659 	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
14541660 		return PCI_CFG_SPACE_SIZE;
....@@ -1614,9 +1820,6 @@
16141820 	dev->revision = class & 0xff;
16151821 	dev->class = class >> 8;		    /* upper 3 bytes */
16161822 
1617
-	pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
1618
-		   dev->vendor, dev->device, dev->hdr_type, dev->class);
1619
-
16201823 	if (pci_early_dump)
16211824 		early_dump_pci_device(dev);
16221825 
....@@ -1626,11 +1829,16 @@
16261829 	/* Need to have dev->cfg_size ready */
16271830 	set_pcie_thunderbolt(dev);
16281831 
1832
+	set_pcie_untrusted(dev);
1833
+
16291834 	/* "Unknown power state" */
16301835 	dev->current_state = PCI_UNKNOWN;
16311836 
16321837 	/* Early fixups, before probing the BARs */
16331838 	pci_fixup_device(pci_fixup_early, dev);
1839
+
1840
+	pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1841
+		 dev->vendor, dev->device, dev->hdr_type, dev->class);
16341842 
16351843 	/* Device class may be changed after fixup */
16361844 	class = dev->class >> 8;
....@@ -1701,9 +1909,6 @@
17011909 		break;
17021910 
17031911 	case PCI_HEADER_TYPE_BRIDGE:		    /* bridge header */
1704
-		if (class != PCI_CLASS_BRIDGE_PCI)
1705
-			goto bad;
1706
-
17071912 		/*
17081913 		 * The PCI-to-PCI bridge spec requires that subtractive
17091914 		 * decoding (i.e. transparent) bridge must have programming
....@@ -1712,6 +1917,7 @@
17121917 		pci_read_irq(dev);
17131918 		dev->transparent = ((dev->class & 0xff) == 1);
17141919 		pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1920
+		pci_read_bridge_windows(dev);
17151921 		set_pcie_hotplug_bridge(dev);
17161922 		pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
17171923 		if (pos) {
....@@ -1814,164 +2020,6 @@
18142020 		 p_mps, mps, mpss);
18152021 }
18162022 
1817
-static struct hpp_type0 pci_default_type0 = {
1818
-	.revision = 1,
1819
-	.cache_line_size = 8,
1820
-	.latency_timer = 0x40,
1821
-	.enable_serr = 0,
1822
-	.enable_perr = 0,
1823
-};
1824
-
1825
-static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1826
-{
1827
-	u16 pci_cmd, pci_bctl;
1828
-
1829
-	if (!hpp)
1830
-		hpp = &pci_default_type0;
1831
-
1832
-	if (hpp->revision > 1) {
1833
-		pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
1834
-			 hpp->revision);
1835
-		hpp = &pci_default_type0;
1836
-	}
1837
-
1838
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1839
-	pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1840
-	pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1841
-	if (hpp->enable_serr)
1842
-		pci_cmd |= PCI_COMMAND_SERR;
1843
-	if (hpp->enable_perr)
1844
-		pci_cmd |= PCI_COMMAND_PARITY;
1845
-	pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1846
-
1847
-	/* Program bridge control value */
1848
-	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1849
-		pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1850
-				      hpp->latency_timer);
1851
-		pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1852
-		if (hpp->enable_serr)
1853
-			pci_bctl |= PCI_BRIDGE_CTL_SERR;
1854
-		if (hpp->enable_perr)
1855
-			pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1856
-		pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1857
-	}
1858
-}
1859
-
1860
-static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1861
-{
1862
-	int pos;
1863
-
1864
-	if (!hpp)
1865
-		return;
1866
-
1867
-	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1868
-	if (!pos)
1869
-		return;
1870
-
1871
-	pci_warn(dev, "PCI-X settings not supported\n");
1872
-}
1873
-
1874
-static bool pcie_root_rcb_set(struct pci_dev *dev)
1875
-{
1876
-	struct pci_dev *rp = pcie_find_root_port(dev);
1877
-	u16 lnkctl;
1878
-
1879
-	if (!rp)
1880
-		return false;
1881
-
1882
-	pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1883
-	if (lnkctl & PCI_EXP_LNKCTL_RCB)
1884
-		return true;
1885
-
1886
-	return false;
1887
-}
1888
-
1889
-static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1890
-{
1891
-	int pos;
1892
-	u32 reg32;
1893
-
1894
-	if (!hpp)
1895
-		return;
1896
-
1897
-	if (!pci_is_pcie(dev))
1898
-		return;
1899
-
1900
-	if (hpp->revision > 1) {
1901
-		pci_warn(dev, "PCIe settings rev %d not supported\n",
1902
-			 hpp->revision);
1903
-		return;
1904
-	}
1905
-
1906
-	/*
1907
-	 * Don't allow _HPX to change MPS or MRRS settings.  We manage
1908
-	 * those to make sure they're consistent with the rest of the
1909
-	 * platform.
1910
-	 */
1911
-	hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1912
-				    PCI_EXP_DEVCTL_READRQ;
1913
-	hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1914
-				    PCI_EXP_DEVCTL_READRQ);
1915
-
1916
-	/* Initialize Device Control Register */
1917
-	pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1918
-			~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1919
-
1920
-	/* Initialize Link Control Register */
1921
-	if (pcie_cap_has_lnkctl(dev)) {
1922
-
1923
-		/*
1924
-		 * If the Root Port supports Read Completion Boundary of
1925
-		 * 128, set RCB to 128.  Otherwise, clear it.
1926
-		 */
1927
-		hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1928
-		hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1929
-		if (pcie_root_rcb_set(dev))
1930
-			hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1931
-
1932
-		pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1933
-			~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1934
-	}
1935
-
1936
-	/* Find Advanced Error Reporting Enhanced Capability */
1937
-	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1938
-	if (!pos)
1939
-		return;
1940
-
1941
-	/* Initialize Uncorrectable Error Mask Register */
1942
-	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1943
-	reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1944
-	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1945
-
1946
-	/* Initialize Uncorrectable Error Severity Register */
1947
-	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1948
-	reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1949
-	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1950
-
1951
-	/* Initialize Correctable Error Mask Register */
1952
-	pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1953
-	reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1954
-	pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1955
-
1956
-	/* Initialize Advanced Error Capabilities and Control Register */
1957
-	pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1958
-	reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1959
-
1960
-	/* Don't enable ECRC generation or checking if unsupported */
1961
-	if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
1962
-		reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
1963
-	if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
1964
-		reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
1965
-	pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1966
-
1967
-	/*
1968
-	 * FIXME: The following two registers are not supported yet.
1969
-	 *
1970
-	 *   o Secondary Uncorrectable Error Severity Register
1971
-	 *   o Secondary Uncorrectable Error Mask Register
1972
-	 */
1973
-}
1974
-
19752023 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
19762024 {
19772025 	struct pci_host_bridge *host;
....@@ -2049,7 +2097,7 @@
20492097 	 * For now, we only deal with Relaxed Ordering issues with Root
20502098 	 * Ports. Peer-to-Peer DMA is another can of worms.
20512099 	 */
2052
-	root = pci_find_pcie_root_port(dev);
2100
+	root = pcie_find_root_port(dev);
20532101 	if (!root)
20542102 		return;
20552103 
....@@ -2069,6 +2117,9 @@
20692117 
20702118 	if (!pci_is_pcie(dev))
20712119 		return;
2120
+
2121
+	/* Read L1 PM substate capabilities */
2122
+	dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
20722123 
20732124 	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
20742125 	if (!(cap & PCI_EXP_DEVCAP2_LTR))
....@@ -2132,25 +2183,34 @@
21322183 #endif
21332184 }
21342185 
2186
+static void pci_configure_serr(struct pci_dev *dev)
2187
+{
2188
+	u16 control;
2189
+
2190
+	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2191
+
2192
+		/*
2193
+		 * A bridge will not forward ERR_ messages coming from an
2194
+		 * endpoint unless SERR# forwarding is enabled.
2195
+		 */
2196
+		pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2197
+		if (!(control & PCI_BRIDGE_CTL_SERR)) {
2198
+			control |= PCI_BRIDGE_CTL_SERR;
2199
+			pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2200
+		}
2201
+	}
2202
+}
2203
+
21352204 static void pci_configure_device(struct pci_dev *dev)
21362205 {
2137
-	struct hotplug_params hpp;
2138
-	int ret;
2139
-
21402206 	pci_configure_mps(dev);
21412207 	pci_configure_extended_tags(dev, NULL);
21422208 	pci_configure_relaxed_ordering(dev);
21432209 	pci_configure_ltr(dev);
21442210 	pci_configure_eetlp_prefix(dev);
2211
+	pci_configure_serr(dev);
21452212 
2146
-	memset(&hpp, 0, sizeof(hpp));
2147
-	ret = pci_get_hp_params(dev, &hpp);
2148
-	if (ret)
2149
-		return;
2150
-
2151
-	program_hpp_type2(dev, hpp.t2);
2152
-	program_hpp_type1(dev, hpp.t1);
2153
-	program_hpp_type0(dev, hpp.t0);
2213
+	pci_acpi_program_hp_params(dev);
21542214 }
21552215 
21562216 static void pci_release_capabilities(struct pci_dev *dev)
....@@ -2179,7 +2239,7 @@
21792239 	pcibios_release_device(pci_dev);
21802240 	pci_bus_put(pci_dev->bus);
21812241 	kfree(pci_dev->driver_override);
2182
-	kfree(pci_dev->dma_alias_mask);
2242
+	bitmap_free(pci_dev->dma_alias_mask);
21832243 	kfree(pci_dev);
21842244 }
21852245 
....@@ -2316,7 +2376,7 @@
23162376 	return dev;
23172377 }
23182378 
2319
-static void pcie_report_downtraining(struct pci_dev *dev)
2379
+void pcie_report_downtraining(struct pci_dev *dev)
23202380 {
23212381 	if (!pci_is_pcie(dev))
23222382 		return;
....@@ -2337,8 +2397,7 @@
23372397 
23382398 static void pci_init_capabilities(struct pci_dev *dev)
23392399 {
2340
-	/* Enhanced Allocation */
2341
-	pci_ea_init(dev);
2400
+	pci_ea_init(dev);		/* Enhanced Allocation */
23422401 
23432402 	/* Setup MSI caps & disable MSI/MSI-X interrupts */
23442403 	pci_msi_setup_pci_dev(dev);
....@@ -2346,29 +2405,17 @@
23462405 	/* Buffers for saving PCIe and PCI-X capabilities */
23472406 	pci_allocate_cap_save_buffers(dev);
23482407 
2349
-	/* Power Management */
2350
-	pci_pm_init(dev);
2351
-
2352
-	/* Vital Product Data */
2353
-	pci_vpd_init(dev);
2354
-
2355
-	/* Alternative Routing-ID Forwarding */
2356
-	pci_configure_ari(dev);
2357
-
2358
-	/* Single Root I/O Virtualization */
2359
-	pci_iov_init(dev);
2360
-
2361
-	/* Address Translation Services */
2362
-	pci_ats_init(dev);
2363
-
2364
-	/* Enable ACS P2P upstream forwarding */
2365
-	pci_enable_acs(dev);
2366
-
2367
-	/* Precision Time Measurement */
2368
-	pci_ptm_init(dev);
2369
-
2370
-	/* Advanced Error Reporting */
2371
-	pci_aer_init(dev);
2408
+	pci_pm_init(dev);		/* Power Management */
2409
+	pci_vpd_init(dev);		/* Vital Product Data */
2410
+	pci_configure_ari(dev);		/* Alternative Routing-ID Forwarding */
2411
+	pci_iov_init(dev);		/* Single Root I/O Virtualization */
2412
+	pci_ats_init(dev);		/* Address Translation Services */
2413
+	pci_pri_init(dev);		/* Page Request Interface */
2414
+	pci_pasid_init(dev);		/* Process Address Space ID */
2415
+	pci_acs_init(dev);		/* Access Control Services */
2416
+	pci_ptm_init(dev);		/* Precision Time Measurement */
2417
+	pci_aer_init(dev);		/* Advanced Error Reporting */
2418
+	pci_dpc_init(dev);		/* Downstream Port Containment */
23722419 
23732420 	pcie_report_downtraining(dev);
23742421 
....@@ -2434,19 +2481,16 @@
24342481 	dev->dev.dma_parms = &dev->dma_parms;
24352482 	dev->dev.coherent_dma_mask = 0xffffffffull;
24362483 
2437
-	pci_set_dma_max_seg_size(dev, 65536);
2438
-	pci_set_dma_seg_boundary(dev, 0xffffffff);
2484
+	dma_set_max_seg_size(&dev->dev, 65536);
2485
+	dma_set_seg_boundary(&dev->dev, 0xffffffff);
24392486 
24402487 	/* Fix up broken headers */
24412488 	pci_fixup_device(pci_fixup_header, dev);
24422489 
2443
-	/* Moved out from quirk header fixup code */
24442490 	pci_reassigndev_resource_alignment(dev);
24452491 
2446
-	/* Clear the state_saved flag */
24472492 	dev->state_saved = false;
24482493 
2449
-	/* Initialize various capabilities */
24502494 	pci_init_capabilities(dev);
24512495 
24522496 	/*
....@@ -2532,12 +2576,8 @@
25322576 	 * A PCIe Downstream Port normally leads to a Link with only Device
25332577 	 * 0 on it (PCIe spec r3.1, sec 7.3.1).  As an optimization, scan
25342578 	 * only for Device 0 in that situation.
2535
-	 *
2536
-	 * Checking has_secondary_link is a hack to identify Downstream
2537
-	 * Ports because sometimes Switches are configured such that the
2538
-	 * PCIe Port Type labels are backwards.
25392579 	 */
2540
-	if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
2580
+	if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
25412581 		return 1;
25422582 
25432583 	return 0;
....@@ -2957,7 +2997,7 @@
29572997 	return bridge->bus;
29582998 
29592999 err_out:
2960
-	kfree(bridge);
3000
+	put_device(&bridge->dev);
29613001 	return NULL;
29623002 }
29633003 EXPORT_SYMBOL_GPL(pci_create_root_bus);
....@@ -3014,7 +3054,7 @@
30143054 	conflict = request_resource_conflict(parent_res, res);
30153055 
30163056 	if (conflict)
3017
-		dev_printk(KERN_DEBUG, &b->dev,
3057
+		dev_info(&b->dev,
30183058 			   "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
30193059 			    res, pci_is_root_bus(b) ? "domain " : "",
30203060 			    parent_res, conflict->name, conflict);
....@@ -3034,8 +3074,7 @@
30343074 
30353075 	size = bus_max - res->start + 1;
30363076 	ret = adjust_resource(res, res->start, size);
3037
-	dev_printk(KERN_DEBUG, &b->dev,
3038
-			"busn_res: %pR end %s updated to %02x\n",
3077
+	dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
30393078 			&old_res, ret ? "can not be" : "is", bus_max);
30403079 
30413080 	if (!ret && !res->parent)
....@@ -3053,8 +3092,7 @@
30533092 		return;
30543093 
30553094 	ret = release_resource(res);
3056
-	dev_printk(KERN_DEBUG, &b->dev,
3057
-			"busn_res: %pR %s released\n",
3095
+	dev_info(&b->dev, "busn_res: %pR %s released\n",
30583096 			res, ret ? "can not be" : "is");
30593097 }
30603098 
....@@ -3070,6 +3108,7 @@
30703108 
30713109 	resource_list_for_each_entry(window, &bridge->windows)
30723110 		if (window->res->flags & IORESOURCE_BUS) {
3111
+			bridge->busnr = window->res->start;
30733112 			found = true;
30743113 			break;
30753114 		}