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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/pci/pci.c
....@@ -164,9 +164,6 @@
164164 }
165165 __setup("pcie_port_pm=", pcie_port_pm_setup);
166166 
167
-/* Time to wait after a reset for device to become responsive */
168
-#define PCIE_RESET_READY_POLL_MS 60000
169
-
170167 /**
171168  * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
172169  * @bus: pointer to PCI bus structure to search
....@@ -1228,7 +1225,7 @@
12281225 			return -ENOTTY;
12291226 		}
12301227 
1231
-		if (delay > 1000)
1228
+		if (delay > PCI_RESET_WAIT)
12321229 			pci_info(dev, "not ready %dms after %s; waiting\n",
12331230 				 delay - 1, reset_type);
12341231 
....@@ -1237,7 +1234,7 @@
12371234 		pci_read_config_dword(dev, PCI_COMMAND, &id);
12381235 	}
12391236 
1240
-	if (delay > 1000)
1237
+	if (delay > PCI_RESET_WAIT)
12411238 		pci_info(dev, "ready %dms after %s\n", delay - 1,
12421239 			 reset_type);
12431240 
....@@ -2840,13 +2837,13 @@
28402837 	{
28412838 		/*
28422839 		 * Downstream device is not accessible after putting a root port
2843
-		 * into D3cold and back into D0 on Elo i2.
2840
+		 * into D3cold and back into D0 on Elo Continental Z2 board
28442841 		 */
2845
-		.ident = "Elo i2",
2842
+		.ident = "Elo Continental Z2",
28462843 		.matches = {
2847
-			DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"),
2848
-			DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"),
2849
-			DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"),
2844
+			DMI_MATCH(DMI_BOARD_VENDOR, "Elo Touch Solutions"),
2845
+			DMI_MATCH(DMI_BOARD_NAME, "Geminilake"),
2846
+			DMI_MATCH(DMI_BOARD_VERSION, "Continental Z2"),
28502847 		},
28512848 	},
28522849 #endif
....@@ -4799,24 +4796,31 @@
47994796 /**
48004797  * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
48014798  * @dev: PCI bridge
4799
+ * @reset_type: reset type in human-readable form
4800
+ * @timeout: maximum time to wait for devices on secondary bus (milliseconds)
48024801  *
48034802  * Handle necessary delays before access to the devices on the secondary
4804
- * side of the bridge are permitted after D3cold to D0 transition.
4803
+ * side of the bridge are permitted after D3cold to D0 transition
4804
+ * or Conventional Reset.
48054805  *
48064806  * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
48074807  * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
48084808  * 4.3.2.
4809
+ *
4810
+ * Return 0 on success or -ENOTTY if the first device on the secondary bus
4811
+ * failed to become accessible.
48094812  */
4810
-void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4813
+int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
4814
+				      int timeout)
48114815 {
48124816 	struct pci_dev *child;
48134817 	int delay;
48144818 
48154819 	if (pci_dev_is_disconnected(dev))
4816
-		return;
4820
+		return 0;
48174821 
4818
-	if (!pci_is_bridge(dev) || !dev->bridge_d3)
4819
-		return;
4822
+	if (!pci_is_bridge(dev))
4823
+		return 0;
48204824 
48214825 	down_read(&pci_bus_sem);
48224826 
....@@ -4828,14 +4832,14 @@
48284832 	 */
48294833 	if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
48304834 		up_read(&pci_bus_sem);
4831
-		return;
4835
+		return 0;
48324836 	}
48334837 
48344838 	/* Take d3cold_delay requirements into account */
48354839 	delay = pci_bus_max_d3cold_delay(dev->subordinate);
48364840 	if (!delay) {
48374841 		up_read(&pci_bus_sem);
4838
-		return;
4842
+		return 0;
48394843 	}
48404844 
48414845 	child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
....@@ -4844,14 +4848,12 @@
48444848 
48454849 	/*
48464850 	 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4847
-	 * accessing the device after reset (that is 1000 ms + 100 ms). In
4848
-	 * practice this should not be needed because we don't do power
4849
-	 * management for them (see pci_bridge_d3_possible()).
4851
+	 * accessing the device after reset (that is 1000 ms + 100 ms).
48504852 	 */
48514853 	if (!pci_is_pcie(dev)) {
48524854 		pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
48534855 		msleep(1000 + delay);
4854
-		return;
4856
+		return 0;
48554857 	}
48564858 
48574859 	/*
....@@ -4868,11 +4870,11 @@
48684870 	 * configuration requests if we only wait for 100 ms (see
48694871 	 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
48704872 	 *
4871
-	 * Therefore we wait for 100 ms and check for the device presence.
4872
-	 * If it is still not present give it an additional 100 ms.
4873
+	 * Therefore we wait for 100 ms and check for the device presence
4874
+	 * until the timeout expires.
48734875 	 */
48744876 	if (!pcie_downstream_port(dev))
4875
-		return;
4877
+		return 0;
48764878 
48774879 	if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
48784880 		pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
....@@ -4883,14 +4885,11 @@
48834885 		if (!pcie_wait_for_link_delay(dev, true, delay)) {
48844886 			/* Did not train, no need to wait any further */
48854887 			pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4886
-			return;
4888
+			return -ENOTTY;
48874889 		}
48884890 	}
48894891 
4890
-	if (!pci_device_is_present(child)) {
4891
-		pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
4892
-		msleep(delay);
4893
-	}
4892
+	return pci_dev_wait(child, reset_type, timeout - delay);
48944893 }
48954894 
48964895 void pci_reset_secondary_bus(struct pci_dev *dev)
....@@ -4909,15 +4908,6 @@
49094908 
49104909 	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
49114910 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4912
-
4913
-	/*
4914
-	 * Trhfa for conventional PCI is 2^25 clock cycles.
4915
-	 * Assuming a minimum 33MHz clock this results in a 1s
4916
-	 * delay before we can consider subordinate devices to
4917
-	 * be re-initialized.  PCIe has some ways to shorten this,
4918
-	 * but we don't make use of them yet.
4919
-	 */
4920
-	ssleep(1);
49214911 }
49224912 
49234913 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
....@@ -4936,7 +4926,8 @@
49364926 {
49374927 	pcibios_reset_secondary_bus(dev);
49384928 
4939
-	return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4929
+	return pci_bridge_wait_for_secondary_bus(dev, "bus reset",
4930
+						 PCIE_RESET_READY_POLL_MS);
49404931 }
49414932 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
49424933 
....@@ -6159,6 +6150,8 @@
61596150 {
61606151 	u32 v;
61616152 
6153
+	/* Check PF if pdev is a VF, since VF Vendor/Device IDs are 0xffff */
6154
+	pdev = pci_physfn(pdev);
61626155 	if (pci_dev_is_disconnected(pdev))
61636156 		return false;
61646157 	return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);