add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/pci/controller/pcie-rockchip.c
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@@ -14,7 +14,8 @@
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 #include <linux/clk.h>
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 #include <linux/delay.h>
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 #include <linux/gpio/consumer.h>
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-#include <linux/of_address.h>
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+#include <linux/iopoll.h>
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+#include <linux/module.h>
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 #include <linux/of_pci.h>
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 #include <linux/phy/phy.h>
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 #include <linux/platform_device.h>
..
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@@ -28,8 +29,6 @@
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 	struct device *dev = rockchip->dev;
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 	struct platform_device *pdev = to_platform_device(dev);
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 	struct device_node *node = dev->of_node;
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-	struct device_node *mem;
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-	struct resource reg;
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 	struct resource *regs;
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 	int err;
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..
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@@ -48,9 +47,8 @@
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 			return -EINVAL;
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 	}
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-	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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-					    "apb-base");
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-	rockchip->apb_base = devm_ioremap_resource(dev, regs);
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+	rockchip->apb_base =
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+		devm_platform_ioremap_resource_byname(pdev, "apb-base");
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 	if (IS_ERR(rockchip->apb_base))
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 		return PTR_ERR(rockchip->apb_base);
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..
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@@ -86,7 +84,7 @@
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 	}
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 	rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
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-								     "mgmt-sticky");
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+								"mgmt-sticky");
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 	if (IS_ERR(rockchip->mgmt_sticky_rst)) {
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 		if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
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 			dev_err(dev, "missing mgmt-sticky reset property in node\n");
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@@ -122,11 +120,11 @@
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 	}
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 	if (rockchip->is_rc) {
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-		rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep", GPIOD_OUT_HIGH);
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-		if (IS_ERR(rockchip->ep_gpio)) {
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-			dev_err(dev, "invalid ep-gpios property in node\n");
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-			return PTR_ERR(rockchip->ep_gpio);
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-		}
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+		rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
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+							    GPIOD_OUT_HIGH);
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+		if (IS_ERR(rockchip->ep_gpio))
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+			return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),
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+					     "failed to get ep GPIO\n");
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 	}
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 	rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
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@@ -153,41 +151,15 @@
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 		return PTR_ERR(rockchip->clk_pcie_pm);
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 	}
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-	if (rockchip->is_rc) {
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-		mem = of_parse_phandle(node, "memory-region", 0);
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-		if (!mem) {
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-			dev_warn(dev, "missing \"memory-region\" property\n");
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-			return 0;
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-		}
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-
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-		err = of_address_to_resource(mem, 0, &reg);
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-		if (err < 0) {
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-			dev_warn(dev, "missing \"reg\" property\n");
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-			return 0;
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-		}
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-
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-		rockchip->mem_reserve_start = reg.start;
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-		rockchip->mem_reserve_size = resource_size(&reg);
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-
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-		err = of_property_read_u32(node, "rockchip,dma_trx_enabled",
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-					   &rockchip->dma_trx_enabled);
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-		if (err < 0) {
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-			dev_warn(dev,
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-				"missing \"rockchip,dma_trx_enabled\" property\n");
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-			return 0;
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-		}
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-
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-		err = of_property_read_u32(node, "rockchip,deferred",
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-					&rockchip->deferred);
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-		if (err < 0) {
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-			dev_warn(dev, "missing \"rockchip,deferred\" property\n");
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-			return 0;
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-		}
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-	}
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-
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 	return 0;
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 }
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 EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
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+
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+#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr)
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+/* 100 ms max wait time for PHY PLLs to lock */
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+#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000
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+/* Sleep should be less than 20ms */
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+#define RK_PHY_PLL_LOCK_SLEEP_US 1000
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 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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 {
..
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@@ -288,6 +260,16 @@
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 			dev_err(dev, "power on phy%d err %d\n", i, err);
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 			goto err_power_off_phy;
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 		}
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+	}
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+
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+	err = readx_poll_timeout(rockchip_pcie_read_addr,
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+				 PCIE_CLIENT_SIDE_BAND_STATUS,
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+				 regs, !(regs & PCIE_CLIENT_PHY_ST),
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+				 RK_PHY_PLL_LOCK_SLEEP_US,
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+				 RK_PHY_PLL_LOCK_TIMEOUT_US);
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+	if (err) {
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+		dev_err(dev, "PHY PLLs could not lock, %d\n", err);
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+		goto err_power_off_phy;
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 	}
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 	/*
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@@ -457,3 +439,7 @@
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 	rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
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 }
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 EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses);
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+
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+MODULE_AUTHOR("Rockchip Inc");
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+MODULE_DESCRIPTION("Rockchip AXI PCIe driver");
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+MODULE_LICENSE("GPL v2");